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PAM1707BZKBD4

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AM1707 ARM Microprocessor

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 AM1707ARM Microprocessor Check forSamples: AM1707

1 AM1707 ARM Microprocessor

1.1 Features

With One Chip-Select• Applications

Programmable Real-TimeUnitSubsystem– IndustrialAutomation (PRUSS)– Home Automation – Two IndependentProgrammable Realtime– Testand Measurement Unit(PRU) Cores– PortableData Terminals • 32-BitLoad/StoreRISC architecture– EduationalConsoles • 4K Byte instructionRAM per core– Power ProtectionSystems • 512 Bytes dataRAM per core• 375/456-MHz ARM926EJ-S ™ RISC Core • PRU Subsystem (PRUSS) can be disabled– 32-Bitand 16-Bit(Thumb ® )Instructions viasoftwaretosave power– SingleCycle MAC – Standard power management mechanism– ARM ® Jazelle® Technology • Clock gating– EmbeddedICE-RT ™ forReal-TimeDebug • Entiresubsystem under a singlePSC• ARM9 Memory Architecture clockgatingdomain – 16K-Byte InstructionCache – Dedicatedinterruptcontroller – 16K-Byte Data Cache – Dedicatedswitchedcentralresource – 8K-Byte RAM (VectorTable) • MultimediaCard (MMC)/Secure Digital(SD) – 64K-Byte ROM Card InterfacewithSecure Data I/O(SDIO)
Enhanced Direct-Memory-AccessController3 • Two Master/SlaveInter-IntegratedCircuit(I2C (EDMA3): Bus ™ ) – 2 TransferControllers • One Host-PortInterface(HPI)With 16-Bit-Wide – 32 IndependentDMA Channels Muxed Address/DataBus For High Bandwidth – 8 Quick DMA Channels • USB 1.1OHCI (Host)With IntegratedPHY (USB1)– Programmable TransferBurstSize
USB 2.0OTG PortWith IntegratedPHY (USB0)• 128K-Byte RAM Memory – USB 2.0High-/Full-SpeedClient• 3.3VLVCMOS IOs (exceptforUSB interfaces) – USB 2.0High-/Full-/Low-SpeedHost• Two ExternalMemory Interfaces: – End Point0 (Control)– EMIFA – End Points1,2,3,4(Control,Bulk,Interruptor• NOR (8-/16-Bit-WideData) ISOC) Rx and Tx• NAND (8-/16-Bit-WideData)
Three MultichannelAudio SerialPorts:• 16-BitSDRAM With 128MB Address – Transmit/ReceiveClocks up to50 MHzSpace – SixClock Zones and 28 SerialData Pins– EMIFB – Supports TDM, I2S,and SimilarFormats• 32-Bitor 16-BitSDRAM With 256MB Address Space – DIT-Capable(McASP2)
Three Configurable16550 typeUART Modules: – FIFO buffersforTransmitand Receive – UART0 With Modem ControlSignals • 10/100Mb/s EthernetMAC (EMAC): – 16-byteFIFO – IEEE 802.3Compliant (3.3-VI/OOnly) – 16x or 13x Oversampling Option – RMII Media IndependentInterface
LCD Controller – Management Data I/O(MDIO) Module
Two SerialPeripheralInterfaces(SPI)Each • Real-TimeClock With 32 KHz Oscillatorand Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2ARM926EJ-S, EmbeddedICE-RT, ETM9, CoreSightaretrademarksofARM Limited. 3ARM, JazelleareregisteredtrademarksofARM Limited. ADVANCE INFORMATION concernsnew productsinthe sampling Copyright© 2010,Texas InstrumentsIncorporatedorpreproductionphase ofdevelopment.Characteristicdataand other specificationsaresubjecttochange withoutnotice.

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com SeparatePower Rail – TripZone Input

One 64-BitGeneral-PurposeTimer • Three 32-BitEnhanced Capture Modules (Configurableas Two 32-BitTimers) (eCAP):
One 64-bitGeneral-Purpose/WatchdogTimer – Configurableas 3 Capture Inputsor 3 (Configurableas Two 32-bitGeneral-Purpose AuxiliaryPulse Width Modulator(APWM) Timers) outputs
Three Enhanced Pulse Width Modulators – SingleShot Capture ofup toFour Event (eHRPWM): Time-Stamps – Dedicated16-BitTime-Base Counter With • Two 32-BitEnhanced QuadratureEncoder PeriodAnd Frequency Control Pulse Modules (eQEP) – 6 SingleEdge, 6 Dual Edge Symmetric or 3 • 256-BallPb-FreePlasticBallGridArray(PBGA) Dual Edge Asymmetric Outputs [ZKB Suffix],1.0-mm BallPitch – Dead-Band Generation • Commercial, Industrial,Automotive or Extended Temperature– PWM Chopping by High-FrequencyCarrier

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010

1.2 Trademarks

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

1.3 Description

The deviceisa low-powerARM microprocessorbased on an ARM926EJ-S ™ . The deviceenables OEMs and ODMs to quicklybringto market devicesfeaturingrobustoperating systems support,richuser interfaces,and high processingperformancelifethroughthe maximum flexibilityofa fullyintegratedmixed processorsolution. The ARM926EJ-S is a 32-bitRISC processorcore thatperforms32-bitor 16-bitinstructionsand processes32-bit,16-bit,or 8-bitdata.The core uses pipeliningso thatallpartsof the processorand memory systemcan operatecontinuously. The ARM core has a coprocessor15 (CP15), protectionmodule, and Data and program Memory Management Units(MMUs) with tablelook-asidebuffers.Ithas separate16K-byte instructionand 16K-bytedatacaches.Both are four-wayassociativewithvirtualindexvirtualtag(VIVT).The ARM core alsohas a 8KB RAM (VectorTable)and 64KB ROM. The peripheralsetincludes:a 10/100Mb/s EthernetMAC (EMAC) witha Management Data Input/Output (MDIO) module;two inter-integratedcircuit(I2C)Bus interfaces;3 multichannelaudioserialport(McASP) with 16/12/4serializersand FIFO buffers;2 64-bitgeneral-purposetimerseach configurable(one configurableas watchdog);a configurable16-bithostportinterface(HPI);up to 8 banks of 16 pinsof general-purposeinput/output(GPIO) withprogrammable interrupt/eventgenerationmodes, multiplexed withotherperipherals;3 UART interfaces(one withRTS and CTS); 3 enhanced high-resolutionpulse widthmodulator(eHRPWM) peripherals;3 32-bitenhanced capture(eCAP) module peripheralswhichcan be configuredas 3 captureinputsor3 auxiliarypulsewidthmodulator(APWM) outputs;2 32-bitenhanced quadraturepulse(eQEP) peripherals;and 2 externalmemory interfaces:an asynchronousand SDRAM externalmemory interface(EMIFA) forslowermemories or peripherals,and a higherspeed memory interface(EMIFB)forSDRAM. The EthernetMedia Access Controller(EMAC) providesan efficientinterfacebetween thedeviceand the network.The EMAC supportsboth10Base-T and 100Base-TX,or10 Mbits/second(Mbps)and 100 Mbps in eitherhalf-or full-duplexmode. Additionallyan Management Data Input/Output(MDIO) interfaceis availableforPHY configuration. The HPI,I2C,SPI,USB1.1 and USB2.0 portsallowthedevicetoeasilycontrolperipheraldevicesand/or communicatewithhostprocessors. The richperipheralsetprovidesthe abilityto controlexternalperipheraldevicesand communicate with externalprocessors.For detailson each oftheperipherals,see therelatedsectionslaterinthisdocument and theassociatedperipheralreferenceguides. The devicehas a completeset of developmenttoolsforthe ARM. These includeC compilersand a Windows ™ debuggerinterfaceforvisibilityintosourcecode execution.

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ADVANCE□INFORMATION Switched Central Resource (SCR) 16 KB I-Cache 16 KB D-Cache

4 KB ETB

ARM SubsystemJTAG Interface System Control Input Clock(s)

64 KB ROM

8 KB RAM

(Vector Table) Power/Sleep Controller Pin Multiplexing RTC/ 32-KHz OSC PLL/Clock Generator w/OSC General- Purpose Timer General- Purpose Timer (Watchdog) Serial Interfaces I C (2)

2 SPI

(2) UART (3) Audio Ports McASP w/FIFO (3) DMA Peripherals Display Internal Memory LCD Ctlr 128 KB RAM External Memory InterfacesConnectivity EDMA3 Control Timers eHRPWM (3) eCAP (3) eQEP (2) (10/100) EMAC (RMII) MDIO USB1.1 OHCI Ctlr PHY USB2.0 OTG Ctlr PHY HPI MMC/SD (8b) EMIFA(8b/16B) NAND/Flash 16b SDRAM EMIFB SDRAM Only (16b/32b) GPIO Customizable Interface PRU Subsystem AM1707 www.ti.com SPRS637 –FEBRUARY 2010

1.4 FunctionalBlock Diagram

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010

2 RevisionHistory

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

3 Device Overview

3.1 Device Characteristics

Table3-1providesan overviewofthedevice.The tableshows significantfeaturesofthedevice,including thecapacityofon-chipRAM, peripherals,and thepackage typewithpincount. Table3-1.Characteristicsofthedevice HARDWARE FEATURES AM1707 EMIFB 16/32bit,upto512Mb SDRAM EMIFA Asynchronous(8/16-bitbus width)RAM, Flash,16bitupto128Mb SDRAM, NOR, NAND FlashCard Interface MMC and SD cardssupported. EDMA3 32 independentchannels,8 QDMA channels,2 Transfercontrollers 2 64-BitGeneralPurpose(configurableas 2 separate32-bittimers,1 configurableasTimers Watch Dog) UART 3 (onewithRTS and CTS flowcontrol) SPI 2 (Eachwithone hardwarechipselect) I2C 2 (bothMaster/Slave) MultichannelAudio 3 (eachwithtransmit/receive,FIFO buffer,16/12/4serializers)Peripherals SerialPort[McASP] Not allperipheralspins 10/100EthernetMAC areavailableatthe withManagement Data 1 (RMIIInterface) same time(formore I/O detail,see theDevice eHRPWM 6 SingleEdge,6 DualEdge Symmetric,or3 DualEdge AsymmetricOutputsConfigurationssection). eCAP 3 32-bitcaptureinputsor3 32-bitauxiliaryPWM outputs eQEP 2 32-bitQEP channelswith4 inputs/channel UHPI 1 (16-bitmultiplexedaddress/data) USB 2.0(USB0) High-SpeedOTG Controllerwithon-chipOTG PHY USB 1.1(USB1) Full-SpeedOHCI (ashost)withon-chipPHY General-Purpose 8 banks of16-bitInput/OutputPort PRU Subsystem 2 Programmable PRU Cores(PRUSS) LCD Controller 1 Size(Bytes) 168KB RAM, 1088KB ROM ARM 16KB I-Cache 16KB D-CacheOn-ChipMemory 8KB RAM (VectorTable)Organization 64KB ROM ADDITIONAL MEMORY 128KB RAM 0x8B7D F02F (SiliconRevision1.1)JTAG BSDL_ID DEVIDR0 register 0x9B7D F02F (SiliconRevision2.0) CPU Frequency MHz ARM926 375 MHz (1.2V)or456 MHz (1.3V) 1.2V nominalfor375 MHz versionCore (V) 1.3V nominalfor456 MHz versionVoltage I/O(V) 3.3V Package 17 mm x 17 mm, 256-Ball1 mm pitch,PBGA (ZKB) ProductPreview(PP), Advance Information ProductStatus(1) (AI), AI orProductionData (PD) (1) ADVANCE INFORMATION concernsnew productsinthesamplingorpreproductionphase ofdevelopment.Characteristicdataand otherspecificationsaresubjecttochange withoutnotice.

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3.2 Device Compatibility

The ARM926EJ-S RISC CPU iscompatiblewithotherARM9 CPUs fromARM Holdingsplc.

3.3 ARM Subsystem

The ARM Subsystem includesthefollowingfeatures:

ARM926EJ-S RISC processor
ARMv5TEJ (32/16-bit)instructionset
Littleendian
System ControlCo-Processor15 (CP15)
MMU
16KB Instructioncache
16KB Data cache
WriteBuffer
Embedded TraceModule and Embedded TraceBuffer(ETM/ETB)
ARM Interruptcontroller

3.3.1 ARM926EJ-S RISC CPU

The ARM Subsystem integratestheARM926EJ-S processor.The ARM926EJ-S processorisa member of ARM9 familyofgeneral-purposemicroprocessors.Thisprocessoristargetedatmulti-taskingapplications where fullmemory management, highperformance,low diesize,and low power are allimportant.The ARM926EJ-S processorsupportsthe32-bitARM and 16 bitTHUMB instructionsets,enablingtheuserto tradeoffbetween high performanceand high code density.Specifically,the ARM926EJ-S processor supportstheARMv5TEJ instructionset,whichincludesfeaturesforefficientexecutionofJava bytecodes, providingJava performancesimilarto JustinTime (JIT)Java interpreter,but withoutassociatedcode overhead. The ARM926EJ-S processorsupportsthe ARM debug architectureand includeslogicto assistinboth hardware and softwaredebug. The ARM926EJ-S processorhas a Harvardarchitectureand providesa completehighperformancesubsystem,including:

ARM926EJ -S integercore
CP15 systemcontrolcoprocessor
Memory Management Unit(MMU)
Separateinstructionand datacaches
Writebuffer
Separateinstructionand data(internalRAM) interfaces
Separateinstructionand dataAHB bus interfaces
Embedded TraceModule and Embedded TraceBuffer(ETM/ETB) For more completedetailson theARM9, refertotheARM926EJ-S TechnicalReferenceManual,available athttp://www.arm.com

3.3.2 CP15

The ARM926EJ-S system controlcoprocessor(CP15) isused to configureand controlinstructionand datacaches,Memory Management Unit(MMU), and otherARM subsystemfunctions.The CP15 registers areprogrammed usingtheMRC and MCR ARM instructions,when theARM ina privilegedmode such as supervisororsystemmode. Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 9 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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3.3.3 MMU

A singlesetoftwo levelpage tablesstoredinmain memory isused tocontroltheaddresstranslation, permissionchecksand memory regionattributesforbothdataand instructionaccesses.The MMU uses a singleunifiedTranslationLookasideBuffer(TLB) to cache the informationheldinthe page tables.The MMU featuresare:

StandardARM architecturev4 and v5 MMU mapping sizes,domains and accessprotectionscheme.
Mapping sizesare: – 1MB (sections) – 64KB (largepages) – 4KB (smallpages) – 1KB (tinypages)
Access permissionsforlargepages and smallpages can be specifiedseparatelyforeach quarterof thepage (subpagepermissions)
Hardware page tablewalks
InvalidateentireTLB, usingCP15 register8
InvalidateTLB entry,selectedby MVA, usingCP15 register8
Lockdown ofTLB entries,usingCP15 register10

3.3.4 Caches and WriteBuffer

The sizeoftheInstructioncache is16KB, Data cache is16KB. Additionally,thecaches have thefollowing features:

Virtualindex,virtualtag,and addressedusingtheModifiedVirtualAddress(MVA)
Four-waysetassociative,witha cache linelengthofeightwords perline(32-bytesperline)and with two dirtybitsintheDcache
Dcache supportswrite-throughand write-back(orcopy back)cache operation,selectedby memory regionusingtheC and B bitsintheMMU translationtables
Critical-wordfirstcache refilling
Cache lockdownregistersenablecontroloverwhich cache ways are used forallocationon a linefill, providinga mechanism forbothlockdown,and controllingcache corruption
Dcache storesthePhysicalAddress TAG (PA TAG) correspondingtoeach Dcache entryintheTAG RAM foruse duringthe cache linewrite-backs,inadditionto the VirtualAddress TAG storedinthe TAG RAM. Thismeans thattheMMU isnotinvolvedinDcache write-backoperations,removingthe possibilityofTLB missesrelatedtothewrite-backaddress.
Cache maintenanceoperationsprovideefficientinvalidationof,theentireDcache orIcache,regionsof theDcache orIcache,and regionsofvirtualmemory. The writebufferisused forallwritestoa noncachablebufferableregion,write-throughregionand write misses toa write-backregion.A separatebufferisincorporatedintheDcache forholdingwrite-backfor cache lineevictionsorcleaningofdirtycache lines.The main writebufferhas 16-worddatabufferand a four-addressbuffer.The Dcache write-backhas eightdataword entriesand a singleaddressentry.

3.3.5 Advanced High-PerformanceBus (AHB)

The ARM Subsystem uses theAHB portoftheARM926EJ-S toconnecttheARM totheConfigbus and theexternalmemories.Arbitersareemployed toarbitrateaccesstotheseparateD-AHB and I-AHB by the ConfigBus and theexternalmemories bus.

3.3.6 Embedded Trace Macrocell(ETM) and Embedded Trace Buffer(ETB)

To supportreal-timetrace,theARM926EJ-S processorprovidesan interfacetoenableconnectionofan Embedded Trace Macrocell(ETM). The ARM926EJ-S Subsystem in the device also includesthe Embedded TraceBuffer(ETB).The ETM consistsoftwo parts:

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TracePortprovidesreal-timetracecapabilityfortheARM9.
Triggeringfacilitiesprovidetriggerresources,which includeaddressand data comparators,counter, and sequencers. The devicetraceportisnotpinnedoutand isinsteadonlyconnectedtotheEmbedded TraceBuffer.The ETB has a 4KB buffermemory. ETB enableddebug toolsarerequiredtoread/interpretthecapturedtrace data. Thisdeviceuses ETM9 ™ versionr2p2 and ETB versionr0p1.Documentationon the ETM and ETB is availablefromARM Ltd.Referencethe'CoreSight™ ETM9 ™ TechnicalReferenceManual,revisionr0p1' and the'ETM9 TechnicalReferenceManual,revisionr2p2'.

3.3.7 ARM Memory Mapping

By defaulttheARM has accesstomost on and offchipmemory areas,EMIFA, EMIFB, and theadditional 128K byteon chipSRAM. Likewisealmostalloftheon chipperipheralsare accessibletotheARM by default. See Table3-2fora detailedtopleveldevicememory map thatincludestheARM memory space. Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 11 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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3.4 Memory Map Summary

Table3-2.AM1707 Top LevelMemory Map StartAddress End Address Size ARM Mem Map EDMA Mem PRUSS Mem Master LCDC Map Map Peripheral Mem Mem Map Map 0x0000 0000 0x0000 0FFF 4K - PRUSS Local Address Space 0x0000 1000 0x01BB FFFF 0x01BC 0000 0x01BC 0FFF 4K ARM ETB - memory 0x01BC 1000 0x01BC 17FF 2K ARM ETB reg - 0x01BC 1800 0x01BC 18FF 256 ARM Ice - Crusher 0x01BC 1900 0x01BF FFFF - 0x01C0 0000 0x01C0 7FFF 32K EDMA3 CC - 0x01C0 8000 0x01C0 83FF 1024 EDMA3 TC0 - 0x01C0 8400 0x01C0 87FF 1024 EDMA3 TC1 - 0x01C0 8800 0x01C0 FFFF - 0x01C1 0000 0x01C1 0FFF 4K PSC 0 - 0x01C1 1000 0x01C1 1FFF 4K PLL Controller - 0x01C1 2000 0x01C1 3FFF - 0x01C1 4000 0x01C1 4FFF 4K SYSCFG - 0x01C1 5000 0x01C1 FFFF - 0x01C2 0000 0x01C2 0FFF 4K Timer64P 0 - 0x01C2 1000 0x01C2 1FFF 4K Timer64P 1 - 0x01C2 2000 0x01C2 2FFF 4K I2C 0 - 0x01C2 3000 0x01C2 3FFF 4K RTC - 0x01C2 4000 0x01C3 FFFF - - 0x01C4 0000 0x01C4 0FFF 4K MMC/SD 0 - 0x01C4 1000 0x01C4 1FFF 4K SPI 0 - 0x01C4 2000 0x01C4 2FFF 4K UART 0 - 0x01C4 3000 0x01CF FFFF - 0x01D0 0000 0x01D0 0FFF 4K McASP 0 Control - 0x01D0 1000 0x01D0 1FFF 4K McASP 0 AFIFO Ctrl - 0x01D0 2000 0x01D0 2FFF 4K McASP 0 Data - 0x01D0 3000 0x01D0 3FFF - 0x01D0 4000 0x01D0 4FFF 4K McASP 1 Control - 0x01D0 5000 0x01D0 5FFF 4K McASP 1 AFIFO Ctrl - 0x01D0 6000 0x01D0 6FFF 4K McASP 1 Data - 0x01D0 7000 0x01D0 7FFF - 0x01D0 8000 0x01D0 8FFF 4K McASP 2 Control - 0x01D0 9000 0x01D0 9FFF 4K McASP 2 AFIFO Ctrl - 0x01D0 A000 0x01D0 AFFF 4K McASP 2 Data - 0x01D0 B000 0x01D0 BFFF - 0x01D0 C000 0x01D0 CFFF 4K UART 1 - 0x01D0 D000 0x01D0 DFFF 4K UART 2 - 0x01D0 E000 0x01DF FFFF - - 0x01E0 0000 0x01E0 FFFF 64K USB0 - 0x01E1 0000 0x01E1 0FFF 4K UHPI -

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table3-2.AM1707 Top LevelMemory Map (continued) StartAddress End Address Size ARM Mem Map EDMA Mem PRUSS Mem Master LCDC Map Map Peripheral Mem Mem Map Map 0x01E1 1000 0x01E1 1FFF - 0x01E1 2000 0x01E1 2FFF 4K SPI 1 - 0x01E1 3000 0x01E1 3FFF 4K LCD Controller - 0x01E1 4000 0x01E1 4FFF 4K Memory ProtectionUnit1 (MPU 1) - 0x01E1 5000 0x01E1 5FFF 4K Memory ProtectionUnit2 (MPU 2) - 0x01E1 6000 0x01E1 FFFF - 0x01E2 0000 0x01E2 1FFF 8K EMAC ControlModule RAM - 0x01E2 2000 0x01E2 2FFF 4K EMAC ControlModule Registers - 0x01E2 3000 0x01E2 3FFF 4K EMAC ControlRegisters - 0x01E2 4000 0x01E2 4FFF 4K EMAC MDIO port - 0x01E2 5000 0x01E2 5FFF 4K USB1 - 0x01E2 6000 0x01E2 6FFF 4K GPIO - 0x01E2 7000 0x01E2 7FFF 4K PSC 1 - 0x01E2 8000 0x01E2 8FFF 4K I2C 1 - 0x01E2 9000 0x01EF FFFF - 0x01F0 0000 0x01F0 0FFF 4K eHRPWM 0 - 0x01F0 1000 0x01F0 1FFF 4K HRPWM 0 - 0x01F0 2000 0x01F0 2FFF 4K eHRPWM 1 - 0x01F0 3000 0x01F0 3FFF 4K HRPWM 1 - 0x01F0 4000 0x01F0 4FFF 4K eHRPWM 2 - 0x01F0 5000 0x01F0 5FFF 4K HRPWM 2 - 0x01F0 6000 0x01F0 6FFF 4K ECAP 0 - 0x01F0 7000 0x01F0 7FFF 4K ECAP 1 - 0x01F0 8000 0x01F0 8FFF 4K ECAP 2 - 0x01F0 9000 0x01F0 9FFF 4K EQEP 0 - 0x01F0 A000 0x01F0 AFFF 4K EQEP 1 - 0x01F0 B000 0x3FFF FFFF - 0x4000 0000 0x47FF FFFF 128M EMIFA SDRAM data(CS0) - 0x4800 0000 0x5FFF FFFF 0x6000 0000 0x61FF FFFF 32M EMIFA asyncdata(CS2) - 0x6200 0000 0x63FF FFFF 32M EMIFA asyncdata(CS3) - 0x6400 0000 0x65FF FFFF 32M EMIFA asyncdata(CS4) - 0x6600 0000 0x67FF FFFF 32M EMIFA asyncdata(CS5) - 0x6800 0000 0x6800 7FFF 32K EMIFA ControlRegs - 0x6800 8000 0x7FFF FFFF - 0x8000 0000 0x8001 FFFF 128K On-chipRAM - 0x8002 0000 0xAFFF FFFF - 0xB000 0000 0xB000 7FFF 32K EMIFB ControlRegs 0xB000 8000 0xBFFF FFFF - 0xC000 0000 0xCFFF FFFF 256M EMIFB SDRAM Data 0xD000 0000 0xFFFC FFFF 0xFFFD 0000 0xFFFD FFFF 64K ARM local - ROM 0xFFFE 0000 0xFFFE DFFF - 0xFFFE E000 0xFFFE FFFF 8K ARM Interrupt - Controller Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 13 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table3-2.AM1707 Top LevelMemory Map (continued) StartAddress End Address Size ARM Mem Map EDMA Mem PRUSS Mem Master LCDC Map Map Peripheral Mem Mem Map Map 0xFFFF 0000 0xFFFF 1FFF 8K ARM local - ARM local RAM RAM (PRU 0 Only) 0xFFFF 2000 0xFFFF FFFF -

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ADVANCE□INFORMATION VSS VSST AXR1[0]/ GP4[0] AXR1[1 1]/ GP5[1 1] SPI0_CLK/ EQEP1I/ GP5[2]/ BOOT[2] SPI1_CLK/ EQEP1S/ GP5[7]/ BOOT[7] 1 2 3 4 5 6 EMA_CS[3]/ AMUTE2/ GP2[6] EMA_CS[0] UHPI_HAS GP2[4] EMA_A[0]/ LCD_D[7]/ GP1[0] EMA_A[4]/ LCD_D[3]/ GP1[4] EMA_A[8]/ LCD_PCLK/ GP1[8] 1 1 EMA_SDCKE/ GP2[0] EMA_D[0]/ MMCSD_DA T[0]/ UHPI_HD[0]/ GP0[0]/ BOOT[12] EMA_D[9]/ UHPI_HD[9]/ LCD_D[9]/ GP0[9] VSS VSS 15 16 DVDDR AXR1[1]/ GP4[1] UART0_RXD/ I2C0_SDA/ TM64P0_IN12/ GP5[8]/ BOOT[8] SPI1_ENA/ UART2_RXD/ GP5[12] SPI0_ENA UART0_CTS EQEP0A/ GP5[3]/ BOOT[3] SPI0_SOMI[0]/ EQEP0I/ GP5[0]/ BOOT[0] EMA_OE UHPI_HDS1 AXR0[13]/ GP2[7] EMA_BA[0]/ LCD_D[4]/ GP1[14] EMA_A[1]/ MMCSD_CLK/ UHPI_HCNTL0/ GP1[1] EMA_A[5]/ LCD_D[2]/ GP1[5] EMA_A[9]/ LCD_HSYNC/ GP1[9] EMA_CLK/ OBSCLK/ AHCLKR2/ GP1[15] EMA_D[2]/ MMCSD_DA T[2]/ UHPI_HD[2]/ GP0[2] EMA_D[10]/ UHPI_HD[10]/ LCD_D[10]/ GP0[10] EMA_D[1]/ MMCSD_DA T[1]/ UHPI_HD[1]/ GP0[1] DVDD P AXR1[3]/ EQEP1A/ GP4[3] AXR1[2]/ GP4[2] UART0_TXD/ I2C0_SCL/ TM64P0_OUT12/ GP5[9]/ BOOT[9] SPI1_SCS[0]/ UART2_TXD/ GP5[13] SPI1_SOMI[0]/ I2C1_SCL/ GP5[5]/ BOOT[5] SPI0_SIMO[0]/ EQEP0S/ GP5[1]/ BOOT[1] EMA_CS[2] UHPI_HCS GP2[5]/ BOOT[15] EMA_BA[1]/ LCD_D[5]/ UHPI_HHWIL/ GP1[13] EMA_A[2]/ MMCSD_CMD/ UHPI_HCNTL1/ GP1[2] EMA_A[6]/ LCD_D[1]/ GP1[6] EMA_A[1 1]/ GP1[1 1] LCD_AC_ ENB_CS EMA_WE_ DQM[1] UHPI_HDS2 AXR0[14]/ GP2[8] EMA_D[4]/ MMCSD_DA T[4]/ UHPI_HD[4]/ GP0[4] EMA_D[12]/ UHPI_HD[12]/ LCD_D[12]/ GP0[12] EMA_D[3]/ MMCSD_DA T[3]/ UHPI_HD[3]/ GP0[3] EMA_D[1 1]/ UHPI_HD[1 1]/ LCD_D[1 1] GP0[1 1] N AXR1[5]/ EPWM2B/ GP4[5] AXR1[4]/ EQEP1B/ GP4[4] AXR1[10]/ GP5[10] SPI0_SCS[0] UART0_RTS EQEP0B/ GP5[4]/ BOOT[4] SPI1_SIMO[0]/ I2C1_SDA/ GP5[6]/ BOOT[6] EMA_WAIT[0]/ GP2[10] UHPI_HRDY EMA_RAS/ EMA_CS[5]/ GP2[2] EMA_A[10]/ LCD_VSYNC/ GP1[10] EMA_A[3]/ LCD_D[6]/ GP1[3] EMA_A[7]/ LCD_D[0]/ GP1[7] EMA_A[12]/ LCD_MCLK/ GP1[12] EMA_D[8]/ UHPI_HD[8]/ LCD_D[8]/ GP0[8] EMA_D[6]/ MMCSD_DA T[6]/ UHPI_HD[6]/ GP0[6] EMA_D[14]/ UHPI_HD[14]/ LCD_D[14]/ GP0[14] EMA_D[5]/ MMCSD_DA T[5]/ UHPI_HD[5]/ GP0[5] EMA_D[13]/ UHPI_HD[13]/ LCD_D[13]/ GP0[13] M AXR1[9]/ GP4[9] AXR1[8]/ EPWM1A/ GP4[8] AXR1[7]/ EPWM1B/ GP4[7] AXR1[6]/ EPWM2A/ GP4[6] DVDD VSS VSS DVDD DVDD VSS VSS DVDD EMA_WE W UHPI_HR / AXR0[12]/ GP2[3]/ BOOT[14]] EMA_WE_ DQM[0] UHPI_HINT AXR0[15]/ GP2[9] EMA_D[7]/ MMCSD_DA T[7]/ UHPI_HD[7]/ GP0[7]/ BOOT[13] EMA_D[15]/ UHPI_HD[15]/ LCD_D[15]/ GP0[15] L AHCLKR1/ GP4[1 1] ACLKR1/ ECAP2/ APWM2/ GP4[12] AFSR1/ GP4[13] AMUTE0/ RESETOUT DVDD CVDD VSS VSS VSS VSS DVDD DVDD EMB_CAS EMB_D[22] EMB_D[23] EMA_CAS EMA_CS[4] GP2[1] K RTCK/GP7[14] AHCLKX1/ EPWM0B/ GP3[14] ACLKX1/ EPWM0A/ GP3[15] AFSX1/ EPWMSYNCI/ EPWMSYNCO/ GP4[10] DVDD CVDD VSS VSS CVDD CVDD DVDD EMB_D[20] EMB_WE_ DQM[0]/ GP5[15] EMB_WE EMB_D[21]CVDD TMSJ TDI TDO TRST EMU0/GP7[15] CVDD CVDD VSS VSS CVDD CVDD CVDD EMB_D[5]/ GP6[5] EMB_D[19] EMB_D[6]/ GP6[6] EMB_D[7]/ GP6[7] RTC_XIH RTC_XO TCK NC USB0_ VDDA33 CVDD VSS VSS CVDD CVDD EMB_D[3]/ GP6[3] EMB_D[17] EMB_D[18] EMB_D[4]/ GP6[4] RTC_CVDDG RTC_VSS RESET USB0_DM DVDD CVDD VSS VSS CVDD CVDD DVDDCVDD EMB_D[1]/ GP6[1] EMB_D[31] EMB_D[16] EMB_D[2]/ GP6[2] OSCOUTF OSCIN NC USB0_DP DVDD CVDD RSV1 VSS VSS VSS DVDD DVDD EMB_D[15]/ GP6[15] EMB_D[29] EMB_D[30] EMB_D[0]/ GP6[0] PLL0_VSSAE OSCVSS USB0_ VDDA18 USB0_ DRVVBUS/ GP4[15] DVDD VSS VSS DVDD VSS VSSDVDD DVDD EMB_D[13]/ GP6[13] EMB_D[27] EMB_D[28] EMB_D[14]/ GP6[14] PLL0_VDDAD USB0_ID USB0_VBUS AMUTE1/ EHRPWMTZ/ GP4[14] AFSX0/ GP2[13]/ BOOT[10] UART1_TXD/ AXR0[10]/ GP3[10] AXR0[6]/ RMII_RXER/ ACLKR2/ GP3[6] AXR0[2]/ RMII_TXEN/ AXR2[3]/ GP3[2] EMB_CS[0] EMB_A[0]/ GP7[2] EMB_A[4]/ GP7[6] EMB_A[8]/ GP7[10] EMB_D[9]/ GP6[9] EMB_D[10]/ GP6[10] EMB_D[1 1]/ GP6[1 1] EMB_D[12]/ GP6[12] USB1_ VDDA33 C USB1_ VDDA18 USB0_ VDDA12 AFSR0/ GP3[12] ACLKX0/ ECAP0/ APWM0/ GP2[12] UART1_RXD/ AXR0[9]/ GP3[9] AXR0[5]/ RMII_RXD[1]/ AFSX2/ GP3[5] AXR0[1]/ RMII_TXD[1]/ ACLKX2/ GP3[1] EMB_BA[0]/ GP7[1] EMB_A[1]/ GP7[3] EMB_A[5]/ GP7[7] EMB_A[9]/ GP7[1 1] EMB_SDCKE EMB_CLK EMB_WE_ DQM[1]/ GP5[14] EMB_D[8]/ GP6[8] B RSV2 VSS USB1_DM ACLKR0/ ECAP1/ APWM1/ GP2[15] AHCLKX0/ AHCLKX2/ USB_ REFCLKIN/ GP2[1 1] AXR0[8]/ MDIO_D/ GP3[8] AXR0[4]/ RMII_RXD[0]/ AXR2[1]/ GP3[4] AXR0[0]/ RMII_TXD[0]/ AFSR2/ GP3[0] 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 EMB_BA[1]/ GP7[0] EMB_A[2]/ GP7[4] EMB_A[6]/ GP7[8] EMB_A[1 1]/ GP7[13] EMB_WE_ DQM[2] EMB_D[25] EMB_A[12]/ GP3[13] DVDD A VSS VSS USB1_DP AHCLKR0/ RMII_MHZ_ 50_CLK/ GP2[14]/ BOOT[1 1] AXR0[1 1]/ AXR2[0]/ GP3[1 1] AXR0[7]/ MDIO_CLK/ GP3[7] AXR0[3]/ RMII_CRS_DV/ AXR2[2]/ GP3[3] EMB_RAS EMB_A[10]/ GP7[12] EMB_A[3]/ GP7[5] EMB_A[7]/ GP7[9] EMB_WE_ DQM[3] EMB_D[24] EMB_D[26] VSS VSS T R P N M L K J H G F E D C B A RVDD RVDD AM1707 www.ti.com SPRS637 –FEBRUARY 2010

3.5 Pin Assignments

Extensiveuse ofpinmultiplexingisused toaccommodate thelargestnumber ofperipheralfunctionsin the smallestpossiblepackage. Pin multiplexingis controlledusing a combinationof hardware configurationatdeviceresetand softwareprogrammableregistersettings.

3.5.1 Pin Map (Bottom View)

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3.6 TerminalFunctions

Table3-3toTable3-23identifytheexternalsignalnames, theassociatedpin/ballnumbers alongwiththe mechanicalpackage designator,thepintype(I,O, IO,OZ, orPWR), whetherthepin/ballhas any internal pullup/pulldownresistors,whetherthepin/ballisconfigurableas an IO inGPIO mode, and a functionalpin description.

3.6.1 Device Reset and JTAG

Table3-3.Reset and JTAG TerminalFunctions PIN No. SIGNAL NAME TYPE (1) PULL (2) DESCRIPTION ZKB RESET RESET G3 I Deviceresetinput AMUTE0/ RESETOUT L4 O (3) IPD Resetoutput.MultiplexedwithMcASP0 mute output. JTAG TMS J1 I IPU JTAG testmode select TDI J2 I IPU JTAG testdatainput TDO J3 O IPD JTAG testdataoutput TCK H3 I IPD JTAG testclock TRST J4 I IPD JTAG testreset EMU[0 ]/GP7[15] J5 I/O IPU EmulationSignal RTCK/ GP7[14] K1 I/O IPD JTAG TestClockReturnClockOutput (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:Formultiplexedpinswhere functionshave differenttypes(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionfor thatparticularperipheral. (2) IPD = InternalPulldownresistor,IPU = InternalPullupresistor (3) Open drainmode forRESETOUT function.

3.6.2 High-FrequencyOscillatorand PLL

Table3-4.High-FrequencyOscillatorand PLL TerminalFunctions PIN No. SIGNAL NAME TYPE (1) PULL (2) DESCRIPTION ZKB EMA_CLK/ OBSCLK /AHCLKR2/ R12 O IPU PLL ObservationClockGP1[15] 1.2-VOSCILLATOR OSCIN F2 I Oscillatorinput OSCOUT F1 O Oscillatoroutput OSCVSS E2 GND Oscillatorground(forfilteronly) 1.2-VPLL PLL0_VDDA D1 PWR PLL analogVDD (1.2-Vfilteredsupply) PLL0_VSSA E1 GND PLL analogVSS (forfilter) (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:Formultiplexedpinswhere functionshave differenttypes(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionfor thatparticularperipheral. (2) IPD = InternalPulldownresistor,IPU = InternalPullupresistor

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3.6.3 Real-TimeClock and 32-kHz Oscillator

Table3-5.Real-TimeClock (RTC) and 1.2-V,32-kHz OscillatorTerminalFunctions PIN No. SIGNAL NAME TYPE (1) PULL (2) DESCRIPTION ZKB RTC_CVDD G1 PWR RTC module corepower (isolatedfromrestofchipCV DD ) RTC_XI H1 I Low-frequency(32-kHz)oscillatorreceiverforreal-timeclock RTC_XO H2 O Low-frequency(32-kHz)oscillatordriverforreal-timeclock RTC_V ss G2 GND Oscillatorground(forfilter) (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:Formultiplexedpinswhere functionshave differenttypes(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionfor thatparticularperipheral. (2) IPD = InternalPulldownresistor,IPU = InternalPullupresistor

3.6.4 ExternalMemory InterfaceA (ASYNC, SDRAM)

Table3-6.ExternalMemory InterfaceA (EMIFA) TerminalFunctions PIN No.SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB EMA_D[15] /UHPI_HD[15]/LCD_D[15]/GP0[15] M16 I/O IPD EMA_D[14] /UHPI_HD[14]/LCD_D[14]/GP0[14] N14 I/O IPD EMA_D[13] /UHPI_HD[13]/LCD_D[13]/GP0[13] N16 I/O IPD EMA_D[12] /UHPI_HD[12]/LCD_D[12]/GP0[12] P14 I/O IPD UHPI, LCD, GPIOEMA_D[11] /UHPI_HD[11]/LCD_D[11]/GP0[11] P16 I/O IPD EMA_D[10] /UHPI_HD[10]/LCD_D[10]/GP0[10] R14 I/O IPD EMA_D[9] /UHPI_HD[9]/LCD_D[9]/GP0[9] T14 I/O IPD EMA_D[8] /UHPI_HD[8]/LCD_D[8]/GP0[8] N12 I/O IPD MMC/SD, UHPI, EMIFA databusEMA_D[7] /MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13] M15 I/O IPU GPIO, BOOT EMA_D[6] /MMCSD_DAT[6]/UHPI_HD[6]/GP0[6] N13 I/O IPU EMA_D[5] /MMCSD_DAT[5]/UHPI_HD[5]/GP0[5] N15 I/O IPU EMA_D[4] /MMCSD_DAT[4]/UHPI_HD[4]/GP0[4] P13 I/O IPU MMC/SD, UHPI, GPIOEMA_D[3] /MMCSD_DAT[3]/UHPI_HD[3]/GP0[3] P15 I/O IPU EMA_D[2] /MMCSD_DAT[2]/UHPI_HD[2]/GP0[2] R13 I/O IPU EMA_D[1] /MMCSD_DAT[1]/UHPI_HD[1]/GP0[1] R15 I/O IPU MMC/SD, UHPI,EMA_D[0] /MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12] T13 I/O IPU GPIO, BOOT (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thethesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor,IPU = InternalPullupresistor Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 17 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table3-6.ExternalMemory InterfaceA (EMIFA) TerminalFunctions(continued) PIN No.SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB EMA_A[12]/LCD_MCLK/GP1[12] N11 O IPU EMA_A[11]/ LCD_AC_ENB_CS/GP1[11] P11 O IPU EMA_A[10]/LCD_VSYNC/GP1[10] N8 O IPU EMA_A[9]/LCD_HSYNC/GP1[9] R11 O IPU EMA_A[8]/LCD_PCLK/GP1[8] T11 O IPU LCD, GPIO EMIFA addressbus EMA_A[7]/LCD_D[0]/GP1[7] N10 O IPD EMA_A[6]/LCD_D[1]/GP1[6] P10 O IPD EMA_A[5]/LCD_D[2]/GP1[5] R10 O IPD EMA_A[4]/LCD_D[3]/GP1[4] T10 O IPD EMA_A[3]/LCD_D[6]/GP1[3] N9 O IPD EMA_A[2] /MMCSD_CMD/UHPI_HCNTL1/GP1[2] P9 O IPU MMCSD, UHPI, GPIOEMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1] R9 O IPU EMIFA addressbus. EMA_A[0]/LCD_D[7]/GP1[0] T9 O IPD LCD, GPIO LCD, UHPI,EMA_BA[1] /LCD_D[5]/UHPI_HHWIL/GP1[13] P8 O IPU GPIO EMIFA bank address EMA_BA[0]/ LCD_D[4]/GP1[14] R8 O IPU LCD, GPIO McASP2, GPIO,EMA_CLK/ OBSCLK/AHCLKR2/GP1[15] R12 O IPU EMIFA clock.OBSCLK EMIFA SDRAM clockEMA_SDCKE/ GP2[0] T12 O IPU GPIO enable. EMIFA SDRAM rowEMA_RAS /EMA_CS[5]/GP2[2] N7 O IPU addressstrobe.EMIF A chip select,GPIO EMIFA SDRAM columnEMA_CAS /EMA_CS[4]/GP2[1] L16 O IPU addressstrobe. EMA_RAS/ EMA_CS[5] /GP2[2] N7 O IPU EMIF A SDRAM, GPIOEMA_CAS/ EMA_CS[4] /GP2[1] L16 O IPU EMIFA Async Chip EMA_CS[3] /AMUTE2/GP2[6] T7 O IPU McASP2, GPIO Select UHPI, GPIO,EMA_CS[2] /UHPI_HCS/GP2[5]/BOOT[15] P7 O IPU BOOT EMIFA SDRAM chipEMA_CS[0] /UHPI_HAS/GP2[4] T8 O IPU UHPI, GPIO select UHPI, MCASP0, EMIFA SDRAM writeEMA_WE /UHPI_HR W/AXR0[12]/GP2[3]/BOOT[14] M13 O IPU GPIO, BOOT enable. EMIFA write EMA_WE_DQM[1] /UHPI_HDS2/AXR0[14]/GP2[8] P12 O IPU enable/datamask for EMA_D[15:8]UHPI, McASP, GPIO EMIFA write EMA_WE_DQM[0] /UHPI_HINT/AXR0[15]/GP2[9] M14 O IPU enable/datamask for EMA_D[7:0]. UHPI, McASP0,EMA_OE /UHPI_HDS1/AXR0[13]/GP2[7] R7 O IPU EMIFA outputenable.GPIO EMIFA waitEMA_WAIT[0]/ UHPI_HRDY/GP2[10] N6 I IPU UHPI, GPIO input/interrupt.

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3.6.5 ExternalMemory InterfaceB (SDRAM only)

Table3-7.ExternalMemory InterfaceB (EMIFB) TerminalFunctions PIN No. SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB EMB_D[31] G14 O IPD EMB_D[30] F15 O IPD EMB_D[29] F14 O IPD EMB_D[28] E15 O IPD EMB_D[27] E14 O IPD EMB_D[26] A14 O IPD EMB_D[25] B14 O IPD EMB_D[24] A13 O IPD EMB_D[23] L15 O IPD EMB_D[22] L14 O IPD EMB_D[21] K16 O IPD EMB_D[20] K13 O IPD EMB_D[19] J14 O IPD EMB_D[18] H15 O IPD EMB_D[17] H14 O IPD EMB_D[16] G15 O IPD EMIFB SDRAM databus. EMB_D[15] /GP6[15] F13 I/O IPD EMB_D[14] /GP6[14] E16 I/O IPD EMB_D[13] /GP6[13] E13 I/O IPD EMB_D[12] /GP6[12] D16 I/O IPD EMB_D[11] /GP6[11] D15 I/O IPD EMB_D[10] /GP6[10] D14 I/O IPD EMB_D[9] /GP6[9] D13 I/O IPD EMB_D[8] /GP6[8] C16 I/O IPD GPIO EMB_D[7] /GP6[7] J16 I/O IPD EMB_D[6] /GP6[6] J15 I/O IPD EMB_D[5] /GP6[5] J13 I/O IPD EMB_D[4]/GP6[4] H16 I/O IPD EMB_D[3]/GP6[3] H13 I/O IPD EMB_D[2] /GP6[2] G16 I/O IPD EMB_D[1] /GP6[1] G13 I/O IPD EMB_D[0]/GP6[0] F16 I/O IPD EMB_A[12] /GP3[13] B15 O IPD EMB_A[11] /GP7[13] B12 O IPD EMB_A[10] /GP7[12] A9 O IPD EMB_A[9]/GP7[11] C12 O IPD EMIFB SDRAM row/columnGPIO addressbus.EMB_A[8] /GP7[10] D12 O IPD EMB_A[7] /GP7[9] A11 O IPD EMB_A[6] /GP7[8] B11 O IPD EMB_A[5] /GP7[7] C11 O IPD (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thethesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor,IPU = InternalPullupresistor Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 19 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table3-7.ExternalMemory InterfaceB (EMIFB) TerminalFunctions(continued) PIN No. SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB EMB_A[4]/GP7[6] D11 O IPD EMB_A[3] /GP7[5] A10 O IPD EMIFB SDRAM row/columnEMB_A[2] /GP7[4] B10 O IPD address. EMB_A[1] /GP7[3] C10 O IPD GPIO EMB_A[0]/GP7[2] D10 O IPD EMB_BA[1]/ GP7[0] B9 O IPU EMIFB SDRAM bank address. EMB_BA[0]/ GP7[1] C9 O IPU EMB_CLK C14 O IPU EMIF SDRAM clock. EMB_SDCKE C13 I/O IPU EMIFB SDRAM clockenable. EMB_WE K15 O IPU EMIFB writeenable EMIFB SDRAM row addressEMB_RAS A8 O IPU strobe. EMB_CAS L13 O IPU EMIFB column addressstrobe. EMB_CS[0] D9 O IPU EMIFB SDRAM chipselect0. EMB_WE_DQM[3] A12 O IPU EMB_WE_DQM[2] B13 O IPU EMIFB writeenable/datamask forEMB_D.EMB_WE_DQM[1] /GP5[14] C15 O IPU GPIO EMB_WE_DQM[0] /GP5[15] K14 O IPU

3.6.6 SerialPeripheralInterfaceModules (SPI0,SPI1)

Table3-8.SerialPeripheralInterface(SPI)TerminalFunctions PIN No.SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB SPI0 UART0, EQEP0B,SPI0_SCS[0] /UART0_RTS/EQEP0B/GP5[4]/BOOT[4] N4 I/O IPU SPI0 chipselect.GPIO, BOOT UART0, EQEP0A,SPI0_ENA /UART0_CTS/EQEP0A/GP5[3]/BOOT[3] R5 I/O IPU SPI0 enable.GPIO, BOOT SPI0_CLK /EQEP1I/GP5[2]/BOOT[2] T5 I/O IPD eQEP1, GPIO, BOOT SPI0 clock. SPI0 dataSPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] P6 I/O IPD slave-in-master-out. eQEP0, GPIO, BOOT SPI0 dataSPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] R6 I/O IPD slave-out-master-in. SPI1 SPI1_SCS[0] /UART2_TXD/GP5[13] P4 I/O IPU SPI1 chipselect. UART2, GPIO SPI1_ENA /UART2_RXD/GP5[12] R4 I/O IPU SPI1 enable. SPI1_CLK /EQEP1S/GP5[7]/BOOT[7] T6 I/O IPD eQEP1, GPIO, BOOT SPI1 clock. SPI1 dataSPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] N5 I/O IPU slave-in-master-out. I2C1,GPIO, BOOT SPI1 dataSPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] P5 I/O IPU slave-out-master-in. (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thethesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor,IPU = InternalPullupresistor

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3.6.7 Enhanced Capture/AuxiliaryPWM Modules (eCAP0, eCAP1, eCAP2)

The eCAP Module pinsfunctionas eitherinputcapturesorauxilaryPWM 32-bitoutputs,dependingupon how theeCAP module isprogrammed. Table3-9.Enhanced Capture Module (eCAP) TerminalFunctions PIN No.SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB eCAP0 enhanced capture 0 inputorACLKX0/ ECAP0/APWM0 /GP2[12] C5 I/O IPD McASP0, GPIO auxiliaryPWM 0 output. eCAP1 enhanced capture 1 inputorACLKR0/ ECAP1/APWM1 /GP2[15] B4 I/O IPD McASP0, GPIO auxiliaryPWM 1 output. eCAP2 enhanced capture 2 inputorACLKR1 /ECAP2/APWM2 /GP4[12] L2 I/O IPD McASP1, GPIO auxiliaryPWM 2 output. (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thethesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor,IPU = InternalPullupresistor Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 21 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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3.6.8 Enhanced Pulse Width Modulators(eHRPWM0, eHRPWM1, eHRPWM2)

Table3-10.Enhanced Pulse Width Modulator(eHRPWM) TerminalFunctions PIN No.SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB eHRPWM0 eHRPWM0 A outputACLKX1/ EPWM0A /GP3[15] K3 I/O IPD (withhigh-resolution).McASP1, GPIO AHCLKX1/ EPWM0B /GP3[14] K2 I/O IPD eHRPWM0 B output. McASP1, eHRPWM1, eHRPWM0 tripzoneAMUTE1/ EPWMTZ /GP4[14] D4 I/O IPD GPIO, eHRPWM2 input. Sync inputto McASP1, eHRPWM0, eHRPWM0 module orAFSX1/EPWMSYNCI /EPWMSYNCO /GP4[10] K4 I/O IPD GPIO syncoutputto externalPWM. eHRPWM1 eHRPWM1 A outputAXR1[8]/EPWM1A /GP4[8] M2 I/O IPD (withhigh-resolution).McASP1, GPIO AXR1[7]/EPWM1B /GP4[7] M3 I/O IPD eHRPWM1 B output. McASP1, eHRPWM1, eHRPWM1 tripzoneAMUTE1/ EPWMTZ /GP4[14] D4 I/O IPD GPIO, eHRPWM2 input. eHRPWM2 eHRPWM2 A outputAXR1[6]/EPWM2A /GP4[6] M4 I/O IPD (withhigh-resolution).McASP1, GPIO AXR1[5]/EPWM2B /GP4[5] N1 I/O IPD eHRPWM2 B output. McASP1, eHRPWM1, eHRPWM2 tripzoneAMUTE1/ EPWMTZ /GP4[14] D4 I/O IPD GPIO, eHRPWM2 input. (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thethesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor,IPU = InternalPullupresistor

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3.6.9 Enhanced QuadratureEncoder Pulse Module (eQEP)

Table3-11.Enhanced QuadratureEncoder Pulse Module (eQEP) TerminalFunctions PIN No.SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB eQEP0 EQEP0A quadratureSPI0_ENA/UART0_CTS/ EQEP0A /GP5[3]/BOOT[3] R5 I IPU input.SPIO, UART0, GPIO, BOOT EQEP0B quadratureSPI0_SCS[0]/UART0_RTS/ EQEP0B /GP5[4]/BOOT[4] N4 I IPU input. SPI0_SOMI[0]/EQEP0I /GP5[0]/BOOT[0] R6 I IPD eQEP0 index. SPI1,GPIO, BOOT SPI0_SIMO[0]/EQEP0S /GP5[1]/BOOT[1] P6 I IPD eQEP0 strobe. eQEP1 eQEP1 quadratureAXR1[3]/EQEP1A /GP4[3] P1 I IPD input.McASP1, GPIO McASP1, GPIO eQEP1 quadratureAXR1[4]/EQEP1B /GP4[4] N2 I IPD input. SPI0_CLK/EQEP1I /GP5[2]/BOOT[2] T5 I IPD eQEP1 index. SPI1,GPIO, BOOT SPI1_CLK/EQEP1S /GP5[7]/BOOT[7] T6 I IPD eQEP1 strobe. (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thethesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor,IPU = InternalPullupresistor Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 23 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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3.6.10 Boot

Table3-12.Boot Mode SelectionTerminalFunctions(1) PIN No. SIGNAL NAME TYPE (2) PULL (3) MUXED DESCRIPTION ZKB EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15] P7 I IPU EMIFA, UHPI, GPIO EMIFA, UHPI,EMA_WE/UHPI_HR W/AXR0[12]/GP2[3]/BOOT[14] M13 I IPU McASP0, GPIO EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13] M15 I IPU EMIFA, MMC/SD, UHPI, GPIOEMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12] T13 I IPU McASP0, EMAC,AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/ BOOT[11] A4 I IPD GPIO AFSX0/GP2[13]/BOOT[10] D5 I IPD McASP0, GPIO UART0, I2C0,Timer0,UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/ BOOT[9] P3 I IPU GPIO UART0, I2C0,Timer0, BootModeUART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/ BOOT[8] R3 I IPU GPIO SelectionPins SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] T6 I IPD SPI1,eQEP1, GPIO SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] N5 I IPU SPI1,I2C1,GPIO SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] P5 I IPU SPI0,UART0,SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/ BOOT[4] N4 I IPU eQEP0, GPIO SPI0,UART0,SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/ BOOT[3] R5 I IPU eQEP0, GPIO SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] T5 I IPD SPIO, eQEP1, GPIO SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] P6 I IPD SPI0,eQEP0, GPIO SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] R6 I IPD (1) Bootdecodingwillbe definedintheROM datasheet. (2) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thethesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (3) IPD = InternalPulldownresistor,IPU = InternalPullupresistor

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3.6.11 UniversalAsynchronous Receiver/Transmitters(UART0, UART1, UART2)

Table3-13.UniversalAsynchronous Receiver/Transmitter(UART) TerminalFunctions PIN No.SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB UART0 I2C0,BOOT,UART0_RXD /I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] R3 I IPU UART0 receivedata.Timer0,GPIO, I2C0,Timer0,GPIO, UART0 transmitUART0_TXD /I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] P3 O IPU BOOT data. UART0SPI0_SCS[0]/UART0_RTS /EQEP0B/GP5[4]/BOOT[4] N4 O IPU ready-to-sendoutputSPIO, eQEP0, GPIO, BOOT UART0SPI0_ENA/ UART0_CTS /EQEP0A/GP5[3]/BOOT[3] R5 I IPU clear-to-sendinput UART1 UART1_RXD /AXR0[9]/GP39 C6 I IPD UART1 receivedata. McASP0, GPIO UART1 transmitUART1_TXD /AXR0[10]/GP310 D6 O IPD data. UART2 SPI1_ENA/UART2_RXD /GP5[12] R4 I IPU UART2 receivedata. SPI1,GPIO UART2 transmitSPI1_SCS[0]/UART2_TXD /GP5[13] P4 O IPU data. (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thethesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor,IPU = InternalPullupresistor (3) As thesesignalsareinternallypulleddown whilethedeviceisinreset,itisnecessarytoexternallypullthem highwithresistorsif UART1 bootmode isused.

3.6.12 Inter-IntegratedCircuitModules(I2C0,I2C1)

Table3-14.Inter-IntegratedCircuit(I2C)TerminalFunctions PIN No.SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB I2C0 UART0, Timer0,UART0_RXD/ I2C0_SDA /TM64P0_IN12/GP5[8]/BOOT[8] R3 I/O IPU I2C0 serialdata.GPIO, BOOT UART0, Timer0,UART0_TXD/ I2C0_SCL /TM64P0_OUT12/GP5[9]/BOOT[9] P3 I/O IPU I2C0 serialclock.GPIO, BOOT I2C1 SPI1_SIMO[0]/I2C1_SDA /GP5[6]/BOOT[6] N5 I/O IPU I2C1 serialdata. SPI1,GPIO, BOOT SPI1_SOMI[0]/I2C1_SCL /GP5[5]/BOOT[5] P5 I/O IPU I2C1 serialclock. (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thethesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor,IPU = InternalPullupresistor Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 25 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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3.6.13 Timers

Table3-15.Timers TerminalFunctions PIN No.SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB TIMER0 UART0_RXD/I2C0_SDA/ TM64P0_IN12 /GP5[8]/BOOT[8] R3 I IPU Timer0lowerinput. UART0, I2C0, Timer0lowerGPIO, BOOTUART0_TXD/I2C0_SCL/ TM64P0_OUT12 /GP5[9]/BOOT[9] P3 O IPU output TIMER1 (Watchdog ) No externalpins.The Timer1peripheralsignalsarenotpinnedoutas externalpins. (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thethesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor,IPU = InternalPullupresistor

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3.6.14 UniversalHost-PortInterface(UHPI)

Table3-16.UniversalHost-PortInterface(UHPI)TerminalFunctions PIN No.SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15] M16 I/O IPD EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14] N14 I/O IPD EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13] N16 I/O IPD EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12] P14 I/O IPD EMIFA, LCD, GPIO EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11] P16 I/O IPD EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10] R14 I/O IPD EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9] T14 I/O IPD EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8] N12 I/O IPD EMA_D[7]/MMCSD_DAT[7]/ UHPI_HD[7]/GP0[7]/ EMIFA, MMC/SD, UHPI databus.M15 I/O IPUBOOT[13] GPIO, BOOT EMA_D[6]/MMCSD_DAT[6]/ UHPI_HD[6]/GP0[6] N13 I/O IPU EMA_D[5]/MMCSD_DAT[5]/ UHPI_HD[5]/GP0[5] N15 I/O IPU EMA_D[4]/MMCSD_DAT[4]/ UHPI_HD[4]/GP0[4] P13 I/O IPU EMIFA, MMC/SD, GPIOEMA_D[3]/MMCSD_DAT[3]/ UHPI_HD[3]/GP0[3] P15 I/O IPU EMA_D[2]/MMCSD_DAT[2]/ UHPI_HD[2]/GP0[2] R13 I/O IPU EMA_D[1]/MMCSD_DAT[1]/ UHPI_HD[1]/GP0[1] R15 I/O IPU EMA_D[0]/MMCSD_DAT[0]/ UHPI_HD[0]/GP0[0]/ EMIFA, MMC/SD,T13 I/O IPUBOOT[12] GPIO, BOOT EMA_A[2]/MMCSD_CMD/ UHPI_HCNTL1 /GP1[2] P9 I/O IPU EMIFA, MMCSD_CMD, UHPI accesscontrol. EMA_A[1]/MMCSD_CLK/ UHPI_HCNTL0 /GP1[1] R9 I/O IPU GPIO UHPI half-wordEMA_BA[1]/LCD_D[5]/UHPI_HHWIL /GP1[13] P8 I/O IPU EMIFA, LCD, GPIO identificationcontrol. EMIFA, McASP,EMA_WE/ UHPI_HR W /AXR0[12]/GP2[3]/BOOT[14] M13 I/O IPU UHPI read/write.GPIO, BOOT EMIFA, GPIO,EMA_CS[2]/ UHPI_HCS /GP2[5]/BOOT[15] P7 I/O IPU UHPI chipselect.BOOT EMA_WE_DQM[1]/ UHPI_HDS2 /AXR0[14]/GP2[8] P12 I/O IPU UHPI datastrobe.EMIFA, McASP0,EMA_OE/ UHPI_HDS1 /AXR0[13]/GP2[7] R7 I/O IPU GPIO EMA_WE_DQM[0]/ UHPI_HINT /AXR0[15]/GP2[9] M14 I/O IPU UHPI hostinterrupt. EMA_WAIT[0]/ UHPI_HRDY /GP2[10] N6 I/O IPU UHPI ready. EMIFA, GPIO UHPI addressEMA_CS[0]/ UHPI_HAS /GP2[4] T8 I/O IPU strobe. (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thethesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor,IPU = InternalPullupresistor Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 27 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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3.6.15 MultichannelAudio SerialPorts(McASP0, McASP1, McASP2)

Table3-17.MultichannelAudio SerialPorts(McASPs) TerminalFunctions PIN No.SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB McASP0 EMA_WE_DQM[0]/ UHPI_HINT/AXR0[15]/GP2[9] M14 I/O IPU EMIFA, UHPI,EMA_WE_DQM[1]/ UHPI_HDS2/ AXR0[14]/GP2[8] P12 I/O IPU GPIO EMA_OE/ UHPI_HDS1/ AXR0[13]/GP2[7] R7 I/O IPU EMIFA, UHPI,EMA_WE/UHPI_HR W/AXR0[12]/GP2[3]/BOOT[14] M13 I/O IPU GPIO, BOOT AXR0[11]/AXR2[0]/GP3[11] A5 I/O IPD McASP2, GPIO UART1_TXD/ AXR0[10]/GP3[10] D6 I/O IPD GPIO UART1_RXD/ AXR0[9]/GP3[9] C6 I/O IPD GPIO McASP0 serialAXR0[8]/MDIO_D/GP3[8] B6 I/O IPU MDIO, GPIO data. AXR0[7]/MDIO_CLK/GP3[7] A6 I/O IPD AXR0[6]/RMII_RXER/ACLKR2/GP3[6] D7 I/O IPD AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5] C7 I/O IPD AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4] B7 I/O IPD EMAC,AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3] A7 I/O IPD McASP2, GPIO AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2] D8 I/O IPD AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1] C8 I/O IPD AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0] B8 I/O IPD McASP2, USB, McASP1 transmitAHCLKX0 /AHCLKX2/USB_REFCLKIN/GP2[11] B5 I/O IPD GPIO masterclock. McASP0 transmitACLKX0 /ECAP0/APWM0/GP2[12] C5 I/O IPD eCAP0, GPIO bitclock. McASP0 transmitAFSX0 /GP2[13]/BOOT[10] D5 I/O IPD GPIO, BOOT framesync. EMAC, GPIO, McASP0 receiveAHCLKR0 /RMII_MHZ_50_CLK/GP2[14]/BOOT[11] A4 I/O IPD BOOT masterclock. McASP0 receiveACLKR0 /ECAP1/APWM1/GP2[15] B4 I/O IPD eCAP1, GPIO bitclock. McASP0 receiveAFSR0 /GP3[12] C4 I/O IPD GPIO framesync. McASP0 muteAMUTE0 /RESETOUT L4 I/O IPD RESETOUT output. (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thethesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor,IPU = InternalPullupresistor

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table3-17.MultichannelAudio SerialPorts(McASPs) TerminalFunctions(continued) PIN No.SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB McASP1 AXR1[11]/GP5[11] T4 I/O IPU AXR1[10]/GP5[10] N3 I/O IPU GPIO AXR1[9]/GP4[9] M1 I/O IPD eHRPWM1 A,AXR1[8]/EPWM1A/GP4[8] M2 I/O IPD GPIO eHRPWM1 B,AXR1[7]/EPWM1B/GP4[7] M3 I/O IPD GPIO eHRPWM2 A, McASP1 serialAXR1[6]/EPWM2A/GP4[6] M4 I/O IPD GPIO data. eHRPWM2 B,AXR1[5]/EPWM2B/GP4[5] N1 I/O IPD GPIO AXR1[4]/EQEP1B/GP4[4] N2 I/O IPD eQEP1, GPIO AXR1[3]/EQEP1A/GP4[3] P1 I/O IPD AXR1[2]/GP4[2] P2 I/O IPD AXR1[1]/GP4[1] R2 I/O IPD GPIO AXR1[0]/GP4[0] T3 I/O IPD eHRPWM0, McASP1 transmitAHCLKX1 /EPWM0B/GP3[14] K2 I/O IPD GPIO masterclock. eHRPWM0, McASP1 transmitACLKX1 /EPWM0A/GP3[15] K3 I/O IPD GPIO bitclock. eHRPWM0, McASP1 transmitAFSX1 /EPWMSYNCI/EPWMSYNCO/GP4[10] K4 I/O IPD GPIO framesync. McASP1 receiveAHCLKR1 /GP4[11] L1 I/O IPD GPIO masterclock. McASP1 receiveACLKR1 /ECAP2/APWM2/GP4[12] L2 I/O IPD eCAP2, GPIO bitclock. McASP1 receiveAFSR1 /GP4[13] L3 I/O IPD GPIO framesync. eHRPWM0, eHRPWM1, McASP1 muteAMUTE1 /EPWMTZ/GP4[14] D4 I/O IPD GPIO, output. eHRPWM2 McASP2 AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2] D8 I/O IPD AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3] A7 I/O IPD McASP0, McASP2 serial EMAC, GPIO data.AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4] B7 I/O IPD AXR0[11]/AXR2[0]/GP3[11] A5 I/O IPD McASP2 transmitAHCLKX0/ AHCLKX2 /USB_REFCLKIN/GP2[11] B5 I/O IPD masterclock.McASP0, USB, GPIO McASP2 transmitAXR0[1]/RMII_TXD[1]/ACLKX2 /GP3[1] C8 I/O IPD bitclock. McASP0, McASP2 transmitAXR0[5]/RMII_RXD[1]/AFSX2 /GP3[5] C7 I/O IPD EMAC, GPIO framesync. EMIFA, GPIO, McASP2 receiveEMA_CLK/OBSCLK/ AHCLKR2 /GP1[15] R12 I/O IPU OBSCLK masterclock. McASP0, McASP2 receiveAXR0[6]/RMII_RXER/ACLKR2 /GP3[6] D7 I/O IPD EMAC, GPIO bitclock. McASP2 muteEMA_CS[3]/AMUTE2 /GP2[6] T7 I/O IPU EMIFA, GPIO output. Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 29 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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3.6.16 UniversalSerialBus Modules (USB0, USB1)

Table3-18.UniversalSerialBus (USB) TerminalFunctions PIN No.SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB USB0 2.0OTG (USB0) USB0_DM G4 A NA USB0 PHY dataminus USB0_DP F4 A NA USB0 PHY dataplus USB0_VDDA33 H5 PWR NA USB0 PHY 3.3-Vsupply USB0_VDDA18 E3 PWR NA USB0 PHY 1.8-Vsupplyinput USB0_VDDA12 (3) C3 PWR NA USB0 PHY 1.2-VLDO outputforbypasscap USB0_ID D2 A NA USB0 PHY identification(mini-Aormini-Bplug) USB0_VBUS D3 A NA USB0 bus voltage USB0 controllerVBUS controloutput.MultiplexedUSB0_DRVVBUS /GP4[15] E4 0 IPD GPIO withGPIO bank 4 pin15. AHCLKX0/AHCLKX2/ USB_REFCLKIN / B5 I IPD USB_REFCLKIN. Optionalclockinput.GP2[11] USB1 1.1OHCI (USB1) USB1_DM B3 A NA USB1 PHY dataminus USB1_DP A3 A NA USB1 PHY dataplus USB1_VDDA33 C1 PWR NA USB1 PHY 3.3-Vsupply USB1_VDDA18 C2 PWR NA USB1 PHY 1.8-Vsupply AHCLKX0/AHCLKX2/ USB_REFCLKIN / B5 I IPD NA USB_REFCLKIN. Optionalclockinput.GP2[11] (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thethesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor,IPU = InternalPullupresistor (3) Core power supplyLDO outputforUSB PHY. Thispinmust be connectedviaa 0.22uF capacitortoVSS.

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3.6.17 EthernetMedia Access Controller(EMAC)

Table3-19.EthernetMedia Access Controller(EMAC) TerminalFunctions PIN No.SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB RMII EMAC 50-MHz AHCLKR0/ RMII_MHZ_50_CLK /GP2[14]/BOOT[11] A4 I/O IPD McASP0, GPIO, BOOT clockinputor output. EMAC RMII receiverAXR0[6]/RMII_RXER /ACLKR2/GP3[6] D7 I IPD error. AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5] C7 I IPD EMAC RMII receive data.AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4] B7 I IPD EMAC RMII carrierAXR0[3]/RMII_CRS_DV/ AXR2[2]/GP3[3] A7 I IPD McASP0, McASP2, GPIO sense datavalid. EMAC RMII transmitAXR0[2]/RMII_TXEN /AXR2[3]/GP3[2] D8 O IPD enable. AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1] C8 O IPD EMAC RMII trasmit data.AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0] B8 O IPD MDIO AXR0[8]/MDIO_D/ GP3[8] B6 I/O IPU MDIO serialdata. McASP0, GPIO AXR0[7]/MDIO_CLK /GP3[7] A6 O IPD MDIO clock (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thethesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor,IPU = InternalPullupresistor

3.6.18 MultimediaCard/SecureDigital(MMC/SD)

Table3-20.MultimediaCard/SecureDigital(MMC/SD) TerminalFunctions PIN No.SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB EMA_A[1]/MMCSD_CLK /UHPI_HCNTL0/GP1[1] R9 O IPU MMCSD Clock. EMIFA, UHPI, GPIO EMA_A[2]/MMCSD_CMD /UHPI_HCNTL1/GP1[2] P9 I/O IPU MMCSD Command. EMIFA, UHPI, GPIO,EMA_D[7]/MMCSD_DAT[7] /UHPI_HD[7]/GP0[7]/BOOT[13] M15 I/O IPU BOOT EMA_D[6]/MMCSD_DAT[6] /UHPI_HD[6]/GP0[6] N13 I/O IPU EMA_D[5]/MMCSD_DAT[5]/ UHPI_HD[5]/GP0[5] N15 I/O IPU EMA_D[4]/MMCSD_DAT[4] /UHPI_HD[4]/GP0[4] P13 I/O IPU EMIFA, UHPI, GPIO MMC/SD data. EMA_D[3]/MMCSD_DAT[3] /UHPI_HD[3]/GP0[3] P15 I/O IPU EMA_D[2]/MMCSD_DAT[2] /UHPI_HD[2]/GP0[2] R13 I/O IPU EMA_D[1]/MMCSD_DAT[1] /UHPI_HD[1]/GP0[1] R15 I/O IPU EMIFA, UHPI, GPIO,EMA_D[0]/MMCSD_DAT[0] /UHPI_HD[0]/GP0[0]/BOOT[12] T13 I/O IPU BOOT (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thethesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor,IPU = InternalPullupresistor Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 31 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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3.6.19 LiquidCrystalDisplayController(LCD)

Table3-21.LiquidCrystalDisplayController(LCD) TerminalFunctions PIN No. SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB EMA_D[15]/UHPI_HD[15]/LCD_D [15]/GP0[15] M16 I/O IPD EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14] N14 I/O IPD EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13] N16 I/O IPD EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12] P14 I/O IPD EMIFA, UHPI, GPIOEMA_D[11]/UHPI_HD[11]/LCD_D[11 ]/GP0[11] P16 I/O IPD EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10] R14 I/O IPD LCD databus. EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9] T14 I/O IPD EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8] N12 I/O IPD EMA_A[0]/LCD_D[7]/GP1[0] T9 I/O IPD EMIFA, GPIO EMA_A[3]/LCD_D[6]/GP1[3] N9 I/O IPD EMIFA, UHPI,EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13] P8 I/O IPU GPIO EMA_BA[0]/LCD_D[4]/GP1[14] R8 I/O IPU EMA_A[4]/LCD_D[3]/GP1[4] T10 I/O IPD EMA_A[5]/LCD_D[2]/GP1[5] R10 I/O IPD LCD databus. EMA_A[6]/LCD_D[1]/GP1[6] P10 I/O IPD EMA_A[7]/LCD_D[0]/GP1[7] N10 I/O IPD EMIFA, GPIOEMA_A[8]/LCD_PCLK /GP1[8] T11 O IPU LCD pixelclock. EMA_A[9]/LCD_HSYNC /GP1[9] R11 O IPU LCD horizontalsync. EMA_A[10]/LCD_VSYNC /GP1[10] N8 O IPU LCD verticalsync. LCD AC biasenableEMA_A[11]/LCD_AC_ENB_CS /GP1[11] P11 O IPU chipselect. EMA_A[12]/LCD_MCLK /GP1[12] N11 O IPU LCD memory clock. (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thethesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor,IPU = InternalPullupresistor

3.6.20 Reserved and No Connect

Table3-22.Reserved and No Connect TerminalFunctions PIN No. SIGNAL NAME TYPE (1) DESCRIPTION ZKB RSV1 F7 PWR Reserved.(Leaveunconnected,do not connecttopower orground.) Reserved.Forproperdeviceoperation,thispinmust be tieddirectlytoRSV2 B1 PWR CV DD . NC F3 - No Connect(leaveunconnected) NC H4 - No Connect(leaveunconnected) (1) PWR = Supplyvoltage.

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3.6.21 Supply and Ground

Table3-23.Supply and Ground TerminalFunctions PIN No. SIGNAL NAME TYPE (1) DESCRIPTION ZKB F6,G6,G7, G10, G11, H7, H10, H11, J6,CVDD (Coresupply) PWR 1.2-VcoresupplyvoltagepinsJ7,J10,J11, J12,K6,K7, K10,K11,L6 RVDD (InternalRAM supply) H6, H12 PWR 1.2Vinternalram supplyvoltagepins B16,E5,E8, E9,E12,F5, F11,F12,G5, DVDD (I/Osupply) G12, K5,K12, PWR 3.3-VI/Osupplyvoltagepins. L5,L11,L12, M5, M8, M9, M12, R1, R16 A1,A2,A15, A16, B2, E6,E7,E10, E11, F8,F9,F10, G8, G9, H8, H9,VSS (Ground) GND Ground pins.J8,J9, K8,K9, L7,L8,L9, L10, M6, M7, M10, M11, T1,T2,T15, T16 (1) PWR = Supplyvoltage,GND -Ground. Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 33 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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4 Device Configuration

4.1 Boot Modes

Thisdevicesupportsa varietyofbootmodes throughan internalROM bootloader.Thisdevicedoes not supportdedicatedhardware boot modes; therefore,allboot modes utilizethe internalROM. The input statesoftheBOOT pinsaresampled and latchedintotheBOOTCFG register,whichispartofthesystem configuration(SYSCFG) module,when deviceresetisdeasserted.Boot mode selectionisdeterminedby thevaluesoftheBOOT pins The followingbootmodes aresupported:

NAND Flashboot – 8-bitNAND
NOR Flashboot – NOR Directboot(8-bitor16-bit) – NOR Legacy boot(8-bitor16-bit) – NOR AIS boot(8-bitor16-bit)
HPI Boot
I2C0 /I2C1 Boot – EEPROM (MasterMode) – ExternalHost(SlaveMode)
SPI0 /SPI1 Boot – SerialFlash(MasterMode) – SERIAL EEPROM (MasterMode) – ExternalHost(SlaveMode)
UART0 /UART1 /UART2 Boot – ExternalHost

4.2 SYSCFG Module

The followingsystemlevelfeaturesofthechiparecontrolledby theSYSCFG peripheral:

ReadableDevice,Die,and ChipRevisionID
ControlofPinMultiplexing
Priorityofbus accessesdifferentbus mastersinthesystem
Captureatpower on resetthechipBOOT[15:0]pinvaluesand make them availabletosoftware
Specialcase settingsforperipherals: – LockingofPLL controllersettings – DefaultburstsizesforEDMA3 TC0 and TC1 – SelectionofthesourcefortheeCAP module inputcapture(includingon chipsources) – McASP AMUTEIN selectionand clearingofAMUTE statusforthethreeMcASP peripherals – Controlofthereferenceclocksourceand otherside-bandsignalsforbothoftheintegratedUSB PHYs – ClocksourceselectionforEMIFA and EMIFB
Selectsthesourceofemulationsuspend signalofperipheralssupportingthisfunction. SincetheSYSCFG peripheralcontrolsglobaloperationofthedevice,itsregistersare protectedagainst erroneousaccessesby severalmechanisms:
A specialkey sequence must be writtento KICK0, KICK1 registersbeforeany otherregistersare writeable.
Additionally,many registersare accessibleonlyby a host(ARM) when itisoperatinginitsprivileged mode. (ex.fromthekernel,butnotfromuserspace code).

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table4-1.System Configuration(SYSCFG) Module RegisterAccess BYTE ADDRESS ACRONYM REGISTER DESCRIPTION ACCESS 0x01C1 4000 REVID RevisionIdentificationRegister — 0x01C14008 DIEIDR0 DeviceIdentificationRegister0 — 0x01C1 400C DIEIDR1 DeviceIdentificationRegister1 — 0x01C1 4010 DIEIDR2 DeviceIdentificationRegister2 — 0x01C1 4014 DIEIDR3 DeviceIdentificationRegister3 — 0x01C1 4018 DEVIDR0 DeviceIdentificationRegister0 — 0x01C1 4020 BOOTCFG BootConfigurationRegister Privilegedmode 0x01C1 4038 KICK0R Kick0 Register Privilegedmode 0x01C1 403C KICK1R Kick1 Register Privilegedmode 0x01C1 4040 HOST0CFG Host0 ConfigurationRegister — 0x01C1 4044 HOST1CFG Host1 ConfigurationRegister — 0x01C1 40E0 IRAWSTAT InterruptRaw Status/SetRegister Privilegedmode 0x01C1 40E4 IENSTAT InterruptEnableStatus/ClearRegister Privilegedmode 0x01C1 40E8 IENSET InterruptEnableRegister Privilegedmode 0x01C1 40EC IENCLR InterruptEnableClearRegister Privilegedmode 0x01C1 40F0 EOI End ofInterruptRegister Privilegedmode 0x01C1 40F4 FLTADDRR FaultAddressRegister Privilegedmode 0x01C1 40F8 FLTSTAT FaultStatusRegister — 0x01C1 4110 MSTPRI0 MasterPriority0 Register Privilegedmode 0x01C1 4114 MSTPRI1 MasterPriority1 Register Privilegedmode 0x01C1 4118 MSTPRI2 MasterPriority2 Register Privilegedmode 0x01C1 4120 PINMUX0 PinMultiplexingControl0 Register Privilegedmode 0x01C1 4124 PINMUX1 PinMultiplexingControl1 Register Privilegedmode 0x01C1 4128 PINMUX2 PinMultiplexingControl2 Register Privilegedmode 0x01C1 412C PINMUX3 PinMultiplexingControl3 Register Privilegedmode 0x01C1 4130 PINMUX4 PinMultiplexingControl4 Register Privilegedmode 0x01C1 4134 PINMUX5 PinMultiplexingControl5 Register Privilegedmode 0x01C1 4138 PINMUX6 PinMultiplexingControl6 Register Privilegedmode 0x01C1 413C PINMUX7 PinMultiplexingControl7 Register Privilegedmode 0x01C1 4140 PINMUX8 PinMultiplexingControl8 Register Privilegedmode 0x01C1 4144 PINMUX9 PinMultiplexingControl9 Register Privilegedmode 0x01C1 4148 PINMUX10 PinMultiplexingControl10 Register Privilegedmode 0x01C1 414C PINMUX11 PinMultiplexingControl11 Register Privilegedmode 0x01C1 4150 PINMUX12 PinMultiplexingControl12 Register Privilegedmode 0x01C1 4154 PINMUX13 PinMultiplexingControl13 Register Privilegedmode 0x01C1 4158 PINMUX14 PinMultiplexingControl14 Register Privilegedmode 0x01C1 415C PINMUX15 PinMultiplexingControl15 Register Privilegedmode 0x01C1 4160 PINMUX16 PinMultiplexingControl16 Register Privilegedmode 0x01C1 4164 PINMUX17 PinMultiplexingControl17 Register Privilegedmode 0x01C1 4168 PINMUX18 PinMultiplexingControl18 Register Privilegedmode 0x01C1 416C PINMUX19 PinMultiplexingControl19 Register Privilegedmode 0x01C1 4170 SUSPSRC Suspend SourceRegister Privilegedmode 0x01C1 4174 - Reserved — 0x01C1 4178 - Reserved — 0x01C1 417C CFGCHIP0 ChipConfiguration0 Register Privilegedmode 0x01C1 4180 CFGCHIP1 ChipConfiguration1 Register Privilegedmode 0x01C1 4184 CFGCHIP2 ChipConfiguration2 Register Privilegedmode Copyright© 2010,Texas InstrumentsIncorporated DeviceConfiguration 35 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table4-1.System Configuration(SYSCFG) Module RegisterAccess (continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION ACCESS 0x01C1 4188 CFGCHIP3 ChipConfiguration3 Register Privilegedmode 0x01C1 418C CFGCHIP4 ChipConfiguration4 Register Privilegedmode

4.3 Pullup/PulldownResistors

Properboard designshouldensurethatinputpinstothedevicealwaysbe ata validlogicleveland not floating.Thismay be achievedviapullup/pulldownresistors.The devicefeaturesinternalpullup(IPU)and internalpulldown(IPD)resistorson most pinstoeliminatetheneed,unlessotherwisenoted,forexternal pullup/pulldownresistors. An externalpullup/pulldownresistorneeds tobe used inthefollowingsituations:

Boot and ConfigurationPins:Ifthe pin is both routedout and 3-stated(notdriven),an external pullup/pulldownresistorisstronglyrecommended, even iftheIPU/IPDmatches thedesiredvalue/state.
Other Input Pins: If the IPU/IPD does not match the desired value/state,use an external pullup/pulldownresistortopullthesignaltotheoppositerail. For the boot and configurationpins,iftheyare both routedout and 3-stated(notdriven),itisstrongly recommended that an external pullup/pulldownresistorbe implemented. Although, internal pullup/pulldownresistorsexiston these pins and they may match the desiredconfigurationvalue, providingexternalconnectivitycan helpensurethatvalidlogiclevelsarelatchedon thesedevicebootand configurationpins.In addition,applyingexternalpullup/pulldownresistorson the boot and configuration pinsadds conveniencetotheuserindebuggingand flexibilityinswitchingoperatingmodes. Tipsforchoosingan externalpullup/pulldownresistor:
Considerthetotalamount ofcurrentthatmay pass throughthepulluporpulldownresistor.Make sure toincludetheleakagecurrentsofallthedevicesconnectedtothenet,as wellas any internalpullupor pulldownresistors.
Decidea targetvalueforthenet.For a pulldownresistor,thisshouldbe below thelowestVIL levelof allinputsconnectedtothenet.For a pullupresistor,thisshouldbe above thehighestVIH levelofall inputson thenet.A reasonablechoicewould be totargettheVOL orVOH levelsforthelogicfamilyof thelimitingdevice;which,by definition,have margintotheVIL and VIH levels.
Selecta pullup/pulldownresistorwiththelargestpossiblevalue;but,whichcan stillensurethatthenet willreachthetargetpulledvaluewhen maximum currentfromalldeviceson thenetisflowingthrough the resistor.The currentto be consideredincludesleakage currentplus,any otherinternaland externalpullup/pulldownresistorson thenet.
For bidirectionalnets,thereisan additionalconsiderationwhich setsa lowerlimiton the resistance valueoftheexternalresistor.Verifythattheresistanceissmallenough thattheweakestoutputbuffer can drivethenettotheoppositelogiclevel(includingmargin).
Remember toincludetoleranceswhen selectingtheresistorvalue.
Forpullupresistors,alsoremember toincludetoleranceson theIO supplyrail.
For most systems,a 1-kΩ resistorcan be used to oppose the IPU/IPD whilemeeting the above criteria.Usersshouldconfirmthisresistorvalueiscorrectfortheirspecificapplication.
For most systems,a 20-kΩ resistorcan be used to compliment the IPU/IPD on the boot and configurationpinswhilemeetingtheabove criteria.Users shouldconfirmthisresistorvalueiscorrect fortheirspecificapplication.
For more detailedinformationon inputcurrent(II),and thelow-/high-levelinputvoltages(VIL and VIH) forthedevice,see Section5.2,Recommended OperatingConditions.
For theinternalpullup/pulldownresistorsforalldevicepins,see theperipheral/system-specificterminal functionstable.

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5 Device OperatingConditions

5.1 AbsoluteMaximum RatingsOver OperatingJunctionTemperature Range

(UnlessOtherwiseNoted) (1) Core -0.5V to1.4V (CVDD, RVDD, RTC_CVDD, PLL0_VDDA ,USB0_VDDA12 (2)) (3) I/O,1.8V -0.5V to2 VSupplyvoltageranges (USB0_VDDA18 ,USB1_VDDA18) (3) I/O,3.3V -0.5V to3.8V (DVDD, USB0_VDDA33 ,USB1_VDDA33) (3) VII/O,1.2V -0.3V toCVDD + 0.3V (OSCIN ,RTC_XI) VII/O,3.3V -0.3VtoDVDD + 0.3V (SteadyState) VII/O,3.3V DVDD + 20%Inputvoltageranges (Transient) up to20% ofSignal Period VII/O,USB 5V TolerantPins: 5.25V(4) (USB0_DM, USB0_DP ,USB0_ID, USB1_DM, USB1_DP) VII/O,USB0 VBUS 5.50V(4) VO I/O,3.3V -0.5V toDVDD + 0.3V (SteadyState) Outputvoltageranges VO I/O,3.3V 20% ofDVDD forup to (TransientOvershoot/Undershoot) 20% ofthesignalperiod InputorOutputVoltages0.3Vabove orbelowtheirrespectivepower ±20mA Clamp Current rails.Limitclamp currentthatflowsthroughtheI/O'sinternaldiode protectioncells. Storagetemperaturerange,Tstg (default) -55°C to150°C Commercial(default) 0°C to90°C OperatingJunctionTemperatureranges, Industrial(D version) -40°C to90°CTJ Extended(A version) -40°C to105°C Automotive(Tversion) -40°C to125°C (1) Stressesbeyond thoselistedunder"absolutemaximum ratings"may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder"recommended operating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) Thispinisan internalLDO outputand connectedvia0.22µF capacitortoVSS (3) AllvoltagevaluesarewithrespecttoVSS, PLL0_VSSA, OSCVSS ,RTC_VSS (4) Up toa max of24 hours. Copyright© 2010,Texas InstrumentsIncorporated DeviceOperatingConditions 37 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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5.2 Recommended OperatingConditions

RVDD SupplyVoltage,InternalRAM 1.14 1.2 1.32 V Supplyvoltage,I/O,1.8V 1.71 1.8 1.89 V(USB0_VDDA18, USB1_VDDA18) DVDD Supplyvoltage,I/O,3.3V 3.15 3.3 3.45 V(DVDD, USB0_VDDA33 ,USB1_VDDA33) SupplygroundVSS 0 0 0 V(VSS,PLL0_VSSA, OSCVSS (1),RTC_VSS (1)) High-levelinputvoltage,I/O,3.3V 2 V VIH (2) High-levelinputvoltage,RTC_XI 0.7*RTC_CVDD V High-levelinputvoltage,OSCIN 0.7*CVDD Low-levelinputvoltage,I/O,3.3V 0.8 V VIL (2) Low-levelinputvoltage,RTC_XI 0.3*RTC_CVDD V Low-levelinputvoltage,OSCIN 0.3*CVDD VHYS InputHysteresis 160 mV USB USB0_VBUS 4.75 5 5.25 V Transitiontime,10%-90%, AllInputs(unlessotherwisespecifiedintt 0.25P (3) nstheelectricaldatasections) 375 (1.2V)Commercial(default) 0 MHz456 (1.3V) FSYSCLK6 ARM OperatingFrequency(SYSCLK6) 375 (1.2V)Industrial(D suffix) 0 MHz456(1.3V) Extended(A suffix) 0 375(1.2V) MHz Automotive(Tsuffix) 0 300 (1.2V) MHz (1) When an externalcrystalisused,oscillator(OSC_VSS ,RTC_VSS) groundmust be keptseparatefromothergroundsand connected directlytothecrystalloadcapacitorground.These pinsareshortedtoVSS on thedeviceitselfand shouldnotbe connectedtoVSS on thecircuitboard.Ifa crystalisnotused and theclockinputisdrivendirectly,thentheoscillatorVSS may be connectedtoboardground. (2) These I/Ospecificationsdo notapplytoUSB I/Os.USB0 I/OsadheretoUSB2.0 specification.USB1 I/OsadheretoUSB1.1 specification. (3) P = theperiodoftheappliedsignal.Maintainingtransitiontimesas fastas possibleisrecommended toimprovenoiseimmunityon input signals.

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5.3 ElectricalCharacteristicsOver Recommended Ranges ofSupply Voltageand

OperatingJunctionTemperature (UnlessOtherwiseNoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Low/fullspeed: 2.8 USB0_VDDA33 VUSB0_DM and USB0_DP VOH Highspeed: 360 440 mVUSB_DM and USB_DP Low/fullspeed: 2.8 USB1_VDDA33 VUSB1_DM and USB1_DP DVDD= 3.15V,IOH = -4mA 2.4 V High-leveloutputvoltage(3.3VI/O) DVDD= 3.15V,IOH = 100 mA 2.95 V Low/fullspeed: 0.0 0.3 VUSB_DM and USB_DP Highspeed: -10 10 mVVOL USB_DM and USB_DP DVDD= 3.15V,IOL = 4mA 0.4 V Low-leveloutputvoltage(3.3VI/O) DVDD= 3.15V,IOL = -100mA 0.2 V VI= VSS toDVDD withoutopposing ±35 mAinternalresistor VI = VSS toDVDD withopposing 30 -200 mAinternalpullupresistor(2) II (1) Inputcurrent VI = VSS toDVDD withopposing -50 300 mAinternalpulldownresistor(2) VI = VSS toUSB1_VDDA33 - ±40 mAUSB1_DM and USB1_DP IOH High-leveloutputcurrent Allperipherals -4 mA IOL Low-leveloutputcurrent Allperipherals 4 mA IOZ (3) I/OOff-stateoutputcurrent VO = VDD orVSS; Internalpulldisabled ±35 mA LVCMOS signals 3 pF C I Inputcapacitance OSCIN and RTC_XI 2 pF C O Outputcapacitance LVCMOS signals 3 pF (1) IIappliestoinput-onlypinsand bi-directionalpins.Forinput-onlypins,IIindicatestheinputleakagecurrent.Forbi-directionalpins,II indicatestheinputleakagecurrentand off-state(Hi-Z)outputleakagecurrent. (2) Appliesonlytopinswithan internalpullup(IPU)orpulldown(IPD)resistor. (3) IOZ appliestooutput-onlypins,indicatingoff-state(Hi-Z)outputleakagecurrent. Copyright© 2010,Texas InstrumentsIncorporated DeviceOperatingConditions 39 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION Transmission□Line 4.0□pF 1.85□pF Z0□=□50 Ω (see□note) Tester Pin□Electronics Data Sheet□Timing□Reference□Point Output Under Test 42 Ω 3.5□nH Device□Pin (see□note) Vref Vref =□VIL MAX□(or□VOL MAX) Vref =□VIH MIN□(or□VOH MIN) AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

6 PeripheralInformationand ElectricalSpecifications

6.1 Parameter Information

6.1.1 Parameter InformationDevice-SpecificInformation

A. The data sheet providestimingat the devicepin.For outputtiminganalysis,the testerpin electronicsand its transmissionlineeffectsmust be takenintoaccount.A transmissionlinewitha delayof2 ns orlongercan be used to producethedesiredtransmissionlineeffect.The transmissionlineisintendedas a loadonly.Itisnotnecessaryto add orsubtractthetransmissionlinedelay(2ns orlonger)fromthedatasheettimings. Inputrequirementsinthisdatasheetaretestedwithan inputslewrateof< 4 Voltspernanosecond (4V/ns)atthe devicepinand theinputsignalsaredrivenbetween 0V and theappropriateIO supplyrailforthesignal. Figure6-1.TestLoad CircuitforAC Timing Measurements The loadcapacitancevaluestatedisonlyforcharacterizationand measurement ofAC timingsignals.This loadcapacitancevaluedoes notindicatethemaximum loadthedeviceiscapableofdriving.

6.1.1.1 SignalTransitionLevels

Allinputand outputtimingparametersarereferencedtoVrefforboth"0"and "1"logiclevels.For3.3V I/O, Figure6-2.Inputand Output VoltageReferenceLevelsforAC Timing Measurements Allriseand falltransitiontimingparametersare referencedto VIL MAX and VIH MIN forinputclocks, VOL MAX and VOH MIN foroutputclocks. Figure6-3.Rise and FallTransitionTime VoltageReferenceLevels

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6.2 Recommended Clock and ControlSignalTransitionBehavior

Allclocksand controlsignalsmust transitionbetween VIH and VIL (orbetween VIL and VIH)ina monotonic manner. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 41 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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6.3 Power Supplies

6.3.1 Power-on Sequence

The deviceshouldbe powered-oninthefollowingorder:

1)RTC (RTC_CVDD) may be powered froman externaldevice(suchas a battery)priortoallother suppliesbeingappliedorpowered-upatthesame timeas CVDD. IftheRTC isnotused,RTC_CVDD shouldbe connectedtoCVDD. RTC_CVDD shouldnotbe leftunpowered whileCVDD ispowered.
2a)CVDD corelogicsupply
2b)Other1.2Vlogicsupplies(RVDD, PLL0_VDDA). Groups 2a)and 2b)may be powered up together or2a)firstfollowedby 2b).
3)All1.8VIO supplies(USB0_VDDA18 ,USB1_VDDA18).
4)AlldigitalIO and analog3.3VPHY supplies(DVDD, USB0_VDDA33 ,USB1_VDDA33). USB0_VDDA33 and USB1_VDDA33 arenotrequiredifboth USB0 and USB1 arenotused)and may be leftunconnected.USB0_VDDA33 isnotrequiredifUSB0 isnotused and may be leftunconnected. Thereisno specificrequiredvoltageramp rateforany ofthesupplies. RESET must be maintainedactiveuntilallpower supplieshave reachedtheirnominalvalues. Note: Futuredevicesmay supporthigherperformanceat a highercore logicvoltage(CVDD). Iffuture migrationisdesired,thecurrentdesignshouldprovideseparatesuppliesfor2a)and 2b).Ifnot,then2a) and 2b)may be providedby a singlesupply.

6.3.2 Power-offSequence

The power suppliescan be powered-offinany orderas longas the3.3V suppliesdo notremainpowered withtheothersuppliesunpowered. 6.4 Unused USB0 (USB2.0)and USB1 (USB1.1)Pin Configurations Ifone or both USB modules on the deviceare not used, then some of the power suppliesto those modules may not be required.Thiscan eliminatethe requirementfora 1.8V power supplyto the USB modules.The requiredpinconfigurationsforunused USB modules areshown below. Table6-1.Unused USB0 and USB1 Pin Configurations SIGNAL NAME Configuration Configuration (When USB0 and USB1 arenot used) (When USB0 isused and USB1 isnot used) USB0_DM No connect Use as USB0 function USB0_DP No connect Use as USB0 function USB0_VDDA33 No connect 3.3V USB0_VDDA18 No connect 1.8V USB0_ID No connect Use as USB0 function USB0_VBUS No connect Use as USB0 function USB0_DRVVBUS/GP4[15] No connectoruse as alternatefunction Use as USB0 oralternatefunction USB0_VDDA12 No connect InternalUSB0 PHY outputconnectedtoan externalfiltercapacitor USB1_DM No connect Ground USB1_DP No connect Ground USB1_VDDA33 No connect No connect USB1_VDDA18 No connect No connect AHCLKX0/AHCLKX2/USB_REFCLKIN/ No connectoruse as alternatefunction Use as USB0 oralternatefunction GP2[11]

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6.5 Reset

6.5.1 Power-On Reset (POR)

A power-onreset(POR) isrequiredtoplacethedeviceina known good stateafterpower-up.Power-On Reset isinitiatedby bringingRESET and TRST low atthesame time.POR setsallofthedeviceinternal logicto itsdefaultstate.Allpinsare 3-statedwiththe exceptionof RESETOUT which remainsactive throughthe resetsequence.RESETOUT isan outputforuse by othercontrollersin the system that indicatesthedeviceiscurrentlyinreset. WhilebothTRST and RESET need tobe assertedupon power up,onlyRESET needs tobe releasedfor thedevicetobootproperly.TRST may be assertedindefinitelyfornormaloperation,keepingtheJTAG portinterfaceand device'semulationlogicintheresetstate. TRST onlyneeds tobe releasedwhen itisnecessarytouse a JTAG controllertodebug thedeviceor exercisethe device'sboundary scan functionality.Note:TRST issynchronousand must be clockedby TCK; otherwise,theboundaryscan logicmay notrespondas expectedafterTRST isasserted. RESET must be releasedonlyin orderforboundary-scanJTAG to read the variantfieldof IDCODE correctly.Other boundary-scaninstructionswork correctlyindependentof currentstateof RESET. For maximum reliability,thedeviceincludesan internalpulldownon theTRST pintoensurethatTRST will always be assertedupon power up and the device'sinternalemulationlogicwillalways be properly initialized. JTAG controllersfrom Texas InstrumentsactivelydriveTRST high.However, some third-partyJTAG controllersmay notdriveTRST highbutexpecttheuse ofa pullupresistoron TRST. When usingthistype of JTAG controller,assertTRST to intializethe deviceafterpowerup and externallydriveTRST high beforeattemptingany emulationorboundaryscan operations. RTCK ismaintainedactivethrougha POR. A summary oftheeffectsofPower-On Resetisgivenbelow:

Allinternallogic(includingemulationlogicand thePLL logic)isresettoitsdefaultstate
Internalmemory isnotmaintainedthrougha POR
RESETOUT goes active
Alldevicepinsgo toa high-impedancestate
The RTC peripheralisnotresetduringa POR. A softwaresequence isrequiredtoresettheRTC. CAUTION: A watchdog resettriggersa POR. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 43 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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6.5.2 Warm Reset

A warm resetprovidesa limitedresettothedevice.Warm Reset isinitiatedby bringingonlyRESET low (TRST ismaintainedhighthrougha warm reset).Warm resetsetscertainportionsofthedevicetotheir defaultstatewhileleavingothersunaltered.Allpinsare3-statedwiththeexceptionofRESETOUT which remainsactivethroughtheresetsequence.RESETOUT isan outputforuse by othercontrollersinthe systemthatindicatesthedeviceiscurrentlyinreset. Duringemulation,theemulatorwillmaintainTRST highand hence onlywarm reset(notPOR) isavailable duringemulationdebug and development. RTCK ismaintainedactivethrougha warm reset. A summary oftheeffectsofWarm Resetisgivenbelow:

Allinternallogic(exceptfortheemulationlogicand thePLL logic)isresettoitsdefaultstate
Internalmemory ismaintainedthrougha warm reset
RESETOUT goes active
Alldevicepinsgo toa high-impedancestate
The RTC peripheralisnot resetduringa warm reset.A softwaresequence isrequiredto resetthe RTC.

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ADVANCE□INFORMATION OSCIN RESET RESETOUT Boot□Pins Config Power Supplies Ramping Power□Supplies□Stable Clock□Source□Stable 2 3 TRST OSCIN TRST RESET RESETOUT Boot□Pins Config Power□Supplies□Stable 2 3 Driven□or□Hi-Z AM1707 www.ti.com SPRS637 –FEBRUARY 2010

6.5.3 Reset ElectricalData Timings

Table6-2assumes testingovertherecommended operatingconditions. Table6-2.Reset Timing Requirements ((1),(2)) No. PARAMETER MIN MAX UNIT 1 tw(RSTL) Pulsewidth,RESET/ TRST low 100 ns 2 tsu(BPV-RSTH) Setuptime,bootpinsvalidbeforeRESET/ TRST high 20 ns 3 th(RSTH-BPV) Holdtime,bootpinsvalidafterRESET/ TRST high 20 ns td(RSTH- RESET hightoRESETOUT high;Warm reset 4096 4 cycles(3) RESETOUTH) RESET hightoRESETOUT high;Power-onReset 6192 (1) RESETOUT ismultiplexedwithotherpinfunctions.See theTerminalFunctionstable,Table3-3fordetails. (2) Forpower-onreset(POR),theresettimingsinthistablerefertoRESET and TRST together.Forwarm reset,theresettimingsinthis tablerefertoRESET only(TRST isheldhigh). (3) OSCIN cycles. Figure6-4.Power-On Reset (RESET and TRST active)Timing Figure6-5.Warm Reset (RESET active,TRST high)Timing Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 45 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION OSCOUT OSCIN OSCVSS Clock□Input to□PLL AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

6.6 CrystalOscillatoror ExternalClock Input

The deviceincludestwo choicesto providean externalclockinput,which isfed to the on-chipPLL to generatehigh-frequencysystem clocks.These optionsare illustratedinFigure6-6 and Figure6-7. For inputclockfrequenciesbetween 12 and 20 MHz, a crystalwith80 ohm max ESR isrecommended. For inputclockfrequenciesbetween 20 and 30 MHz, a crystalwith60 ohm max ESR isrecommended. TypicalC1, C2 valuesare10-20pF.

Figure6-6illustratestheoptionthatuses on-chip1.2Voscillatorwithexternalcrystalcircuit.
Figure6-7illustratestheoptionthatuses an external1.2Vclockinput. Figure6-6.On-Chip 1.2VOscillator Table6-3.OscillatorTiming Requirements PARAMETER MIN MAX UNIT fosc Oscillatorfrequencyrange(OSCIN/OSCOUT) 12 30 MHz

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ADVANCE□INFORMATION OSCOUT OSCIN OSCVSS Clock Input to□PLL NC AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Figure6-7.External1.2VClock Source Table6-4.OSCIN Timing Requirements No. PARAMETER MIN MAX UNIT fOSCIN OSCIN frequencyrange(OSCIN) 12 50 MHz tc(OSCIN) Cycletime,externalclockdrivenon OSCIN 20 ns tw(OSCINH) Pulsewidthhigh,externalclockon OSCIN 0.4tc(OSCIN) ns tw(OSCINL) Pulsewidthlow,externalclockon OSCIN 0.4tc(OSCIN) ns tt(OSCIN) Transitiontime,OSCIN 0.25P (1) ns tj(OSCIN) Periodjitter,OSCIN 0.02P ns (1) P = theperiodoftheappliedsignal.Maintainingtransitiontimesas fastas possibleisrecommended toimprovenoiseimmunityon input signals. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 47 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION 0.1 µF 0.01 µF 50R1.14V□-□1.32V 50RVSS PLL0_VDDA PLL0_VSSA Ferrite□Bead:□Murata□BLM31PG500SN1L or□Equivalent AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

6.7 Clock PLLs

The devicehas one PLL controllerthatprovidesclockto differentpartsof the system.PLL0 provides clocks(thoughvariousdividers)tomost ofthecomponents ofthedevice. The PLL controllerprovidesthefollowing:

Glitch-FreeTransitions(onchangingclocksettings)
Domain ClocksAlignment
ClockGating
PLL power down The variousclockoutputsgivenby thecontrollerareas follows:
Domain Clocks:SYSCLK [1:n]
AuxiliaryClockfromreferenceclocksource:AUXCLK Variousdividersthatcan be used areas follows:
Post-PLLDivider:POSTDIV
SYSCLK Divider:D1, ¼ ,Dn Variousothercontrolssupportedareas follows:
PLL MultiplierControl:PLLM
SoftwareprogrammablePLL Bypass:PLLEN

6.7.1 PLL Device-SpecificInformation

The PLL requiressome externalfilteringcomponents to reduce power supply noise as shown in Figure6-8. Figure6-8.PLL ExternalFilteringComponents The inputto the PLL iseitherfrom the on-chiposcillator(OSCIN pin)or from an externalclockon the CLKIN pin.The PLL outputsseven clocksthathave programmable divideroptions.Figure6-9 illustrates thePLL Topology. The PLL isdisabledby defaultaftera devicereset.Itmust be configuredby softwareaccordingtothe allowableoperatingconditionslistedinTable6-5 beforeenablingtheprocessortorun from thePLL by settingPLLEN = 1.

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ADVANCE□INFORMATION PLLDIV1 (/1) SYSCLK1 PLLDIV2 (/2) SYSCLK2 PLLDIV3 (/3) SYSCLK3 PLLDIV4 (/4) SYSCLK4 PLLDIV5 (/3) SYSCLK5 PLLDIV6 (/1) SYSCLK6 PLLDIV7 (/6) SYSCLK7 DIV4.5 1

0 EMIFA

CFGCHIP3[EMA_CLKSRC] DIV4.5 EMIFB Internal Clock Source CFGCHIP3[EMB_CLKSRC] Pre-Div PLLM CLKMODE PLLEN AUXCLK PLL Post-Div OBSCLK Pin Square Wave Crystal OSCIN DIV4.5OSCDIV14h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh SYSCLK1 SYSCLK2 SYSCLK3 SYSCLK4 SYSCLK5 SYSCLK6 SYSCLK7 OCSEL[OCSRC] AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Figure6-9.PLL Topology Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 49 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION

2000 NMax PLL Lock Time =

m where N = Pre-Divider Ratio M = PLL Multiplier AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-5.Allowed PLL OperatingConditions DefaultNo. PARAMETER MIN MAX UNITValue PLLRST: Assertiontimeduring1 N/A 1000 N/A nsinitialization Lock time:The timethattheapplication has towaitforthePLL toacquirelocks OSCIN2 N/A N/AbeforesettingPLLEN, afterchanging cycles PREDIV, PLLM, orOSCIN (1)

3 PREDIV /1 /1 /32 ns

PLL inputfrequency4 12 50 MHz(PLLREF)

5 PLL multipliervalues(PLLM) (1) x20 x4 x32

6 PLL outputfrequency.(PLLOUT ) N/A 400 600(2) MHz

7 POSTDIV /1 /2(2) /32 ns

(1) The multipliervaluesmust be chosen such thatthePLL outputfrequency(atPLLOUT) isbetween 400 and 600 MHz, butthefrequency goingintotheSYSCLK dividers(afterthepostdivider)cannotexceed 300 MHz. The PostDividerand SYSCLK dividervaluesmust be chosen such thattheCPU clocksdo notexceed 300 MHz. (2) PLL postdivider/2 must be used.The /4.5clockpathcan be used togeneratean EMIF clockfromtheundivided(i.e.600 MHz) PLL outputclock.

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6.7.2 Device Clock Generation

PLL0 iscontrolledby PLL Controller0.The PLLC0 manages theclockratios,alignment,and gatingforthe system clockstothechip.The PLLC isresponsibleforcontrollingallmodes ofthePLL throughsoftware, intermsofpre-divisionoftheclockinputs,multiplyfactorwithinthePLL, and post-divisionforeach ofthe chip-levelclocksfrom thePLL output.The PLLC alsocontrolsresetpropagationthroughthechip,clock alignment,and testpoints.

6.7.3 PLL Controller0 Registers

Table6-6.PLL Controller0 Registers BYTE ACRONYM REGISTER DESCRIPTIONADDRESS 0x01C1 1000 REVID RevisionIdentificationRegister 0x01C1 10E4 RSTYPE ResetType StatusRegister 0x01C1 1100 PLLCTL PLL ControlRegister 0x01C1 1104 OCSEL OBSCLK SelectRegister 0x01C1 1110 PLLM PLL MultiplierControlRegister 0x01C1 1114 PREDIV PLL Pre-DividerControlRegister 0x01C1 1118 PLLDIV1 PLL ControllerDivider1 Register 0x01C1 111C PLLDIV2 PLL ControllerDivider2 Register 0x01C1 1120 PLLDIV3 PLL ControllerDivider3 Register 0x01C1 1124 OSCDIV OscillatorDivider1 Register(OBSCLK) 0x01C1 1128 POSTDIV PLL Post-DividerControlRegister 0x01C1 1138 PLLCMD PLL ControllerCommand Register 0x01C1 113C PLLSTAT PLL ControllerStatusRegister 0x01C1 1140 ALNCTL PLL ControllerClockAlignControlRegister 0x01C1 1144 DCHANGE PLLDIV RatioChange StatusRegister 0x01C1 1148 CKEN ClockEnableControlRegister 0x01C1 114C CKSTAT ClockStatusRegister 0x01C1 1150 SYSTAT SYSCLK StatusRegister 0x01C1 1160 PLLDIV4 PLL ControllerDivider4 Register 0x01C1 1164 PLLDIV5 PLL ControllerDivider5 Register 0x01C1 1168 PLLDIV6 PLL ControllerDivider6 Register 0x01C1 116C PLLDIV7 PLL ControllerDivider7 Register Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 51 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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6.8 Interrupts

6.8.1 ARM CPU Interrupts

The ARM9 CPU coresupports2 directinterrupts:FIQ and IRQ. The ARM InterruptControllerextendsthe number ofinterruptsto100,and providesfeatureslikeprogrammablemasking,priority,hardwarenesting support,and interruptvectorgeneration.

6.8.1.1 ARM InterruptController(AINTC)InterruptSignalHierarchy

The ARM Interruptcontrollerorganizesinterruptsintothefollowinghierarchy:

PeripheralInterruptRequests – IndividualInterruptSourcesfromPeripherals
100 System Interrupts – One ormore PeripheralInterruptRequestsarecombined (fixedconfiguration)togeneratea System Interrupt. – Afterprioritization,theAINTC willprovidean interruptvectorbased uniquetoeach System Interrupt
32 InterruptChannels – Each System Interruptismapped toone ofthe32 InterruptChannels – ChannelNumber determinesthefirstlevelofprioritization,Channel0 ishighestpriorityand 31 lowest. – Ifmore thanone systeminterruptismapped toa channel,prioritywithinthechannelisdetermined by systeminterruptnumber (0highestpriority)
HostInterrupts(FIQand IRQ) – InterruptChannels0 and 1 generatetheARM FIQ interrupt – InterruptChannels2 through31 GeneratetheARM IRQ interrupt
Debug Interrupts – Two Debug Interruptsaresupportedand can be used totriggereventsinthedebug subsystem – Sourcescan be selectedfromany oftheSystem InterruptsorHostInterrupts

6.8.1.2 AINTC Hardware VectorGeneration

The AINTC alsogeneratesan interruptvectorinhardwareforbothIRQ and FIQ hostinterrupts.Thismay be used to accelerateinterruptdispatch.A unique vectoris generatedforeach of the 100 system interrupts.The vectoriscomputed inhardwareas: VECTOR = BASE + (SYSTEM INTERRUPT NUMBER × SIZE) Where BASE and SIZE are programmable. The computed vectoris a 32-bitaddress which may dispatchedtousinga singleinstructionoftypeLDR PC, [PC,#-<offset_12>]attheFIQ and IRQ vector locations(0xFFFF0018 and 0xFFFF001C respectively).

6.8.1.3 AINTC Hardware InterruptNestingSupport

Interruptnestingoccurs when an interruptserviceroutinere-enablesinterrupts,to allowthe CPU to interruptthe ISR ifa higherpriorityevent occurs.The AINTC provideshardware supportto facilitate interruptnesting.Itsupportsboth globaland per host interrupt(FIQ and IRQ in thiscase) automatic nesting.Ifenabled,theAINTC willautomaticallyupdatean internalnestingregisterthattemporarilymasks interruptsatand below thepriorityofthecurrentinterruptchannel.Then iftheISR re-enablesinterrupts; onlyhigherprioritychannelswillbe abletointerruptit.The nestinglevelisrestoredby theISR by writing tothenestinglevelregisteron completion.Supportfornestingcan be enabled/disabledby software,with theoptionofautomaticnestingon a globalorperhostinterruptbasis;ormanual nesting.

6.8.1.4 AINTC System InterruptAssignments on thedevice

System InterruptassignmentsforthedevicearelistedinTable6-7

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-7.AINTC System InterruptAssignments System Interrupt InterruptName Source

0 COMMTX ARM

1 COMMRX ARM

2 NINT ARM

3 PRU_EVTOUT0 PRUSS Interrupt

4 PRU_EVTOUT1 PRUSS Interrupt

5 PRU_EVTOUT2 PRUSS Interrupt

6 PRU_EVTOUT3 PRUSS Interrupt

7 PRU_EVTOUT4 PRUSS Interrupt

8 PRU_EVTOUT5 PRUSS Interrupt

9 PRU_EVTOUT6 PRUSS Interrupt

10 PRU_EVTOUT7 PRUSS Interrupt

11 EDMA3_CC0_CCINT EDMA CC Region0

12 EDMA3_CC0_CCERRINT EDMA CC

13 EDMA3_TC0_TCERRINT EDMA TC0

14 EMIFA_INT EMIFA

15 IIC0_INT I2C0

16 MMCSD_INT0 MMCSD

17 MMCSD_INT1 MMCSD

18 PSC0_ALLINT PSC0

19 RTC_IRQS[1:0] RTC

20 SPI0_INT SPI0

21 T64P0_TINT12 Timer64P0 Interrupt12

22 T64P0_TINT34 Timer64P0 Interrupt34

23 T64P1_TINT12 Timer64P1 Interrupt12

24 T64P1_TINT34 Timer64P1 Interrupt34

25 UART0_INT UART0

27 PROTERR SYSCFG ProtectionShared Interrupt

32 EDMA3_TC1_TCERRINT EDMA TC1

33 EMAC_C0RXTHRESH EMAC -Core 0 ReceiveThresholdInterrupt

34 EMAC_C0RX EMAC -Core 0 ReceiveInterrupt

35 EMAC_C0TX EMAC -Core 0 TransmitInterrupt

36 EMAC_C0MISC EMAC -Core 0 MiscellaneousInterrupt

37 EMAC_C1RXTHRESH EMAC -Core 1 ReceiveThresholdInterrupt

38 EMAC_C1RX EMAC -Core 1 ReceiveInterrupt

39 EMAC_C1TX EMAC -Core 1 TransmitInterrupt

40 EMAC_C1MISC EMAC -Core 1 MiscellaneousInterrupt

41 EMIF_MEMERR EMIFB

42 GPIO_B0INT GPIO Bank 0 Interrupt

43 GPIO_B1INT GPIO Bank 1 Interrupt

44 GPIO_B2INT GPIO Bank 2 Interrupt

45 GPIO_B3INT GPIO Bank 3 Interrupt

46 GPIO_B4INT GPIO Bank 4 Interrupt

47 GPIO_B5INT GPIO Bank 5 Interrupt

48 GPIO_B6INT GPIO Bank 6 Interrupt

49 GPIO_B7INT GPIO Bank 7 Interrupt

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-7.AINTC System InterruptAssignments (continued) System Interrupt InterruptName Source 50 - Reserved

51 IIC1_INT I2C1

52 LCDC_INT LCD Controller

53 UART_INT1 UART1

54 MCASP_INT McASP0, 1,2 Combined RX /TX Interrupts

55 PSC1_ALLINT PSC1

56 SPI1_INT SPI1

57 UHPI_ARMINT HPI Arm Interrupt

58 USB0_INT USB0 Interrupt

59 USB1_HCINT USB1 OHCI HostControllerInterrupt

60 USB1_RWAKEUP USB1 Remote Wakeup Interrupt

61 UART2_INT UART2

63 EHRPWM0 HiResTimer/PWM0 Interrupt

64 EHRPWM0TZ HiResTimer/PWM0 TripZone Interrupt

65 EHRPWM1 HiResTimer/PWM1 Interrupt

66 EHRPWM1TZ HiResTimer/PWM1 TripZone Interrupt

67 EHRPWM2 HiResTimer/PWM2 Interrupt

68 EHRPWM2TZ HiResTimer/PWM2 TripZone Interrupt

69 ECAP0 ECAP0

70 ECAP1 ECAP1

71 ECAP2 ECAP2

72 EQEP0 EQEP0

73 EQEP1 EQEP1

74 T64P0_CMPINT0 Timer64P0 -Compare 0

75 T64P0_CMPINT1 Timer64P0 -Compare 1

76 T64P0_CMPINT2 Timer64P0 -Compare 2

77 T64P0_CMPINT3 Timer64P0 -Compare 3

78 T64P0_CMPINT4 Timer64P0 -Compare 4

79 T64P0_CMPINT5 Timer64P0 -Compare 5

80 T64P0_CMPINT6 Timer64P0 -Compare 6

81 T64P0_CMPINT7 Timer64P0 -Compare 7

82 T64P1_CMPINT0 Timer64P1 -Compare 0

83 T64P1_CMPINT1 Timer64P1 -Compare 1

84 T64P1_CMPINT2 Timer64P1 -Compare 2

85 T64P1_CMPINT3 Timer64P1 -Compare 3

86 T64P1_CMPINT4 Timer64P1 -Compare 4

87 T64P1_CMPINT5 Timer64P1 -Compare 5

88 T64P1_CMPINT6 Timer64P1 -Compare 6

89 T64P1_CMPINT7 Timer64P1 -Compare 7

90 ARMCLKSTOPREQ PSC0

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6.8.1.5 AINTC Memory Map

Table6-8.AINTC Memory Map BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0xFFFE E000 REV RevisionRegister 0xFFFE E004 CR ControlRegister 0xFFFE E008 -0xFFFE E00F - Reserved 0xFFFE E010 GER GlobalEnableRegister 0xFFFE E014 -0xFFFE E01B - Reserved 0xFFFE E01C GNLR GlobalNestingLevelRegister 0xFFFE E020 SISR System InterruptStatusIndexedSetRegister 0xFFFE E024 SICR System InterruptStatusIndexedClearRegister 0xFFFE E028 EISR System InterruptEnableIndexedSetRegister 0xFFFE E02C EICR System InterruptEnableIndexedClearRegister 0xFFFE E030 - Reserved 0xFFFE E034 HIEISR HostInterruptEnableIndexedSetRegister 0xFFFE E038 HIEICR HostInterruptEnableIndexedClearRegister 0xFFFE E03C -0xFFFE E04F - Reserved 0xFFFE E050 VBR VectorBase Register 0xFFFE E054 VSR VectorSizeRegister 0xFFFE E058 VNR VectorNullRegister 0xFFFE E05C -0xFFFE E07F - Reserved 0xFFFE E080 GPIR GlobalPrioritizedIndexRegister 0xFFFE E084 GPVR GlobalPrioritizedVectorRegister 0xFFFE E088 -0xFFFE E1FF - Reserved 0xFFFE E200 -0xFFFE E20B SRSR[1] -SRSR[3] System InterruptStatusRaw /SetRegisters 0xFFFE E20C- 0xFFFE E27F - Reserved 0xFFFE E280 -0xFFFE E28B SECR[1] -SECR[3] System InterruptStatusEnabled/ClearRegisters 0xFFFE E28C -0xFFFE E2FF - Reserved 0xFFFE E300 -0xFFFE E30B ESR[1]-ESR[3] System InterruptEnableSetRegisters 0xFFFE E30C -0xFFFE E37F - Reserved 0xFFFE E380 -0xFFFE E38B ECR[1] -ECR[3] System InterruptEnableClearRegisters 0xFFFE E38C -0xFFFE E3FF - Reserved 0xFFFE E400 -0xFFFE E458 CMR[0] -CMR[22] ChannelMap Registers(ByteWide Registers) 0xFFFE E459 -0xFFFE E7FF - Reserved 0xFFFE E800 -0xFFFE E81F - Reserved 0xFFFE E820 -0xFFFE E8FF - Reserved 0xFFFE E900 -0xFFFE E904 HIPIR[1]-HIPIR[2] HostInterruptPrioritizedIndexRegisters 0xFFFE E908 -0xFFFE EEFF - Reserved 0xFFFE EF00 -0xFFFE EF04 - Reserved 0xFFFE EF08 -0xFFFE F0FF - Reserved 0xFFFE F100 -0xFFFE F104 HINLR[1]-HINLR[2] HostInterruptNestingLevelRegisters 0xFFFE F108 -0xFFFE F4FF - Reserved 0xFFFE F500 HIER[0] HostInterruptEnableRegister 0xFFFE F504 -0xFFFE F5FF - Reserved 0xFFFE F600 HIPVR[1]-HIPVR[2] HostInterruptPrioritizedVectorRegisters 0xFFFE F608 -0xFFFE FFFF - Reserved Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 55 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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6.9 General-PurposeInput/Output(GPIO)

The GPIO peripheralprovidesgeneral-purposepinsthatcan be configuredas eitherinputsor outputs. When configuredas an output,a writetoan internalregistercan controlthestatedrivenon theoutputpin. When configuredas an input,the stateof the inputisdetectableby readingthe stateof an internal register.In addition,the GPIO peripheralcan produce CPU interruptsand EDMA events in different interrupt/eventgenerationmodes. The GPIO peripheralprovidesgenericconnectionstoexternaldevices. The GPIO pinsaregroupedintobanks of16 pinsperbank (i.e.,bank 0 consistsofGPIO [0:15]). The deviceGPIO peripheralsupportsthefollowing:

Up to128 Pinson ZKB package configurableas GPIO
ExternalInterruptand DMA requestCapability – EveryGPIO pinmay be configuredtogeneratean interruptrequeston detectionofrisingand/or fallingedges on thepin. – The interruptrequestswithineach bank arecombined (logicalor)tocreateeightuniquebank level interruptrequests. – The bank levelinterruptserviceroutinemay polltheINTSTATx registerforitsbank todetermine whichpin(s)have triggeredtheinterrupt. – GPIO Banks 0,1,2,3,4,5,6,and 7 InterruptsassignedtoARM INTC InterruptRequests42,43, 44,45,46,47,48,and 49 respectively – Additionally,GPIO Banks 0,1,2,3,4,and 5 InterruptsassignedtoEDMA events6,7,22,23,28, and 29 respectively.
Set/clearfunctionality:Firmware writes1 to correspondingbitposition(s)to set or to clearGPIO signal(s).ThisallowsmultiplefirmwareprocessestotoggleGPIO outputsignalswithoutcriticalsection protection(disableinterrupts,program GPIO, re-enableinterrupts,to preventcontextswitchingto antherprocessduringGPIO programming).
SeparateInput/Outputregisters
Outputregisterinadditiontoset/clearso that,ifpreferredby firmware,some GPIO outputsignalscan be toggledby directwritetotheoutputregister(s).
Outputregister,when read,reflectsoutputdrivestatus.This,inadditiontotheinputregisterreflecting pinstatusand open-drainI/Ocell,allowswiredlogicbe implemented. The memory map fortheGPIO registersisshown inTable6-9.

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6.9.1 GPIO RegisterDescription(s)

Table6-9.GPIO Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E2 6000 REV PeripheralRevisionRegister 0x01E2 6004 RESERVED Reserved 0x01E2 6008 BINTEN GPIO InterruptPer-BankEnableRegister GPIO BANKS 0 AND 1 0x01E2 6010 DIR01 GPIO Banks 0 and 1 DirectionRegister 0x01E2 6014 OUT_DATA01 GPIO Banks 0 and 1 OutputData Register 0x01E2 6018 SET_DATA01 GPIO Banks 0 and 1 SetData Register 0x01E2 601C CLR_DATA01 GPIO Banks 0 and 1 ClearData Register 0x01E2 6020 IN_DATA01 GPIO Banks 0 and 1 InputData Register 0x01E2 6024 SET_RIS_TRIG01 GPIO Banks 0 and 1 SetRisingEdge InterruptRegister 0x01E2 6028 CLR_RIS_TRIG01 GPIO Banks 0 and 1 ClearRisingEdge InterruptRegister 0x01E2 602C SET_FAL_TRIG01 GPIO Banks 0 and 1 SetFallingEdge InterruptRegister 0x01E2 6030 CLR_FAL_TRIG01 GPIO Banks 0 and 1 ClearFallingEdge InterruptRegister 0x01E2 6034 INTSTAT01 GPIO Banks 0 and 1 InterruptStatusRegister GPIO BANKS 2 AND 3 0x01E2 6038 DIR23 GPIO Banks 2 and 3 DirectionRegister 0x01E2 603C OUT_DATA23 GPIO Banks 2 and 3 OutputData Register 0x01E2 6040 SET_DATA23 GPIO Banks 2 and 3 SetData Register 0x01E2 6044 CLR_DATA23 GPIO Banks 2 and 3 ClearData Register 0x01E2 6048 IN_DATA23 GPIO Banks 2 and 3 InputData Register 0x01E2 604C SET_RIS_TRIG23 GPIO Banks 2 and 3 SetRisingEdge InterruptRegister 0x01E2 6050 CLR_RIS_TRIG23 GPIO Banks 2 and 3 ClearRisingEdge InterruptRegister 0x01E2 6054 SET_FAL_TRIG23 GPIO Banks 2 and 3 SetFallingEdge InterruptRegister 0x01E2 6058 CLR_FAL_TRIG23 GPIO Banks 2 and 3 ClearFallingEdge InterruptRegister 0x01E2 605C INTSTAT23 GPIO Banks 2 and 3 InterruptStatusRegister GPIO BANKS 4 AND 5 0x01E2 6060 DIR45 GPIO Banks 4 and 5 DirectionRegister 0x01E2 6064 OUT_DATA45 GPIO Banks 4 and 5 OutputData Register 0x01E2 6068 SET_DATA45 GPIO Banks 4 and 5 SetData Register 0x01E2 606C CLR_DATA45 GPIO Banks 4 and 5 ClearData Register 0x01E2 6070 IN_DATA45 GPIO Banks 4 and 5 InputData Register 0x01E2 6074 SET_RIS_TRIG45 GPIO Banks 4 and 5 SetRisingEdge InterruptRegister 0x01E2 6078 CLR_RIS_TRIG45 GPIO Banks 4 and 5 ClearRisingEdge InterruptRegister 0x01E2 607C SET_FAL_TRIG45 GPIO Banks 4 and 5 SetFallingEdge InterruptRegister 0x01E2 6080 CLR_FAL_TRIG45 GPIO Banks 4 and 5 ClearFallingEdge InterruptRegister 0x01E2 6084 INTSTAT45 GPIO Banks 4 and 5 InterruptStatusRegister GPIO BANKS 6 AND 7 0x01E2 6088 DIR67 GPIO Banks 6 and 7 DirectionRegister 0x01E2 608C OUT_DATA67 GPIO Banks 6 and 7 OutputData Register 0x01E2 6090 SET_DATA67 GPIO Banks 6 and 7 SetData Register 0x01E2 6094 CLR_DATA67 GPIO Banks 6 and 7 ClearData Register 0x01E2 6098 IN_DATA67 GPIO Banks 6 and 7 InputData Register 0x01E2 609C SET_RIS_TRIG67 GPIO Banks 6 and 7 SetRisingEdge InterruptRegister 0x01E2 60A0 CLR_RIS_TRIG67 GPIO Banks 6 and 7 ClearRisingEdge InterruptRegister 0x01E2 60A4 SET_FAL_TRIG67 GPIO Banks 6 and 7 SetFallingEdge InterruptRegister Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 57 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION GP [ ]□as□inputn m GP [ ]□as□outputn m GP [ ]□as□inputn m AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-9.GPIO Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E2 60A8 CLR_FAL_TRIG67 GPIO Banks 6 and 7 ClearFallingEdge InterruptRegister 0x01E2 60AC INTSTAT67 GPIO Banks 6 and 7 InterruptStatusRegister

6.9.2 GPIO PeripheralInput/OutputElectricalData/Timing

Table6-10.Timing Requirements forGPIO Inputs(1)(seeFigure6-10) No. PARAMETER MIN MAX UNIT 1 tw(GPIH) Pulseduration,GP n[m]as inputhigh 2C (1)(2) ns 2 tw(GPIL) Pulseduration,GP n[m]as inputlow 2C (1)(2) ns (1) The pulsewidthgivenissufficienttogeneratea CPU interruptoran EDMA event.However,ifa userwantstohave thedevice recognizetheGPIx changes throughsoftwarepollingoftheGPIO register,theGPIx durationmust be extendedtoallowthedevice enough timetoaccesstheGPIO registerthroughtheinternalbus. (2) C=SYSCLK4 periodinns. Table6-11.SwitchingCharacteristicsOver Recommended OperatingConditionsforGPIO Outputs (seeFigure6-10) No. PARAMETER MIN MAX UNIT 3 tw(GPOH) Pulseduration,GP n[m]as outputhigh 2C (1)(2) ns 4 tw(GPOL) Pulseduration,GP n[m]as outputlow 2C (1)(2) ns (1) Thisparametervalueshouldnotbe used as a maximum performancespecification.Actualperformanceofback-to-backaccessesofthe GPIO isdependentupon internalbus activity. (2) C=SYSCLK4 periodinns. Figure6-10.GPIO PortTiming

6.9.3 GPIO PeripheralExternalInterruptsElectricalData/Timing

Table6-12.Timing Requirements forExternalInterrupts(1)(seeFigure6-11) No. PARAMETER MIN MAX UNIT 1 tw(ILOW) Widthoftheexternalinterruptpulselow 2C (1)(2) ns 2 tw(IHIGH) Widthoftheexternalinterruptpulsehigh 2C (1)(2) ns (1) The pulsewidthgivenissufficienttogeneratean interruptoran EDMA event.However,ifa userwantstohave devicerecognizethe GPIO changes throughsoftwarepollingoftheGPIO register,theGPIO durationmust be extendedtoallowthedeviceenough timeto accesstheGPIO registerthroughtheinternalbus. (2) C=SYSCLK4 periodinns. Figure6-11.GPIO ExternalInterruptTiming

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6.10 EDMA

Table6-13isthelistofEDMA3 Channel ContollerRegistersand Table6-14isthelistofEDMA3 Transfer Controllerregisters. Table6-13.EDMA3 Channel Controller(EDMA3CC) Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01C0 0000 PID PeripheralIdentificationRegister 0x01C0 0004 CCCFG EDMA3CC ConfigurationRegister GLOBAL REGISTERS 0x01C0 0200 QCHMAP0 QDMA Channel0 Mapping Register 0x01C0 0204 QCHMAP1 QDMA Channel1 Mapping Register 0x01C0 0208 QCHMAP2 QDMA Channel2 Mapping Register 0x01C0 020C QCHMAP3 QDMA Channel3 Mapping Register 0x01C0 0210 QCHMAP4 QDMA Channel4 Mapping Register 0x01C0 0214 QCHMAP5 QDMA Channel5 Mapping Register 0x01C0 0218 QCHMAP6 QDMA Channel6 Mapping Register 0x01C0 021C QCHMAP7 QDMA Channel7 Mapping Register 0x01C0 0240 DMAQNUM0 DMA ChannelQueue Number Register0 0x01C0 0244 DMAQNUM1 DMA ChannelQueue Number Register1 0x01C0 0248 DMAQNUM2 DMA ChannelQueue Number Register2 0x01C0 024C DMAQNUM3 DMA ChannelQueue Number Register3 0x01C0 0260 QDMAQNUM QDMA ChannelQueue Number Register 0x01C0 0284 QUEPRI Queue PriorityRegister(1) 0x01C0 0300 EMR EventMissedRegister 0x01C0 0308 EMCR EventMissedClearRegister 0x01C0 0310 QEMR QDMA EventMissedRegister 0x01C0 0314 QEMCR QDMA EventMissedClearRegister 0x01C0 0318 CCERR EDMA3CC ErrorRegister 0x01C0 031C CCERRCLR EDMA3CC ErrorClearRegister 0x01C0 0320 EEVAL ErrorEvaluateRegister 0x01C0 0340 DRAE0 DMA RegionAccess EnableRegisterforRegion0 0x01C0 0348 DRAE1 DMA RegionAccess EnableRegisterforRegion1 0x01C0 0350 DRAE2 DMA RegionAccess EnableRegisterforRegion2 0x01C0 0358 DRAE3 DMA RegionAccess EnableRegisterforRegion3 0x01C0 0380 QRAE0 QDMA RegionAccess EnableRegisterforRegion0 0x01C0 0384 QRAE1 QDMA RegionAccess EnableRegisterforRegion1 0x01C0 0388 QRAE2 QDMA RegionAccess EnableRegisterforRegion2 0x01C0 038C QRAE3 QDMA RegionAccess EnableRegisterforRegion3 0x01C0 0400 -0x01C0 043C Q0E0-Q0E15 EventQueue EntryRegistersQ0E0-Q0E15 0x01C0 0440 -0x01C0 047C Q1E0-Q1E15 EventQueue EntryRegistersQ1E0-Q1E15 0x01C0 0600 QSTAT0 Queue 0 StatusRegister 0x01C0 0604 QSTAT1 Queue 1 StatusRegister 0x01C0 0620 QWMTHRA Queue Watermark ThresholdA Register 0x01C0 0640 CCSTAT EDMA3CC StatusRegister GLOBAL CHANNEL REGISTERS 0x01C0 1000 ER EventRegister 0x01C0 1008 ECR EventClearRegister (1) On previousarchitectures,theEDMA3TC prioritywas controlledby thequeue priorityregister(QUEPRI) intheEDMA3CC memory-map. However forthisdevice,theprioritycontrolforthetransfercontrollersiscontrolledby thechip-levelregistersinthe System ConfigurationModule.You shoulduse thechip-levelregistersand notQUEPRI toconfiguretheTC priority. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 59 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-13.EDMA3 Channel Controller(EDMA3CC) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01C0 1010 ESR EventSetRegister 0x01C0 1018 CER ChainedEventRegister 0x01C0 1020 EER EventEnableRegister 0x01C0 1028 EECR EventEnableClearRegister 0x01C0 1030 EESR EventEnableSetRegister 0x01C0 1038 SER SecondaryEventRegister 0x01C0 1040 SECR SecondaryEventClearRegister 0x01C0 1050 IER InterruptEnableRegister 0x01C0 1058 IECR InterruptEnableClearRegister 0x01C0 1060 IESR InterruptEnableSetRegister 0x01C0 1068 IPR InterruptPendingRegister 0x01C0 1070 ICR InterruptClearRegister 0x01C0 1078 IEVAL InterruptEvaluateRegister 0x01C0 1080 QER QDMA EventRegister 0x01C0 1084 QEER QDMA EventEnableRegister 0x01C0 1088 QEECR QDMA EventEnableClearRegister 0x01C0 108C QEESR QDMA EventEnableSetRegister 0x01C0 1090 QSER QDMA SecondaryEventRegister 0x01C0 1094 QSECR QDMA SecondaryEventClearRegister SHADOW REGION 0 CHANNEL REGISTERS 0x01C0 2000 ER EventRegister 0x01C0 2008 ECR EventClearRegister 0x01C0 2010 ESR EventSetRegister 0x01C0 2018 CER ChainedEventRegister 0x01C0 2020 EER EventEnableRegister 0x01C0 2028 EECR EventEnableClearRegister 0x01C0 2030 EESR EventEnableSetRegister 0x01C0 2038 SER SecondaryEventRegister 0x01C0 2040 SECR SecondaryEventClearRegister 0x01C0 2050 IER InterruptEnableRegister 0x01C0 2058 IECR InterruptEnableClearRegister 0x01C0 2060 IESR InterruptEnableSetRegister 0x01C0 2068 IPR InterruptPendingRegister 0x01C0 2070 ICR InterruptClearRegister 0x01C0 2078 IEVAL InterruptEvaluateRegister 0x01C0 2080 QER QDMA EventRegister 0x01C0 2084 QEER QDMA EventEnableRegister 0x01C0 2088 QEECR QDMA EventEnableClearRegister 0x01C0 208C QEESR QDMA EventEnableSetRegister 0x01C0 2090 QSER QDMA SecondaryEventRegister 0x01C0 2094 QSECR QDMA SecondaryEventClearRegister SHADOW REGION 1 CHANNEL REGISTERS 0x01C0 2200 ER EventRegister 0x01C0 2208 ECR EventClearRegister 0x01C0 2210 ESR EventSetRegister 0x01C0 2218 CER ChainedEventRegister 0x01C0 2220 EER EventEnableRegister

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-13.EDMA3 Channel Controller(EDMA3CC) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01C0 2228 EECR EventEnableClearRegister 0x01C0 2230 EESR EventEnableSetRegister 0x01C0 2238 SER SecondaryEventRegister 0x01C0 2240 SECR SecondaryEventClearRegister 0x01C0 2250 IER InterruptEnableRegister 0x01C0 2258 IECR InterruptEnableClearRegister 0x01C0 2260 IESR InterruptEnableSetRegister 0x01C0 2268 IPR InterruptPendingRegister 0x01C0 2270 ICR InterruptClearRegister 0x01C0 2278 IEVAL InterruptEvaluateRegister 0x01C0 2280 QER QDMA EventRegister 0x01C0 2284 QEER QDMA EventEnableRegister 0x01C0 2288 QEECR QDMA EventEnableClearRegister 0x01C0 228C QEESR QDMA EventEnableSetRegister 0x01C0 2290 QSER QDMA SecondaryEventRegister 0x01C0 2294 QSECR QDMA SecondaryEventClearRegister 0x01C0 4000 -0x01C0 4FFF — ParameterRAM (PaRAM) Table6-14.EDMA3 TransferController(EDMA3TC) Registers TRANSFER TRANSFER CONTROLLER 0 CONTROLLER 1 ACRONYM REGISTER DESCRIPTION BYTE ADDRESS BYTE ADDRESS 0x01C0 8000 0x01C0 8400 PID PeripheralIdentificationRegister 0x01C0 8004 0x01C0 8404 TCCFG EDMA3TC ConfigurationRegister 0x01C0 8100 0x01C0 8500 TCSTAT EDMA3TC ChannelStatusRegister 0x01C0 8120 0x01C0 8520 ERRSTAT ErrorStatusRegister 0x01C0 8124 0x01C0 8524 ERREN ErrorEnableRegister 0x01C0 8128 0x01C0 8528 ERRCLR ErrorClearRegister 0x01C0 812C 0x01C0 852C ERRDET ErrorDetailsRegister 0x01C0 8130 0x01C0 8530 ERRCMD ErrorInterruptCommand Register 0x01C0 8140 0x01C0 8540 RDRATE Read Command Rate Register 0x01C0 8240 0x01C0 8640 SAOPT SourceActiveOptionsRegister 0x01C0 8244 0x01C0 8644 SASRC SourceActiveSourceAddressRegister 0x01C0 8248 0x01C0 8648 SACNT SourceActiveCount Register 0x01C0 824C 0x01C0 864C SADST SourceActiveDestinationAddressRegister 0x01C0 8250 0x01C0 8650 SABIDX SourceActiveB-IndexRegister 0x01C0 8254 0x01C0 8654 SAMPPRXY SourceActiveMemory ProtectionProxyRegister 0x01C0 8258 0x01C0 8658 SACNTRLD SourceActiveCount ReloadRegister 0x01C0 825C 0x01C0 865C SASRCBREF SourceActiveSourceAddressB-ReferenceRegister 0x01C0 8260 0x01C0 8660 SADSTBREF SourceActiveDestinationAddressB-ReferenceRegister 0x01C0 8280 0x01C0 8680 DFCNTRLD DestinationFIFO SetCount ReloadRegister 0x01C0 8284 0x01C0 8684 DFSRCBREF DestinationFIFO SetSourceAddressB-ReferenceRegister 0x01C0 8288 0x01C0 8688 DFDSTBREF DestinationFIFO SetDestinationAddressB-ReferenceRegister 0x01C0 8300 0x01C0 8700 DFOPT0 DestinationFIFO OptionsRegister0 0x01C0 8304 0x01C0 8704 DFSRC0 DestinationFIFO SourceAddressRegister0 0x01C0 8308 0x01C0 8708 DFCNT0 DestinationFIFO Count Register0 0x01C0 830C 0x01C0 870C DFDST0 DestinationFIFO DestinationAddressRegister0 Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 61 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-14.EDMA3 TransferController(EDMA3TC) Registers(continued) TRANSFER TRANSFER CONTROLLER 0 CONTROLLER 1 ACRONYM REGISTER DESCRIPTION BYTE ADDRESS BYTE ADDRESS 0x01C0 8310 0x01C0 8710 DFBIDX0 DestinationFIFO B-IndexRegister0 0x01C0 8314 0x01C0 8714 DFMPPRXY0 DestinationFIFO Memory ProtectionProxyRegister0 0x01C0 8340 0x01C0 8740 DFOPT1 DestinationFIFO OptionsRegister1 0x01C0 8344 0x01C0 8744 DFSRC1 DestinationFIFO SourceAddressRegister1 0x01C0 8348 0x01C0 8748 DFCNT1 DestinationFIFO Count Register1 0x01C0 834C 0x01C0 874C DFDST1 DestinationFIFO DestinationAddressRegister1 0x01C0 8350 0x01C0 8750 DFBIDX1 DestinationFIFO B-IndexRegister1 0x01C0 8354 0x01C0 8754 DFMPPRXY1 DestinationFIFO Memory ProtectionProxyRegister1 0x01C0 8380 0x01C0 8780 DFOPT2 DestinationFIFO OptionsRegister2 0x01C0 8384 0x01C0 8784 DFSRC2 DestinationFIFO SourceAddressRegister2 0x01C0 8388 0x01C0 8788 DFCNT2 DestinationFIFO Count Register2 0x01C0 838C 0x01C0 878C DFDST2 DestinationFIFO DestinationAddressRegister2 0x01C0 8390 0x01C0 8790 DFBIDX2 DestinationFIFO B-IndexRegister2 0x01C0 8394 0x01C0 8794 DFMPPRXY2 DestinationFIFO Memory ProtectionProxyRegister2 0x01C0 83C0 0x01C0 87C0 DFOPT3 DestinationFIFO OptionsRegister3 0x01C0 83C4 0x01C0 87C4 DFSRC3 DestinationFIFO SourceAddressRegister3 0x01C0 83C8 0x01C0 87C8 DFCNT3 DestinationFIFO Count Register3 0x01C0 83CC 0x01C0 87CC DFDST3 DestinationFIFO DestinationAddressRegister3 0x01C0 83D0 0x01C0 87D0 DFBIDX3 DestinationFIFO B-IndexRegister3 0x01C0 83D4 0x01C0 87D4 DFMPPRXY3 DestinationFIFO Memory ProtectionProxyRegister3 Table6-15shows an abbreviationofthesetofregisterswhichmake up theparametersetforeach of128 EDMA events.Each oftheparameterregistersetsconsistof8 32-bitword entries.Table6-16shows the parametersetentryregisterswithrelativememory addresslocationswithineach oftheparametersets. Table6-15.EDMA Parameter Set RAM BYTE ADDRESS DESCRIPTION 0x01C0 4000 -0x01C0 401F ParametersSet0 (832-bitwords) 0x01C0 4020 -0x01C0 403F ParametersSet1 (832-bitwords) 0x01C0 4040 -0x01C0 405F ParametersSet2 (832-bitwords) 0x01C0 4060 -0x01C0 407F ParametersSet3 (832-bitwords) 0x01C0 4080 -0x01C0 409F ParametersSet4 (832-bitwords) 0x01C0 40A0 -0x01C0 40BF ParametersSet5 (832-bitwords) 0x01C0 4FC0 -0x01C0 4FDF ParametersSet126 (832-bitwords) 0x01C0 4FE0 -0x01C0 4FFF ParametersSet127 (832-bitwords) Table6-16.Parameter Set Entries HEX OFFSET ADDRESS ACRONYM PARAMETER ENTRYWITHIN THE PARAMETER SET 0x0000 OPT Option 0x0004 SRC SourceAddress 0x0008 A_B_CNT A Count,B Count 0x000C DST DestinationAddress 0x0010 SRC_DST_BIDX SourceB Index,DestinationB Index 0x0014 LINK_BCNTRLD LinkAddress,B Count Reload

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-16.Parameter Set Entries(continued) HEX OFFSET ADDRESS ACRONYM PARAMETER ENTRYWITHIN THE PARAMETER SET 0x0018 SRC_DST_CIDX SourceC Index,DestinationC Index 0x001C CCNT C Count Table6-17.EDMA Events Event Event Name /Source Event Event Name /Source

0 McASP0 Receive 16 MMCSD Receive

1 McASP0 Transmit 17 MMCSD Transmit

2 McASP1 Receive 18 SPI1 Receive

3 McASP1 Transmit 19 SPI1 Transmit

4 McASP2 Receive 20 PRU_EVTOUT6

5 McASP2 Transmit 21 PRU_EVTOUT7

6 GPIO Bank 0 Interrupt 22 GPIO Bank 2 Interrupt

7 GPIO Bank 1 Interrupt 23 GPIO Bank 3 Interrupt

8 UART0 Receive 24 I2C0 Receive

9 UART0 Transmit 25 I2C0 Transmit

10 Timer64P0 EventOut 12 26 I2C1 Receive

11 Timer64P0 EventOut 34 27 I2C1 Transmit

12 UART1 Receive 28 GPIO Bank 4 Interrupt

13 UART1 Transmit 29 GPIO Bank 5 Interrupt

14 SPI0 Receive 30 UART2 Receive

15 SPI0 Transmit 31 UART2 Transmit

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6.11 ExternalMemory InterfaceA (EMIFA)

EMIFA isone of two externalmemory interfacessupportedon the device. Itisprimarilyintendedto supportasynchronousmemory types,such as NAND and NOR flashand AsynchronousSRAM. However theEMIFA alsoprovidesa secondaryinterfacetoSDRAM.

6.11.1 EMIFA Asynchronous Memory Support

EMIFA supportsasynchronous:

SRAM memories
NAND Flashmemories
NOR Flashmemories The EMIFA data bus widthisup to 16-bitson the ZKB package . The devicesupportsup to fifteen addresslinesand an externalwait/interruptinput.Up tofourasynchronouschipselectsaresupportedby EMIFA (EMA_CS[5:2]). Allfourchipselectsareavailableon theZKB package. Each chipselecthas thefollowingindividuallyprogrammableattributes:
Data Bus Width
Read cycletimings:setup,hold,strobe
Writecycletimings:setup,hold,strobe
Bus turnaroundtime
ExtendedWaitOptionWithProgrammable Timeout
SelectStrobeOption
NAND flashcontrollersupports1-bitand 4-bitECC calculationon blocksof512 bytes.

6.11.2 EMIFA Synchronous DRAM Memory Support

The deviceZKB package supports16-bitSDRAM in additionto the asynchronousmemories listedin Section6.11.1. Ithas a singleSDRAM chip select(EMA_CS[0]). SDRAM configurationsthatare supportedare:

One, Two, and FourBank SDRAM devices
DeviceswithEight,Nine,Ten,and ElevenColumn Address
CAS Latencyoftwo orthreeclockcycles
SixteenBitData Bus Width
3.3VLVCMOS Interface Additionally,theSDRAM interfaceofEMIFA supportsplacingtheSDRAM inSelfRefreshand Powerdown Modes. SelfRefreshmode allowstheSDRAM tobe putintoa lowpower statewhilestillretainingmemory contents.Powerdown mode achieveseven lowerpower,excepttheprocessormust periodicallywake the SDRAM up and issuerefreshesifdataretentionisrequired. Finally,note thatthe EMIFA does not supportMobileSDRAM devices.Table 6-18 below shows the supportedSDRAM configurationsforEMIFA.

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-18.EMIFA Supported SDRAM Configurations(1) SDRAM Memory MemoryNumber of EMIFB Data TotalMemory TotalMemoryData Bus Rows Columns Banks DensityMemories Bus Size (Mbits) (Mbytes)Width (Mbits) (bits) 1 16 13 8 1 32 4 32 1 16 13 8 2 64 8 64 1 16 13 8 4 128 16 128 1 16 13 9 1 64 8 64 1 16 13 9 2 128 16 128 1 16 13 9 4 256 32 256 1 16 13 10 1 128 16 128 1 16 13 10 2 256 32 256 1 16 13 10 4 512 64 512 1 16 13 11 1 256 32 256 1 16 13 11 2 512 64 512 1 16 13 11 4 1024 128 1024 2 16 13 8 1 32 4 16 2 16 13 8 2 64 8 32 2 16 13 8 4 128 16 64 2 16 13 9 1 64 8 32 2 16 13 9 2 128 16 64 2 16 13 9 4 256 32 128 2 16 13 10 1 128 16 64 2 16 13 10 2 256 32 128 2 16 13 10 4 512 64 256 2 16 13 11 1 256 32 128 2 16 13 11 2 512 64 256 2 16 13 11 4 1024 128 512 (1) The shaded cellsindicateconfigurationsthatarepossibleon theEMIFA interfacebutas ofthiswritingSDRAM memories capableof supportingthesedensitiesarenotavailableinthemarket.

6.11.3 EMIFA SDRAM Loading Limitations

EMIFA supportsSDRAM up to 100 MHz with up to two SDRAM or asynchronous memory loads. Additionalloadswilllimitthe SDRAM operationto lowerspeeds and the maximum speed shouldbe confirmedby boardsimulationusingIBISmodels.

6.11.4 EMIFA Connection Examples

Figure6-12illustratesan example ofhow SDRAM, NOR, and NAND flashdevicesmightbe connectedto EMIFA of the devicesimultaneously.The SDRAM chipselectmust be EMA_CS[0]. Note thatthe NOR flashisconnectedtoEMA_CS[2] and theNAND flashisconnectedtoEMA_CS[3] inthisexample.Note thatany typeofasynchronousmemory may be connectedtoEMA_CS[5:2]. The on-chipbootloadermakes some assumptionson whichchipselectthecontainsthebootimage,and thisdepends on thebootmode. For NOR bootmode; theon-chipbootloaderrequiresthattheimage be storedinNOR flashon EMA_CS[2]. For NAND bootmode, thebootloaderrequiresthatthebootimage is storedinNAND flashon EMA_CS[3]. Itisalwayspossibletohave theimage span multiplechipselects, butthismust be supportedby second stagebootcode storedintheexternalflash. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 65 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION EMA_CLK EMA_BA[1:0] EMA_CS[0] EMA_CAS EMA_RAS EMA_WE CLK CE WE EMIFA SDRAM 2M□x□16□x□4 BankEMA_SDCKE CAS RAS CKE BA[1:0] LDQM UDQM DQ[15:0] A[11:0] EMA_A[12:0] EMA_WE_DQM[0] EMA_WE_DQM[1] EMA_D[15:0] EMA_CS[2] EMA_CS[3] EMA_WAIT EMA_OE GPIO (6□Pins)RESET A[0] A[12:1] DQ[15:0] CE WE OE RESET A[18:13] RY/ YB NOR FLASH 512K□x□16 ALE CLE DQ[15:0] CE WE RE RB NAND FLASH 1Gb□x□16 EMA_BA[1] EMA_A[1] EMA_A[2] ... DVDD RESET AM1707 SPRS637 –FEBRUARY 2010 www.ti.com A likelyuse case withmore thanone EMIFA chipselectused forNAND flashisillustratedinFigure6-13. Thisfigureshows how two multiplaneNAND flashdeviceswithtwo chipselectseach wouldconnecttothe EMIFA. Inthiscase ifNAND isthebootmemory, thenthebootimage needs tobe storedintheNAND area selectedby EMA_CS[3]. Part of the applicationimage could spillover intothe NAND regions selectedby otherEMIFA chipselects;but would relyon the code storedin the EMA_CS[3] area to bootloadit. Figure6-12.Device Connection Diagram: SDRAM, NOR, NAND

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ADVANCE□INFORMATION EMA_A[1] EMA_A[2] EMA_D[7:0] EMA_CS[2] EMA_CS[3] EMA_WE EMA_OE ALE CLE DQ[7:0] CE1 CE2 WE RE R/ 1B R/ 2B EMIFA NAND FLASH x8, MultiPlane ALE CLE DQ[7:0] CE1 CE2 WE RE R/ 1B R/ 2B NAND FLASH x8, MultiPlane DVDD EMA_WAIT EMA_CS[4] EMA_CS[5] AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Figure6-13.EMIFA Connection Diagram: MultipleNAND FlashPlanes Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 67 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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6.11.5 ExternalMemory InterfaceA (EMIFA) Registers

Table6-19isa listoftheEMIF registers. Table6-19.ExternalMemory Interface(EMIFA) Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x6800 0000 MIDR Module ID Register 0x6800 0004 AWCC AsynchronousWaitCycleConfigurationRegister 0x6800 0008 SDCR SDRAM ConfigurationRegister 0x6800 000C SDRCR SDRAM RefreshControlRegister 0x6800 0010 CE2CFG Asynchronous1 ConfigurationRegister 0x6800 0014 CE3CFG Asynchronous2 ConfigurationRegister 0x6800 0018 CE4CFG Asynchronous3 ConfigurationRegister 0x6800 001C CE5CFG Asynchronous4 ConfigurationRegister 0x6800 0020 SDTIMR SDRAM TimingRegister 0x6800 003C SDSRETR SDRAM SelfRefreshExitTimingRegister 0x6800 0040 INTRAW EMIFA InterruptRaw Register 0x6800 0044 INTMSK EMIFA InterruptMask Register 0x6800 0048 INTMSKSET EMIFA InterruptMask SetRegister 0x6800 004C INTMSKCLR EMIFA InterruptMask ClearRegister 0x6800 0060 NANDFCR NAND FlashControlRegister 0x6800 0064 NANDFSR NAND FlashStatusRegister 0x6800 0070 NANDF1ECC NAND Flash1 ECC Register(CS2 Space) 0x6800 0074 NANDF2ECC NAND Flash2 ECC Register(CS3 Space) 0x6800 0078 NANDF3ECC NAND Flash3 ECC Register(CS4 Space) 0x6800 007C NANDF4ECC NAND Flash4 ECC Register(CS5 Space) 0x6800 00BC NAND4BITECCLOAD NAND Flash4-BitECC Load Register 0x6800 00C0 NAND4BITECC1 NAND Flash4-BitECC Register1 0x6800 00C4 NAND4BITECC2 NAND Flash4-BitECC Register2 0x6800 00C8 NAND4BITECC3 NAND Flash4-BitECC Register3 0x6800 00CC NAND4BITECC4 NAND Flash4-BitECC Register4 0x6800 00D0 NANDERRADD1 NAND Flash4-BitECC ErrorAddressRegister1 0x6800 00D4 NANDERRADD2 NAND Flash4-BitECC ErrorAddressRegister2 0x6800 00D8 NANDERRVAL1 NAND Flash4-BitECC ErrorValueRegister1 0x6800 00DC NANDERRVAL2 NAND Flash4-BitECC ErrorValueRegister2

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6.11.6 EMIFA ElectricalData/Timing

The followingassume testingoverrecommended operatingconditions. Table6-20.EMIFA SDRAM InterfaceTiming Requirements No. PARAMETER MIN MAX UNIT Inputsetuptime,readdatavalidon EMA_D[15:0]beforeEMA_CLK19 tsu(DV-CLKH) 1.3 nsrising Inputholdtime,readdatavalidon EMA_D[15:0]afterEMA_CLK20 th(CLKH-DIV) 1.5 nsrising Table6-21.EMIFA SDRAM InterfaceSwitchingCharacteristics No. PARAMETER MIN MAX UNIT 1 tc(CLK) Cycletime,EMIF clockEMA_CLK 10 ns 2 tw(CLK) Pulsewidth,EMIF clockEMA_CLK highorlow 3 ns 3 td(CLKH-CSV) Delaytime,EMA_CLK risingtoEMA_CS[0] valid 7 ns 4 toh(CLKH-CSIV) Outputholdtime,EMA_CLK risingtoEMA_CS[0] invalid 1 ns 5 td(CLKH-DQMV) Delaytime,EMA_CLK risingtoEMA_ WE_DQM[1:0] valid 7 ns 6 toh(CLKH-DQMIV) Outputholdtime,EMA_CLK risingtoEMA_ WE_DQM[1:0] invalid 1 ns Delaytime,EMA_CLK risingtoEMA_A[12:0]and EMA_BA[1:0]7 td(CLKH-AV) 7 nsvalid Outputholdtime,EMA_CLK risingtoEMA_A[12:0]and8 toh(CLKH-AIV) 1 nsEMA_BA[1:0] invalid 9 td(CLKH-DV) Delaytime,EMA_CLK risingtoEMA_D[15:0]valid 7 ns 10 toh(CLKH-DIV) Outputholdtime,EMA_CLK risingtoEMA_D[15:0]invalid 1 ns 11 td(CLKH-RASV) Delaytime,EMA_CLK risingtoEMA_RAS valid 7 ns 12 toh(CLKH-RASIV) Outputholdtime,EMA_CLK risingtoEMA_RAS invalid 1 ns 13 td(CLKH-CASV) Delaytime,EMA_CLK risingtoEMA_CAS valid 7 ns 14 toh(CLKH-CASIV) Outputholdtime,EMA_CLK risingtoEMA_CAS invalid 1 ns 15 td(CLKH-WEV) Delaytime,EMA_CLK risingtoEMA_WE valid 7 ns 16 toh(CLKH-WEIV) Outputholdtime,EMA_CLK risingtoEMA_WE invalid 1 ns 17 tdis(CLKH-DHZ) Delaytime,EMA_CLK risingtoEMA_D[15:0]3-stated 7 ns 18 tena(CLKH-DLZ) Outputholdtime,EMA_CLK risingtoEMA_D[15:0]driving 1 ns Table6-22.EMIFA Asynchronous Memory Timing Requirements(1) No. PARAMETER MIN NOM MAX UNIT READS and WRITES E tc(CLK) Cycletime,EMIFA module clock 10 ns Pulseduration,EM_WAIT assertionand2 tw(EM_WAIT) 2E nsdeassertion READS Setuptime,EM_D[15:0]validbeforeEM_OE12 tsu(EMDV-EMOEH) 3 nshigh 13 th(EMOEH-EMDIV) Holdtime,EM_D[15:0]validafterEM_OE high 0 ns SetupTime,EM_WAIT assertedbeforeend of14 tsu (EMOEL-EMWAIT) 4E+3 nsStrobePhase (2) WRITES (1) E = EMA_CLK periodorinns.EMA_CLK isselectedeitheras SYSCLK3 orthePLL outputclockdividedby 4.5.As an example,when SYSCLK3 isselectedand setto100MHz, E=10ns. (2) Setupbeforeend ofSTROBE phase (ifno extendedwaitstatesareinserted)by whichEM_WAIT must be assertedtoadd extended waitstates.Figure6-18and Figure6-19describeEMIF transactionsthatincludeextendedwaitstatesinsertedduringtheSTROBE phase.However,cyclesinsertedas partofthisextendedwaitperiodshouldnotbe counted;the4E requirementistothestartofwhere theHOLD phase wouldbeginiftherewere no extendedwaitcycles. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 69 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-22.EMIFA Asynchronous Memory Timing Requirements (1) (continued) No. PARAMETER MIN NOM MAX UNIT SetupTime,EM_WAIT assertedbeforeend of28 tsu (EMWEL-EMWAIT) 4E+3 nsStrobePhase(2) Table6-23.EMIFA Asynchronous Memory SwitchingCharacteristics(1)(2)(3) No. PARAMETER MIN NOM MAX UNIT READS and WRITES 1 td(TURNAROUND) Turnaroundtime (TA)*E-3 (TA)*E (TA)*E+ 3 ns READS (RS+RST+RH)*E (RS+RST+RH)*EEMIF readcycletime(EW = 0) (RS+RST+RH)*E ns-3 + 3 3 tc(EMRCYCLE) (RS+RST+RH+(E (RS+RST+RH+(EW (RS+RST+RH+(EMIF readcycletime(EW = 1) nsWC*16))*E -3 C*16))*E EWC*16))*E + 3 Outputsetuptime,EMA_CE[5:2] lowto (RS)*E-3 (RS)*E (RS)*E+3 nsEMA_OE low(SS = 0) 4 tsu(EMCEL-EMOEL) Outputsetuptime,EMA_CE[5:2] lowto -3 0 +3 nsEMA_OE low(SS = 1) Outputholdtime,EMA_OE highto (RH)*E-3 (RH)*E (RH)*E+ 3 nsEMA_CE[5:2] high(SS = 0) 5 th(EMOEH-EMCEH) Outputholdtime,EMA_OE highto -3 0 +3 nsEMA_CE[5:2] high(SS = 1) Outputsetuptime,EMA_BA[1:0] validto6 tsu(EMBAV-EMOEL) (RS)*E-3 (RS)*E (RS)*E+3 nsEMA_OE low Outputholdtime,EMA_OE highto7 th(EMOEH-EMBAIV) (RH)*E-3 (RH)*E (RH)*E+3 nsEMA_BA[1:0] invalid Outputsetuptime,EMA_A[13:0]validto8 tsu(EMBAV-EMOEL) (RS)*E-3 (RS)*E (RS)*E+3 nsEMA_OE low Outputholdtime,EMA_OE highto9 th(EMOEH-EMAIV) (RH)*E-3 (RH)*E (RH)*E+3 nsEMA_A[13:0]invalid EMA_OE activelowwidth(EW = 0) (RST)*E-3 (RST)*E (RST)*E+3 ns 10 tw(EMOEL) (RST+(EWC*16))* (RST+(EWC*16)EMA_OE activelowwidth(EW = 1) (RST+(EWC*16))*E nsE-3 )*E+3 td(EMWAITH- DelaytimefromEMA_WAIT deassertedto11 3E-3 4E 4E+3 ns EMOEH) EMA_OE high WRITES (WS+WST+WH)* (WS+WST+WH)*EMIF writecycletime(EW = 0) (WS+WST+WH)*E nsE-3 E+3 15 tc(EMWCYCLE) (WS+WST+WH+( (WS+WST+WH+(E (WS+WST+WH+EMIF writecycletime(EW = 1) nsEWC*16))*E -3 WC*16))*E (EWC*16))*E+ 3 Outputsetuptime,EMA_CE[5:2] lowto (WS)*E -3 (WS)*E (WS)*E + 3 nsEMA_WE low(SS = 0) 16 tsu(EMCEL-EMWEL) Outputsetuptime,EMA_CE[5:2] lowto -3 0 +3 nsEMA_WE low(SS = 1) Outputholdtime,EMA_WE highto (WH)*E-3 (WH)*E (WH)*E+3 nsEMA_CE[5:2] high(SS = 0) 17 th(EMWEH-EMCEH) Outputholdtime,EMA_WE highto -3 0 +3 nsEMA_CE[5:2] high(SS = 1) tsu(EMDQMV- Outputsetuptime,EMA_BA[1:0] validto18 (WS)*E-3 (WS)*E (WS)*E+3 ns EMWEL) EMA_WE low (1) TA = Turnaround,RS = Read setup,RST = Read strobe,RH = Read hold,WS = Writesetup,WST = Writestrobe,WH = Writehold, MEWC = Maximum externalwaitcycles.These parametersareprogrammed viatheAsynchronousBank and AsynchronousWaitCycle ConfigurationRegisters.These supportthefollowingrangeofvalues:TA[4-1],RS[16-1],RST[64-1],RH[8-1],WS[16-1],WST[64-1], WH[8-1],and MEW[1-256]. (2) E = EMA_CLK periodorinns.EMA_CLK isselectedeitheras SYSCLK3 orthePLL outputclockdividedby 4.5.As an example,when SYSCLK3 isselectedand setto100MHz, E=10ns. (3) EWC = externalwaitcyclesdeterminedby EMA_WAIT inputsignal.EWC supportsthefollowingrangeofvaluesEWC[256-1].Note that themaximum waittimebeforetimeoutisspecifiedby bitfieldMEWC intheAsynchronousWaitCycleConfigurationRegister.

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ADVANCE□INFORMATION EMA_CLK EMA_BA[1:0] EMA_A[12:0] EMA_D[15:0] 2 2 BASIC SDRAM WRITE OPERA TION EMA_CS[0] EMA_WE _DQM[1:0] EMA_RAS EMA_CAS EMA_WE AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-23.EMIFA Asynchronous Memory SwitchingCharacteristics(1)(2)(3) (continued) No. PARAMETER MIN NOM MAX UNIT th(EMWEH- Outputholdtime,EMA_WE highto19 (WH)*E-3 (WH)*E (WH)*E+3 ns EMDQMIV) EMA_BA[1:0] invalid tsu(EMBAV- Outputsetuptime,EMA_BA[1:0] validto20 (WS)*E-3 (WS)*E (WS)*E+3 ns EMWEL) EMA_WE low Outputholdtime,EMA_WE highto21 th(EMWEH-EMBAIV) (WH)*E-3 (WH)*E (WH)*E+3 nsEMA_BA[1:0] invalid Outputsetuptime,EMA_A[13:0]validto22 tsu(EMAV-EMWEL) (WS)*E-3 (WS)*E (WS)*E+3 nsEMA_WE low Outputholdtime,EMA_WE highto23 th(EMWEH-EMAIV) (WH)*E-3 (WH)*E (WH)*E+3 nsEMA_A[13:0]invalid EMA_WE activelowwidth(EW = 0) (WST)*E-3 (WST)*E (WST)*E+3 ns 24 tw(EMWEL) (WST+(EWC*16)) (WST+(EWC*16)EMA_WE activelowwidth(EW = 1) (WST+(EWC*16))*E ns*E-3 )*E+3 td(EMWAITH- DelaytimefromEMA_WAIT deassertedto25 3E-3 4E 4E+3 ns EMWEH) EMA_WE high Outputsetuptime,EMA_D[15:0]validto26 tsu(EMDV-EMWEL) (WS)*E-3 (WS)*E (WS)*E+3 nsEMA_WE low Outputholdtime,EMA_WE highto27 th(EMWEH-EMDIV) (WH)*E-3 (WH)*E (WH)*E+3 nsEMA_D[15:0]invalid Figure6-14.EMIFA Basic SDRAM WriteOperation Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 71 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION EMA_CLK EMA_BA[1:0] EMA_A[12:0] EMA_D[15:0] 2 2 17 182 EM_CLK Delay BASIC SDRAM READ OPERA TION EMA_CS[0] EMA_WE _DQM[1:0] EMA_RAS EMA_CAS EMA_WE EMA_CS[5:2] EMA_BA[1:0] EMA_A[12:0] EMA_OE EMA_D[15:0] EMA_WE 3 1 EMA_ _DQM[1:0]WE 3029 AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Figure6-15.EMIFA Basic SDRAM Read Operation Figure6-16.Asynchronous Memory Read Timing forEMIFA

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ADVANCE□INFORMATION EMA_CS[5:2] EMA_BA[1:0] EMA_A[12:0] EMA_WE EMA_D[15:0] EMA_OE 26 27 EMA_ _DQM[1:0]WE 31 32 EMA_CS[5:2] Asserted Deasserted EMA_BA[1:0] EMA_A[12:0] EMA_D[15:0] EMA_OE EMA_WAIT SETUP STROBE Extended Due to EMA_WAIT STROBE HOLD AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Figure6-17.Asynchronous Memory WriteTiming forEMIFA Figure6-18.EMA_WAIT Read Timing Requirements Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 73 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Figure6-19.EMA_WAIT WriteTiming Requirements

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ADVANCE□INFORMATION EMB_CS EMB_CAS EMB_RAS EMB_WE EMB_CLK EMB_SDCKE EMB_BA[1:0] EMB_A[x:0] EMB_D[x:0] EMB_WE_DQM[x:0] SDRAM Interface Cmd/Write FIFO Registers Read FIFO Crossbar EMIFB Master Peripherals (USB,□UHPI...) EDMA CPU AM1707 www.ti.com SPRS637 –FEBRUARY 2010

6.12 ExternalMemory InterfaceB (EMIFB)

The followingEMIFB FunctionalBlock Diagram illustratesa high-levelview of the EMIFB and its connectionswithinthe device.Multiplerequestershave access to EMIFB througha switchedcentral resource(indicatedas crossbarin the figure).The EMIFB implementsa splittransactioninternalbus, allowingconcurrencebetween readsand writesfromthevariousrequesters. Figure6-20.EMIFB FunctionalBlock Diagram EMIFB supportsa 3.3VLVCMOS Interface. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 75 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

6.12.1 InterfacingtoSDRAM

The EMIFB supportsa gluelessinterfacetoSDRAM deviceswiththefollowingcharacteristics:

Pre-chargebitisA[10]
Supports8,9,10 or11 column addressbits
Supportsup to13 row addressbits
Supports1,2 or4 internalbanks Table6-24shows thesupportedSDRAM configurationsforEMIFB. Table6-24.EMIFB Supported SDRAM Configurations(1) SDRAM Memory MemoryNumber of EMIFB Data TotalMemory TotalMemoryData Bus Rows Columns Banks DensityMemories Bus Size (Mbits) (Mbytes)Width (Mbits) (bits) 1 32 13 8 1 64 8 64 1 32 13 8 2 128 16 128 1 32 13 8 4 256 32 256 1 32 13 9 1 128 16 128 1 32 13 9 2 256 32 256 1 32 13 9 4 512 64 512 1 32 13 10 1 256 32 256 1 32 13 10 2 512 64 512 1 32 13 10 4 1024 128 1024 1 32 13 11 1 512 64 512 1 32 13 11 2 1024 128 1024 1 32 13 11 4 2048 256 2048 2 32 13 8 1 64 8 32 2 32 13 8 2 128 16 64 2 32 13 8 4 256 32 128 2 32 13 9 1 128 16 64 2 32 13 9 2 256 32 128 2 32 13 9 4 512 64 256 2 32 13 10 1 256 32 128 2 32 13 10 2 512 64 256 2 32 13 10 4 1024 128 512 2 32 13 11 1 512 64 256 2 32 13 11 2 1024 128 512 2 32 13 11 4 2048 256 1024 (1) The shaded cellsindicateconfigurationsthatarepossibleon theEMIFB interfacebutas ofthiswritingSDRAM memories capableof supportingthesedensitiesarenotavailableinthemarket. Figure6-21shows an interfacebetween theEMIFB and a 2M × 16 × 4 bank SDRAM device.Inaddition, Figure6-22 shows an interfacebetween the EMIFB and a 2M × 32 × 4 bank SDRAM deviceand Figure6-23shows an interfacebetween theEMIFB and two 4M × 16 × 4 bank SDRAM devices.Referto Table 6-25 , as an example thatshows additionallistof commonly-supportedSDRAM devicesand the requiredconnectionsfortheaddresspins.Note thatinTable6-25,page size/columnsize(notindicatedin thetable)isvariedtogettherequiredaddressabilityrange.

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ADVANCE□INFORMATION EMB_CS EMB_CAS EMB_RAS EMB_WE EMB_CLK EMB_SDCKE EMB_BA[1:0] EMB_A[11:0] EMB_WE_DQM[0] EMB_WE_DQM[1] EMB_D[15:0] EMIFB CE CAS RAS WE CLK CKE BA[1:0] A[11:0] LDQM UDQM DQ[15:0] SDRAM 2M□x□16□x□4 Bank EMB_CS EMB_CAS EMB_RAS EMB_WE EMB_CLK EMB_SDCKE EMB_BA[1:0] EMB_A[11:0] EMB_WE_DQM[3:0] EMB_D[31:0] EMIFB CE CAS RAS WE CLK CKE BA[1:0] A[11:0] DQM[3:0] DQ[31:0] SDRAM 2M□x□32□x□4 Bank AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Figure6-21.EMIFB to2M × 16 × 4 bank SDRAM Interface Figure6-22.EMIFB to2M × 32 × 4 bank SDRAM Interface Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 77 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION EMB_CS EMB_CAS EMB_RAS EMB_WE EMB_CLK EMB_SDCKE EMB_BA[1:0] EMB_A[12:0] EMB_WE_DQM[0] EMB_D[15:0] EMIFB CE CAS RAS WE CLK CKE BA[1:0] A[12:0] LDQM DQ[15:0] SDRAM 4M□x□16□x□4 Bank EMB_WE_DQM[1] UDQM EMB_WE_DQM[2] EMB_D[31:16] EMB_WE_DQM[3] CE CAS RAS WE CLK CKE BA[1:0] A[12:0] LDQM DQ[15:0] SDRAM 4M□x□16□x□4 Bank UDQM AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Figure6-23.EMIFB toDual 4M × 16 × 4 bank SDRAM Interface Table6-25.Example of16/32-bitEMIFB Address Pin Connections SDRAM Size Width Banks Address Pins 64M bits ×16 4 SDRAM A[11:0] EMIFB EMB_A[11:0] ×32 4 SDRAM A[10:0] EMIFB EMB_A[10:0] 128M bits ×16 4 SDRAM A[11:0] EMIFB EMB_A[11:0] ×32 4 SDRAM A[11:0] EMIFB EMB_A[11:0] 256M bits ×16 4 SDRAM A[12:0] EMIFB EMB_A[12:0] ×32 4 SDRAM A[11:0] EMIFB EMB_A[11:0] 512M bits ×16 4 SDRAM A[12:0] EMIFB EMB_A[12:0] ×32 4 SDRAM A[12:0] EMIFB EMB_A[12:0]

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-26isa listoftheEMIFB registers. Table6-26.EMIFB ControllerRegisters BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0xB000 0000 MIDR Module ID Register 0xB000 0008 SDCFG SDRAM ConfigurationRegister 0xB000 000C SDRFC SDRAM RefreshControlRegister 0xB000 0010 SDTIM1 SDRAM TimingRegister1 0xB000 0014 SDTIM2 SDRAM TimingRegister2 0xB000 001C SDCFG2 SDRAM Configuration2 Register 0xB000 0020 BPRIO PeripheralBus BurstPriorityRegister 0xB000 0040 PC1 PerformanceCounter1 Register 0xB000 0044 PC2 PerformanceCounter2 Register 0xB000 0048 PCC PerformanceCounterConfigurationRegister 0xB000 004C PCMRS PerformanceCounterMasterRegionSelectRegister 0xB000 0050 PCT PerformanceCounterTime Register 0xB000 00C0 IRR InterruptRaw Register 0xB000 00C4 IMR InterruptMask Register 0xB000 00C8 IMSR InterruptMask SetRegister 0xB000 00CC IMCR InterruptMask ClearRegister Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 79 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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6.12.2 EMIFB ElectricalData/Timing

Table6-27.EMIFB SDRAM InterfaceTiming Requirements No. PARAMETER MIN MAX UNIT 19 tsu(DV-CLKH) Inputsetuptime,readdatavalidon EMB_D[31:0]beforeEMB_CLK rising 0.8 ns 20 th(CLKH-DIV) Inputholdtime,readdatavalidon EMB_D[31:0]afterEMB_CLK rising 1.5 ns Table6-28.EMIFB SDRAM InterfaceSwitchingCharacteristics No. PARAMETER MIN MAX UNIT 1 tc(CLK) Cycletime,EMIF clockEMB_CLK 7.5 ns 2 tw(CLK) Pulsewidth,EMIF clockEMB_CLK highorlow 3 ns 3 td(CLKH-CSV) Delaytime,EMB_CLK risingtoEMB_CS[0] valid 5.1 ns 4 toh(CLKH-CSIV) Outputholdtime,EMB_CLK risingtoEMB_CS[0] invalid 0.9 ns 5 td(CLKH-DQMV) Delaytime,EMB_CLK risingtoEMB_ WE_DQM[3:0] valid 5.1 ns 6 toh(CLKH-DQMIV) Outputholdtime,EMB_CLK risingtoEMB_ WE_DQM[3:0] invalid 0.9 ns 7 td(CLKH-AV) Delaytime,EMB_CLK risingtoEMB_A[12:0]and EMB_BA[1:0] valid 5.1 ns 8 toh(CLKH-AIV) Outputholdtime,EMB_CLK risingtoEMB_A[12:0]and EMB_BA[1:0] invalid 0.9 ns 9 td(CLKH-DV) Delaytime,EMB_CLK risingtoEMB_D[31:0]valid 5.1 ns 10 toh(CLKH-DIV) Outputholdtime,EMB_CLK risingtoEMB_D[31:0]invalid 0.9 ns 11 td(CLKH-RASV) Delaytime,EMB_CLK risingtoEMB_RAS valid 5.1 ns 12 toh(CLKH-RASIV) Outputholdtime,EMB_CLK risingtoEMB_RAS invalid 0.9 ns 13 td(CLKH-CASV) Delaytime,EMB_CLK risingtoEMB_CAS valid 5.1 ns 14 toh(CLKH-CASIV) Outputholdtime,EMB_CLK risingtoEMB_CAS invalid 0.9 ns 15 td(CLKH-WEV) Delaytime,EMB_CLK risingtoEMB_WE valid 5.1 ns 16 toh(CLKH-WEIV) Outputholdtime,EMB_CLK risingtoEMB_WE invalid 0.9 ns 17 tdis(CLKH-DHZ) Delaytime,EMB_CLK risingtoEMB_D[31:0]3-stated 5.1 ns 18 tena(CLKH-DLZ) Outputholdtime,EMB_CLK risingtoEMB_D[31:0]driving 0.9 ns

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ADVANCE□INFORMATION EMB_CLK EMB_BA[1:0] EMB_A[12:0] EMB_D[31:0] 2 2 BASIC SDRAM WRITE OPERA TION EMB_CS[0] EMB_WE _DQM[3:0] EMB_RAS EMB_CAS EMB_WE EMB_CLK EMB_BA[1:0] EMB_A[12:0] EMB_D[31:0] 2 2 17 182 EM_CLK Delay BASIC SDRAM READ OPERA TION EMB_CS[0] EMB_WE _DQM[3:0] EMB_RAS EMB_CAS EMB_WE AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Figure6-24.EMIFB Basic SDRAM WriteOperation Figure6-25.EMIFB Basic SDRAM Read Operation Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 81 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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6.13 Memory ProtectionUnits

The MPU performsmemory protectionchecking.Itreceivesrequestsfroma bus masterinthesystemand checkstheaddressagainstthefixedand programmableregionstosee iftheaccessisallowed.Ifallowed, thetransferispassed unmodifiedtoitsoutputbus (tothetargetedaddress).Ifthetransferisillegal(fails theprotectioncheck)thentheMPU does notpass thetransfertotheoutputbus butratherservicesthe transferinternallyback totheinputbus (topreventa hang) returningthefaultstatustotherequestoras wellas generatingan interruptaboutthefault.The followingfeaturesaresupportedby theMPU:

Providesmemory protectionforfixedand programmableaddressranges.
Supportsmultipleprogrammableaddressregion.
Supportssecureand debug accessprivileges.
Supportsread,write,and executeaccessprivileges.
Supportsprivid(8)associationswithranges.
Generatesan interruptwhen thereisa protectionviolation,and savesviolatingtransferparameters.
MMR accessisalsoprotected. Table6-29.MPU1 ConfigurationRegisters MPU1 ACRONYM REGISTER DESCRIPTIONBYTE ADDRESS 0x01E1 4000 REVID RevisionID 0x01E1 4004 CONFIG Configuration 0x01E1 4010 IRAWSTAT Interruptraw status/set 0x01E1 4014 IENSTAT Interruptenablestatus/clear 0x01E1 4018 IENSET Interruptenable 0x01E1 401C IENCLR Interruptenableclear 0x01E1 4020 -0x01E1 41FF - Reserved 0x01E1 4200 PROG1_MPSAR Programmable range1,startaddress 0x01E1 4204 PROG1_MPEAR Programmable range1,end address 0x01E1 4208 PROG1_MPPA Programmable range1,memory page protectionattributes 0x01E1 420C -0x01E1 420F - Reserved 0x01E1 4210 PROG2_MPSAR Programmable range2,startaddress 0x01E1 4214 PROG2_MPEAR Programmable range2,end address 0x01E1 4218 PROG2_MPPA Programmable range2,memory page protectionattributes 0x01E1 421C -0x01E1 421F - Reserved 0x01E1 4220 PROG3_MPSAR Programmable range3,startaddress 0x01E1 4224 PROG3_MPEAR Programmable range3,end address 0x01E1 4228 PROG3_MPPA Programmable range3,memory page protectionattributes 0x01E1 422C -0x01E1 422F - Reserved 0x01E1 4230 PROG4_MPSAR Programmable range4,startaddress 0x01E1 4234 PROG4_MPEAR Programmable range4,end address 0x01E1 4238 PROG4_MPPA Programmable range4,memory page protectionattributes 0x01E1 423C -0x01E1 423F - Reserved 0x01E1 4240 PROG5_MPSAR Programmable range5,startaddress 0x01E1 4244 PROG5_MPEAR Programmable range5,end address 0x01E1 4248 PROG5_MPPA Programmable range5,memory page protectionattributes 0x01E1 424C -0x01E1 424F - Reserved 0x01E1 4250 PROG6_MPSAR Programmable range6,startaddress 0x01E1 4254 PROG6_MPEAR Programmable range6,end address 0x01E1 4258 PROG6_MPPA Programmable range6,memory page protectionattributes 0x01E1 425C -0x01E1 42FF - Reserved

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-29.MPU1 ConfigurationRegisters(continued) MPU1 ACRONYM REGISTER DESCRIPTIONBYTE ADDRESS 0x01E14300 FLTADDRR Faultaddress 0x01E1 4304 FLTSTAT Faultstatus 0x01E1 4308 FLTCLR Faultclear 0x01E1 430C -0x01E1 4FFF - Reserved Table6-30.MPU2 ConfigurationRegisters MPU1 ACRONYM REGISTER DESCRIPTIONBYTE ADDRESS 0x01E1 5000 REVID RevisionID 0x01E1 5004 CONFIG Configuration 0x01E1 5010 IRAWSTAT Interruptraw status/set 0x01E1 5014 IENSTAT Interruptenablestatus/clear 0x01E1 5018 IENSET Interruptenable 0x01E1 501C IENCLR Interruptenableclear 0x01E1 5020 -0x01E1 50FF - Reserved 0x01E1 5100 FXD_MPSAR Fixedrangestartaddress 0x01E1 5104 FXD_MPEAR Fixedrangeend startaddress 0x01E1 5108 FXD_MPPA Fixedrangememory page protectionattributes 0x01E1 510C -0x01E1 51FF - Reserved 0x01E1 5200 PROG1_MPSAR Programmable range1,startaddress 0x01E1 5204 PROG1_MPEAR Programmable range1,end address 0x01E1 5208 PROG1_MPPA Programmable range1,memory page protectionattributes 0x01E1 520C -0x01E1 520F - Reserved 0x01E1 5210 PROG2_MPSAR Programmable range2,startaddress 0x01E1 5214 PROG2_MPEAR Programmable range2,end address 0x01E1 5218 PROG2_MPPA Programmable range2,memory page protectionattributes 0x01E1 521C -0x01E1 521F - Reserved 0x01E1 5220 PROG3_MPSAR Programmable range3,startaddress 0x01E1 5224 PROG3_MPEAR Programmable range3,end address 0x01E1 5228 PROG3_MPPA Programmable range3,memory page protectionattributes 0x01E1 522C -0x01E1 522F - Reserved 0x01E1 5230 PROG4_MPSAR Programmable range4,startaddress 0x01E1 5234 PROG4_MPEAR Programmable range4,end address 0x01E1 5238 PROG4_MPPA Programmable range4,memory page protectionattributes 0x01E1 523C -0x01E1 523F - Reserved 0x01E1 5240 PROG5_MPSAR Programmable range5,startaddress 0x01E1 5244 PROG5_MPEAR Programmable range5,end address 0x01E1 5248 PROG5_MPPA Programmable range5,memory page protectionattributes 0x01E1 524C -0x01E1 524F - Reserved 0x01E1 5250 PROG6_MPSAR Programmable range6,startaddress 0x01E1 5254 PROG6_MPEAR Programmable range6,end address 0x01E1 5258 PROG6_MPPA Programmable range6,memory page protectionattributes 0x01E1 525C -0x01E1 525F - Reserved 0x01E1 5260 PROG7_MPSAR Programmable range7,startaddress 0x01E1 5264 PROG7_MPEAR Programmable range7,end address 0x01E1 5268 PROG7_MPPA Programmable range7,memory page protectionattributes Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 83 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-30.MPU2 ConfigurationRegisters(continued) MPU1 ACRONYM REGISTER DESCRIPTIONBYTE ADDRESS 0x01E1 526C -0x01E1 526F - Reserved 0x01E1 5270 PROG8_MPSAR Programmable range8,startaddress 0x01E1 5274 PROG8_MPEAR Programmable range8,end address 0x01E1 5278 PROG8_MPPA Programmable range8,memory page protectionattributes 0x01E1 527C -0x01E1 527F - Reserved 0x01E1 5280 PROG9_MPSAR Programmable range9,startaddress 0x01E1 5284 PROG9_MPEAR Programmable range9,end address 0x01E1 5288 PROG9_MPPA Programmable range9,memory page protectionattributes 0x01E1 528C -0x01E1 528F - Reserved 0x01E1 5290 PROG10_MPSAR Programmable range10,startaddress 0x01E1 5294 PROG10_MPEAR Programmable range10,end address 0x01E1 5298 PROG10_MPPA Programmable range10,memory page protectionattributes 0x01E1 529C -0x01E1 529F - Reserved 0x01E1 52A0 PROG11_MPSAR Programmable range11,startaddress 0x01E1 52A4 PROG11_MPEAR Programmable range11,end address 0x01E1 52A8 PROG11_MPPA Programmable range11,memory page protectionattributes 0x01E1 52AC -0x01E1 52AF - Reserved 0x01E1 52B0 PROG12_MPSAR Programmable range12,startaddress 0x01E1 52B4 PROG12_MPEAR Programmable range12,end address 0x01E1 52B8 PROG12_MPPA Programmable range12,memory page protectionattributes 0x01E1 52BC -0x01E1 52FF - Reserved 0x01E1 5300 FLTADDRR Faultaddress 0x01E1 5304 FLTSTAT Faultstatus 0x01E1 5308 FLTCLR Faultclear 0x01E1 530C -0x01E1 5FFF - Reserved

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6.14 MMC /SD /SDIO (MMCSD)

6.14.1 MMCSD PeripheralDescription

The deviceincludesan MMCSD controllerwhich iscompliantwithMMC V3.31,Secure DigitalPart1 PhysicalLayerSpecificationV1.1and SecureDigitalInputOutput(SDIO)V2.0specifications. The MMC/SD Controllerhas followingfeatures:

MultiMediaCard(MMC).
SecureDigital(SD)Memory Card.
MMC/SD protocolsupport.
SDIO protocolsupport.
Programmable clockfrequency.
512 bitRead/WriteFIFO tolowersystemoverhead.
SlaveEDMA transfercapability. The deviceMMC/SD Controllerdoes notsupportSPI mode.

6.14.2 MMCSD PeripheralRegisterDescription(s)

Table6-31.MultimediaCard/SecureDigital(MMC/SD) Card ControllerRegisters BYTE ACRONYM REGISTER DESCRIPTION ADDRESS 0x01C4 0000 MMCCTL MMC ControlRegister 0x01C4 0004 MMCCLK MMC Memory ClockControlRegister 0x01C4 0008 MMCST0 MMC StatusRegister0 0x01C4 000C MMCST1 MMC StatusRegister1 0x01C4 0010 MMCIM MMC InterruptMask Register 0x01C4 0014 MMCTOR MMC Response Time-OutRegister 0x01C4 0018 MMCTOD MMC Data Read Time-OutRegister 0x01C4 001C MMCBLEN MMC BlockLengthRegister 0x01C4 0020 MMCNBLK MMC Number ofBlocksRegister 0x01C4 0024 MMCNBLC MMC Number ofBlocksCounterRegister 0x01C4 0028 MMCDRR MMC Data ReceiveRegister 0x01C4 002C MMCDXR MMC Data TransmitRegister 0x01C4 0030 MMCCMD MMC Command Register 0x01C4 0034 MMCARGHL MMC Argument Register 0x01C4 0038 MMCRSP01 MMC Response Register0 and 1 0x01C4 003C MMCRSP23 MMC Response Register2 and 3 0x01C4 0040 MMCRSP45 MMC Response Register4 and 5 0x01C4 0044 MMCRSP67 MMC Response Register6 and 7 0x01C4 0048 MMCDRSP MMC Data Response Register 0x01C4 0050 MMCCIDX MMC Command IndexRegister 0x01C4 0064 SDIOCTL SDIO ControlRegister 0x01C4 0068 SDIOST0 SDIO StatusRegister0 0x01C4 006C SDIOIEN SDIO InterruptEnableRegister 0x01C4 0070 SDIOIST SDIO InterruptStatusRegister 0x01C4 0074 MMCFIFOCTL p MMC FIFO ControlRegister Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 85 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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6.14.3 MMC/SD ElectricalData/Timing

Table6-32.Timing Requirements forMMC/SD Module (seeFigure6-27and Figure6-29) No. PARAMETER MIN MAX UNIT 1 tsu(CMDV-CLKH) Setuptime,MMCSD_CMD validbeforeMMCSD_CLK high 3.2 ns 2 th(CLKH-CMDV) Holdtime,MMCSD_CMD validafterMMCSD_CLK high 1.5 ns 3 tsu(DATV-CLKH) Setuptime,MMCSD_DATx validbeforeMMCSD_CLK high 3.2 ns 4 th(CLKH-DATV) Holdtime,MMCSD_DATx validafterMMCSD_CLK high 1.5 ns Table6-33.SwitchingCharacteristicsOver Recommended OperatingConditionsforMMC/SD Module (seeFigure6-26through Figure6-29) No. PARAMETER MIN MAX UNIT 7 f(CLK) Operatingfrequency,MMCSD_CLK 0 52 MHz 8 f(CLK_ID) Identificationmode frequency,MMCSD_CLK 0 400 KHz 9 tW(CLKL) Pulsewidth,MMCSD_CLK low 6.5 ns 10 tW(CLKH) Pulsewidth,MMCSD_CLK high 6.5 ns 11 tr(CLK) Risetime,MMCSD_CLK 3 ns 12 tf(CLK) Falltime,MMCSD_CLK 3 ns 13 td(CLKL-CMD) Delaytime,MMCSD_CLK lowtoMMCSD_CMD transition -4.5 2.5 ns 14 td(CLKL-DAT) Delaytime,MMCSD_CLK lowtoMMCSD_DATx transition -4.5 2 ns

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ADVANCE□INFORMATION ST ART XMIT V alid Valid Valid END MMCSD_CLK MMCSD_CMD 13 13 13 ST ART XMIT V alid Valid Valid END MMCSD_CLK MMCSD_CMD 1097 ST ART D0 D1 Dx END MMCSD_CLK MMCSD_DATx 1414 14 14 Start D0 D1 Dx End MMCSD_CLK MMCSD_DA Tx 3 3 AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Figure6-26.MMC/SD Host Command Timing Figure6-27.MMC/SD Card Response Timing Figure6-28.MMC/SD Host WriteTiming Figure6-29.MMC/SD Host Read and Card CRC StatusTiming Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 87 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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6.15 EthernetMedia Access Controller(EMAC)

The EthernetMedia Access Controller(EMAC) providesan efficientinterfacebetween thedeviceand the network.The EMAC supportsboth10Base-T and 100Base-TX,or10 Mbits/second(Mbps)and 100 Mbps ineitherhalf-orfull-duplexmode, withhardwareflowcontroland qualityofservice(QOS) support. The EMAC controlstheflowofpacketdatafromthedevicetothePHY. The MDIO module controlsPHY configurationand statusmonitoring. Both the EMAC and the MDIO modules interfaceto the devicethrougha custom interfacethatallows efficientdata transmissionand reception.This custom interfaceis referredto as the EMAC control module,and isconsideredintegralto the EMAC/MDIO peripheral.The controlmodule isalsoused to multiplexand controlinterrupts.

6.15.1 EMAC PeripheralRegisterDescription(s)

Table6-34.EthernetMedia Access Controller(EMAC) Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E2 3000 TXREV TransmitRevisionRegister 0x01E2 3004 TXCONTROL TransmitControlRegister 0x01E2 3008 TXTEARDOWN TransmitTeardown Register 0x01E2 3010 RXREV ReceiveRevisionRegister 0x01E2 3014 RXCONTROL ReceiveControlRegister 0x01E2 3018 RXTEARDOWN ReceiveTeardown Register 0x01E2 3080 TXINTSTATRAW TransmitInterruptStatus(Unmasked) Register 0x01E2 3084 TXINTSTATMASKED TransmitInterruptStatus(Masked)Register 0x01E2 3088 TXINTMASKSET TransmitInterruptMask SetRegister 0x01E2 308C TXINTMASKCLEAR TransmitInterruptClearRegister 0x01E2 3090 MACINVECTOR MAC InputVectorRegister 0x01E2 3094 MACEOIVECTOR MAC End Of InterruptVectorRegister 0x01E2 30A0 RXINTSTATRAW ReceiveInterruptStatus(Unmasked) Register 0x01E2 30A4 RXINTSTATMASKED ReceiveInterruptStatus(Masked)Register 0x01E2 30A8 RXINTMASKSET ReceiveInterruptMask SetRegister 0x01E2 30AC RXINTMASKCLEAR ReceiveInterruptMask ClearRegister 0x01E2 30B0 MACINTSTATRAW MAC InterruptStatus(Unmasked) Register 0x01E2 30B4 MACINTSTATMASKED MAC InterruptStatus(Masked)Register 0x01E2 30B8 MACINTMASKSET MAC InterruptMask SetRegister 0x01E2 30BC MACINTMASKCLEAR MAC InterruptMask ClearRegister 0x01E2 3100 RXMBPENABLE ReceiveMulticast/Broadcast/PromiscuousChannelEnableRegister 0x01E2 3104 RXUNICASTSET ReceiveUnicastEnableSetRegister 0x01E2 3108 RXUNICASTCLEAR ReceiveUnicastClearRegister 0x01E2 310C RXMAXLEN ReceiveMaximum LengthRegister 0x01E2 3110 RXBUFFEROFFSET ReceiveBufferOffsetRegister 0x01E2 3114 RXFILTERLOWTHRESH ReceiveFilterLow PriorityFrame ThresholdRegister 0x01E2 3120 RX0FLOWTHRESH ReceiveChannel0 Flow ControlThresholdRegister 0x01E2 3124 RX1FLOWTHRESH ReceiveChannel1 Flow ControlThresholdRegister 0x01E2 3128 RX2FLOWTHRESH ReceiveChannel2 Flow ControlThresholdRegister 0x01E2 312C RX3FLOWTHRESH ReceiveChannel3 Flow ControlThresholdRegister 0x01E2 3130 RX4FLOWTHRESH ReceiveChannel4 Flow ControlThresholdRegister 0x01E2 3134 RX5FLOWTHRESH ReceiveChannel5 Flow ControlThresholdRegister 0x01E2 3138 RX6FLOWTHRESH ReceiveChannel6 Flow ControlThresholdRegister 0x01E2 313C RX7FLOWTHRESH ReceiveChannel7 Flow ControlThresholdRegister

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-34.EthernetMedia Access Controller(EMAC) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E2 3140 RX0FREEBUFFER ReceiveChannel0 FreeBufferCount Register 0x01E2 3144 RX1FREEBUFFER ReceiveChannel1 FreeBufferCount Register 0x01E2 3148 RX2FREEBUFFER ReceiveChannel2 FreeBufferCount Register 0x01E2 314C RX3FREEBUFFER ReceiveChannel3 FreeBufferCount Register 0x01E2 3150 RX4FREEBUFFER ReceiveChannel4 FreeBufferCount Register 0x01E2 3154 RX5FREEBUFFER ReceiveChannel5 FreeBufferCount Register 0x01E2 3158 RX6FREEBUFFER ReceiveChannel6 FreeBufferCount Register 0x01E2 315C RX7FREEBUFFER ReceiveChannel7 FreeBufferCount Register 0x01E2 3160 MACCONTROL MAC ControlRegister 0x01E2 3164 MACSTATUS MAC StatusRegister 0x01E2 3168 EMCONTROL EmulationControlRegister 0x01E2 316C FIFOCONTROL FIFO ControlRegister 0x01E2 3170 MACCONFIG MAC ConfigurationRegister 0x01E2 3174 SOFTRESET SoftResetRegister 0x01E2 31D0 MACSRCADDRLO MAC SourceAddressLow BytesRegister 0x01E2 31D4 MACSRCADDRHI MAC SourceAddressHighBytesRegister 0x01E2 31D8 MACHASH1 MAC Hash AddressRegister1 0x01E2 31DC MACHASH2 MAC Hash AddressRegister2 0x01E2 31E0 BOFFTEST Back OffTestRegister 0x01E2 31E4 TPACETEST TransmitPacingAlgorithmTestRegister 0x01E2 31E8 RXPAUSE ReceivePause TimerRegister 0x01E2 31EC TXPAUSE TransmitPause TimerRegister 0x01E2 3200 -0x01E2 32FC (seeTable6-35) EMAC StatisticsRegisters 0x01E2 3500 MACADDRLO MAC AddressLow BytesRegister,Used inReceiveAddressMatching 0x01E2 3504 MACADDRHI MAC AddressHighBytesRegister,Used inReceiveAddressMatching 0x01E2 3508 MACINDEX MAC IndexRegister 0x01E2 3600 TX0HDP TransmitChannel0 DMA Head DescriptorPointerRegister 0x01E2 3604 TX1HDP TransmitChannel1 DMA Head DescriptorPointerRegister 0x01E2 3608 TX2HDP TransmitChannel2 DMA Head DescriptorPointerRegister 0x01E2 360C TX3HDP TransmitChannel3 DMA Head DescriptorPointerRegister 0x01E2 3610 TX4HDP TransmitChannel4 DMA Head DescriptorPointerRegister 0x01E2 3614 TX5HDP TransmitChannel5 DMA Head DescriptorPointerRegister 0x01E2 3618 TX6HDP TransmitChannel6 DMA Head DescriptorPointerRegister 0x01E2 361C TX7HDP TransmitChannel7 DMA Head DescriptorPointerRegister 0x01E2 3620 RX0HDP ReceiveChannel0 DMA Head DescriptorPointerRegister 0x01E2 3624 RX1HDP ReceiveChannel1 DMA Head DescriptorPointerRegister 0x01E2 3628 RX2HDP ReceiveChannel2 DMA Head DescriptorPointerRegister 0x01E2 362C RX3HDP ReceiveChannel3 DMA Head DescriptorPointerRegister 0x01E2 3630 RX4HDP ReceiveChannel4 DMA Head DescriptorPointerRegister 0x01E2 3634 RX5HDP ReceiveChannel5 DMA Head DescriptorPointerRegister 0x01E2 3638 RX6HDP ReceiveChannel6 DMA Head DescriptorPointerRegister 0x01E2 363C RX7HDP ReceiveChannel7 DMA Head DescriptorPointerRegister 0x01E2 3640 TX0CP TransmitChannel0 CompletionPointerRegister 0x01E2 3644 TX1CP TransmitChannel1 CompletionPointerRegister 0x01E2 3648 TX2CP TransmitChannel2 CompletionPointerRegister 0x01E2 364C TX3CP TransmitChannel3 CompletionPointerRegister 0x01E2 3650 TX4CP TransmitChannel4 CompletionPointerRegister Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 89 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-34.EthernetMedia Access Controller(EMAC) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E2 3654 TX5CP TransmitChannel5 CompletionPointerRegister 0x01E2 3658 TX6CP TransmitChannel6 CompletionPointerRegister 0x01E2 365C TX7CP TransmitChannel7 CompletionPointerRegister 0x01E2 3660 RX0CP ReceiveChannel0 CompletionPointerRegister 0x01E2 3664 RX1CP ReceiveChannel1 CompletionPointerRegister 0x01E2 3668 RX2CP ReceiveChannel2 CompletionPointerRegister 0x01E2 366C RX3CP ReceiveChannel3 CompletionPointerRegister 0x01E2 3670 RX4CP ReceiveChannel4 CompletionPointerRegister 0x01E2 3674 RX5CP ReceiveChannel5 CompletionPointerRegister 0x01E2 3678 RX6CP ReceiveChannel6 CompletionPointerRegister 0x01E2 367C RX7CP ReceiveChannel7 CompletionPointerRegister Table6-35.EMAC StatisticsRegisters BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E2 3200 RXGOODFRAMES Good ReceiveFrames Register BroadcastReceiveFrames Register0x01E2 3204 RXBCASTFRAMES (Totalnumber ofgood broadcastframesreceived) MulticastReceiveFrames Register0x01E2 3208 RXMCASTFRAMES (Totalnumber ofgood multicastframesreceived) 0x01E2 320C RXPAUSEFRAMES Pause ReceiveFrames Register ReceiveCRC ErrorsRegister0x01E2 3210 RXCRCERRORS (Totalnumber offramesreceivedwithCRC errors) ReceiveAlignment/CodeErrorsRegister0x01E2 3214 RXALIGNCODEERRORS (Totalnumber offramesreceivedwithalignment/codeerrors) ReceiveOversizedFrames Register0x01E2 3218 RXOVERSIZED (Totalnumber ofoversizedframesreceived) ReceiveJabberFrames Register0x01E2 321C RXJABBER (Totalnumber ofjabberframesreceived) ReceiveUndersizedFrames Register0x01E2 3220 RXUNDERSIZED (Totalnumber ofundersizedframesreceived) 0x01E2 3224 RXFRAGMENTS ReceiveFrame FragmentsRegister 0x01E2 3228 RXFILTERED FilteredReceiveFrames Register 0x01E2 322C RXQOSFILTERED ReceivedQOS FilteredFrames Register ReceiveOctetFrames Register0x01E2 3230 RXOCTETS (Totalnumber ofreceivedbytesingood frames) Good TransmitFrames Register0x01E2 3234 TXGOODFRAMES (Totalnumber ofgood framestransmitted) 0x01E2 3238 TXBCASTFRAMES BroadcastTransmitFrames Register 0x01E2 323C TXMCASTFRAMES MulticastTransmitFrames Register 0x01E2 3240 TXPAUSEFRAMES Pause TransmitFrames Register 0x01E2 3244 TXDEFERRED DeferredTransmitFrames Register 0x01E2 3248 TXCOLLISION TransmitCollisionFrames Register 0x01E2 324C TXSINGLECOLL TransmitSingleCollisionFrames Register 0x01E2 3250 TXMULTICOLL TransmitMultipleCollisionFrames Register 0x01E2 3254 TXEXCESSIVECOLL TransmitExcessiveCollisionFrames Register 0x01E2 3258 TXLATECOLL TransmitLateCollisionFrames Register 0x01E2 325C TXUNDERRUN TransmitUnderrunErrorRegister 0x01E2 3260 TXCARRIERSENSE TransmitCarrierSense ErrorsRegister 0x01E2 3264 TXOCTETS TransmitOctetFrames Register 0x01E2 3268 FRAME64 Transmitand Receive64 OctetFrames Register

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-35.EMAC StatisticsRegisters(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E2 326C FRAME65T127 Transmitand Receive65 to127 OctetFrames Register 0x01E2 3270 FRAME128T255 Transmitand Receive128 to255 OctetFrames Register 0x01E2 3274 FRAME256T511 Transmitand Receive256 to511 OctetFrames Register 0x01E2 3278 FRAME512T1023 Transmitand Receive512 to1023 OctetFrames Register 0x01E2 327C FRAME1024TUP Transmitand Receive1024 to1518 OctetFrames Register 0x01E2 3280 NETOCTETS NetworkOctetFrames Register 0x01E2 3284 RXSOFOVERRUNS ReceiveFIFO orDMA StartofFrame OverrunsRegister 0x01E2 3288 RXMOFOVERRUNS ReceiveFIFO orDMA MiddleofFrame OverrunsRegister 0x01E2 328C RXDMAOVERRUNS ReceiveDMA StartofFrame and MiddleofFrame OverrunsRegister Table6-36.EMAC ControlModule Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E2 2000 REV EMAC ControlModule RevisionRegister 0x01E2 2004 SOFTRESET EMAC ControlModule SoftwareResetRegister 0x01E2 200C INTCONTROL EMAC ControlModule InterruptControlRegister 0x01E2 2010 C0RXTHRESHEN EMAC ControlModule InterruptCore 0 ReceiveThresholdInterruptEnableRegister 0x01E2 2014 C0RXEN EMAC ControlModule InterruptCore 0 ReceiveInterruptEnableRegister 0x01E2 2018 C0TXEN EMAC ControlModule InterruptCore 0 TransmitInterruptEnableRegister 0x01E2 201C C0MISCEN EMAC ControlModule InterruptCore 0 MiscellaneousInterruptEnableRegister 0x01E2 2020 C1RXTHRESHEN EMAC ControlModule InterruptCore 1 ReceiveThresholdInterruptEnableRegister 0x01E2 2024 C1RXEN EMAC ControlModule InterruptCore 1 ReceiveInterruptEnableRegister 0x01E2 2028 C1TXEN EMAC ControlModule InterruptCore 1 TransmitInterruptEnableRegister 0x01E2 202C C1MISCEN EMAC ControlModule InterruptCore 1 MiscellaneousInterruptEnableRegister 0x01E2 2030 C2RXTHRESHEN EMAC ControlModule InterruptCore 2 ReceiveThresholdInterruptEnableRegister 0x01E2 2034 C2RXEN EMAC ControlModule InterruptCore 2 ReceiveInterruptEnableRegister 0x01E2 2038 C2TXEN EMAC ControlModule InterruptCore 2 TransmitInterruptEnableRegister 0x01E2 203C C2MISCEN EMAC ControlModule InterruptCore 2 MiscellaneousInterruptEnableRegister 0x01E2 2040 C0RXTHRESHSTAT EMAC ControlModule InterruptCore 0 ReceiveThresholdInterruptStatusRegister 0x01E2 2044 C0RXSTAT EMAC ControlModule InterruptCore 0 ReceiveInterruptStatusRegister 0x01E2 2048 C0TXSTAT EMAC ControlModule InterruptCore 0 TransmitInterruptStatusRegister 0x01E2 204C C0MISCSTAT EMAC ControlModule InterruptCore 0 MiscellaneousInterruptStatusRegister 0x01E2 2050 C1RXTHRESHSTAT EMAC ControlModule InterruptCore 1 ReceiveThresholdInterruptStatusRegister 0x01E2 2054 C1RXSTAT EMAC ControlModule InterruptCore 1 ReceiveInterruptStatusRegister 0x01E2 2058 C1TXSTAT EMAC ControlModule InterruptCore 1 TransmitInterruptStatusRegister 0x01E2 205C C1MISCSTAT EMAC ControlModule InterruptCore 1 MiscellaneousInterruptStatusRegister 0x01E2 2060 C2RXTHRESHSTAT EMAC ControlModule InterruptCore 2 ReceiveThresholdInterruptStatusRegister 0x01E2 2064 C2RXSTAT EMAC ControlModule InterruptCore 2 ReceiveInterruptStatusRegister 0x01E2 2068 C2TXSTAT EMAC ControlModule InterruptCore 2 TransmitInterruptStatusRegister 0x01E2 206C C2MISCSTAT EMAC ControlModule InterruptCore 2 MiscellaneousInterruptStatusRegister 0x01E2 2070 C0RXIMAX EMAC ControlModule InterruptCore 0 ReceiveInterruptsPer MillisecondRegister 0x01E2 2074 C0TXIMAX EMAC ControlModule InterruptCore 0 TransmitInterruptsPer MillisecondRegister 0x01E2 2078 C1RXIMAX EMAC ControlModule InterruptCore 1 ReceiveInterruptsPer MillisecondRegister 0x01E2 207C C1TXIMAX EMAC ControlModule InterruptCore 1 TransmitInterruptsPer MillisecondRegister 0x01E2 2080 C2RXIMAX EMAC ControlModule InterruptCore 2 ReceiveInterruptsPer MillisecondRegister 0x01E2 2084 C2TXIMAX EMAC ControlModule InterruptCore 2 TransmitInterruptsPer MillisecondRegister Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 91 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION RMII_MHz_50_CLK RMII_TXEN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRS_DV RMII_RXER 2 3 5 5 8 9 AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-37.EMAC ControlModule RAM HEX ADDRESS RANGE 0x01E2 0000 -0x01E2 1FFF EMAC LocalBufferDescriptorMemory Table6-38.RMII Timing Requirements No. PARAMETER MIN TYP MAX UNIT 1 tc(REFCLK) CycleTime,REF_CLK 20 ns 2 tw(REFCLKH) PulseWidth,REF_CLK High 7 13 ns 3 tw(REFCLKL) PulseWidth,REF_CLK Low 7 13 ns 6 tsu(RXD-REFCLK) InputSetupTime,RXD ValidbeforeREF_CLK High 4 ns 7 th(REFCLK-RXD) InputHoldTime,RXD ValidafterREF_CLK High 2 ns 8 tsu(CRSDV-REFCLK) InputSetupTime,CRSDV ValidbeforeREF_CLK High 4 ns 9 th(REFCLK-CRSDV) InputHoldTime,CRSDV ValidafterREF_CLK High 2 ns 10 tsu(RXER-REFCLK) InputSetupTime,RXER ValidbeforeREF_CLK High 4 ns 11 th(REFCLKR-RXER) InputHoldTime,RXER ValidafterREF_CLK High 2 ns Table6-39.RMII Timing Requirements No. PARAMETER MIN TYP MAX UNIT 4 td(REFCLK-TXD) OutputDelayTime,REF_CLK HightoTXD Valid 2.5 13 ns 5 td(REFCLK-TXEN) OutputDelayTime,REF_CLK HightoTXEN Valid 2.5 13 ns Figure6-30.RMII Timing Diagram

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6.16 Management Data Input/Output(MDIO)

The Management Data Input/Output(MDIO) module continuouslypollsall32 MDIO addressesinorderto enumerateallPHY devicesinthesystem. The Management Data Input/Output(MDIO) module implementsthe802.3serialmanagement interfaceto interrogateand controlEthernetPHY(s) usinga shared two-wirebus. Host softwareuses the MDIO module to configurethe auto-negotiationparametersof each PHY attachedto the EMAC, retrievethe negotiationresults,and configurerequiredparametersinthe EMAC module forcorrectoperation.The module is designed to allow almost transparentoperationof the MDIO interface,with very little maintenancefromthecoreprocessor.Onlyone PHY may be connectedatany giventime.

6.16.1 MDIO Registers

Fora listofsupportedMDIO registerssee Table6-40[MDIO Registers]. Table6-40.MDIO RegisterMemory Map BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E2 4000 REV RevisionIdentificationRegister 0x01E2 4004 CONTROL MDIO ControlRegister 0x01E2 4008 ALIVE MDIO PHY AliveStatusRegister 0x01E2 400C LINK MDIO PHY LinkStatusRegister 0x01E2 4010 LINKINTRAW MDIO LinkStatusChange Interrupt(Unmasked) Register 0x01E2 4014 LINKINTMASKED MDIO LinkStatusChange Interrupt(Masked)Register 0x01E2 4018 – Reserved 0x01E2 4020 USERINTRAW MDIO User Command CompleteInterrupt(Unmasked) Register 0x01E2 4024 USERINTMASKED MDIO User Command CompleteInterrupt(Masked)Register 0x01E2 4028 USERINTMASKSET MDIO User Command CompleteInterruptMask SetRegister 0x01E2 402C USERINTMASKCLEAR MDIO User Command CompleteInterruptMask ClearRegister 0x01E2 4030 -0x01E2 407C – Reserved 0x01E2 4080 USERACCESS0 MDIO User Access Register0 0x01E2 4084 USERPHYSEL0 MDIO User PHY SelectRegister0 0x01E2 4088 USERACCESS1 MDIO User Access Register1 0x01E2 408C USERPHYSEL1 MDIO User PHY SelectRegister1 0x01E2 4090 -0x01E2 47FF – Reserved Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 93 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION MDIO_CLK MDIO_D (input) 3 3 MDIO_CLK MDIO_D (output) AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

6.16.2 Management Data Input/Output(MDIO) ElectricalData/Timing

Table6-41.Timing Requirements forMDIO Input(seeFigure6-31and Figure6-32) No. PARAMETER MIN MAX UNIT 1 tc(MDIO_CLK) Cycletime,MDIO_CLK 400 ns 2 tw(MDIO_CLK) Pulseduration,MDIO_CLK high/low 180 ns 3 tt(MDIO_CLK) Transitiontime,MDIO_CLK 5 ns 4 tsu(MDIO-MDIO_CLKH) Setuptime,MDIO_D datainputvalidbeforeMDIO_CLK high 10 ns 5 th(MDIO_CLKH-MDIO) Holdtime,MDIO_D datainputvalidafterMDIO_CLK high 10 ns Figure6-31.MDIO InputTiming Table6-42.SwitchingCharacteristicsOver Recommended OperatingConditionsforMDIO Output (seeFigure6-32) No. PARAMETER MIN MAX UNIT 7 td(MDIO_CLKL-MDIO) Delaytime,MDIO_CLK lowtoMDIO_D dataoutputvalid 0 100 ns Figure6-32.MDIO Output Timing

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ADVANCE□INFORMATION Receive Logic Clock/Frame Generator State Machine Clock Check and Serializer 0 Serializer 1 Serializer y GIO Control DIT RAM 384 C 384 U Optional Transmit Formatter Receive Formatter Transmit Logic Clock/Frame Generator State Machine McASPx (x = 0, 1, 2) Peripheral Configuration Bus McASP DMA Bus (Dedicated) AHCLKRx ACLKRx AFSRx AMUTEINx AMUTEx AFSXx ACLKXx AHCLKXx AXRx[0] AXRx[1] AXRx[y] Pins Function Receive Master Clock Receive Bit Clock Receive Left/Right Clock or Frame Sync Transmit Master Clock Transmit Bit Clock Transmit Left/Right Clock or Frame Sync Transmit/Receive Serial Data Pin Transmit/Receive Serial Data Pin Transmit/Receive Serial Data Pin Error Detection The McASPs DO NOT have dedicated AMUTEINx pins. AM1707 www.ti.com SPRS637 –FEBRUARY 2010

6.17 MultichannelAudio SerialPorts(McASP0, McASP1 ,and McASP2)

The McASP serialportisspecificallydesignedformultichannelaudioapplications.Itskey featuresare:

Flexibleclockand framesyncgenerationlogicand on-chipdividers
Up tosixteentransmitorreceivedatapinsand serializers
Largenumber ofserialdataformatoptions,including: – TDM Frames with2 to32 timeslotsperframe(periodic)or1 slotperframe(burst) – Time slotsof8,12,16,20,24,28,and 32 bits – Firstbitdelay0,1,or2 clocks – MSB orLSB firstbitorder – Left-orright-aligneddatawords withintimeslots
DIT Mode (optional)with384-bitChannelStatusand 384-bitUser Data registers
Extensiveerrorcheckingand mute generationlogic
Allunused pinsGPIO-capable
Transmit& ReceiveFIFO Buffersforeach McASP. AllowstheMcASP tooperateata highersample rateby making itmore toleranttoDMA latency.
Dynamic AdjustmentofClockDividers – ClockDividerValuemay be changed withoutresettingtheMcASP The threeMcASPs on thedeviceareconfiguredwiththefollowingoptions: Table6-43.McASP Configurations(1) Module Serializers AFIFO DIT Pins

64 Word RXMcASP0 16 N AXR0[15:0],AHCLKR0, ACLKR0, AFSR0, AHCLKX0, ACLKX0, AFSX0, AMUTE064 Word TX

64 Word RX AXR1[11:10],AXR1[8:0],AHCLKR1, ACLKR1, AFSR1, AHCLKX1, ACLKX1, AFSX1,McASP1 12 N64 Word TX AMUTE1

16 Word RXMcASP2 4 Y AXR2[3:0],AHCLKR2, ACLKR2, AFSR2, AHCLKX2, ACLKX2, AFSX2, AMUTE216 Word TX

(1) Pinsavailablearethemaximum number ofpinsthatmay be configuredfora particularMcASP; notincludingpinmultiplexing. Figure6-33.McASP Block Diagram Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 95 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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6.17.1 McASP PeripheralRegistersDescription(s)

Registersforthe McASP are summarized in Table 6-44. The registersare accessed throughthe peripheralconfigurationport.The receivebufferregisters(RBUF) and transmitbufferregisters(XBUF) can alsobe accessedthroughtheDMA port,as listedinTable6-45 RegistersfortheMcASP Audio FIFO (AFIFO)are summarized inTable6-46.Note thattheAFIFO Write FIFO (WFIFO) and Read FIFO (RFIFO)have independentcontroland statusregisters.The AFIFO control registersareaccessedthroughtheperipheralconfigurationport. Table6-44.McASP RegistersAccessed Through PeripheralConfigurationPort McASP0 McASP1 McASP2 ACRONYM REGISTER DESCRIPTION BYTE BYTE BYTE ADDRESS ADDRESS ADDRESS 0x01D0 0000 0x01D0 4000 0x01D0 8000 REV Revisionidentificationregister 0x01D0 0010 0x01D0 4010 0x01D0 8010 PFUNC Pinfunctionregister 0x01D0 0014 0x01D0 4014 0x01D0 8014 PDIR Pindirectionregister 0x01D0 0018 0x01D0 4018 0x01D0 8018 PDOUT Pindataoutputregister 0x01D0 001C 0x01D0 401C 0x01D0 801C PDIN Read returns:Pindatainputregister 0x01D0 001C 0x01D0 401C 0x01D0 801C PDSET Writesaffect:Pindatasetregister(alternatewriteaddress:PDOUT) 0x01D0 0020 0x01D0 4020 0x01D0 8020 PDCLR Pindataclearregister(alternatewriteaddress:PDOUT) 0x01D0 0044 0x01D0 4044 0x01D0 8044 GBLCTL Globalcontrolregister 0x01D0 0048 0x01D0 4048 0x01D0 8048 AMUTE Audiomute controlregister 0x01D0 004C 0x01D0 404C 0x01D0 804C DLBCTL Digitalloopbackcontrolregister 0x01D0 0050 0x01D0 4050 0x01D0 8050 DITCTL DIT mode controlregister 0x01D0 0060 0x01D0 4060 0x01D0 8060 RGBLCTL Receiverglobalcontrolregister:AliasofGBLCTL, onlyreceivebitsare affected-allowsreceivertobe resetindependentlyfromtransmitter 0x01D0 0064 0x01D0 4064 0x01D0 8064 RMASK Receiveformatunitbitmask register 0x01D0 0068 0x01D0 4068 0x01D0 8068 RFMT Receivebitstreamformatregister 0x01D0 006C 0x01D0 406C 0x01D0 806C AFSRCTL Receiveframesynccontrolregister 0x01D0 0070 0x01D0 4070 0x01D0 8070 ACLKRCTL Receiveclockcontrolregister 0x01D0 0074 0x01D0 4074 0x01D0 8074 AHCLKRCTL Receivehigh-frequencyclockcontrolregister 0x01D0 0078 0x01D0 4078 0x01D0 8078 RTDM ReceiveTDM timeslot0-31register 0x01D0 007C 0x01D0 407C 0x01D0 807C RINTCTL Receiverinterruptcontrolregister 0x01D0 0080 0x01D0 4080 0x01D0 8080 RSTAT Receiverstatusregister 0x01D0 0084 0x01D0 4084 0x01D0 8084 RSLOT CurrentreceiveTDM timeslotregister 0x01D0 0088 0x01D0 4088 0x01D0 8088 RCLKCHK Receiveclockcheckcontrolregister 0x01D0 008C 0x01D0 408C 0x01D0 808C REVTCTL ReceiverDMA eventcontrolregister 0x01D0 00A0 0x01D0 40A0 0x01D0 80A0 XGBLCTL Transmitterglobalcontrolregister.AliasofGBLCTL, onlytransmitbitsare affected-allowstransmittertobe resetindependentlyfromreceiver 0x01D0 00A4 0x01D0 40A4 0x01D0 80A4 XMASK Transmitformatunitbitmask register 0x01D0 00A8 0x01D0 40A8 0x01D0 80A8 XFMT Transmitbitstreamformatregister 0x01D0 00AC 0x01D0 40AC 0x01D0 80AC AFSXCTL Transmitframesynccontrolregister 0x01D0 00B0 0x01D0 40B0 0x01D0 80B0 ACLKXCTL Transmitclockcontrolregister 0x01D0 00B4 0x01D0 40B4 0x01D0 80B4 AHCLKXCTL Transmithigh-frequencyclockcontrolregister 0x01D0 00B8 0x01D0 40B8 0x01D0 80B8 XTDM TransmitTDM timeslot0-31register 0x01D0 00BC 0x01D0 40BC 0x01D0 80BC XINTCTL Transmitterinterruptcontrolregister 0x01D0 00C0 0x01D0 40C0 0x01D0 80C0 XSTAT Transmitterstatusregister 0x01D0 00C4 0x01D0 40C4 0x01D0 80C4 XSLOT CurrenttransmitTDM timeslotregister 0x01D0 00C8 0x01D0 40C8 0x01D0 80C8 XCLKCHK Transmitclockcheckcontrolregister 0x01D0 00CC 0x01D0 40CC 0x01D0 80CC XEVTCTL TransmitterDMA eventcontrolregister 0x01D0 0100 0x01D0 4100 0x01D0 8100 DITCSRA0 Left(evenTDM timeslot)channelstatusregister(DITmode) 0

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-44.McASP RegistersAccessed Through PeripheralConfigurationPort(continued) McASP0 McASP1 McASP2 ACRONYM REGISTER DESCRIPTION BYTE BYTE BYTE ADDRESS ADDRESS ADDRESS 0x01D0 0104 0x01D0 4104 0x01D0 8104 DITCSRA1 Left(evenTDM timeslot)channelstatusregister(DITmode) 1 0x01D0 0108 0x01D0 4108 0x01D0 8108 DITCSRA2 Left(evenTDM timeslot)channelstatusregister(DITmode) 2 0x01D0 010C 0x01D0 410C 0x01D0 810C DITCSRA3 Left(evenTDM timeslot)channelstatusregister(DITmode) 3 0x01D0 0110 0x01D0 4110 0x01D0 8110 DITCSRA4 Left(evenTDM timeslot)channelstatusregister(DITmode) 4 0x01D0 0114 0x01D0 4114 0x01D0 8114 DITCSRA5 Left(evenTDM timeslot)channelstatusregister(DITmode) 5 0x01D0 0118 0x01D0 4118 0x01D0 8118 DITCSRB0 Right(oddTDM timeslot)channelstatusregister(DITmode) 0 0x01D0 011C 0x01D0 411C 0x01D0 811C DITCSRB1 Right(oddTDM timeslot)channelstatusregister(DITmode) 1 0x01D0 0120 0x01D0 4120 0x01D0 8120 DITCSRB2 Right(oddTDM timeslot)channelstatusregister(DITmode) 2 0x01D0 0124 0x01D0 4124 0x01D0 8124 DITCSRB3 Right(oddTDM timeslot)channelstatusregister(DITmode) 3 0x01D0 0128 0x01D0 4128 0x01D0 8128 DITCSRB4 Right(oddTDM timeslot)channelstatusregister(DITmode) 4 0x01D0 012C 0x01D0 412C 0x01D0 812C DITCSRB5 Right(oddTDM timeslot)channelstatusregister(DITmode) 5 0x01D0 0130 0x01D0 4130 0x01D0 8130 DITUDRA0 Left(evenTDM timeslot)channeluserdataregister(DITmode) 0 0x01D0 0134 0x01D0 4134 0x01D0 8134 DITUDRA1 Left(evenTDM timeslot)channeluserdataregister(DITmode) 1 0x01D0 0138 0x01D0 4138 0x01D0 8138 DITUDRA2 Left(evenTDM timeslot)channeluserdataregister(DITmode) 2 0x01D0 013C 0x01D0 413C 0x01D0 813C DITUDRA3 Left(evenTDM timeslot)channeluserdataregister(DITmode) 3 0x01D0 0140 0x01D0 4140 0x01D0 8140 DITUDRA4 Left(evenTDM timeslot)channeluserdataregister(DITmode) 4 0x01D0 0144 0x01D0 4144 0x01D0 8144 DITUDRA5 Left(evenTDM timeslot)channeluserdataregister(DITmode) 5 0x01D0 0148 0x01D0 4148 0x01D0 8148 DITUDRB0 Right(oddTDM timeslot)channeluserdataregister(DITmode) 0 0x01D0 014C 0x01D0 414C 0x01D0 814C DITUDRB1 Right(oddTDM timeslot)channeluserdataregister(DITmode) 1 0x01D0 0150 0x01D0 4150 0x01D0 8150 DITUDRB2 Right(oddTDM timeslot)channeluserdataregister(DITmode) 2 0x01D0 0154 0x01D0 4154 0x01D0 8154 DITUDRB3 Right(oddTDM timeslot)channeluserdataregister(DITmode) 3 0x01D0 0158 0x01D0 4158 0x01D0 8158 DITUDRB4 Right(oddTDM timeslot)channeluserdataregister(DITmode) 4 0x01D0 015C 0x01D0 415C 0x01D0 815C DITUDRB5 Right(oddTDM timeslot)channeluserdataregister(DITmode) 5 0x01D0 0180 0x01D0 4180 0x01D0 8180 SRCTL0 Serializercontrolregister0 0x01D0 0184 0x01D0 4184 0x01D0 8184 SRCTL1 Serializercontrolregister1 0x01D0 0188 0x01D0 4188 0x01D0 8188 SRCTL2 Serializercontrolregister2 0x01D0 018C 0x01D0 418C 0x01D0 818C SRCTL3 Serializercontrolregister3 0x01D0 0190 0x01D0 4190 0x01D0 8190 SRCTL4 Serializercontrolregister4 0x01D0 0194 0x01D0 4194 0x01D0 8194 SRCTL5 Serializercontrolregister5 0x01D0 0198 0x01D0 4198 0x01D0 8198 SRCTL6 Serializercontrolregister6 0x01D0 019C 0x01D0 419C 0x01D0 819C SRCTL7 Serializercontrolregister7 0x01D0 01A0 0x01D0 41A0 0x01D0 81A0 SRCTL8 Serializercontrolregister8 0x01D0 01A4 0x01D0 41A4 0x01D0 81A4 SRCTL9 Serializercontrolregister9 0x01D0 01A8 0x01D0 41A8 0x01D0 81A8 SRCTL10 Serializercontrolregister10 0x01D0 01AC 0x01D0 41AC 0x01D0 81AC SRCTL11 Serializercontrolregister11 0x01D0 01B0 0x01D0 41B0 0x01D0 81B0 SRCTL12 Serializercontrolregister12 0x01D0 01B4 0x01D0 41B4 0x01D0 81B4 SRCTL13 Serializercontrolregister13 0x01D0 01B8 0x01D0 41B8 0x01D0 81B8 SRCTL14 Serializercontrolregister14 0x01D0 01BC 0x01D0 41BC 0x01D0 81BC SRCTL15 Serializercontrolregister15 0x01D0 0200 0x01D0 4200 0x01D0 8200 XBUF0 (1) Transmitbufferregisterforserializer0 0x01D0 0204 0x01D0 4204 0x01D0 8204 XBUF1 (1) Transmitbufferregisterforserializer1 0x01D0 0208 0x01D0 4208 0x01D0 8208 XBUF2 (1) Transmitbufferregisterforserializer2 0x01D0 020C 0x01D0 420C 0x01D0 820C XBUF3 (1) Transmitbufferregisterforserializer3 0x01D0 0210 0x01D0 4210 0x01D0 8210 XBUF4 (1) Transmitbufferregisterforserializer4 0x01D0 0214 0x01D0 4214 0x01D0 8214 XBUF5 (1) Transmitbufferregisterforserializer5 (1) WritestoXRBUF originatefromperipheralconfigurationportonlywhen XBUSEL = 1 inXFMT. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 97 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-44.McASP RegistersAccessed Through PeripheralConfigurationPort(continued) McASP0 McASP1 McASP2 ACRONYM REGISTER DESCRIPTION BYTE BYTE BYTE ADDRESS ADDRESS ADDRESS 0x01D0 0218 0x01D0 4218 0x01D0 8218 XBUF6 (1) Transmitbufferregisterforserializer6 0x01D0 021C 0x01D0 421C 0x01D0 821C XBUF7 (1) Transmitbufferregisterforserializer7 0x01D0 0220 0x01D0 4220 0x01D0 8220 XBUF8 (1) Transmitbufferregisterforserializer8 0x01D0 0224 0x01D0 4224 0x01D0 8224 XBUF9 (1) Transmitbufferregisterforserializer9 0x01D0 0228 0x01D0 4228 0x01D0 8228 XBUF10 (1) Transmitbufferregisterforserializer10 0x01D0 022C 0x01D0 422C 0x01D0 822C XBUF11 (1) Transmitbufferregisterforserializer11 0x01D0 0230 0x01D0 4230 0x01D0 8230 XBUF12 (1) Transmitbufferregisterforserializer12 0x01D0 0234 0x01D0 4234 0x01D0 8234 XBUF13 (1) Transmitbufferregisterforserializer13 0x01D0 0238 0x01D0 4238 0x01D0 8238 XBUF14 (1) Transmitbufferregisterforserializer14 0x01D0 023C 0x01D0 423C 0x01D0 823C XBUF15 (1) Transmitbufferregisterforserializer15 0x01D0 0280 0x01D0 4280 0x01D0 8280 RBUF0 (2) Receivebufferregisterforserializer0 0x01D0 0284 0x01D0 4284 0x01D0 8284 RBUF1 (2) Receivebufferregisterforserializer1 0x01D0 0288 0x01D0 4288 0x01D0 8288 RBUF2 (2) Receivebufferregisterforserializer2 0x01D0 028C 0x01D0 428C 0x01D0 828C RBUF3 (2) Receivebufferregisterforserializer3 0x01D0 0290 0x01D0 4290 0x01D0 8290 RBUF4 (3) Receivebufferregisterforserializer4 0x01D0 0294 0x01D0 4294 0x01D0 8294 RBUF5 (3) Receivebufferregisterforserializer5 0x01D0 0298 0x01D0 4298 0x01D0 8298 RBUF6 (3) Receivebufferregisterforserializer6 0x01D0 029C 0x01D0 429C 0x01D0 829C RBUF7 (3) Receivebufferregisterforserializer7 0x01D0 02A0 0x01D0 42A0 0x01D0 82A0 RBUF8 (3) Receivebufferregisterforserializer8 0x01D0 02A4 0x01D0 42A4 0x01D0 82A4 RBUF9 (3) Receivebufferregisterforserializer9 0x01D0 02A8 0x01D0 42A8 0x01D0 82A8 RBUF10 (3) Receivebufferregisterforserializer10 0x01D0 02AC 0x01D0 42AC 0x01D0 82AC RBUF11 (3) Receivebufferregisterforserializer11 0x01D0 02B0 0x01D0 42B0 0x01D0 82B0 RBUF12 (3) Receivebufferregisterforserializer12 0x01D0 02B4 0x01D0 42B4 0x01D0 82B4 RBUF13 (3) Receivebufferregisterforserializer13 0x01D0 02B8 0x01D0 42B8 0x01D0 82BB RBUF14 (3) Receivebufferregisterforserializer14 0x01D0 02BC 0x01D0 42BC 0x01D0 82BC RBUF15 (3) Receivebufferregisterforserializer15 (2) Reads fromXRBUF originateon peripheralconfigurationportonlywhen RBUSEL = 1 inRFMT. (3) Reads fromXRBUF originateon peripheralconfigurationportonlywhen RBUSEL = 1 inRFMT. Table6-45.McASP RegistersAccessed Through DMA Port McASP0 McASP1 McASP2 BYTE BYTE BYTE ACRONYM REGISTER DESCRIPTION ADDRESS ADDRESS ADDRESS ReceivebufferDMA portaddress.Cyclesthroughreceive serializers,skippingovertransmitserializersand inactiveRead 01D0 2000 01D0 6000 01D0 A000 RBUF serializers.StartsatthelowestserializeratthebeginningofAccesses each timeslot.Reads fromDMA portonlyifXBUSEL = 0 in XFMT. TransmitbufferDMA portaddress.Cyclesthroughtransmit Write serializers,skippingoverreceiveand inactiveserializers.01D0 2000 01D0 6000 01D0 A000 XBUFAccesses Startsatthelowestserializeratthebeginningofeach time slot.WritestoDMA portonlyifRBUSEL = 0 inRFMT. Table6-46.McASP AFIFO RegistersAccessed Through PeripheralConfigurationPort McASP0 McASP1 McASP2 ACRONYM REGISTER DESCRIPTION BYTE ADDRESS BYTE ADDRESS BYTE ADDRESS 0x01D0 1000 0x01D0 5000 0x01D0 9000 AFIFOREV AFIFO revisionidentificationregister 0x01D0 1010 0x01D0 5010 0x01D0 9010 WFIFOCTL WriteFIFO controlregister

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-46.McASP AFIFO RegistersAccessed Through PeripheralConfigurationPort(continued) McASP0 McASP1 McASP2 ACRONYM REGISTER DESCRIPTION BYTE ADDRESS BYTE ADDRESS BYTE ADDRESS 0x01D0 1014 0x01D0 5014 0x01D0 9014 WFIFOSTS WriteFIFO statusregister 0x01D0 1018 0x01D0 5018 0x01D0 9018 RFIFOCTL Read FIFO controlregister 0x01D0 101C 0x01D0 501C 0x01D0 901C RFIFOSTS Read FIFO statusregister Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 99 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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6.17.2 McASP ElectricalData/Timing

6.17.2.1MultichannelAudio SerialPort0 (McASP0) Timing Table6-47and Table6-48assume testingoverrecommended operatingconditions(seeFigure6-34and Figure6-35). Table6-47.McASP0 Timing Requirements(1)(2) No. PARAMETER MIN MAX UNIT Cycletime,AHCLKR0 external,AHCLKR0 input 20 1 tc(AHCLKRX) ns Cycletime,AHCLKX0 external,AHCLKX0 input 20 Pulseduration,AHCLKR0 external,AHCLKR0 input 10 2 tw(AHCLKRX) ns Pulseduration,AHCLKX0 external,AHCLKX0 input 10 Cycletime,ACLKR0 external,ACLKR0 input greaterof2P or20 3 tc(ACLKRX) ns Cycletime,ACLKX0 external,ACLKX0 input greaterof2P or20 Pulseduration,ACLKR0 external,ACLKR0 input 10 4 tw(ACLKRX) ns Pulseduration,ACLKX0 external,ACLKX0 input 10 Setuptime,AFSR0 inputtoACLKR0 internal(3) 9.4 Setuptime,AFSX0 inputtoACLKX0 internal 9.4 Setuptime,AFSR0 inputtoACLKR0 externalinput(3) 3 5 tsu(AFSRX-ACLKRX) ns Setuptime,AFSX0 inputtoACLKX0 externalinput 3 Setuptime,AFSR0 inputtoACLKR0 externaloutput(3) 3 Setuptime,AFSX0 inputtoACLKX0 externaloutput 3 Holdtime,AFSR0 inputafterACLKR0 internal(3) -1.9 Holdtime,AFSX0 inputafterACLKX0 internal -1.9 Holdtime,AFSR0 inputafterACLKR0 externalinput(3) 0.5 6 th(ACLKRX-AFSRX) ns Holdtime,AFSX0 inputafterACLKX0 externalinput 0.8 Holdtime,AFSR0 inputafterACLKR0 externaloutput(3) 0.5 Holdtime,AFSX0 inputafterACLKX0 externaloutput 0.5 Setuptime,AXR0[n]inputtoACLKR0 internal(3) 9.4 Setuptime,AXR0[n]inputtoACLKX0 internal(4) 9.4 Setuptime,AXR0[n]inputtoACLKR0 externalinput(3) 3 7 tsu(AXR-ACLKRX) ns Setuptime,AXR0[n]inputtoACLKX0 externalinput(4) 3 Setuptime,AXR0[n]inputtoACLKR0 externaloutput(3) 3 Setuptime,AXR0[n]inputtoACLKX0 externaloutput(4) 3 Holdtime,AXR0[n]inputafterACLKR0 internal(3) -1.7 Holdtime,AXR0[n]inputafterACLKX0 internal(4) -1.7 Holdtime,AXR0[n]inputafterACLKR0 externalinput(3) 0.6 8 th(ACLKRX-AXR) ns Holdtime,AXR0[n]inputafterACLKX0 externalinput(4) 0.6 Holdtime,AXR0[n]inputafterACLKR0 externaloutput(3) 0.6 Holdtime,AXR0[n]inputafterACLKX0 externaloutput(4) 0.6 (1) ACLKX0 internal– McASP0 ACLKXCTL.CLKXM = 1,PDIR.ACLKX = 1 ACLKX0 externalinput– McASP0 ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 0 ACLKX0 externaloutput– McASP0 ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 1 ACLKR0 internal– McASP0 ACLKRCTL.CLKRM = 1,PDIR.ACLKR =1 ACLKR0 externalinput– McASP0 ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 0 ACLKR0 externaloutput– McASP0 ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 1 (2) P = SYSCLK2 period (3) McASP0 ACLKXCTL.ASYNC=1: Receiverisclockedby itsown ACLKR0 (4) McASP0 ACLKXCTL.ASYNC=0: Receiverisclockedby transmitter's ACLKX0

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-48.McASP0 SwitchingCharacteristics(1) No. PARAMETER MIN MAX UNIT Cycletime,AHCLKR0 internal,AHCLKR0 output 20 Cycletime,AHCLKR0 external,AHCLKR0 output 20 9 tc(AHCLKRX) ns Cycletime,AHCLKX0 internal,AHCLKX0 output 20 Cycletime,AHCLKX0 external,AHCLKX0 output 20 Pulseduration,AHCLKR0 internal,AHCLKR0 output (AHR/2)– 2.5(2) Pulseduration,AHCLKR0 external,AHCLKR0 output (AHR/2)– 2.5(2) 10 tw(AHCLKRX) ns Pulseduration,AHCLKX0 internal,AHCLKX0 output (AHX/2)– 2.5(3) Pulseduration,AHCLKX0 external,AHCLKX0 output (AHX/2)– 2.5(3) Cycletime,ACLKR0 internal,ACLKR0 output greaterof2P or20 ns(4) Cycletime,ACLKR0 external,ACLKR0 output greaterof2P or20 ns(4) 11 tc(ACLKRX) ns Cycletime,ACLKX0 internal,ACLKX0 output greaterof2P or20 ns(4) Cycletime,ACLKX0 external,ACLKX0 output greaterof2P or20 ns(4) Pulseduration,ACLKR0 internal,ACLKR0 output (AR/2)– 2.5(5) Pulseduration,ACLKR0 external,ACLKR0 output (AR/2)– 2.5(5) 12 tw(ACLKRX) ns Pulseduration,ACLKX0 internal,ACLKX0 output (AX/2)– 2.5(6) Pulseduration,ACLKX0 external,ACLKX0 output (AX/2)– 2.5(6) Delaytime,ACLKR0 internal,AFSR output(7) 0 6 Delaytime,ACLKX0 internal,AFSX output 0 6 Delaytime,ACLKR0 externalinput,AFSR output(7) 3 11.7 13 td(ACLKRX-AFSRX) ns Delaytime,ACLKX0 externalinput,AFSX output 3 11.7 Delaytime,ACLKR0 externaloutput,AFSR output(7) 3 11.7 Delaytime,ACLKX0 externaloutput,AFSX output 3 11.7 Delaytime,ACLKX0 internal,AXR0[n]output 0 6 14 td(ACLKX-AXRV) Delaytime,ACLKX0 externalinput,AXR0[n]output 2.75 11.7 ns Delaytime,ACLKX0 externaloutput,AXR0[n]output 3 11.7 Disabletime,ACLKX0 internal,AXR0[n]output 0 6 15 tdis(ACLKX-AXRHZ) Disabletime,ACLKX0 externalinput,AXR0[n]output 3 11.7 ns Disabletime,ACLKX0 externaloutput,AXR0[n]output 3 11.7 (1) McASP0 ACLKX0 internal– ACLKXCTL.CLKXM = 1,PDIR.ACLKX = 1 ACLKX0 externalinput– McASP0 ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 0 ACLKX0 externaloutput– McASP0ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 1 ACLKR0 internal– McASP0 ACLKR0CTL.CLKRM = 1,PDIR.ACLKR =1 ACLKR0 externalinput– McASP0 ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 0 ACLKR0 externaloutput– McASP0 ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 1 (2) AHR -Cycletime,AHCLKR0. (3) AHX -Cycletime,AHCLKX0. (4) P = SYSCLK2 period (5) AR -ACLKR0 period. (6) AX -ACLKX0 period. (7) McASP0 ACLKXCTL.ASYNC=1: Receiverisclockedby itsown ACLKR0 Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 101 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com 6.17.2.2MultichannelAudio SerialPort1 (McASP1) Timing Table6-49and Table6-50assume testingoverrecommended operatingconditions(seeFigure6-34and Figure6-35). Table6-49.McASP1 Timing Requirements(1)(2) No. PARAMETER MIN MAX UNIT Cycletime,AHCLKR1 external,AHCLKR1 input 20 1 tc(AHCLKRX) ns Cycletime,AHCLKX1 external,AHCLKX1 input 20 Pulseduration,AHCLKR1 external,AHCLKR1 input 10 2 tw(AHCLKRX) ns Pulseduration,AHCLKX1 external,AHCLKX1 input 10 Cycletime,ACLKR1 external,ACLKR1 input greaterof2P or20 3 tc(ACLKRX) ns Cycletime,ACLKX1 external,ACLKX1 input greaterof2P or20 Pulseduration,ACLKR1 external,ACLKR1 input 10 4 tw(ACLKRX) ns Pulseduration,ACLKX1 external,ACLKX1 input 10 Setuptime,AFSR1 inputtoACLKR1 internal(3) 10.4 Setuptime,AFSX1 inputtoACLKX1 internal 10.4 Setuptime,AFSR1 inputtoACLKR1 externalinput(3) 2.6 5 tsu(AFSRX-ACLKRX) ns Setuptime,AFSX1 inputtoACLKX1 externalinput 2.6 Setuptime,AFSR1 inputtoACLKR1 externaloutput(3) 2.6 Setuptime,AFSX1 inputtoACLKX1 externaloutput 2.6 Holdtime,AFSR1 inputafterACLKR1 internal(3) -2.4 Holdtime,AFSX1 inputafterACLKX1 internal -2.4 Holdtime,AFSR1 inputafterACLKR1 externalinput(3) 0.85 6 th(ACLKRX-AFSRX) ns Holdtime,AFSX1 inputafterACLKX1 externalinput 0.8 Holdtime,AFSR1 inputafterACLKR1 externaloutput(3) 0.3 Holdtime,AFSX1 inputafterACLKX1 externaloutput 0.3 Setuptime,AXR1[n]inputtoACLKR1 internal(3) 10.4 Setuptime,AXR1[n]inputtoACLKX1 internal(4) 10.4 Setuptime,AXR1[n]inputtoACLKR1 externalinput(3) 2.6 7 tsu(AXR-ACLKRX) ns Setuptime,AXR1[n]inputtoACLKX1 externalinput(4) 2.6 Setuptime,AXR1[n]inputtoACLKR1 externaloutput(3) 2.6 Setuptime,AXR1[n]inputtoACLKX1 externaloutput(4) 2.6 Holdtime,AXR1[n]inputafterACLKR1 internal(3) -2.4 Holdtime,AXR1[n]inputafterACLKX1 internal(4) -2.4 Holdtime,AXR1[n]inputafterACLKR1 externalinput(3) 0.65 8 th(ACLKRX-AXR) ns Holdtime,AXR1[n]inputafterACLKX1 externalinput(4) 0.4 Holdtime,AXR1[n]inputafterACLKR1 externaloutput(3) 0.4 Holdtime,AXR1[n]inputafterACLKX1 externaloutput(4) 0.4 (1) ACLKX1 internal– McASP1 ACLKXCTL.CLKXM = 1,PDIR.ACLKX = 1 ACLKX1 externalinput– McASP1 ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 0 ACLKX1 externaloutput– McASP1 ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 1 ACLKR1 internal– McASP1 ACLKRCTL.CLKRM = 1,PDIR.ACLKR =1 ACLKR1 externalinput– McASP1 ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 0 ACLKR1 externaloutput– McASP1 ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 1 (2) P = SYSCLK2 period (3) McASP1 ACLKXCTL.ASYNC=1: Receiverisclockedby itsown ACLKR1 (4) McASP1 ACLKXCTL.ASYNC=0: Receiverisclockedby transmitter's ACLKX1

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-50.McASP1 SwitchingCharacteristics(1) No. PARAMETER MIN MAX UNIT Cycletime,AHCLKR1 internal,AHCLKR1 output 20 Cycletime,AHCLKR1 external,AHCLKR1 output 20 9 tc(AHCLKRX) ns Cycletime,AHCLKX1 internal,AHCLKX1 output 20 Cycletime,AHCLKX1 external,AHCLKX1 output 20 Pulseduration,AHCLKR1 internal,AHCLKR1 output (AHR/2)– 2.5(2) Pulseduration,AHCLKR1 external,AHCLKR1 output (AHR/2)– 2.5(2) 10 tw(AHCLKRX) ns Pulseduration,AHCLKX1 internal,AHCLKX1 output (AHX/2)– 2.5(3) Pulseduration,AHCLKX1 external,AHCLKX1 output (AHX/2)– 2.5(3) Cycletime,ACLKR1 internal,ACLKR1 output greaterof2P or20 ns(4) Cycletime,ACLKR1 external,ACLKR1 output greaterof2P or20 ns(4) 11 tc(ACLKRX) ns Cycletime,ACLKX1 internal,ACLKX1 output greaterof2P or20 ns(4) Cycletime,ACLKX1 external,ACLKX1 output greaterof2P or20 ns(4) Pulseduration,ACLKR1 internal,ACLKR1 output (AR/2)– 2.5(5) Pulseduration,ACLKR1 external,ACLKR1 output (AR/2)– 2.5(5) 12 tw(ACLKRX) ns Pulseduration,ACLKX1 internal,ACLKX1 output (AX/2)– 2.5(6) Pulseduration,ACLKX1 external,ACLKX1 output (AX/2)– 2.5(6) Delaytime,ACLKR1 internal,AFSR output(7) 0.5 6.7 Delaytime,ACLKX1 internal,AFSX output 0.5 6.7 Delaytime,ACLKR1 externalinput,AFSR output(7) 3.9 13.8 13 td(ACLKRX-AFSRX) ns Delaytime,ACLKX1 externalinput,AFSX output 3.9 13.8 Delaytime,ACLKR1 externaloutput,AFSR output(7) 3.9 13.8 Delaytime,ACLKX1 externaloutput,AFSX output 3.9 13.8 Delaytime,ACLKX1 internal,AXR1[n]output 0.5 6.7 14 td(ACLKX-AXRV) Delaytime,ACLKX1 externalinput,AXR1[n]output 3.8 13.8 ns Delaytime,ACLKX1 externaloutput,AXR1[n]output 3.9 13.8 Disabletime,ACLKX1 internal,AXR1[n]output 0.5 6.7 15 tdis(ACLKX-AXRHZ) Disabletime,ACLKX1 externalinput,AXR1[n]output 3.9 13.8 ns Disabletime,ACLKX1 externaloutput,AXR1[n]output 3.9 13.8 (1) McASP1 ACLKX1 internal– ACLKXCTL.CLKXM = 1,PDIR.ACLKX = 1 McASP1 ACLKX1 externalinput– ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 0 McASP1 ACLKX1 externaloutput– ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 1 McASP1 ACLKR1 internal– ACLKR1CTL.CLKRM = 1,PDIR.ACLKR =1 McASP1 ACLKR1 externalinput– ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 0 McASP1 ACLKR1 externaloutput– ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 1 (2) AHR -Cycletime,AHCLKR1. (3) AHX -Cycletime,AHCLKX1. (4) P = SYSCLK2 period (5) AR -ACLKR1 period. (6) AX -ACLKX1 period. (7) McASP1 ACLKXCTL.ASYNC=1: Receiverisclockedby itsown ACLKR1 Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 103 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com 6.17.2.3MultichannelAudio SerialPort2 (McASP2) Timing Table6-51and Table6-52assume testingoverrecommended operatingconditions(seeFigure6-34and Figure6-35). Table6-51.McASP2 Timing Requirements(1)(2) No. PARAMETER MIN MAX UNIT Cycletime,AHCLKR2 external,AHCLKR2 input 13 1 tc(AHCLKRX) ns Cycletime,AHCLKX2 external,AHCLKX2 input 13 Pulseduration,AHCLKR2 external,AHCLKR2 input 6.5 2 tw(AHCLKRX) ns Pulseduration,AHCLKX2 external,AHCLKX2 input 6.5 Cycletime,ACLKR2 external,ACLKR2 input greaterof2P or13 3 tc(ACLKRX) ns Cycletime,ACLKX2 external,ACLKX2 input greaterof2P or13 Pulseduration,ACLKR2 external,ACLKR2 input 6.5 4 tw(ACLKRX) ns Pulseduration,ACLKX2 external,ACLKX2 input 6.5 Setuptime,AFSR2 inputtoACLKR2 internal(3) 10 Setuptime,AFSX2 inputtoACLKX2 internal 10 Setuptime,AFSR2 inputtoACLKR2 externalinput(3) 1.6 5 tsu(AFSRX-ACLKRX) ns Setuptime,AFSX2 inputtoACLKX2 externalinput 1.6 Setuptime,AFSR2 inputtoACLKR2 externaloutput(3) 1.6 Setuptime,AFSX2 inputtoACLKX2 externaloutput 1.6 Holdtime,AFSR2 inputafterACLKR2 internal(3) -1.9 Holdtime,AFSX2 inputafterACLKX2 internal -2 Holdtime,AFSR2 inputafterACLKR2 externalinput(3) 1.4 6 th(ACLKRX-AFSRX) ns Holdtime,AFSX2 inputafterACLKX2 externalinput 1.4 Holdtime,AFSR2 inputafterACLKR2 externaloutput(3) 1.4 Holdtime,AFSX2 inputafterACLKX2 externaloutput 1.4 Setuptime,AXR2[n]inputtoACLKR2 internal(3) 10 Setuptime,AXR2[n]inputtoACLKX2 internal(4) 10 Setuptime,AXR2[n]inputtoACLKR2 externalinput(3) 1.6 7 tsu(AXR-ACLKRX) ns Setuptime,AXR2[n]inputtoACLKX2 externalinput(4) 1.6 Setuptime,AXR2[n]inputtoACLKR2 externaloutput(3) 1.6 Setuptime,AXR2[n]inputtoACLKX2 externaloutput(4) 1.6 Holdtime,AXR2[n]inputafterACLKR2 internal(3) -2.2 Holdtime,AXR2[n]inputafterACLKX2 internal(4) -2.2 Holdtime,AXR2[n]inputafterACLKR2 externalinput(3) 1.3 8 th(ACLKRX-AXR) ns Holdtime,AXR2[n]inputafterACLKX2 externalinput(4) 1.3 Holdtime,AXR2[n]inputafterACLKR2 externaloutput(3) 1.3 Holdtime,AXR2[n]inputafterACLKX2 externaloutput(4) 1.3 (1) ACLKX2 internal– McASP2 ACLKXCTL.CLKXM = 1,PDIR.ACLKX = 1 ACLKX2 externalinput– McASP2 ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 0 ACLKX2 externaloutput– McASP2 ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 1 ACLKR2 internal– McASP2 ACLKRCTL.CLKRM = 1,PDIR.ACLKR =1 ACLKR2 externalinput– McASP2 ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 0 ACLKR2 externaloutput– McASP2 ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 1 (2) P = SYSCLK2 period (3) McASP2 ACLKXCTL.ASYNC=1: Receiverisclockedby itsown ACLKR2 (4) McASP2 ACLKXCTL.ASYNC=0: Receiverisclockedby transmitter's ACLKX2

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-52.McASP2 SwitchingCharacteristics(1) No. PARAMETER MIN MAX UNIT Cycletime,AHCLKR2 internal,AHCLKR2 output 13 Cycletime,AHCLKR2 external,AHCLKR2 output 13 9 tc(AHCLKRX) ns Cycletime,AHCLKX2 internal,AHCLKX2 output 13 Cycletime,AHCLKX2 external,AHCLKX2 output 13 Pulseduration,AHCLKR2 internal,AHCLKR2 output (AHR/2)– 2.5(2) Pulseduration,AHCLKR2 external,AHCLKR2 output (AHR/2)– 2.5(2) 10 tw(AHCLKRX) ns Pulseduration,AHCLKX2 internal,AHCLKX2 output (AHX/2)– 2.5(3) Pulseduration,AHCLKX2 external,AHCLKX2 output (AHX/2)– 2.5(3) Cycletime,ACLKR2 internal,ACLKR2 output greaterof2P or13 ns(4) Cycletime,ACLKR2 external,ACLKR2 output greaterof2P or13 ns(4) 11 tc(ACLKRX) ns Cycletime,ACLKX2 internal,ACLKX2 output greaterof2P or13 ns(4) Cycletime,ACLKX2 external,ACLKX2 output greaterof2P or13 ns(4) Pulseduration,ACLKR2 internal,ACLKR2 output (AR/2)– 2.5(5) Pulseduration,ACLKR2 external,ACLKR2 output (AR/2)– 2.5(5) 12 tw(ACLKRX) ns Pulseduration,ACLKX2 internal,ACLKX2 output (AX/2)– 2.5(6) Pulseduration,ACLKX2 external,ACLKX2 output (AX/2)– 2.5(6) Delaytime,ACLKR2 internal,AFSR output(7) -1.4 2.8 Delaytime,ACLKX2 internal,AFSX output -1.4 2.8 Delaytime,ACLKR2 externalinput,AFSR output(7) 2.6 10 13 td(ACLKRX-AFSRX) ns Delaytime,ACLKX2 externalinput,AFSX output 2.9 10 Delaytime,ACLKR2 externaloutput,AFSR output(7) 2.9 10 Delaytime,ACLKX2 externaloutput,AFSX output 2.9 10 Delaytime,ACLKX2 internal,AXR2[n]output -1.4 2.8 14 td(ACLKX-AXRV) Delaytime,ACLKX2 externalinput,AXR2[n]output 2.75 10 ns Delaytime,ACLKX2 externaloutput,AXR2[n]output 2.75 10 Disabletime,ACLKX2 internal,AXR2[n]output -1.4 2.8 15 tdis(ACLKX-AXRHZ) Disabletime,ACLKX2 externalinput,AXR2[n]output 2.9 10 ns Disabletime,ACLKX2 externaloutput,AXR2[n]output 2.9 10 (1) McASP2 ACLKX2 internal– ACLKXCTL.CLKXM = 1,PDIR.ACLKX = 1 McASP2 ACLKX2 externalinput– ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 0 McASP2 ACLKX2 externaloutput– ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 1 McASP2 ACLKR2 internal– ACLKR2CTL.CLKRM = 1,PDIR.ACLKR =1 McASP2 ACLKR2 externalinput– ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 0 McASP2 ACLKR2 externaloutput– ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 1 (2) AHR -Cycletime,AHCLKR2. (3) AHX -Cycletime,AHCLKX2. (4) P = SYSCLK2 period (5) AR -ACLKR2 period. (6) AX -ACLKX2 period. (7) McASP2 ACLKXCTL.ASYNC=1: Receiverisclockedby itsown ACLKR2 Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 105 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION A0 A1 B0 B1 A30 A31 B30 B31 C0 C1 C2 C3 C31 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) AXR[n] (Data In/Receive) ACLKR/X (CLKRP = CLKXP = 0)(A) ACLKR/X (CLKRP = CLKXP = 1)(B) AM1707 SPRS637 –FEBRUARY 2010 www.ti.com A. For CLKRP = CLKXP = 0, the McASP transmitterisconfiguredforrisingedge (toshiftdata out)and the McASP receiverisconfiguredforfallingedge (toshiftdatain). B. For CLKRP = CLKXP = 1,theMcASP transmitterisconfiguredforfallingedge (toshiftdataout)and theMcASP receiverisconfiguredforrisingedge (toshiftdatain). Figure6-34.McASP InputTimings

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ADVANCE□INFORMATION 131313 1313 1211 A0 A1 B0 B1 A30 A31 B30 B31 C0 C1 C2 C3 C31 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) AXR[n] (Data Out/Transmit) ACLKR/X (CLKRP = CLKXP = 0)(B) ACLKR/X (CLKRP = CLKXP = 1)(A) AM1707 www.ti.com SPRS637 –FEBRUARY 2010 A. For CLKRP = CLKXP = 1,theMcASP transmitterisconfiguredforfallingedge (toshiftdataout)and theMcASP receiverisconfiguredforrisingedge (toshiftdatain). B. For CLKRP = CLKXP = 0, the McASP transmitterisconfiguredforrisingedge (toshiftdata out)and the McASP receiverisconfiguredforfallingedge (toshiftdatain). Figure6-35.McASP Output Timings Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 107 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION Peripheral Configuration Bus Interrupt and DMA Requests 16-Bit Shift Register 16-Bit Buffer GPIO Control (all pins) State Machine Clock Control SPIx_SIMO SPIx_SOMI SPIx_ENA SPIx_SCS SPIx_CLK AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

6.18 SerialPeripheralInterfacePorts(SPI0,SPI1)

Figure6-36isa blockdiagramoftheSPI module,whichisa simpleshiftregisterand bufferpluscontrol logic.Data iswrittentotheshiftregisterbeforetransmissionoccursand isreadfromthebufferattheend oftransmission.The SPI can operateeitheras a master,inwhich case,itinitiatesa transferand drives theSPIx_CLK pin,or as a slave.Four clockphase and polarityoptionsare supportedas wellas many dataformattingoptions. Figure6-36.Block Diagram ofSPI Module The SPI supports3-, 4-, and 5-pinoperationwith three basic pins (SPIx_CLK, SPIx_SIMO, and SPIx_SOMI) and two optionalpins(SPIx_SCS, SPIx_ENA). The optionalSPIx_SCS (SlaveChip Select)pinismost usefultoenableinslavemode when thereare otherslavedeviceson thesame SPI port.The devicewillonlyshiftdataand drivetheSPIx_SOMI pin when SPIx_SCS isheldlow. In slavemode, SPIx_ENA isan optionaloutputand can be drivenineithera push-pullor open-drain manner.The SPIx_ENA outputprovidesthestatusoftheinternaltransmitbuffer(SPIDAT0/1registers).In four-pinmode withtheenableoption,SPIx_ENA isassertedonlywhen thetransmitbufferisfull,indicating thattheslaveisreadytobeginanothertransfer.Infive-pinmode, theSPIx_ENA isadditionallyqualified by SPIx_SCS beingasserted.Thisallowsa singlehandshake linetobe sharedby multipleslaveson the same SPI bus. Inmastermode, theSPIx_ENA pinisan optionalinputand themastercan be configuredtodelaythestart ofthenexttransferuntiltheslaveassertsSPIx_ENA. The additionofthishandshake signalsimplifiesSPI communicationsand,on average,increasesSPI bus throughputsincethemasterdoes notneed todelay each transferlongenough toallowfortheworst-caselatencyoftheslavedevice.Instead,each transfer can beginas soon as boththemasterand slavehave actuallyservicedthepreviousSPI transfer. AlthoughtheSPI module supportstwo interruptoutputs,SPIx_INT1 istheonlyinterruptconnectedon this device.

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ADVANCE□INFORMATION Optional − Slave Chip Select Optional Enable (Ready) SLA VE SPIMASTER SPI SPIx_SIMOSPIx_SIMO SPIx_SOMI SPIx_SOMI SPIx_CLK SPIx_CLK SPIx_ENA SPIx_ENA SPIx_SCS SPIx_SCS AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Figure6-37.IllustrationofSPI Master-to-SPISlaveConnection Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 109 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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6.18.1 SPI PeripheralRegistersDescription(s)

Table6-53isa listoftheSPI registers. Table6-53.SPIx ConfigurationRegisters SPI0 SPI1 ACRONYM REGISTER DESCRIPTIONBYTE ADDRESS BYTE ADDRESS 0x01C4 1000 0x01E1 2000 SPIGCR0 GlobalControlRegister0 0x01C4 1004 0x01E1 2004 SPIGCR1 GlobalControlRegister1 0x01C4 1008 0x01E1 2008 SPIINT0 InterruptRegister 0x01C4 100C 0x01E1 200C SPILVL InterruptLevelRegister 0x01C4 1010 0x01E1 2010 SPIFLG FlagRegister 0x01C4 1014 0x01E1 2014 SPIPC0 PinControlRegister0 (PinFunction) 0x01C4 1018 0x01E1 2018 SPIPC1 PinControlRegister1 (PinDirection) 0x01C4 101C 0x01E1 201C SPIPC2 PinControlRegister2 (PinData In) 0x01C4 1020 0x01E1 2020 SPIPC3 PinControlRegister3 (PinData Out) 0x01C4 1024 0x01E1 2024 SPIPC4 PinControlRegister4 (PinData Set) 0x01C4 1028 0x01E1 2028 SPIPC5 PinControlRegister5 (PinData Clear) 0x01C4 102C 0x01E1 202C Reserved Reserved-Do notwritetothisregister 0x01C4 1030 0x01E1 2030 Reserved Reserved-Do notwritetothisregister 0x01C4 1034 0x01E1 2034 Reserved Reserved-Do notwritetothisregister 0x01C4 1038 0x01E1 2038 SPIDAT0 ShiftRegister0 (withoutformatselect) 0x01C4 103C 0x01E1 203C SPIDAT1 ShiftRegister1 (withformatselect) 0x01C4 1040 0x01E1 2040 SPIBUF BufferRegister 0x01C4 1044 0x01E1 2044 SPIEMU EmulationRegister 0x01C4 1048 0x01E1 2048 SPIDELAY DelayRegister 0x01C4 104C 0x01E1 204C SPIDEF DefaultChipSelectRegister 0x01C4 1050 0x01E1 2050 SPIFMT0 FormatRegister0 0x01C4 1054 0x01E1 2054 SPIFMT1 FormatRegister1 0x01C4 1058 0x01E1 2058 SPIFMT2 FormatRegister2 0x01C4 105C 0x01E1 205C SPIFMT3 FormatRegister3 0x01C4 1060 0x01E1 2060 Reserved Reserved-Do notwritetothisregister 0x01C4 1064 0x01E1 2064 INTVEC1 InterruptVectorforSPI INT1

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010

6.18.2 SPI ElectricalData/Timing

6.18.2.1SerialPeripheralInterface(SPI)Timing Table6-54throughTable6-69assume testingoverrecommended operatingconditions(seeFigure6-38 throughFigure6-41). Table6-54.GeneralTiming Requirements forSPI0 Master Modes (1) No. PARAMETER MIN MAX UNIT greaterof2P or1 tc(SPC)M CycleTime,SPI0_CLK, AllMasterModes 256P ns20 ns 2 tw(SPCH)M PulseWidthHigh,SPI0_CLK, AllMasterModes 0.5tc(SPC)M -1 ns 3 tw(SPCL)M PulseWidthLow, SPI0_CLK, AllMasterModes 0.5tc(SPC)M -1 ns Polarity= 0,Phase = 0, 5toSPI0_CLK rising Polarity= 0,Phase = 1, -0.5tc(SPC)M + 5toSPI0_CLK risingDelay,initialdatabitvalidon SPI0_SIMO4 td(SIMO_SPC)M nsafterinitialedge on SPI0_CLK (2) Polarity= 1,Phase = 0, 5toSPI0_CLK falling Polarity= 1,Phase = 1, -0.5tc(SPC)M + 5toSPI0_CLK falling Polarity= 0,Phase = 0, 5fromSPI0_CLK rising Polarity= 0,Phase = 1, 5Delay,subsequentbitsvalidon fromSPI0_CLK falling 5 td(SPC_SIMO)M SPI0_SIMO aftertransmitedge of ns Polarity= 1,Phase = 0,SPI0_CLK 5fromSPI0_CLK falling Polarity= 1,Phase = 1, 5fromSPI0_CLK rising Polarity= 0,Phase = 0, 0.5tc(SPC)M -3fromSPI0_CLK falling Polarity= 0,Phase = 1, 0.5tc(SPC)M -3fromSPI0_CLK risingOutputholdtime,SPI0_SIMO valid6 toh(SPC_SIMO)M nsafterreceiveedge ofSPI0_CLK Polarity= 1,Phase = 0, 0.5tc(SPC)M -3fromSPI0_CLK rising Polarity= 1,Phase = 1, 0.5tc(SPC)M -3fromSPI0_CLK falling Polarity= 0,Phase = 0, 0toSPI0_CLK falling Polarity= 0,Phase = 1, 0toSPI0_CLK risingInputSetupTime,SPI0_SOMI valid7 tsu(SOMI_SPC)M nsbeforereceiveedge ofSPI0_CLK Polarity= 1,Phase = 0, 0toSPI0_CLK rising Polarity= 1,Phase = 1, 0toSPI0_CLK falling Polarity= 0,Phase = 0, 5fromSPI0_CLK falling Polarity= 0,Phase = 1, 5fromSPI0_CLK risingInputHoldTime,SPI0_SOMI validafter8 tih(SPC_SOMI)M nsreceiveedge ofSPI0_CLK Polarity= 1,Phase = 0, 5fromSPI0_CLK rising Polarity= 1,Phase = 1, 5fromSPI0_CLK falling (1) P = SYSCLK2 period (2) Firstbitmay be MSB orLSB dependingupon SPI configuration.MO(0) referstofirstbitand MO(n) referstolastbitoutputon SPI0_SIMO. MI(0)referstothefirstbitinputand MI(n)referstothelastbitinputon SPI0_SOMI. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 111 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-55.GeneralTiming Requirements forSPI0 SlaveModes (1) No. PARAMETER MIN MAX UNIT greaterof2P or9 tc(SPC)S CycleTime,SPI0_CLK, AllSlaveModes 256P ns20 ns 10 tw(SPCH)S PulseWidthHigh,SPI0_CLK, AllSlaveModes 18 ns 11 tw(SPCL)S PulseWidthLow, SPI0_CLK, AllSlaveModes 18 ns Polarity= 0,Phase = 0, 2PtoSPI0_CLK rising Polarity= 0,Phase = 1, 2PSetuptime,transmitdatawrittentoSPI toSPI0_CLK rising 12 tsu(SOMI_SPC)S beforeinitialclockedge frommaster.(2) ns Polarity= 1,Phase = 0,(3) 2PtoSPI0_CLK falling Polarity= 1,Phase = 1, 2PtoSPI0_CLK falling Polarity= 0,Phase = 0, 18.5fromSPI0_CLK rising Polarity= 0,Phase = 1, 18.5Delay,subsequentbitsvalidon fromSPI0_CLK falling 13 td(SPC_SOMI)S SPI0_SOMI aftertransmitedge of ns Polarity= 1,Phase = 0,SPI0_CLK 18.5fromSPI0_CLK falling Polarity= 1,Phase = 1, 18.5fromSPI0_CLK rising Polarity= 0,Phase = 0, 0.5tc(SPC)S -3fromSPI0_CLK falling Polarity= 0,Phase = 1, 0.5tc(SPC)S -3fromSPI0_CLK risingOutputholdtime,SPI0_SOMI validafte14 toh(SPC_SOMI)S nsreceiveedge ofSPI0_CLK Polarity= 1,Phase = 0, 0.5tc(SPC)S -3fromSPI0_CLK rising Polarity= 1,Phase = 1, 0.5tc(SPC)S -3fromSPI0_CLK falling Polarity= 0,Phase = 0, 0toSPI0_CLK falling Polarity= 0,Phase = 1, 0toSPI0_CLK risingInputSetupTime,SPI0_SIMO valid15 tsu(SIMO_SPC)S nsbeforereceiveedge ofSPI0_CLK Polarity= 1,Phase = 0, 0toSPI0_CLK rising Polarity= 1,Phase = 1, 0toSPI0_CLK falling Polarity= 0,Phase = 0, 5fromSPI0_CLK falling Polarity= 0,Phase = 1, 5fromSPI0_CLK risingInputHoldTime,SPI0_SIMO validafter16 tih(SPC_SIMO)S nsreceiveedge ofSPI0_CLK Polarity= 1,Phase = 0, 5fromSPI0_CLK rising Polarity= 1,Phase = 1, 5fromSPI0_CLK falling (1) P = SYSCLK2 period (2) Firstbitmay be MSB orLSB dependingupon SPI configuration.SO(0) referstofirstbitand SO(n) referstolastbitoutputon SPI0_SOMI. SI(0)referstothefirstbitinputand SI(n)referstothelastbitinputon SPI0_SIMO. (3) Measured fromtheterminationofthewriteofnew datatotheSPI module,Inanalyzingthroughputrequirements,additionalinternalbus cyclesmust be accountedfortoallowdatatobe writtentotheSPI module by theCPU.

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-56.Additional(1)SPI0 Master Timings,4-PinEnable Option(2)(3) No. PARAMETER MIN MAX UNIT Polarity= 0,Phase = 0, 3P + 3toSPI0_CLK rising Polarity= 0,Phase = 1, 0.5tc(SPC)M + 3P + 3Delayfromslaveassertionof toSPI0_CLK rising 17 td(ENA_SPC)M SPI0_ENA activetofirstSPI0_CLK ns Polarity= 1,Phase = 0,frommaster.(4) 3P + 3toSPI0_CLK falling Polarity= 1,Phase = 1, 0.5tc(SPC)M + 3P + 3toSPI0_CLK falling Polarity= 0,Phase = 0, 0.5tc(SPC)M + P + 5fromSPI0_CLK falling Polarity= 0,Phase = 1,Max delayforslavetodeassert P + 5fromSPI0_CLK fallingSPI0_ENA afterfinalSPI0_CLK edge18 td(SPC_ENA)M nstoensuremasterdoes notbeginthe Polarity= 1,Phase = 0, 0.5tc(SPC)M + P + 5nexttransfer.(5) fromSPI0_CLK rising Polarity= 1,Phase = 1, P + 5fromSPI0_CLK rising (1) These parametersareinadditiontothegeneraltimingsforSPI mastermodes (Table6-54). (2) P = SYSCLK2 period (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourmasterclockingmodes. (4) Inthecase where themasterSPI isreadywithnew databeforeSPI0_ENA assertion. (5) Inthecase where themasterSPI isreadywithnew databeforeSPI0_EN A deassertion. Table6-57.Additional(1)SPI0 Master Timings,4-PinChip SelectOption(2)(3) No. PARAMETER MIN MAX UNIT Polarity= 0,Phase = 0, 2P -5toSPI0_CLK rising Polarity= 0,Phase = 1, 0.5tc(SPC)M + 2P -5toSPI0_CLK risingDelayfromSPI0_SCS activetofirst19 td(SCS_SPC)M nsSPI0_CLK (4)(5) Polarity= 1,Phase = 0, 2P -5toSPI0_CLK falling Polarity= 1,Phase = 1, 0.5tc(SPC)M + 2P -5toSPI0_CLK falling Polarity= 0,Phase = 0, 0.5tc(SPC)M + P -3fromSPI0_CLK falling Polarity= 0,Phase = 1, P -3fromSPI0_CLK fallingDelayfromfinalSPI0_CLK edge to20 td(SPC_SCS)M nsmasterdeassertingSPI0_SCS (6)(7) Polarity= 1,Phase = 0, 0.5tc(SPC)M + P -3fromSPI0_CLK rising Polarity= 1,Phase = 1, P -3fromSPI0_CLK rising (1) These parametersareinadditiontothegeneraltimingsforSPI mastermodes (Table6-54). (2) P = SYSCLK2 period (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourmasterclockingmodes. (4) Inthecase where themasterSPI isreadywithnew databeforeSPI0_SCS assertion. (5) Thisdelaycan be increasedundersoftwarecontrolby theregisterbitfieldSPIDELAY.C2TDELAY[4:0]. (6) Exceptformodes when SPIDAT1.CSHOLD isenabledand thereisadditionaldatatotransmit.Inthiscase,SPI0_SCS willremain asserted. (7) Thisdelaycan be increasedundersoftwarecontrolby theregisterbitfieldSPIDELAY.T2CDELAY[4:0]. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 113 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-58.Additional(1)SPI0 Master Timings,5-PinOption(2)(3) No. PARAMETER MIN MAX UNIT Polarity= 0,Phase = 0, 0.5tc(SPC)M + P + 5fromSPI0_CLK falling Max delayforslaveto Polarity= 0,Phase = 1, P + 5deassertSPI0_ENA after fromSPI0_CLK falling 18 td(SPC_ENA)M finalSPI0_CLK edge to ns Polarity= 1,Phase = 0,ensuremasterdoes not 0.5tc(SPC)M + P + 5fromSPI0_CLK risingbeginthenexttransfer.(4) Polarity= 1,Phase = 1, P + 5fromSPI0_CLK rising Polarity= 0,Phase = 0, 0.5tc(SPC)M + P -3fromSPI0_CLK falling Polarity= 0,Phase = 1,Delayfromfinal P -3fromSPI0_CLK fallingSPI0_CLK edge to20 td(SPC_SCS)M nsmasterdeasserting Polarity= 1,Phase = 0, 0.5tc(SPC)M + P -3SPI0_SCS (5)(6) fromSPI0_CLK rising Polarity= 1,Phase = 1, P -3fromSPI0_CLK rising Max delayforslaveSPI todriveSPI0_ENA valid 21 td(SCSL_ENAL)M aftermasterassertsSPI0_SCS todelaythe C2TDELAY + P ns masterfrombeginningthenexttransfer, Polarity= 0,Phase = 0, 2P -5toSPI0_CLK rising Polarity= 0,Phase = 1, 0.5tc(SPC)M + 2P -5DelayfromSPI0_SCS toSPI0_CLK rising 22 td(SCS_SPC)M activetofirst ns Polarity= 1,Phase = 0,SPI0_CLK (7)(8)(9) 2P -5toSPI0_CLK falling Polarity= 1,Phase = 1, 0.5tc(SPC)M + 2P -5toSPI0_CLK falling Polarity= 0,Phase = 0, 3P + 3toSPI0_CLK rising Polarity= 0,Phase = 1, 0.5tc(SPC)M + 3P + 3Delayfromassertionof toSPI0_CLK rising 23 td(ENA_SPC)M SPI0_ENA lowtofirst ns Polarity= 1,Phase = 0,SPI0_CLK edge.(10) 3P + 3toSPI0_CLK falling Polarity= 1,Phase = 1, 0.5tc(SPC)M + 3P + 3toSPI0_CLK falling (1) These parametersareinadditiontothegeneraltimingsforSPI mastermodes (Table6-55). (2) P = SYSCLK2 period (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourmasterclockingmodes. (4) Inthecase where themasterSPI isreadywithnew databeforeSPI0_ENA deassertion. (5) Exceptformodes when SPIDAT1.CSHOLD isenabledand thereisadditionaldatatotransmit.Inthiscase,SPI0_SCS willremain asserted. (6) Thisdelaycan be increasedundersoftwarecontrolby theregisterbitfieldSPIDELAY.T2CDELAY[4:0]. (7) IfSPI0_ENA isassertedimmediatelysuch thatthetransmissionisnotdelayedby SPI0_ENA. (8) Inthecase where themasterSPI isreadywithnew databeforeSPI0_SCS assertion. (9) Thisdelaycan be increasedundersoftwarecontrolby theregisterbitfieldSPIDELAY.C2TDELAY[4:0]. (10)IfSPI0_ENA was initiallydeassertedhighand SPI0_CLK isdelayed.

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-59.Additional(1)SPI0 SlaveTimings,4-PinEnable Option(2)(3) No. PARAMETER MIN MAX UNIT Polarity= 0,Phase = 0, 1.5P -3 2.5P + 18.5fromSPI0_CLK falling 24 td(SPC_ENAH)S toslave ns Polarity= 1,Phase = 0,deasserting 1.5P -3 2.5P + 18.5fromSPI0_CLK risingSPI0_ENA. (1) These parametersareinadditiontothegeneraltimingsforSPI slavemodes (Table6-55). (2) P = SYSCLK2 period (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourslaveclockingmodes. Table6-60.Additional(1)SPI0 SlaveTimings,4-PinChip SelectOption(2)(3) No. PARAMETER MIN MAX UNIT RequireddelayfromSPI0_SCS assertedatslavetofirst25 td(SCSL_SPC)S P nsSPI0_CLK edge atslave. Polarity= 0,Phase = 0, 0.5tc(SPC)M + P+5fromSPI0_CLK falling Polarity= 0,Phase = 1, P+5Requireddelayfromfinal fromSPI0_CLK falling 26 td(SPC_SCSH)S SPI0_CLK edge beforeSPI0_SCS ns Polarity= 1,Phase = 0,isdeasserted. 0.5tc(SPC)M + P+5fromSPI0_CLK rising Polarity= 1,Phase = 1, P+5fromSPI0_CLK rising DelayfrommasterassertingSPI0_SCS toslavedriving27 tena(SCSL_SOMI)S P + 18.5 nsSPI0_SOMI valid DelayfrommasterdeassertingSPI0_SCS toslave3-stating28 tdis(SCSH_SOMI)S P + 18.5 nsSPI0_SOMI (1) These parametersareinadditiontothegeneraltimingsforSPI slavemodes (Table6-55). (2) P = SYSCLK2 period (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourslaveclockingmodes. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 115 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-61.Additional(1)SPI0 SlaveTimings,5-PinOption(2)(3) No. PARAMETER MIN MAX UNIT RequireddelayfromSPI0_SCS assertedatslavetofirst25 td(SCSL_SPC)S P nsSPI0_CLK edge atslave. Polarity= 0,Phase = 0, 0.5tc(SPC)M + P + 5fromSPI0_CLK falling Polarity= 0,Phase = 1, P + 5Requireddelayfromfinal fromSPI0_CLK falling 26 td(SPC_SCSH)S SPI0_CLK edge before ns Polarity= 1,Phase = 0,SPI0_SCS isdeasserted. 0.5tc(SPC)M + P + 5fromSPI0_CLK rising Polarity= 1,Phase = 1, P + 5fromSPI0_CLK rising DelayfrommasterassertingSPI0_SCS toslavedriving27 tena(SCSL_SOMI)S P + 18.5 nsSPI0_SOMI valid DelayfrommasterdeassertingSPI0_SCS toslave28 tdis(SCSH_SOMI)S P + 18.5 ns3-statingSPI0_SOMI DelayfrommasterdeassertingSPI0_SCS toslavedriving29 tena(SCSL_ENA)S 18.5 nsSPI0_ENA valid Polarity= 0,Phase = 0, 2.5P + 18.5fromSPI0_CLK falling fromSPI0_CLK rising Polarity= 1,Phase = 1, 2.5P + 18.5fromSPI0_CLK falling (1) These parametersareinadditiontothegeneraltimingsforSPI slavemodes (Table6-55). (2) P = SYSCLK2 period (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourslaveclockingmodes. (4) SPI0_ENA isdrivenlowafterthetransmissioncompletesiftheSPIINT0.ENABLE_HIGHZ bitisprogrammed to0.Otherwiseitis 3-stated.If3-stated,an externalpullupresistorshouldbe used toprovidea validleveltothemaster.Thisoptionisusefulwhen tying severalSPI slavedevicestoa singlemaster. Table6-62.GeneralTiming Requirements forSPI1 Master Modes (1) No. PARAMETER MIN MAX UNIT 1 tc(SPC)M CycleTime,SPI1_CLK, AllMasterModes greaterof2P or20 ns 256P ns 2 tw(SPCH)M PulseWidthHigh,SPI1_CLK, AllMasterModes 0.5tc(SPC)M -1 ns 3 tw(SPCL)M PulseWidthLow, SPI1_CLK, AllMasterModes 0.5tc(SPC)M -1 ns Polarity= 0,Phase = 0, 5toSPI1_CLK rising Polarity= 0,Phase = 1, -0.5tc(SPC)M + 5Delay,initialdatabitvalidon toSPI1_CLK rising 4 td(SIMO_SPC)M SPI1_SIMO toinitialedge on ns Polarity= 1,Phase = 0,SPI1_CLK (2) 5toSPI1_CLK falling Polarity= 1,Phase = 1, -0.5tc(SPC)M + 5toSPI1_CLK falling Polarity= 0,Phase = 0, 5fromSPI1_CLK rising Polarity= 0,Phase = 1, 5Delay,subsequentbitsvalid fromSPI1_CLK falling 5 td(SPC_SIMO)M on SPI1_SIMO aftertransmit ns Polarity= 1,Phase = 0,edge ofSPI1_CLK 5fromSPI1_CLK falling Polarity= 1,Phase = 1, 5fromSPI1_CLK rising (1) P = SYSCLK2 period (2) Firstbitmay be MSB orLSB dependingupon SPI configuration.MO(0) referstofirstbitand MO(n) referstolastbitoutputon SPI1_SIMO. MI(0)referstothefirstbitinputand MI(n)referstothelastbitinputon SPI1_SOMI.

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-62.GeneralTiming Requirements forSPI1 Master Modes (1) (continued) No. PARAMETER MIN MAX UNIT Polarity= 0,Phase = 0, 0.5tc(SPC)M -3fromSPI1_CLK falling Polarity= 0,Phase = 1, 0.5tc(SPC)M -3Outputholdtime,SPI1_SIMO fromSPI1_CLK rising 6 toh(SPC_SIMO)M validafter ns Polarity= 1,Phase = 0,receiveedge ofSPI1_CLK 0.5tc(SPC)M -3fromSPI1_CLK rising Polarity= 1,Phase = 1, 0.5tc(SPC)M -3fromSPI1_CLK falling Polarity= 0,Phase = 0, 0toSPI1_CLK falling Polarity= 0,Phase = 1, 0InputSetupTime, toSPI1_CLK rising 7 tsu(SOMI_SPC)M SPI1_SOMI validbefore ns Polarity= 1,Phase = 0,receiveedge ofSPI1_CLK 0toSPI1_CLK rising Polarity= 1,Phase = 1, 0toSPI1_CLK falling Polarity= 0,Phase = 0, 5fromSPI1_CLK falling Polarity= 0,Phase = 1, 5InputHoldTime,SPI1_SOMI fromSPI1_CLK rising 8 tih(SPC_SOMI)M validafterreceiveedge of ns Polarity= 1,Phase = 0,SPI1_CLK 5fromSPI1_CLK rising Polarity= 1,Phase = 1, 5fromSPI1_CLK falling Table6-63.GeneralTiming Requirements forSPI1 SlaveModes (1) No. PARAMETER MIN MAX UNIT 9 tc(SPC)S CycleTime,SPI1_CLK, AllSlaveModes greaterof2P or20 ns 256P ns 10 tw(SPCH)S PulseWidthHigh,SPI1_CLK, AllSlaveModes 18 ns 11 tw(SPCL)S PulseWidthLow, SPI1_CLK, AllSlaveModes 18 ns Polarity= 0,Phase = 0, 2PtoSPI1_CLK rising Polarity= 0,Phase = 1,Setuptime,transmitdata 2PtoSPI1_CLK risingwrittentoSPI beforeinitial12 tsu(SOMI_SPC)S nsclockedge from Polarity= 1,Phase = 0, 2Pmaster.(2)(3) toSPI1_CLK falling Polarity= 1,Phase = 1, 2PtoSPI1_CLK falling Polarity= 0,Phase = 0, 19fromSPI1_CLK rising Polarity= 0,Phase = 1, 19Delay,subsequentbitsvalid fromSPI1_CLK falling 13 td(SPC_SOMI)S on SPI1_SOMI aftertransmit ns Polarity= 1,Phase = 0,edge ofSPI1_CLK 19fromSPI1_CLK falling Polarity= 1,Phase = 1, 19fromSPI1_CLK rising (1) P = SYSCLK2 period (2) Firstbitmay be MSB orLSB dependingupon SPI configuration.SO(0) referstofirstbitand SO(n) referstolastbitoutputon SPI1_SOMI. SI(0)referstothefirstbitinputand SI(n)referstothelastbitinputon SPI1_SIMO. (3) Measured fromtheterminationofthewriteofnew datatotheSPI module,Inanalyzingthroughputrequirements,additionalinternalbus cyclesmust be accountedfortoallowdatatobe writtentotheSPI module by theCPU. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 117 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-63.GeneralTiming Requirements forSPI1 SlaveModes (1) (continued) No. PARAMETER MIN MAX UNIT Polarity= 0,Phase = 0, 0.5tc(SPC)S -3fromSPI1_CLK falling Polarity= 0,Phase = 1, 0.5tc(SPC)S -3Outputholdtime,SPI1_SOMI fromSPI1_CLK rising 14 toh(SPC_SOMI)S validafterreceiveedge of ns Polarity= 1,Phase = 0,SPI1_CLK 0.5tc(SPC)S -3fromSPI1_CLK rising Polarity= 1,Phase = 1, 0.5tc(SPC)S -3fromSPI1_CLK falling Polarity= 0,Phase = 0, 0toSPI1_CLK falling Polarity= 0,Phase = 1, 0InputSetupTime, toSPI1_CLK rising 15 tsu(SIMO_SPC)S SPI1_SIMO validbefore ns Polarity= 1,Phase = 0,receiveedge ofSPI1_CLK 0toSPI1_CLK rising Polarity= 1,Phase = 1, 0toSPI1_CLK falling Polarity= 0,Phase = 0, 5fromSPI1_CLK falling Polarity= 0,Phase = 1, 5InputHoldTime,SPI1_SIMO fromSPI1_CLK rising 16 tih(SPC_SIMO)S validafterreceiveedge of ns Polarity= 1,Phase = 0,SPI1_CLK 5fromSPI1_CLK rising Polarity= 1,Phase = 1, 5fromSPI1_CLK falling Table6-64.Additional(1)SPI1 Master Timings,4-PinEnable Option(2)(3) No. PARAMETER MIN MAX UNIT Polarity= 0,Phase = 0, 3P + 3toSPI1_CLK rising Polarity= 0,Phase = 1, 0.5tc(SPC)M + 3P + 3toSPI1_CLK risingDelayfromslaveassertionofSPI1_ENA17 td(EN A_SPC)M nsactivetofirstSPI1_CLK frommaster.(4) Polarity= 1,Phase = 0, 3P + 3toSPI1_CLK falling Polarity= 1,Phase = 1, 0.5tc(SPC)M + 3P + 3toSPI1_CLK falling Polarity= 0,Phase = 0, 0.5tc(SPC)M + P + 5fromSPI1_CLK falling Polarity= 0,Phase = 1,Max delayforslavetodeassert P + 5fromSPI1_CLK fallingSPI1_ENA afterfinalSPI1_CLK edge to18 td(SPC_ENA)M nsensuremasterdoes notbeginthenext Polarity= 1,Phase = 0, 0.5tc(SPC)M + P + 5transfer.(5) fromSPI1_CLK rising Polarity= 1,Phase = 1, P + 5fromSPI1_CLK rising (1) These parametersareinadditiontothegeneraltimingsforSPI mastermodes (Table6-62). (2) P = SYSCLK2 period (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourmasterclockingmodes. (4) Inthecase where themasterSPI isreadywithnew databeforeSPI1_ENA assertion. (5) Inthecase where themasterSPI isreadywithnew databeforeSPI1_ENA deassertion.

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-65.Additional(1)SPI1 Master Timings,4-PinChip SelectOption(2)(3) No. PARAMETER MIN MAX UNIT Polarity= 0,Phase = 0, 2P -5 toSPI1_CLK rising Polarity= 0,Phase = 1, 0.5tc(SPC)M + 2P -5 toSPI1_CLK risingDelayfromSPI1_SCS activetofirst19 td(SCS_SPC)M nsSPI1_CLK (4)(5) Polarity= 1,Phase = 0, 2P -5 toSPI1_CLK falling Polarity= 1,Phase = 1, 0.5tc(SPC)M + 2P -5 toSPI1_CLK falling Polarity= 0,Phase = 0, 0.5tc(SPC)M + P -3fromSPI1_CLK falling Polarity= 0,Phase = 1, P -3fromSPI1_CLKDelayfromfinalSPI1_CLK edge tomaster20 td(SPC_SCS)M nsfallingdeassertingSPI1_SCS (6)(7) Polarity= 1,Phase = 0, 0.5tc(SPC)M + P -3 fromSPI1_CLK rising Polarity= 1,Phase = 1, P -3 fromSPI1_CLK rising (1) These parametersareinadditiontothegeneraltimingsforSPI mastermodes (Table6-62). (2) P = SYSCLK2 period (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourmasterclockingmodes. (4) Inthecase where themasterSPI isreadywithnew databeforeSPI1_SCS assertion. (5) Thisdelaycan be increasedundersoftwarecontrolby theregisterbitfieldSPIDELAY.C2TDELAY[4:0]. (6) Exceptformodes when SPIDAT1.CSHOLD isenabledand thereisadditionaldatatotransmit.Inthiscase,SPI1_SCS willremain asserted. (7) Thisdelaycan be increasedundersoftwarecontrolby theregisterbitfieldSPIDELAY.T2CDELAY[4:0]. Table6-66.Additional(1)SPI1 Master Timings,5-PinOption(2)(3) No. PARAMETER MIN MAX UNIT Polarity= 0,Phase = 0, 0.5tc(SPC)M +P+5fromSPI1_CLK fallingMax delayforslaveto deassertSPI1_ENA Polarity= 0,Phase = 1, P+5afterfinalSPI1_CLK fromSPI1_CLK falling 18 td(SPC_ENA)M edge toensure ns Polarity= 1,Phase = 0,masterdoes not 0.5tc(SPC)M +P+5fromSPI1_CLK risingbeginthenext transfer.(4) Polarity= 1,Phase = 1, P+5fromSPI1_CLK rising Polarity= 0,Phase = 0, 0.5tc(SPC)M + P -3fromSPI1_CLK falling Polarity= 0,Phase = 1,Delayfromfinal P -3fromSPI1_CLK fallingSPI1_CLK edge to20 td(SPC_SCS)M nsmasterdeasserting Polarity= 1,Phase = 0, 0.5tc(SPC)M + P -3SPI1_SCS (5)(6) fromSPI1_CLK rising Polarity= 1,Phase = 1, P -3fromSPI1_CLK rising (1) These parametersareinadditiontothegeneraltimingsforSPI mastermodes (Table6-63). (2) P = SYSCLK2 period (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourmasterclockingmodes. (4) Inthecase where themasterSPI isreadywithnew databeforeSPI1_ENA deassertion. (5) Exceptformodes when SPIDAT1.CSHOLD isenabledand thereisadditionaldatatotransmit.Inthiscase,SPI1_SCS willremain asserted. (6) Thisdelaycan be increasedundersoftwarecontrolby theregisterbitfieldSPIDELAY.T2CDELAY[4:0]. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 119 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-66.Additional(1)SPI1 Master Timings,5-PinOption (2)(3) (continued) No. PARAMETER MIN MAX UNIT Max delayforslaveSPI todriveSPI1_ENA 21 td(SCSL_ENAL)M validaftermasterassertsSPI1_SCS todelay C2TDELAY + P ns themasterfrombeginningthenexttransfer. Polarity= 0,Phase = 0, 2P -5toSPI1_CLK rising Polarity= 0,Phase = 1,Delayfrom 0.5tc(SPC)M + 2P -5toSPI1_CLK risingSPI1_SCS activeto22 td(SCS_SPC)M nsfirstSPI1_CLK (7)(8) Polarity= 1,Phase = 0, 2P -5(9) toSPI1_CLK falling Polarity= 1,Phase = 1, 0.5tc(SPC)M + 2P -5toSPI1_CLK falling Polarity= 0,Phase = 0, 3P + 3toSPI1_CLK rising Polarity= 0,Phase = 1,Delayfromassertion 0.5tc(SPC)M + 3P + 3toSPI1_CLK risingofSPI1_ENA lowto23 td(ENA_SPC)M nsfirstSPI1_CLK Polarity= 1,Phase = 0, 3P + 3edge.(10) toSPI1_CLK falling Polarity= 1,Phase = 1, 0.5tc(SPC)M + 3P + 3toSPI1_CLK falling (7) IfSPI1_ENA isassertedimmediatelysuch thatthetransmissionisnotdelayedby SPI1_ENA. (8) Inthecase where themasterSPI isreadywithnew databeforeSPI1_SCS assertion. (9) Thisdelaycan be increasedundersoftwarecontrolby theregisterbitfieldSPIDELAY.C2TDELAY[4:0]. (10)IfSPI1_ENA was initiallydeassertedhighand SPI1_CLK isdelayed. Table6-67.Additional(1)SPI1 SlaveTimings,4-PinEnable Option(2)(3) No. PARAMETER MIN MAX UNIT Polarity= 0,Phase = 0, 1.5P -3 2.5P + 19fromSPI1_CLK fallingDelayfrom (1) These parametersareinadditiontothegeneraltimingsforSPI slavemodes (Table6-63). (2) P = SYSCLK2 period (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourslaveclockingmodes. Table6-68.Additional(1)SPI1 SlaveTimings,4-PinChip SelectOption(2)(3) No. PARAMETER MIN MAX UNIT RequireddelayfromSPI1_SCS assertedatslavetofirst25 td(SCSL_SPC)S P nsSPI1_CLK edge atslave. Polarity= 0,Phase = 0, 0.5tc(SPC)M + P + 5fromSPI1_CLK falling Polarity= 0,Phase = 1, P + 5Requireddelayfromfinal fromSPI1_CLK falling 26 td(SPC_SCSH)S SPI1_CLK edge before ns Polarity= 1,Phase = 0,SPI1_SCS isdeasserted. 0.5tc(SPC)M + P + 5fromSPI1_CLK rising Polarity= 1,Phase = 1, P + 5fromSPI1_CLK rising DelayfrommasterassertingSPI1_SCS toslavedriving27 tena(SCSL_SOMI)S P + 19 nsSPI1_SOMI valid (1) These parametersareinadditiontothegeneraltimingsforSPI slavemodes (Table6-63). (2) P = SYSCLK2 period (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourslaveclockingmodes.

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-68.Additional(1)SPI1 SlaveTimings,4-PinChip SelectOption (2)(3) (continued) No. PARAMETER MIN MAX UNIT DelayfrommasterdeassertingSPI1_SCS toslave28 tdis(SCSH_SOMI)S P + 19 ns3-statingSPI1_SOMI Table6-69.Additional(1)SPI1 SlaveTimings,5-PinOption(2)(3) No. PARAMETER MIN MAX UNIT RequireddelayfromSPI1_SCS assertedatslaveto25 td(SCSL_SPC)S P nsfirstSPI1_CLK edge atslave. Polarity= 0,Phase = 0, 0.5tc(SPC)M + P + 5fromSPI1_CLK falling Polarity= 0,Phase = 1, P + 5Requireddelayfromfinal fromSPI1_CLK falling 26 td(SPC_SCSH)S SPI1_CLK edge before ns Polarity= 1,Phase = 0,SPI1_SCS isdeasserted. 0.5tc(SPC)M + P + 5fromSPI1_CLK rising Polarity= 1,Phase = 1, P + 5fromSPI1_CLK rising DelayfrommasterassertingSPI1_SCS toslave27 tena(SCSL_SOMI)S P + 19 nsdrivingSPI1_SOMI valid DelayfrommasterdeassertingSPI1_SCS toslave28 tdis(SCSH_SOMI)S P + 19 ns3-statingSPI1_SOMI DelayfrommasterdeassertingSPI1_SCS toslave29 tena(SCSL_ENA)S 19 nsdrivingSPI1_ENA valid Polarity= 0,Phase = 0, 2.5P + 19fromSPI1_CLK falling Polarity= 0,Phase = 1,Delayfromfinalclock 2.5P + 19fromSPI1_CLK risingreceiveedge on SPI1_CLK30 tdis(SPC_ENA)S nstoslave3-statingordriving Polarity= 1,Phase = 0, 2.5P + 19highSPI1_ENA. (4) fromSPI1_CLK rising Polarity= 1,Phase = 1, 2.5P + 19fromSPI1_CLK falling (1) These parametersareinadditiontothegeneraltimingsforSPI slavemodes (Table6-63). (2) P = SYSCLK2 period (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourslaveclockingmodes. (4) SPI1_ENA isdrivenlowafterthetransmissioncompletesiftheSPIINT0.ENABLE_HIGHZ bitisprogrammed to0.Otherwiseitis 3-stated.If3-stated,an externalpullupresistorshouldbe used toprovidea validleveltothemaster.Thisoptionisusefulwhen tying severalSPI slavedevicestoa singlemaster. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 121 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) 4 5 5 6 MASTER MODE POLARITY = 0 PHASE = 0 MASTER MODE POLARITY = 0 PHASE = 1 MASTER MODE POLARITY = 1 PHASE = 0 MASTER MODE POLARITY = 1 PHASE = 1 AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Figure6-38.SPI Timings— Master Mode

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ADVANCE□INFORMATION SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) 1110 SLA VE MODE POLARITY = 0 PHASE = 0 SLA VE MODE POLARITY = 0 PHASE = 1 SLA VE MODE POLARITY = 1 PHASE = 0 SLA VE MODE POLARITY = 1 PHASE = 1 AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Figure6-39.SPI Timings— SlaveMode Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 123 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION MASTER MODE 4 PIN WITH CHIP SELECT SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_ENA SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_SCS SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_ENA SPIx_SCS MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MASTER MODE 4 PIN WITH ENABLE MASTER MODE 5 PIN A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3−STATE (REQUIRES EXTERNAL PULLUP) DESEL (A) DESEL (A) AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Figure6-40.SPI Timings— Master Mode (4-Pinand 5-Pin)

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ADVANCE□INFORMATION SPIx_CLK SPIx_SOMI SPIx_SIMO SPIx_ENA SPIx_CLK SPIx_SOMI SPIx_SIMO SPIx_SCS SPIx_CLK SPIx_SOMI SPIx_SIMO SPIx_ENA SPIx_SCS SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SLA VE MODE 4 PIN WITH ENABLE SLA VE MODE 4 PIN WITH CHIP SELECT SLA VE MODE 5 PIN DESEL (A) DESEL (A) A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3−STATE (REQUIRES EXTERNAL PULLUP) AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Figure6-41.SPI Timings— SlaveMode (4-Pinand 5-Pin) Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 125 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

6.19 Enhanced Capture (eCAP) Peripheral

The devicecontainsup tothreeenhanced capture(eCAP) modules.Figure6-42shows a functionalblock diagramofa module. Uses forECAP include:

Speed measurements ofrotatingmachinery(e.g.toothedsprocketssensed viaHallsensors)
Elapsedtimemeasurements between positionsensortriggers
Periodand dutycyclemeasurements ofPulsetrainsignals
Decodingcurrentorvoltageamplitudederivedfromcutycycleencoded current/voltagesensors The ECAP module describedinthisspecificationincludesthefollowingfeatures:
32 bittimebase
4 eventtime-stampregisters(each32 bits)
Edge polarityselectionforup to4 sequenced time-stampcaptureevents
Interrupton eitherofthe4 events
Singleshotcaptureofup to4 eventtime-stamps
Continuousmode captureoftime-stampsina 4 deep circularbuffer
Absolutetime-stampcapture
Differencemode time-stampcapture
Alltheabove resourcesarededicatedtoa singleinputpin The eCAP modules areclockedattheSYSCLK2 rate.

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ADVANCE□INFORMATION TSCTR (counter−32 bit) RST CAP1 (APRD active) LD CAP2 (ACMP active) LD CAP3 (APRD shadow) LD CAP4 (ACMP shadow) LD Continuous / Oneshot Capture Control LD1 LD2 LD3 LD4 PRD [0−31] CMP [0−31] CTR [0−31] eCAPx Interrupt Trigger and Flag control to Interrupt Controller CTR=CMP ACMP shadow Event Pre-scale CTRPHS (phase register−32 bit) SYNCOut SYNCIn Event qualifier Polarity select Polarity select Polarity select Polarity select CTR=PRD CTR_OVF PWM compare logic CTR [0−31] PRD [0−31] CMP [0−31] CTR=CMP CTR=PRD CTR_OVFOVF APWM mode Delta−mode SYNC 4Capture events CEVT[1:4] APRD shadow MODE SELECT AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Figure6-42.eCAP FunctionalBlock Diagram Table6-70isthelistoftheECAP registers. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 127 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-70.ECAPx ConfigurationRegisters ECAP0 ECAP1 ECAP2 ACRONYM REGISTER DESCRIPTIONBYTE ADDRESS BYTE ADDRESS BYTE ADDRESS 0x01F0 6000 0x01F0 7000 0x01F0 8000 TSCTR Time-Stamp Counter 0x01F0 6004 0x01F0 7004 0x01F0 8004 CTRPHS CounterPhase OffsetValueRegister 0x01F0 6008 0x01F0 7008 0x01F0 8008 CAP1 Capture1 Register 0x01F0 600C 0x01F0 700C 0x01F0 800C CAP2 Capture2 Register 0x01F0 6010 0x01F0 7010 0x01F0 8010 CAP3 Capture3 Register 0x01F0 6014 0x01F0 7014 0x01F0 8014 CAP4 Capture4 Register 0x01F0 6028 0x01F0 7028 0x01F0 8028 ECCTL1 CaptureControlRegister1 0x01F0 602A 0x01F0 702A 0x01F0 802A ECCTL2 CaptureControlRegister2 0x01F0 602C 0x01F0 702C 0x01F0 802C ECEINT CaptureInterruptEnableRegister 0x01F0 602E 0x01F0 702E 0x01F0 802E ECFLG CaptureInterruptFlagRegister 0x01F0 6030 0x01F0 7030 0x01F0 8030 ECCLR CaptureInterruptClearRegister 0x01F0 6032 0x01F0 7032 0x01F0 8032 ECFRC CaptureInterruptForceRegister 0x01F0 605C 0x01F0 705C 0x01F0 805C REVID RevisionID Table6-71shows theeCAP timingrequirementand Table6-72shows theeCAP switchingcharacteristics. Table6-71.Enhanced Capture (eCAP) Timing Requirement PARAMETER TEST CONDITIONS MIN MAX UNIT tw(CAP) Captureinputpulsewidth Asynchronous 2tc(SCO) cycles Synchronous 2tc(SCO) cycles Table6-72.eCAP SwitchingCharacteristics PARAMETER MIN MAX UNIT tw(APWM) Pulseduration,APWMx outputhigh/low 20 ns

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ADVANCE□INFORMATION QWDTMR QWDPRD QWDOGUTIME QUPRD QUTMR UTOUT WDTOUT Quadrature capture unit (QCAP) QCPRDLAT QCTMRLAT QFLG QEPSTS QEPCTL Registers used by multiple units QCLK QDIR QI QS PHE PCSOUT Quadrature decoder (QDU) QDECCTL Position counter/ control unit (PCCU)QPOSLAT QPOSSLAT QPOSILAT EQEPxAIN EQEPxBIN EQEPxIIN EQEPxIOUT EQEPxIOE EQEPxSIN EQEPxSOUT EQEPxSOE GPIO MUX EQEPxA/XCLK EQEPxB/XDIR EQEPxS EQEPxI QPOSCMP QEINT QFRC QCLR QPOSCTL 1632 QPOSCNT QPOSMAX QPOSINIT EQEPxINT Enhanced QEP (eQEP) peripheral System control registers QCTMR QCPRD 1616 QCAPCTL EQEPxENCLK SYSCLK2 Data bus To CPU Interrupt Controller AM1707 www.ti.com SPRS637 –FEBRUARY 2010

6.20 Enhanced QuadratureEncoder (eQEP) Peripheral

The devicecontainsup totwo enhanced quadratureencoder(eQEP) modules. Figure6-43.eQEP FunctionalBlock Diagram Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 129 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-73isthelistoftheEQEP registers. Table 6-74 shows the eQEP timing requirementand Table 6-75 shows the eQEP switching characteristics. Table6-73.EQEP Registers EQEP0 EQEP1 BYTE ADDRESS BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01F0 9000 0x01F0 A000 QPOSCNT eQEP PositionCounter 0x01F0 9004 0x01F0 A004 QPOSINIT eQEP InitializationPositionCount 0x01F0 9008 0x01F0 A008 QPOSMAX eQEP Maximum PositionCount 0x01F0 900C 0x01F0 A00C QPOSCMP eQEP Position-compare 0x01F0 9010 0x01F0 A010 QPOSILAT eQEP IndexPositionLatch 0x01F0 9014 0x01F0 A014 QPOSSLAT eQEP StrobePositionLatch 0x01F0 9018 0x01F0 A018 QPOSLAT eQEP PositionLatch 0x01F0 901C 0x01F0 A01C QUTMR eQEP UnitTimer 0x01F0 9020 0x01F0 A020 QUPRD eQEP UnitPeriodRegister 0x01F0 9024 0x01F0 A024 QWDTMR eQEP Watchdog Timer 0x01F0 9026 0x01F0 A026 QWDPRD eQEP Watchdog PeriodRegister 0x01F0 9028 0x01F0 A028 QDECCTL eQEP Decoder ControlRegister 0x01F0 902A 0x01F0 A02A QEPCTL eQEP ControlRegister 0x01F0 902C 0x01F0 A02C QCAPCTL eQEP CaptureControlRegister 0x01F0 902E 0x01F0 A02E QPOSCTL eQEP Position-compareControlRegister 0x01F0 9030 0x01F0 A030 QEINT eQEP InterruptEnableRegister 0x01F0 9032 0x01F0 A032 QFLG eQEP InterruptFlagRegister 0x01F0 9034 0x01F0 A034 QCLR eQEP InterruptClearRegister 0x01F0 9036 0x01F0 A036 QFRC eQEP InterruptForceRegister 0x01F0 9038 0x01F0 A038 QEPSTS eQEP StatusRegister 0x01F0 903A 0x01F0 A03A QCTMR eQEP CaptureTimer 0x01F0 903C 0x01F0 A03C QCPRD eQEP CapturePeriodRegister 0x01F0 903E 0x01F0 A03E QCTMRLAT eQEP CaptureTimerLatch 0x01F0 9040 0x01F0 A040 QCPRDLAT eQEP CapturePeriodLatch 0x01F0 905C 0x01F0 A05C REVID eQEP RevisionID Table6-74.Enhanced QuadratureEncoder Pulse (eQEP) Timing Requirements PARAMETER TEST CONDITIONS MIN MAX UNIT tw(QEPP) QEP inputperiod Asynchronous/synchronous 2tc(SCO) cycles tw(INDEXH) QEP IndexInputHightime Asynchronous/synchronous 2tc(SCO) cycles tw(INDEXL) QEP IndexInputLow time Asynchronous/synchronous 2tc(SCO) cycles tw(STROBH) QEP StrobeHightime Asynchronous/synchronous 2tc(SCO) cycles tw(STROBL) QEP StrobeInputLow time Asynchronous/synchronous 2tc(SCO) cycles Table6-75.eQEP SwitchingCharacteristics PARAMETER MIN MAX UNIT td(CNTR)xin Delaytime,externalclocktocounterincrement 4tc(SCO) cycles td(PCS-OUT)QEP Delaytime,QEP inputedge topositioncompare syncoutput 6tc(SCO) cycles

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ADVANCE□INFORMATION EPWMTZ Peripheral Bus eHRPWM0 module eHRPWM1 module EPWM0SYNCI EPWM1SYNCI EPWM1SYNCO EPWM2SYNCI EPWM2SYNCO GPIO MUX EPWMSYNCI EPWM2A EPWM2B EPWM1A EPWM1B EPWM0A EPWM0B EPWM0INT EPWM1INT EPWM2INT EPWMTZ EPWMTZ EPWM0SYNCO Interrupt Controllers EPWMSYNCOTo eCAP0 module (sync in) eHRPWM2 module AM1707 www.ti.com SPRS637 –FEBRUARY 2010

6.21 Enhanced High-ResolutionPulse-WidthModulator(eHRPWM)

The devicecontainsup tothreeenhanced PWM Modules (eHRPWM). Figure6-44shows a blockdiagram ofmultipleeHRPWM modules.Figure4-4shows thesignalinterconnectionswiththeeHRPWM. Figure6-44.MultiplePWM Modules intheSystem Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 131 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION CTR=PRD TBPRD shadow (16) TBPRD active (16) Counter up/down (16 bit) TBCNT active (16) TBCTL[CNTLDE] TBCTL[SWFSYNC] (software forced sync) EPWMSYNCI CTR=ZERO CTR_Dir CTR=CMPB Disabled Sync in/out select Mux TBCTL[SYNCOSEL] EPWMSYNCO TBPHS active (24) 16 8 TBPHSHR (8) Phase control Time−base (TB) CTR=CMPA CMP A active (24) CMP A shadow (24) Action qualifier (AQ) Counter compare (CC) CMPB active (16) CTR=CMPB CMPB shadow (16) CMP AHR (8) EPWMA EPWMB Dead band (DB) (PC) chopper PWM zone (TZ) Trip CTR = ZERO EPWMxA EPWMxB EPWMxTZINT TZ HiRes PWM (HRPWM) CTR = PRD CTR = ZERO CTR = CMPB CTR = CMP A CTR_Dir Event trigger and interrupt (ET) EPWMxINT CTR=ZERO AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Figure6-45.eHRPWM Sub-Modules Showing CriticalInternalSignalInterconnections Table6-76.eHRPWM Module Controland StatusRegistersGrouped by Submodule eHRPWM0 eHRPWM1 eHRPWM2 SIZEACRONYM SHADOW REGISTER DESCRIPTIONBYTE ADDRESS BYTE ADDRESS BYTE ADDRESS (×16) TIME-BASE SUBMODULE REGISTERS 0x01F0 0000 0x01F0 2000 0x01F0 4000 TBCTL 1 No Time-BaseControlRegister 0x01F0 0002 0x01F0 2002 0x01F0 4002 TBSTS 1 No Time-BaseStatusRegister 0x01F0 0004 0x01F0 2004 0x01F0 4004 TBPHSHR 1 No ExtensionforHRPWM Phase Register(1) 0x01F0 0006 0x01F0 2006 0x01F0 4006 TBPHS 1 No Time-BasePhase Register 0x01F0 0008 0x01F0 2008 0x01F0 4008 TBCNT 1 No Time-BaseCounterRegister 0x01F0 000A 0x01F0 200A 0x01F0 400A TBPRD 1 Yes Time-BasePeriodRegister COUNTER-COMPARE SUBMODULE REGISTER 0x01F0 000E 0x01F0 200E 0x01F0 400E CMPCTL 1 No Counter-CompareControlRegister CMPAHR 1 No ExtensionforHRPWM Counter-Compare0x01F0 0010 0x01F0 2010 0x01F0 4010 A Register(1) 0x01F0 0012 0x01F0 2012 0x01F0 4012 CMPA 1 Yes Counter-CompareA Register 0x01F0 0014 0x01F0 2014 0x01F0 4014 CMPB 1 Yes Counter-CompareB Register ACTION-QUALIFIER SUBMODULE REGISTER (1) These registersareonlyavailableon eHRPWM instancesthatincludethehigh-resolutionPWM (HRPWM) extension;otherwise,these locationsarereserved.

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-76.eHRPWM Module Controland StatusRegistersGrouped by Submodule (continued) eHRPWM0 eHRPWM1 eHRPWM2 SIZEACRONYM SHADOW REGISTER DESCRIPTIONBYTE ADDRESS BYTE ADDRESS BYTE ADDRESS (×16) AQCTLA 1 No Action-QualifierControlRegisterfor0x01F0 0016 0x01F0 2016 0x01F0 4016 OutputA (eHRPWMxA) AQCTLB 1 No Action-QualifierControlRegisterfor0x01F0 0018 0x01F0 2018 0x01F0 4018 OutputB (eHRPWMxB) 0x01F0 001A 0x01F0 201A 0x01F0 401A AQSFRC 1 No Action-QualifierSoftwareForceRegister AQCSFRC 1 Yes Action-QualifierContinuousS/W Force0x01F0 001C 0x01F0 201C 0x01F0 401C RegisterSet DEAD-BAND GENERATOR SUBMODULE REGISTER 0x01F0 001E 0x01F0 201E 0x01F0 401E DBCTL 1 No Dead-Band GeneratorControlRegister DBRED 1 No Dead-Band GeneratorRisingEdge Delay0x01F0 0020 0x01F0 2020 0x01F0 4020 Count Register DBFED 1 No Dead-Band GeneratorFallingEdge Delay0x01F0 0022 0x01F0 2022 0x01F0 4022 Count Register PWM-CHOPPER SUBMODULE REGISTER 0x01F0 003C 0x01F0 203C 0x01F0 403C PCCTL 1 No PWM-Chopper ControlRegister TRIP-ZONE SUBMODULE REGISTER 0x01F0 0024 0x01F0 2024 0x01F0 4024 TZSEL 1 No Trip-ZoneSelectRegister 0x01F0 0028 0x01F0 2028 0x01F0 4028 TZCTL 1 No Trip-ZoneControlRegister 0x01F0 002A 0x01F0 202A 0x01F0 402A TZEINT 1 No Trip-ZoneEnableInterruptRegister 0x01F0 002C 0x01F0 202C 0x01F0 402C TZFLG 1 No Trip-ZoneFlagRegister 0x01F0 002E 0x01F0 202E 0x01F0 402E TZCLR 1 No Trip-ZoneClearRegister 0x01F0 0030 0x01F0 2030 0x01F0 4030 TZFRC 1 No Trip-ZoneForceRegister EVENT-TRIGGER SUBMODULE REGISTER 0x01F0 0032 0x01F0 2032 0x01F0 4032 ETSEL 1 No Event-TriggerSelectionRegister 0x01F0 0034 0x01F0 2034 0x01F0 4034 ETPS 1 No Event-TriggerPre-ScaleRegister 0x01F0 0036 0x01F0 2036 0x01F0 4036 ETFLG 1 No Event-TriggerFlagRegister 0x01F0 0038 0x01F0 2038 0x01F0 4038 ETCLR 1 No Event-TriggerClearRegister 0x01F0 003A 0x01F0 203A 0x01F0 403A ETFRC 1 No Event-TriggerForceRegister HIGH-RESOLUTION PWM (HRPWM) SUBMODULE 0x01F0 1020 0x01F0 3020 0x01F0 5020 HRCNFG 1 No HRPWM ConfigurationRegister(2) (2) These registersareonlyavailableon eHRPWM instancesthatincludethehigh-resolutionPWM (HRPWM) extension;otherwise,these locationsarereserved. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 133 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION PWM (A) TZ tw(TZ) td(TZ-PWM)HZ AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

6.21.1 Enhanced Pulse Width Modulator(eHRPWM) Timing

PWM refersto PWM outputson eHRPWM1-6. Table 6-77 shows the PWM timingrequirementsand Table6-78,switchingcharacteristics. Table6-77.eHRPWM Timing Requirements PARAMETER TEST CONDITIONS MIN MAX UNIT tw(SYNCIN) Sync inputpulsewidth Asynchronous 2tc(SCO) cycles Synchronous 2tc(SCO) cycles Table6-78.eHRPWM SwitchingCharacteristics PARAMETER TEST CONDITIONS MIN MAX UNIT tw(PWM) Pulseduration,PWMx outputhigh/low 20 ns tw(SYNCOUT) Sync outputpulsewidth 8tc(SCO) cycles td(PWM)TZA Delaytime,tripinputactivetoPWM forcedhigh no pinload;no additional ns25Delaytime,tripinputactivetoPWM forcedlow programmabledelay td(TZ-PWM)HZ Delaytime,tripinputactivetoPWM Hi-Z no additionalprogrammable ns20delay

6.21.2 Trip-ZoneInputTiming

A. PWM referstoallthePWM pinsinthedevice.The stateofthePWM pinsafterTZ istakenhighdepends on thePWM recoverysoftware. Figure6-46.PWM Hi-ZCharacteristics Table6-79.Trip-ZoneinputTiming Requirements PARAMETER MIN MAX UNIT tw(TZ) Pulseduration,TZx inputlow Asynchronous cycle1tc(SCO) s Synchronous cycle2tc(SCO) s Table6-80shows thehigh-resolutionPWM switchingcharacteristics. Table6-80.High ResolutionPWM CharacteristicsatSYSCLKOUT = (60-100 MHz) PARAMETER MIN TYP MAX UNIT MicroEdge Positioning(MEP) stepsize(1) 200 ps (1) MEP stepsizewillincreasewithlowvoltageand hightemperatureand decreasewithhighvoltageand coldtemperature.

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010

6.22 LCD Controller

Table6-81liststheLCD Controllerregisters. Table6-81.LCD Controller(LCDC) Registers BYTE ACRONYM REGISTER DESCRIPTION ADDRESS 0x01E1 3000 REVID LCD RevisionIdentificationRegister 0x01E1 3004 LCD_CTRL LCD ControlRegister 0x01E1 3008 LCD_STAT LCD StatusRegister 0x01E1 300C LIDD_CTRL LCD LIDD ControlRegister 0x01E1 3010 LIDD_CS0_CONF LCD LIDD CS0 ConfigurationRegister 0x01E1 3014 LIDD_CS0_ADDR LCD LIDD CS0 AddressRead/WriteRegister 0x01E1 3018 LIDD_CS0_DATA LCD LIDD CS0 Data Read/WriteRegister 0x01E1 301C LIDD_CS1_CONF LCD LIDD CS1 ConfigurationRegister 0x01E1 3020 LIDD_CS1_ADDR LCD LIDD CS1 AddressRead/WriteRegister 0x01E1 3024 LIDD_CS1_DATA LCD LIDD CS1 Data Read/WriteRegister 0x01E1 3028 RASTER_CTRL LCD RasterControlRegister 0x01E1 302C RASTER_TIMING_0 LCD RasterTiming0 Register 0x01E1 3030 RASTER_TIMING_1 LCD RasterTiming1 Register 0x01E1 3034 RASTER_TIMING_2 LCD RasterTiming2 Register 0x01E1 3038 RASTER_SUBPANEL LCD RasterSubpanelDisplayRegister 0x01E1 3040 LCDDMA_CTRL LCD DMA ControlRegister 0x01E1 3044 LCDDMA_FB0_BASE LCD DMA Frame Buffer0 Base AddressRegister 0x01E1 3048 LCDDMA_FB0_CEILING LCD DMA Frame Buffer0 CeilingAddressRegister 0x01E1 304C LCDDMA_FB1_BASE LCD DMA Frame Buffer1 Base AddressRegister 0x01E1 3050 LCDDMA_FB1_CEILING LCD DMA Frame Buffer1 CeilingAddressRegister Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 135 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION LCD_AC_ENB_CS LCD_PCLK

1 W_SU

(0 to 31) W_STROBE (1 to 63) W_HOLD (1 to 15) CS_DELAY (0 to 3) R_SU (0 to 31) R_STROBE (1 to 63) R_HOLD (1 to 15) CS_DELAY (0 to 3) LCD_CLK (SYSCLK2) Write Data 5 14 Data[7:0] Not Used 8 9 10 11 RS R/W LCD_D[15:0] LCD_VSYNC LCD_HSYNC Read Status AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

6.22.1 LCD InterfaceDisplayDriver(LIDD Mode)

Table6-82.LCD LIDD Mode Timing Requirements(1) No. PARAMETER MIN MAX UNIT 16 tsu(LCD_D) Setuptime,LCD_D[15:0]validbeforeLCD_CLK (SYSCLK2) ↑ 7 ns 17 th(LCD_D) Holdtime,LCD_D[15:0]validafterLCD_CLK (SYSCLK2) ↑ 0 ns (1) Over operatingfree-airtemperaturerange(unlessotherwisenoted) Table6-83.LCD LIDD Mode Timing Characteristics No. PARAMETER MIN MAX UNIT 4 td(LCD_D_V) Delaytime,LCD_CLK (SYSCLK2) ↑ toLCD_D[15:0]valid(write) 0 7 ns 5 td(LCD_D_I) Delaytime,LCD_CLK (SYSCLK2) ↑ toLCD_D[15:0]invalid(write) 0 7 ns 6 td(LCD_E_A ) Delaytime,LCD_CLK (SYSCLK2) ↑ toLCD_AC_ENB_CS ↓ 0 7 ns 7 td(LCD_E_I) Delaytime,LCD_CLK (SYSCLK2) ↑ toLCD_AC_ENB_CS ↑ 0 7 ns 8 td(LCD_A_A) Delaytime,LCD_CLK (SYSCLK2) ↑ toLCD_VSYNC ↓ 0 7 ns 9 td(LCD_A_I) Delaytime,LCD_CLK (SYSCLK2) ↑ toLCD_VSYNC ↑ 0 7 ns 10 td(LCD_W_A) Delaytime,LCD_CLK (SYSCLK2) ↑ toLCD_HSYNC ↓ 0 7 ns 11 td(LCD_W_I) Delaytime,LCD_CLK (SYSCLK2) ↑ toLCD_HSYNC ↑ 0 7 ns 12 td(LCD_STRB_A) Delaytime,LCD_CLK (SYSCLK2) ↑ toLCD_PCLK ↑ 0 7 ns 13 td(LCD_STRB_I) Delaytime,LCD_CLK (SYSCLK2) ↑ toLCD_PCLK ↓ 0 7 ns 14 td(LCD_D_Z) Delaytime,LCD_CLK (SYSCLK2) ↑ toLCD_D[15:0]in3-state 0 7 ns Delaytime,LCD_CLK (SYSCLK2) ↑ to15 td(Z_LCD_D)3-state)LCD_D[15:0]15 td(Z_LCD_D) 0 7 ns(validfrom3-state) Figure6-47.CharacterDisplayHD44780 Write

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ADVANCE□INFORMATION LCD_AC_ENB_CS LCD_PCLK LCD_VSYNC LCD_HSYNC R_SU R_STROBE R_HOLD (0–31) (1–63) (1–5) CS_DELA Y (0−3) Not Used RS R/W LCD_CLK (SYSCLK2) 2 3 W_SU W_STROBE W_HOLD (0–31) (1–63) (1–15) CS_DELA Y (0 − 3) 8 9 12 13 10 11 Not Used LCD_D[7:0] 14 1716 Read Data 15 4 5 12 13 Data[7:0]W rite Instruction AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Figure6-48.CharacterDisplayHD44780 Read Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 137 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION LCD_D[15:0] LCD_AC_ENB_CS (async mode) LCD_VSYNC LCD_HSYNC LCD_CLK (SYSCLK2) LCD_PCLK W_SU W_STROBE W_HOLD (0−31) (1−63) (1−15) CS_DELA Y (0−3) CS0 CS1 R/W E Clock 2 3 W_SU W_STROBE W_HOLD (0−31) (1−63) (1−15) CS_DELA Y (0−3) 5 4 5 6 7 6 7 8 9 12 13 W rite Address W rite Data 12 13 10 11 10 11 Data[15:0] AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Figure6-49.Micro-InterfaceGraphic Display6800 Write

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ADVANCE□INFORMATION LCD_D[15:0] LCD_AC_ENB_CS (async mode) LCD_VSYNC LCD_HSYNC LCD_CLK (SYSCLK2) LCD_PCLK W_SU W_STROBE W_HOLD (0−31) (1−63) (1−15) CS_DELA Y (0−3) CS0 CS1 R/W E Clock 2 3 R_SU R_STROBE R_HOLD (0−31) (1−63 (1−15) CS_DELA Y (0−3) 5 14 15 6 7 6 7 8 9 12 13 1716 W rite Address Read Data 10 11 1213 Data[15:0] AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Figure6-50.Micro-InterfaceGraphic Display6800 Read Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 139 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION Read Data LCD_D[15:0] LCD_AC_ENB_CS (async mode) LCD_VSYNC LCD_HSYNC LCD_CLK (SYSCLK2) LCD_PCLK R_SU R_STROBE R_HOLD (0−31) (1−63) (1−15) CS_DELA Y (0−3) CS0 CS1 R/W E Clock 2 3 R_STROBE R_HOLD (1−63) (1−15) CS_DELA Y (0−3) 14 15 6 7 6 7 8 9 12 13 171614 1716 15 12 13 Data[15:0] R_SU (0−31) Read Status AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Figure6-51.Micro-InterfaceGraphic Display6800 Status

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ADVANCE□INFORMATION LCD_D[15:0] LCD_AC_ENB_CS (async mode) LCD_VSYNC LCD_HSYNC LCD_CLK (SYSCLK2) LCD_PCLK W_SU W_STROBE W_HOLD (0−31) (1−63) (1−15) CS_DELA Y (0−3) DATA[15:0] CS0 CS1 WR RD Clock 2 3 W_SU W_STROBE W_HOLD (0−31) (1−63) (1−15) CS_DELA Y (0 − 3) 5 4 5 6 7 6 7 8 9 10 11 W rite Address W rite Data 10 11 AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Figure6-52.Micro-InterfaceGraphic Display8080 Write Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 141 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION LCD_D[15:0] LCD_AC_ENB_CS (async mode) LCD_VSYNC LCD_HSYNC LCD_CLK (SYSCLK2) LCD_PCLK W_SU W_STROBE W_HOLD (0−31) (1−63) (1−15) CS_DELA Y (0−3) CS0 CS1 WR RD Clock 2 3 R_SU R_STROBE R_HOLD (0−31) (1−63) (1−15) CS_DELA Y (0−3) 5 14 15 6 7 6 7 8 9 12 13 1716 Read Data 10 11 Data[15:0]W rite Address AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Figure6-53.Micro-InterfaceGraphic Display8080 Read

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ADVANCE□INFORMATION LCD_D[15:0] LCD_AC_ENB_CS LCD_VSYNC LCD_HSYNC LCD_CLK (SYSCLK2) LCD_PCLK R_SU R_STROBE R_HOLD (0−31) (1−63) (1−15) CS_DELA Y (0−3) CS0 CS1 WR RD Clock R_STROBE R_HOLD (1−63) (1−15) CS_DELA Y (0−3) 14 15 6 7 6 12 13 1716 Read Status 14 1716 Read Data 12 13 Data[15:0] R_SU (0−31) AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Figure6-54.Micro-InterfaceGraphic Display8080 Status Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 143 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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6.22.2 LCD RasterMode

Table6-84.LCD RasterMode Timing See Figure6-55throughFigure6-59 No. PARAMETER MIN MAX UNIT 1 tc(PIXEL_CLK) Cycletime,pixelclock 26.6 ns 2 tw(PIXEL_CLK_H) Pulseduration,pixelclockhigh 10 ns 3 tw(PIXEL_CLK_L) Pulseduration,pixelclocklow 10 ns 4 td(LCD_D_V) Delaytime,LCD_PCLK ↑ toLCD_D[15:0]valid(write) 0 12 ns 5 td(LCD_D_IV) Delaytime,LCD_PCLK ↑ toLCD_D[15:0]invalid(write) 0 12 ns 6 td(LCD_AC_ENB_CS_A ) Delaytime,LCD_PCLK ↓ toLCD_AC_ENB_CS ↑ S2 + 0 (1) S2 + 12 (1) ns 7 td(LCD_AC_ENB_CS_I) Delaytime,LCD_PCLK ↓ toLCD_AC_ENB_CS ↓ S2 + 0 (1) S2 + 12 (1) ns 8 td(LCD_VSYNC_A) Delaytime,LCD_PCLK ↓ toLCD_VSYNC ↑ 0 12 ns 9 td(LCD_VSYNC_I) Delaytime,LCD_PCLK ↓ toLCD_VSYNC ↓ 0 12 ns 10 td(LCD_HSYNC_A) Delaytime,LCD_PCLK ↑ toLCD_HSYNC ↑ 0 12 ns 11 td(LCD_HSYNC_I) Delaytime,LCD_PCLK ↑ toLCD_HSYNC ↓ 0 12 ns (1) S2 = SYSCLK2 cycletimeinns Frame-to-frametimingis derivedthroughthe followingparametersin the LCD (RASTER_TIMING_1) register:

Verticalfrontporch(VFP)
Verticalsyncpulsewidth(VSW)
Verticalback porch(VBP)
Linesperpanel(LPP) Line-to-linetimingisderivedthroughthefollowingparametersintheLCD (RASTER_TIMING_0) register:
Horizontalfrontporch(HFP)
Horizontalsyncpulsewidth(HSW)
Horizontalback porch(HBP)
Pixelsperpanel(PPL) LCD_AC_ENB_CS timingisderivedthroughthe followingparameterinthe LCD (RASTER_TIMING_2) register:
AC biasfrequency(ACB) The displayformatproducedinrastermode isshown inFigure6-55.An entireframeisdeliveredone line at a time.The firstlinedeliveredstartsat data pixel(1,1) and ends at data pixel(P,1).The lastline deliveredstartsat data pixel(1,L) and ends at data pixel(P,L).The beginningof each new frame is denotedby theactivationofI/OsignalLCD_VSYNC. The beginningofeach new lineisdenotedby the activationofI/OsignalLCD_HSYNC.

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ADVANCE□INFORMATION LCD 1, 1 2, 1 3, 1 1, 2 2, 2 1, 3 P, 1P−1, P−2, P, 2P−1, P, 3 1, L L−1 L−2 3, L2, L L−1 P, L P−1, L−1 L−1 P−1, L L−2 P−2, L Data Pixels (From 1 to P) Data Lines (From 1 to L) AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Figure6-55.LCD Raster-Mode DisplayFormat Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 145 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION CLK LCD_HSYNC Hsync LCD_VSYNC (1 to 64) VSW (1 to 64) VSW (0 to 255) VFP (1 to 1024) Frame Time ~ 70Hz LPP (0 to 255) LCD_D[15:0] 1, 1 P, 1 1, 2 P, 2 1, L P, L 1, L−1 P, L−1 Line Time LCD_HSYNC Hsync 10 11 LCD_PCLK PLL 16 /C0121 (1 to 1024) HBP (1 to 256) Line 1 (1 to 256) HFP (1 to 64) HSW PLL 16 /C0121 (1 to 1024) Line 2 Vsync Data Data Active TFT ACB (0 to 255) LCD_AC_ENB_CS Enable ACB (0 to 255) VBP AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Figure6-56.LCD Raster-Mode Active

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ADVANCE□INFORMATION LCD_HSYNC LP LCD_VSYNC VSW = 1 (1 to 1024) Frame Time ~ 70Hz LPP LCD_D[7:0] 1, L−2 P, L−2 1, L−4 P, L−4 Line Time LCD_HSYNC LP 10 11 LCD_PCLK PPL 16 /C0121 (1 to 1024) HBP (1 to 256) Line 5 HFP (1 to 64) HSW PPL 16 /C0121 (1 to 2024) Line 6 1, 1: P, 1 1, 5: P, 5 1, L−1 P, L−1 1, L 1, L−1 P, L−1 1, L−3 P, L−3 (1 to 64) VSW = 1 (1 to 64) VFP = 0 VBP = 0 VFP = 0 VBP = 0 FP Data CP Data Passive STN LCD_AC_ENB_CS M ACB (0 to 255) ACB (0 to 255) 1, 4: P, 4 1, 3: P, 3 1, 2: P, 2 1, L: P, L 1, 6: P, 6 1, 2 P, 2 1, 1 P, 1 1, L P, L (1 to 256) AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Figure6-57.LCD Raster-Mode Passive Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 147 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION LCD_HSYNC LCD_PCLK (active mode) LCD_D[15:0] (active mode) 1,□L P,□L2,□L PPL 16 ×(1□to□1024) HBP (1□to□256 Line□L (1□to□256) HFP (1□to□64) HSW PPL 16 ×(1□to□1024) Line□1□(Passive□Only) LCD_VSYNC LCD_PCLK (passive mode) LCD_AC_ENB_CS LCD_D[7:0] (passive mode) 1,□L 2,□1 P,□1P,□L2,□L 1,□1 10 11 2 3 2 3 VSW = 1 VFP =□0 VBP =□0 AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Figure6-58.LCD Raster-Mode ControlSignalActivation

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ADVANCE□INFORMATION LCD_HSYNC LCD_PCLK (active mode) LCD_D[15:0] (active mode) PPL 16 ×(1□to□1024) HBP (1□to□256 Line□1□for□passive (1□to□256) HFP (1□to□64) HSW PPL 16 ×(1□to□1024) Line□1□for□active LCD_VSYNC LCD_PCLK (passive mode) LCD_AC_ENB_CS LCD_D[7:0] (passive mode) 1,□1 2,□2 P,□2P,□12,□1 1,□2 10 11 4 5 2 3 VSW = 1 VFP =□0 VBP =□0 P,□11,□1 2,□1 4 5 Line□2□for□passive AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Figure6-59.LCD Raster-Mode ControlSignalDeactivation Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 149 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

6.23 Timers

The timerssupportthefollowingfeatures:

Configurableas single64-bittimerortwo 32-bittimers
Periodtimeoutsgenerateinterrupts,DMA eventsorexternalpinevents
8 32-bitcompare registers
Compare matches generateinterruptevents
Capturecapability
64-bitWatchdog capability(Timer64P1only) Table6-85liststhetimerregisters. Table6-85.Timer Registers Timer64P 0 Timer64P 1 ACRONYM REGISTER DESCRIPTION 0x01C2 0000 0x01C2 1000 REV RevisionRegister 0x01C2 0004 0x01C2 1004 EMUMGT EmulationManagement Register 0x01C2 0008 0x01C2 1008 GPINTGPEN GPIO Interruptand GPIO EnableRegister 0x01C2 000C 0x01C2 100C GPDATGPDIR GPIO Data and GPIO DirectionRegister 0x01C2 0010 0x01C2 1010 TIM12 TimerCounterRegister12 0x01C2 0014 0x01C2 1014 TIM34 TimerCounterRegister34 0x01C2 0018 0x01C2 1018 PRD12 TimerPeriodRegister12 0x01C2 001C 0x01C2 101C PRD34 TimerPeriodRegister34 0x01C2 0020 0x01C2 1020 TCR TimerControlRegister 0x01C2 0024 0x01C2 1024 TGCR TimerGlobalControlRegister 0x01C2 0028 0x01C2 1028 WDTCR Watchdog TimerControlRegister 0x01C2 0034 0x01C2 1034 REL12 TimerReloadRegister12 0x01C2 0038 0x01C2 1038 REL34 TimerReloadRegister34 0x01C2 003C 0x01C2 103C CAP12 TimerCaptureRegister12 0x01C2 0040 0x01C2 1040 CAP34 TimerCaptureRegister34 0x01C2 0044 0x01C2 1044 INTCTLSTAT TimerInterruptControland StatusRegister 0x01C2 0060 0x01C2 1060 CMP0 Compare Register0 0x01C2 0064 0x01C2 1064 CMP1 Compare Register1 0x01C2 0068 0x01C2 1068 CMP2 Compare Register2 0x01C2 006C 0x01C2 106C CMP3 Compare Register3 0x01C2 0070 0x01C2 1070 CMP4 Compare Register4 0x01C2 0074 0x01C2 1074 CMP5 Compare Register5 0x01C2 0078 0x01C2 1078 CMP6 Compare Register6 0x01C2 007C 0x01C2 107C CMP7 Compare Register7

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ADVANCE□INFORMATION TM64P0_IN12 TM64P0_OUT12 5 6 AM1707 www.ti.com SPRS637 –FEBRUARY 2010

6.23.1 Timer ElectricalData/Timing

Table6-86.Timing Requirements forTimer Input(1)(2)(seeFigure6-60) No. PARAMETER MIN MAX UNIT 1 tc(TM64Px_IN12) Cycletime,TM64Px_IN12 4P ns 2 tw(TINPH) Pulseduration,TM64Px_IN12 high 0.45C 0.55C ns 3 tw(TINPL) Pulseduration,TM64Px_IN12 low 0.45C 0.55C ns 4 tt(TM64Px_IN12) Transitiontime,TM64Px_IN12 0.05C ns (1) P = OSCIN cycletimeinns.Forexample,when OSCIN frequencyis27 MHz, use P = 37.037 ns. (2) C = TM64P0_IN12 cycletimeinns.Forexample,when TM64Px_IN12 frequencyis27 MHz, use C = 37.037 ns Figure6-60.Timer Timing Table6-87.SwitchingCharacteristicsOver Recommended OperatingConditionsforTimer Output (1) No. PARAMETER MIN MAX UNIT 5 tw(TOUTH) Pulseduration,TM64P0_OUT12 high 4P ns 6 tw(TOUTL) Pulseduration,TM64P0_OUT12 low 4P ns (1) P = OSCIN cycletimeinns.Forexample,when OSCIN frequencyis27 MHz, use P = 37.037 ns. Figure6-61.Timer Timing Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 151 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION Peripheral Configuration Bus Noise Filter Noise Filter Clock Prescaler I2CPSCx Prescaler Register Bit Clock Generator I2CCLKHx Clock Divide High Register I2CCLKLx Clock Divide Low Register Control I2CCOARx Own Address Register I2CSARx Slave Address Register I2CCMDRx Mode Register I2CEMDRx Extended Mode Register I2CCNTx Data Count Register I2CPID1 Peripheral ID Register 1 I2CPID2 Peripheral ID Register 2 Transmit I2CXSRx Transmit Shift Register I2CDXRx T ransmit Buffer Receive I2CDRRx Receive Buffer I2CRSRx Receive Shift Register I2Cx_SCL I2Cx_SDA Control Interrupt/DMA I2CIERx Interrupt Enable Register I2CSTRx Interrupt Status Register I2CSRCx Interrupt Source Register Control I2CPFUNC Pin Function Register I2CPDIR Pin Direction Register I2CPDIN Pin Data In Register I2CPDOUT Pin Data Out Register I2CPDSET Pin Data Set Register I2CPDCLR Pin Data Clear Register Interrupt DMA Requests AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

6.24 Inter-IntegratedCircuitSerialPorts(I2C0,I2C1)

6.24.1 I2C Device-SpecificInformation

Havingtwo I2C modules on thedevicesimplifiessystem architecture.Figure6-62isblockdiagramofthe I2C Module. Each I2C portsupports:

CompatiblewithPhilips® I2C SpecificationRevision2.1(January2000)
FastMode up to400 Kbps (nofail-safeI/Obuffers)
NoiseFiltertoRemove Noise50 ns orless
Seven-and Ten-BitDeviceAddressingModes
Master(Transmit/Receive)and Slave(Transmit/Receive)Functionality
Events:DMA, Interrupt,orPolling
General-PurposeI/OCapabilityifnotused as I2C Figure6-62.I2C Module Block Diagram

6.24.2 I2C PeripheralRegistersDescription(s)

Table6-88isthelistoftheI2C registers.

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-88.Inter-IntegratedCircuit(I2C)Registers I2C0 I2C1 ACRONYM REGISTER DESCRIPTION BYTE ADDRESS BYTE ADDRESS 0x01C2 2000 0x01E2 8000 ICOAR I2C Own AddressRegister 0x01C2 2004 0x01E2 8004 ICIMR I2C InterruptMask Register 0x01C2 2008 0x01E2 8008 ICSTR I2C InterruptStatusRegister 0x01C2 200C 0x01E2 800C ICCLKL I2C ClockLow-Time DividerRegister 0x01C2 2010 0x01E2 8010 ICCLKH I2C ClockHigh-TimeDividerRegister 0x01C2 2014 0x01E2 8014 ICCNT I2C Data Count Register 0x01C2 2018 0x01E2 8018 ICDRR I2C Data ReceiveRegister 0x01C2 201C 0x01E2 801C ICSAR I2C SlaveAddressRegister 0x01C2 2020 0x01E2 8020 ICDXR I2C Data TransmitRegister 0x01C2 2024 0x01E2 8024 ICMDR I2C Mode Register 0x01C2 2028 0x01E2 8028 ICIVR I2C InterruptVectorRegister 0x01C2 202C 0x01E2 802C ICEMDR I2C ExtendedMode Register 0x01C2 2030 0x01E2 8030 ICPSC I2C PrescalerRegister 0x01C2 2034 0x01E2 8034 REVID1 I2C RevisionIdentificationRegister1 0x01C2 2038 0x01E2 8038 REVID2 I2C RevisionIdentificationRegister2 0x01C2 2048 0x01E2 8048 ICPFUNC I2C PinFunctionRegister 0x01C2 204C 0x01E2 804C ICPDIR I2C PinDirectionRegister 0x01C2 2050 0x01E2 8050 ICPDIN I2C PinData InRegister 0x01C2 2054 0x01E2 8054 ICPDOUT I2C PinData Out Register 0x01C2 2058 0x01E2 8058 ICPDSET I2C PinData SetRegister 0x01C2 205C 0x01E2 805C ICPDCLR I2C PinData ClearRegister Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 153 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

6.24.3 I2C ElectricalData/Timing

6.24.3.1Inter-IntegratedCircuit(I2C)Timing Table6-89and Table6-90assume testingoverrecommended operatingconditions(seeFigure6-63and Figure6-64). Table6-89.I2C InputTiming Requirements No. PARAMETER MIN MAX UNIT StandardMode 10 1 tc(SCL) Cycletime,I2Cx_SCL ms FastMode 2.5 StandardMode 4.7 2 tsu(SCLH-SDAL) Setuptime,I2Cx_SCL highbeforeI2Cx_SDA low ms FastMode 0.6 StandardMode 4 3 th(SCLL-SDAL) Holdtime,I2Cx_SCL lowafterI2Cx_SDA low ms FastMode 0.6 StandardMode 4.7 4 tw(SCLL) Pulseduration,I2Cx_SCL low ms FastMode 1.3 StandardMode 4 5 tw(SCLH) Pulseduration,I2Cx_SCL high ms FastMode 0.6 StandardMode 250 6 tsu(SDA-SCLH) Setuptime,I2Cx_SDA beforeI2Cx_SCL high ns FastMode 100 StandardMode 0 7 th(SDA-SCLL) Holdtime,I2Cx_SDA afterI2Cx_SCL low ms FastMode 0 0.9 StandardMode 4.7 8 tw(SDAH) Pulseduration,I2Cx_SDA high ms FastMode 1.3 StandardMode 1000 9 tr(SDA) Risetime,I2Cx_SDA ns FastMode 20 + 0.1Cb 300 StandardMode 1000 10 tr(SCL) Risetime,I2Cx_SCL ns FastMode 20 + 0.1Cb 300 StandardMode 300 11 tf(SDA) Falltime,I2Cx_SDA ns FastMode 20 + 0.1Cb 300 StandardMode 300 12 tf(SCL) Falltime,I2Cx_SCL ns FastMode 20 + 0.1Cb 300 StandardMode 4 13 tsu(SCLH-SDAH) Setuptime,I2Cx_SCL highbeforeI2Cx_SDA high ms FastMode 0.6 StandardMode N/A 14 tw(SP) Pulseduration,spike(mustbe suppressed) ns FastMode 0 50 StandardMode 400

15 C b Capacitiveloadforeach bus line pF

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ADVANCE□INFORMATION 6 14 Stop Start Repeated Start Stop I2Cx_SDA I2Cx_SCL 11 9 AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-90.I2C SwitchingCharacteristics(1) No. PARAMETER MIN MAX UNIT StandardMode 10 16 tc(SCL) Cycletime,I2Cx_SCL ms FastMode 2.5 StandardMode 4.7Setuptime,I2Cx_SCL highbeforeI2Cx_SDA17 tsu(SCLH-SDAL) mslow FastMode 0.6 StandardMode 4 18 th(SDAL-SCLL) Holdtime,I2Cx_SCL lowafterI2Cx_SDA low ms FastMode 0.6 StandardMode 4.7 19 tw(SCLL) Pulseduration,I2Cx_SCL low ms FastMode 1.3 StandardMode 4 20 tw(SCLH) Pulseduration,I2Cx_SCL high ms FastMode 0.6 StandardMode 250Setuptime,I2Cx_SDA validbeforeI2Cx_SCL21 tsu(SDAV-SCLH) nshigh FastMode 100 StandardMode 0 22 th(SCLL-SDAV) Holdtime,I2Cx_SDA validafterI2Cx_SCL low ms FastMode 0 0.9 StandardMode 4.7 23 tw(SDAH) Pulseduration,I2Cx_SDA high ms FastMode 1.3 StandardMode 4Setuptime,I2Cx_SCL highbeforeI2Cx_SDA28 tsu(SCLH-SDAH) mshigh FastMode 0.6 (1) I2C must be configuredcorrectlytomeet thetimingsinTable6-90. Figure6-63.I2C Receive Timings Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 155 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION Stop Start Repeated Start Stop I2Cx_SDA I2Cx_SCL 26 24 AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Figure6-64.I2C TransmitTimings

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010

6.25 UniversalAsynchronous Receiver/Transmitter(UART)

The devicehas 3 UART peripherals.Each UART has thefollowingfeatures:

16-bytestoragespace forboththetransmitterand receiverFIFOs
1,4,8,or14 byteselectablereceiverFIFO triggerlevelforautoflowcontroland DMA
DMA signalingcapabilityforbothreceivedand transmitteddata
Programmable auto-rtsand auto-ctsforautoflowcontrol
Programmable Baud Rate up to3MBaud
Programmable OversamplingOptionsofx13 and x16
Frequencypre-scalevaluesfrom1 to65,535togenerateappropriatebaud rates
Prioritizedinterrupts
Programmable serialdataformats – 5,6,7,or8-bitcharacters – Even,odd,orno paritybitgenerationand detection – 1,1.5,or2 stopbitgeneration
Falsestartbitdetection
Linebreakgenerationand detection
Internaldiagnosticcapabilities – Loopback controlsforcommunicationslinkfaultisolation – Break,parity,overrun,and framingerrorsimulation
Modem controlfunctions(CTS,RTS) on UART0 only. The UART registersarelistedinSection6.25.1

6.25.1 UART PeripheralRegistersDescription(s)

Table6-91isthelistofUART registers. Table6-91.UART Registers UART0 UART1 UART2 ACRONYM REGISTER DESCRIPTION BYTE ADDRESS BYTE ADDRESS BYTE ADDRESS 0x01C4 2000 0x01D0 C000 0x01D0 D000 RBR ReceiverBufferRegister(readonly) 0x01C4 2000 0x01D0 C000 0x01D0 D000 THR TransmitterHoldingRegister(writeonly) 0x01C4 2004 0x01D0 C004 0x01D0 D004 IER InterruptEnableRegister 0x01C4 2008 0x01D0 C008 0x01D0 D008 IIR InterruptIdentificationRegister(readonly) 0x01C4 2008 0x01D0 C008 0x01D0 D008 FCR FIFO ControlRegister(writeonly) 0x01C4 200C 0x01D0 C00C 0x01D0 D00C LCR LineControlRegister 0x01C4 2010 0x01D0 C010 0x01D0 D010 MCR Modem ControlRegister 0x01C4 2014 0x01D0 C014 0x01D0 D014 LSR LineStatusRegister 0x01C4 2018 0x01D0 C018 0x01D0 D018 MSR Modem StatusRegister 0x01C4 201C 0x01D0 C01C 0x01D0 D01C SCR ScratchpadRegister 0x01C4 2020 0x01D0 C020 0x01D0 D020 DLL DivisorLSB Latch 0x01C4 2024 0x01D0 C024 0x01D0 D024 DLH DivisorMSB Latch 0x01C4 2028 0x01D0 C028 0x01D0 D028 REVID1 RevisionIdentificationRegister1 0x01C4 2030 0x01D0 C030 0x01D0 D030 PWREMU_MGMT Power and EmulationManagement Register 0x01C4 2034 0x01D0 C034 0x01D0 D034 MDR Mode DefinitionRegister Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 157 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION Start Bit Data Bits UART_TXDn UART_RXDn Data Bits Bit Start AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

6.25.2 UART ElectricalData/Timing

Table6-92.Timing Requirements forUARTx Receive(1)(seeFigure6-65) No. PARAMETER MIN MAX UNIT 4 tw(URXDB) Pulseduration,receivedatabit(RXDn) 0.96U 1.05U ns 5 tw(URXSB) Pulseduration,receivestartbit 0.96U 1.05U ns (1) U = UART baud time= 1/programmedbaud rate. Table6-93.SwitchingCharacteristicsOver Recommended OperatingConditionsforUARTx Transmit(1) (seeFigure6-65) No. PARAMETER MIN MAX UNIT 1 f(baud) Maximum programmablebaud rate D/E (2)(3) MBaud (4) 2 tw(UTXDB) Pulseduration,transmitdatabit(TXDn) U -2 U + 2 ns 3 tw(UTXSB) Pulseduration,transmitstartbit U -2 U + 2 ns (1) U = UART baud time= 1/programmedbaud rate. (2) D = UART inputclockinMHz. The UART(s) inputclocksourceisPLL0_SYSCLK2. (3) E = UART divisorx UART samplingrate.The UART divisorissetthroughtheUART divisorlatchregisters(DLL and DLH).The UART samplingrateissetthroughtheover-samplingmode selectbit(OSM_SEL) oftheUART mode definitionregister(MDR). (4) Baud rateisnotindicativeofdatarate.Actualdataratewillbe limitedby systemfactorssuch as EDMA loading,EMIF loading,system frequency,etc. Figure6-65.UART Transmit/ReceiveTiming

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 6.26 USB1 Host ControllerRegisters(USB1.1 OHCI) AllthedeviceUSB interfacesarecompliantwithUniversalSerialBus Specifications,Revision1.1. Table6-94isthelistofUSB HostControllerregisters. Table6-94.USB1 Host ControllerRegisters USB 1 ACRONYM REGISTER DESCRIPTION BYTE ADDRESS 0x01E2 5000 HCREVISION OHCI RevisionNumber Register 0x01E2 5004 HCCONTROL HC OperatingMode Register 0x01E2 5008 HCCOMMANDSTATUS HC Command and StatusRegister 0x01E2 500C HCINTERRUPTSTATUS HC Interruptand StatusRegister 0x01E2 5010 HCINTERRUPTENABLE HC InterruptEnableRegister 0x01E2 5014 HCINTERRUPTDISABLE HC InterruptDisableRegister 0x01E2 5018 HCHCCA HC HCAA AddressRegister(1) 0x01E2 501C HCPERIODCURRENTED HC CurrentPeriodicRegister(1) 0x01E2 5020 HCCONTROLHEADED HC Head ControlRegister(1) 0x01E2 5024 HCCONTROLCURRENTED HC CurrentControlRegister(1) 0x01E2 5028 HCBULKHEADED HC Head BulkRegister(1) 0x01E2 502C HCBULKCURRENTED HC CurrentBulkRegister(1) 0x01E2 5030 HCDONEHEAD HC Head Done Register(1) 0x01E2 5034 HCFMINTERVAL HC Frame IntervalRegister 0x01E2 5038 HCFMREMAINING HC Frame RemainingRegister 0x01E2 503C HCFMNUMBER HC Frame Number Register 0x01E2 5040 HCPERIODICSTART HC PeriodicStartRegister 0x01E2 5044 HCLSTHRESHOLD HC Low-Speed ThresholdRegister 0x01E2 5048 HCRHDESCRIPTORA HC Root Hub A Register 0x01E2 504C HCRHDESCRIPTORB HC Root Hub B Register 0x01E2 5050 HCRHSTATUS HC Root Hub StatusRegister 0x01E2 5054 HCRHPORTSTATUS1 HC Port1 Statusand ControlRegister(2) 0x01E2 5058 HCRHPORTSTATUS2 HC Port2 Statusand ControlRegister(3) (1) Restrictionsapplytothephysicaladdressesused intheseregisters. (2) ConnectedtotheintegratedUSB1.1 phy pins(USB1_DM, USB1_DP). (3) Althoughthecontrollerimplementstwo ports,thesecond portcannotbe used. Table6-95.SwitchingCharacteristicsOver Recommended OperatingConditionsforUSB1 LOW SPEED FULL SPEED No. PARAMETER UNIT MIN MAX MAX MAX U1 tr Risetime,USB1_DP and USB1_DM signals(1) 75(1) 300(1) 4(1) 20(1) ns U2 tf Falltime,USB1_DP and USB1_DM signals(1) 75(1) 300(1) 4(1) 20(1) ns U3 tRFM Rise/Falltimematching(2) 80(2) 120(2) 90(2) 110(2) % U4 VCRS Outputsignalcross-overvoltage(1) 1.3(1) 2(1) 1.3(1) 2(1) V U5 tj Differentialpropagationjitter(3) -25(3) 25(3) -2(3) 2(3) ns U6 fop Operatingfrequency(4) 1.5 12 MHz (1) Low Speed:C L = 200 pF.HighSpeed:C L = 50pF (2) tRFM =(tr/tf)x 100 (3) tjr= tpx(1)-tpx(0) (4) fop = 1/tper Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 159 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

6.26.1 USB1 Unused SignalConfiguration

IfUSB1 isunused,thentheUSB1 signalsshouldbe configuredas shown belowinTable6-1.

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 6.27 USB0 OTG (USB2.0 OTG) The deviceUSB2.0 peripheralsupportsthefollowingfeatures:

USB 2.0peripheralatspeeds highspeed (HS:480 Mb/s )and fullspeed (FS:12 Mb/s)
USB 2.0hostatspeeds HS, FS, and lowspeed (LS:1.5Mb/s)
Alltransfermodes (control,bulk,interrupt,and isochronous)
4 Transmit(TX)and 4 Receive(RX)endpointsinadditiontoendpoint0
FIFO RAM – 4K endpoint – Programmable size
IntegratedUSB 2.0HighSpeed PHY
Connectstoa standardCharge Pump forVBUS 5 V generation
RNDIS mode foracceleratingRNDIS typeprotocolsusingshortpacketterminationoverUSB ImportantNotice:On the originaldevicepinout(marked "A"inthe lowerrightcornerof the package), pinsUSB0_VSSA33 (H4) and USB0_VSSA (F3)were connectedto ground outsidethe package.For more robustESD performance,theUSB0 ground referencesare now connectedinsidethepackage on packages marked "B"and thepackage pinsare unconnected.Thischange willrequirethatany external filtercircuitspreviouslyreferencedtogroundatthesepinswillneed toreferencetheboardgroundinstead. Table6-96isthelistofUSB OTG registers. Table6-96.UniversalSerialBus OTG (USB0) Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E0 0000 REVID RevisionRegister 0x01E0 0004 CTRLR ControlRegister 0x01E0 0008 STATR StatusRegister 0x01E0 000C EMUR EmulationRegister 0x01E0 0010 MODE Mode Register 0x01E0 0014 AUTOREQ AutorequestRegister 0x01E0 0018 SRPFIXTIME SRP FixTime Register 0x01E0 001C TEARDOWN Teardown Register 0x01E0 0020 INTSRCR USB InterruptSourceRegister 0x01E0 0024 INTSETR USB InterruptSourceSetRegister 0x01E0 0028 INTCLRR USB InterruptSourceClearRegister 0x01E0 002C INTMSKR USB InterruptMask Register 0x01E0 0030 INTMSKSETR USB InterruptMask SetRegister 0x01E0 0034 INTMSKCLRR USB InterruptMask ClearRegister 0x01E0 0038 INTMASKEDR USB InterruptSourceMasked Register 0x01E0 003C EOIR USB End ofInterruptRegister 0x01E0 0040 INTVECTR USB InterruptVectorRegister 0x01E0 0050 GENRNDISSZ1 GenericRNDIS SizeEP1 0x01E0 0054 GENRNDISSZ2 GenericRNDIS SizeEP2 0x01E0 0058 GENRNDISSZ3 GenericRNDIS SizeEP3 0x01E0 005C GENRNDISSZ4 GenericRNDIS SizeEP4 0x01E0 0400 FADDR FunctionAddressRegister 0x01E0 0401 POWER Power Management Register 0x01E0 0402 INTRTX InterruptRegisterforEndpoint0 plusTransmitEndpoints1 to4 0x01E0 0404 INTRRX InterruptRegisterforReceiveEndpoints1 to4 0x01E0 0406 INTRTXE InterruptenableregisterforINTRTX 0x01E0 0408 INTRRXE InterruptEnableRegisterforINTRRX Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 161 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-96.UniversalSerialBus OTG (USB0) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E0 040A INTRUSB InterruptRegisterforCommon USB Interrupts 0x01E0 040B INTRUSBE InterruptEnableRegisterforINTRUSB 0x01E0 040C FRAME Frame Number Register 0x01E0 040E INDEX IndexRegisterforSelectingtheEndpointStatusand ControlRegisters 0x01E0 040F TESTMODE RegistertoEnabletheUSB 2.0TestModes INDEXED REGISTERS These registersoperateon theendpointselectedby theINDEX register 0x01E0 0410 TXMAXP Maximum PacketSizeforPeripheral/HostTransmitEndpoint(Indexregistersettoselect Endpoints1-4only) 0x01E0 0412 PERI_CSR0 ControlStatusRegisterforEndpoint0 inPeripheralMode. (IndexregistersettoselectEndpoint HOST_CSR0 ControlStatusRegisterforEndpoint0 inHostMode. (IndexregistersettoselectEndpoint0) PERI_TXCSR ControlStatusRegisterforPeripheralTransmitEndpoint.(IndexregistersettoselectEndpoints 1-4) HOST_TXCSR ControlStatusRegisterforHostTransmitEndpoint. (IndexregistersettoselectEndpoints1-4) 0x01E0 0414 RXMAXP Maximum PacketSizeforPeripheral/HostReceiveEndpoint(Indexregistersettoselect Endpoints1-4only) 0x01E0 0416 PERI_RXCSR ControlStatusRegisterforPeripheralReceiveEndpoint.(IndexregistersettoselectEndpoints 1-4) HOST_RXCSR ControlStatusRegisterforHostReceiveEndpoint. (IndexregistersettoselectEndpoints1-4) 0x01E0 0418 COUNT0 Number ofReceivedBytesinEndpoint0 FIFO. (IndexregistersettoselectEndpoint0) RXCOUNT Number ofBytesinHostReceiveEndpointFIFO. (IndexregistersettoselectEndpoints1-4) 0x01E0 041A HOST_TYPE0 Definesthespeed ofEndpoint0 HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehost Transmitendpoint.(IndexregistersettoselectEndpoints1-4only) 0x01E0 041B HOST_NAKLIMIT0 SetstheNAK responsetimeouton Endpoint0. (IndexregistersettoselectEndpoint0) HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK responsetimeouton Bulk transactionsforhostTransmitendpoint.(IndexregistersettoselectEndpoints1-4only) 0x01E0 041C HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehost Receiveendpoint.(IndexregistersettoselectEndpoints1-4only) 0x01E0 041D HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK responsetimeouton Bulk transactionsforhostReceiveendpoint.(IndexregistersettoselectEndpoints1-4only) 0x01E0 041F CONFIGDATA Returnsdetailsofcoreconfiguration.(IndexregistersettoselectEndpoint0) FIFO 0x01E0 0420 FIFO0 Transmitand ReceiveFIFO RegisterforEndpoint0 0x01E0 0424 FIFO1 Transmitand ReceiveFIFO RegisterforEndpoint1 0x01E0 0428 FIFO2 Transmitand ReceiveFIFO RegisterforEndpoint2 0x01E0 042C FIFO3 Transmitand ReceiveFIFO RegisterforEndpoint3 0x01E0 0430 FIFO4 Transmitand ReceiveFIFO RegisterforEndpoint4 OTG DEVICE CONTROL 0x01E0 0460 DEVCTL DeviceControlRegister

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-96.UniversalSerialBus OTG (USB0) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION DYNAMIC FIFO CONTROL 0x01E0 0462 TXFIFOSZ TransmitEndpointFIFO Size (IndexregistersettoselectEndpoints1-4only) 0x01E0 0463 RXFIFOSZ ReceiveEndpointFIFO Size (IndexregistersettoselectEndpoints1-4only) 0x01E0 0464 TXFIFOADDR TransmitEndpointFIFO Address (IndexregistersettoselectEndpoints1-4only) 0x01E0 0466 RXFIFOADDR ReceiveEndpointFIFO Address (IndexregistersettoselectEndpoints1-4only) 0x01E0 046C HWVERS Hardware VersionRegister TARGET ENDPOINT 0 CONTROL REGISTERS, VALID ONLY IN HOST MODE 0x01E0 0480 TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedTransmit Endpoint. 0x01E0 0482 TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint.Thisis used onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 0483 TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 0484 RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedReceive Endpoint. 0x01E0 0486 RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint.Thisis used onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 0487 RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. TARGET ENDPOINT 1 CONTROL REGISTERS, VALID ONLY IN HOST MODE 0x01E0 0488 TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedTransmit Endpoint. 0x01E0 048A TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint.Thisis used onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 048B TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 048C RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedReceive Endpoint. 0x01E0 048E RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint.Thisis used onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 048F RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. TARGET ENDPOINT 2 CONTROL REGISTERS, VALID ONLY IN HOST MODE 0x01E0 0490 TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedTransmit Endpoint. 0x01E0 0492 TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint.Thisis used onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 0493 TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 0494 RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedReceive Endpoint. 0x01E0 0496 RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint.Thisis used onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 0497 RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. TARGET ENDPOINT 3 CONTROL REGISTERS, VALID ONLY IN HOST MODE 0x01E0 0498 TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedTransmit Endpoint. 0x01E0 049A TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint.Thisis used onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 163 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-96.UniversalSerialBus OTG (USB0) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E0 049B TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 049C RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedReceive Endpoint. 0x01E0 049E RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint.Thisis used onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 049F RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. TARGET ENDPOINT 4 CONTROL REGISTERS, VALID ONLY IN HOST MODE 0x01E0 04A0 TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedTransmit Endpoint. 0x01E0 04A2 TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint.Thisis used onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 04A3 TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 04A4 RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedReceive Endpoint. 0x01E0 04A6 RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint.Thisis used onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 04A7 RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub.

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-96.UniversalSerialBus OTG (USB0) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION CONTROL AND STATUS REGISTER FOR ENDPOINT 0 0x01E0 0502 PERI_CSR0 ControlStatusRegisterforEndpoint0 inPeripheralMode HOST_CSR0 ControlStatusRegisterforEndpoint0 inHostMode 0x01E0 0508 COUNT0 Number ofReceivedBytesinEndpoint0 FIFO 0x01E0 050A HOST_TYPE0 DefinestheSpeed ofEndpoint0 0x01E0 050B HOST_NAKLIMIT0 SetstheNAK Response Timeouton Endpoint0 0x01E0 050F CONFIGDATA Returnsdetailsofcoreconfiguration. CONTROL AND STATUS REGISTER FOR ENDPOINT 1 0x01E0 0510 TXMAXP Maximum PacketSizeforPeripheral/HostTransmitEndpoint 0x01E0 0512 PERI_TXCSR ControlStatusRegisterforPeripheralTransmitEndpoint(peripheralmode) HOST_TXCSR ControlStatusRegisterforHostTransmitEndpoint(hostmode) 0x01E0 0514 RXMAXP Maximum PacketSizeforPeripheral/HostReceiveEndpoint 0x01E0 0516 PERI_RXCSR ControlStatusRegisterforPeripheralReceiveEndpoint(peripheralmode) HOST_RXCSR ControlStatusRegisterforHostReceiveEndpoint(hostmode) 0x01E0 0518 RXCOUNT Number ofBytesinHostReceiveendpointFIFO 0x01E0 051A HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehost Transmitendpoint. 0x01E0 051B HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK responsetimeouton Bulk transactionsforhostTransmitendpoint. 0x01E0 051C HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehost Receiveendpoint. 0x01E0 051D HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK responsetimeouton Bulk transactionsforhostReceiveendpoint. CONTROL AND STATUS REGISTER FOR ENDPOINT 2 0x01E0 0520 TXMAXP Maximum PacketSizeforPeripheral/HostTransmitEndpoint 0x01E0 0522 PERI_TXCSR ControlStatusRegisterforPeripheralTransmitEndpoint(peripheralmode) HOST_TXCSR ControlStatusRegisterforHostTransmitEndpoint(hostmode) 0x01E0 0524 RXMAXP Maximum PacketSizeforPeripheral/HostReceiveEndpoint 0x01E0 0526 PERI_RXCSR ControlStatusRegisterforPeripheralReceiveEndpoint(peripheralmode) HOST_RXCSR ControlStatusRegisterforHostReceiveEndpoint(hostmode) 0x01E0 0528 RXCOUNT Number ofBytesinHostReceiveendpointFIFO 0x01E0 052A HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehost Transmitendpoint. 0x01E0 052B HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK responsetimeouton Bulk transactionsforhostTransmitendpoint. 0x01E0 052C HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehost Receiveendpoint. 0x01E0 052D HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK responsetimeouton Bulk transactionsforhostReceiveendpoint. CONTROL AND STATUS REGISTER FOR ENDPOINT 3 0x01E0 0530 TXMAXP Maximum PacketSizeforPeripheral/HostTransmitEndpoint 0x01E0 0532 PERI_TXCSR ControlStatusRegisterforPeripheralTransmitEndpoint(peripheralmode) HOST_TXCSR ControlStatusRegisterforHostTransmitEndpoint(hostmode) 0x01E0 0534 RXMAXP Maximum PacketSizeforPeripheral/HostReceiveEndpoint 0x01E0 0536 PERI_RXCSR ControlStatusRegisterforPeripheralReceiveEndpoint(peripheralmode) HOST_RXCSR ControlStatusRegisterforHostReceiveEndpoint(hostmode) 0x01E0 0538 RXCOUNT Number ofBytesinHostReceiveendpointFIFO 0x01E0 053A HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehost Transmitendpoint. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 165 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-96.UniversalSerialBus OTG (USB0) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E0 053B HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK responsetimeouton Bulk transactionsforhostTransmitendpoint. 0x01E0 053C HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehost Receiveendpoint. 0x01E0 053D HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK responsetimeouton Bulk transactionsforhostReceiveendpoint. CONTROL AND STATUS REGISTER FOR ENDPOINT 4 0x01E0 0540 TXMAXP Maximum PacketSizeforPeripheral/HostTransmitEndpoint 0x01E0 0542 PERI_TXCSR ControlStatusRegisterforPeripheralTransmitEndpoint(peripheralmode) HOST_TXCSR ControlStatusRegisterforHostTransmitEndpoint(hostmode) 0x01E0 0544 RXMAXP Maximum PacketSizeforPeripheral/HostReceiveEndpoint 0x01E0 0546 PERI_RXCSR ControlStatusRegisterforPeripheralReceiveEndpoint(peripheralmode) HOST_RXCSR ControlStatusRegisterforHostReceiveEndpoint(hostmode) 0x01E0 0548 RXCOUNT Number ofBytesinHostReceiveendpointFIFO 0x01E0 054A HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehost Transmitendpoint. 0x01E0 054B HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK responsetimeouton Bulk transactionsforhostTransmitendpoint. 0x01E0 054C HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehost Receiveendpoint. 0x01E0 054D HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK responsetimeouton Bulk transactionsforhostReceiveendpoint. DMA REGISTERS 0x01E0 1000 DMAREVID DMA RevisionRegister 0x01E0 1004 TDFDQ DMA Teardown FreeDescriptorQueue ControlRegister 0x01E0 1008 DMAEMU DMA EmulationControlRegister 0x01E0 1800 TXGCR[0] TransmitChannel0 GlobalConfigurationRegister 0x01E0 1808 RXGCR[0] ReceiveChannel0 GlobalConfigurationRegister 0x01E0 180C RXHPCRA[0] ReceiveChannel0 HostPacketConfigurationRegisterA 0x01E0 1810 RXHPCRB[0] ReceiveChannel0 HostPacketConfigurationRegisterB 0x01E0 1820 TXGCR[1] TransmitChannel1 GlobalConfigurationRegister 0x01E0 1828 RXGCR[1] ReceiveChannel1 GlobalConfigurationRegister 0x01E0 182C RXHPCRA[1] ReceiveChannel1 HostPacketConfigurationRegisterA 0x01E0 1830 RXHPCRB[1] ReceiveChannel1 HostPacketConfigurationRegisterB 0x01E0 1840 TXGCR[2] TransmitChannel2 GlobalConfigurationRegister 0x01E0 1848 RXGCR[2] ReceiveChannel2 GlobalConfigurationRegister 0x01E0 184C RXHPCRA[2] ReceiveChannel2 HostPacketConfigurationRegisterA 0x01E0 1850 RXHPCRB[2] ReceiveChannel2 HostPacketConfigurationRegisterB 0x01E0 1860 TXGCR[3] TransmitChannel3 GlobalConfigurationRegister 0x01E0 1868 RXGCR[3] ReceiveChannel3 GlobalConfigurationRegister 0x01E0 186C RXHPCRA[3] ReceiveChannel3 HostPacketConfigurationRegisterA 0x01E0 1870 RXHPCRB[3] ReceiveChannel3 HostPacketConfigurationRegisterB 0x01E0 2C00 DMA_SCHED_CTRL DMA SchedulerControlRegister 0x01E0 2D00 ENTRY[0] DMA SchedulerTableWord 0 0x01E0 2D04 ENTRY[1] DMA SchedulerTableWord 1 0x01E0 2DFC ENTRY[63] DMA SchedulerTableWord 63 QUEUE MANAGER REGISTERS 0x01E0 4000 QMGRREVID Queue Manager RevisionRegister

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-96.UniversalSerialBus OTG (USB0) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E0 4008 DIVERSION Queue DiversionRegister 0x01E0 4020 FDBSC0 FreeDescriptor/BufferStarvationCount Register0 0x01E0 4024 FDBSC1 FreeDescriptor/BufferStarvationCount Register1 0x01E0 4028 FDBSC2 FreeDescriptor/BufferStarvationCount Register2 0x01E0 402C FDBSC3 FreeDescriptor/BufferStarvationCount Register3 0x01E0 4080 LRAM0BASE LinkingRAM Region0 Base AddressRegister 0x01E0 4084 LRAM0SIZE LinkingRAM Region0 SizeRegister 0x01E0 4088 LRAM1BASE LinkingRAM Region1 Base AddressRegister 0x01E0 4090 PEND0 Queue PendingRegister0 0x01E0 4094 PEND1 Queue PendingRegister1 0x01E0 5000 QMEMRBASE[0] Memory Region0 Base AddressRegister 0x01E0 5004 QMEMRCTRL[0] Memory Region0 ControlRegister 0x01E0 5010 QMEMRBASE[1] Memory Region1 Base AddressRegister 0x01E0 5014 QMEMRCTRL[1] Memory Region1 ControlRegister 0x01E0 5070 QMEMRBASE[7] Memory Region7 Base AddressRegister 0x01E0 5074 QMEMRCTRL[7] Memory Region7 ControlRegister 0x01E0 600C CTRLD[0] Queue Manager Queue 0 ControlRegisterD 0x01E0 601C CTRLD[1] Queue Manager Queue 1 ControlRegisterD 0x01E0 63FC CTRLD[63] Queue Manager Queue 63 StatusRegisterD 0x01E0 6800 QSTATA[0] Queue Manager Queue 0 StatusRegisterA 0x01E0 6804 QSTATB[0] Queue Manager Queue 0 StatusRegisterB 0x01E0 6808 QSTATC[0] Queue Manager Queue 0 StatusRegisterC 0x01E0 6810 QSTATA[1] Queue Manager Queue 1 StatusRegisterA 0x01E0 6814 QSTATB[1] Queue Manager Queue 1 StatusRegisterB 0x01E0 6818 QSTATC[1] Queue Manager Queue 1 StatusRegisterC 0x01E0 6BF0 QSTATA[63] Queue Manager Queue 63 StatusRegisterA 0x01E0 6BF4 QSTATB[63] Queue Manager Queue 63 StatusRegisterB 0x01E0 6BF8 QSTATC[63] Queue Manager Queue 63 StatusRegisterC Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 167 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION tr tf VCRS 90% VOH 10% VOL USB0_DM USB0_DP t -□tper jr AM1707 SPRS637 –FEBRUARY 2010 www.ti.com 6.27.1 USB2.0 (USB0) ElectricalData/Timing Table6-97.SwitchingCharacteristicsOver Recommended OperatingConditionsforUSB2.0 [USB0] (see Figure6-66) LOW SPEED FULL SPEED HIGH SPEED 1.5Mbps 12 Mbps 480 MbpsNo. PARAMETER UNIT MIN MAX MIN MAX MIN MAX 1 tr(D) Risetime,USB0_DP and USB0_DM signals(1) 75 300 4 20 0.5 ns 2 tf(D) Falltime,USB0_DP and USB0_DM signals(1) 75 300 4 20 0.5 ns 3 trfM Rise/Falltime,matching(2) 80 120 90 111 – – % 4 VCRS Outputsignalcross-overvoltage(1) 1.3 2 1.3 2 – – V 5 tjr(source)NT Source(Host)Driverjitter,nexttransition 2 2 (3)ns tjr(FUNC)NT FunctionDriverjitter,nexttransition 25 2 (3) ns 6 tjr(source)PT Source(Host)Driverjitter,pairedtransition(4) 1 1 (3) ns tjr(FUNC)PT FunctionDriverjitter,pairedtransition 10 1 (3) ns 7 tw(EOPT) Pulseduration,EOP transmitter(5) 1250 1500 160 175 – – ns 8 tw(EOPR) Pulseduration,EOP receiver(5) 670 82 – ns 9 t(DRATE) Data Rate 1.5 12 480 Mb/s 10 ZDRV DriverOutputResistance – – 40.5 49.5 40.5 49.5 Ω

11 ZINP ReceiverInputImpedance 100k 100k - - Ω

(1) Low Speed:C L = 200 pF,FullSpeed:C L = 50 pF,HighSpeed:C L = 50 pF (2) tRFM = (tr/tf)x 100.[ExcludingthefirsttransactionfromtheIdlestate.] (3) Formore detailedinformation,see theUniversalSerialBus SpecificationRevision2.0,Chapter7.Electrical. (4) tjr= tpx(1)-tpx(0) (5) Must acceptas validEOP Figure6-66.USB0 IntegratedTransceiverInterfaceTiming

6.27.2 USB0 Unused SignalConfiguration

IfUSB0 isunused,thentheUSB0 signalsshouldbe configuredas shown belowin.

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010

6.28 Host-PortInterface(UHPI)

6.28.1 HPI Device-SpecificInformation

The deviceincludesa user-configurable16-bitHost-portinterface(HPI16).

6.28.2 HPI PeripheralRegisterDescription(s)

Table6-98.HPI ControlRegisters BYTE ACRONYM REGISTER DESCRIPTION COMMENTSADDRESS 0x01E1 0000 PID PeripheralIdentificationRegister HPI power and emulationmanagement The CPU has read/writeaccesstothe0x01E1 0004 PWREMU_MGMT register PWREMU_MGMT register. 0x01E1 0008 - Reserved 0x01E1 000C GPIO_EN GeneralPurposeIO EnableRegister 0x01E1 0010 GPIO_DIR1 GeneralPurposeIO DirectionRegister1 0x01E1 0014 GPIO_DAT1 GeneralPurposeIO Data Register1 0x01E1 0018 GPIO_DIR2 GeneralPurposeIO DirectionRegister2 0x01E1 001C GPIO_DAT2 GeneralPurposeIO Data Register2 0x01E1 0020 GPIO_DIR3 GeneralPurposeIO DirectionRegister3 0x01E1 0024 GPIO_DAT3 GeneralPurposeIO Data Register3 0x01E1 0028 - Reserved 0x01E1 002C - Reserved The Hostand theCPU bothhave read/writeaccess0x01E1 0030 HPIC HPI controlregister totheHPIC register. HPIA HPI addressregister0x01E1 0034 The Hosthas read/writeaccesstotheHPIA(HPIAW) (1) (Write) registers.The CPU has onlyreadaccesstothe HPIA HPI addressregister HPIA registers.0x01E1 0038 (HPIAR)(1) (Read) 0x01E1 000C- - Reserved0x01E1 07FF (1) Therearetwo 32-bitHPIA registers:HPIAR forreadoperationsand HPIAW forwriteoperations.The HPI can be configuredsuch that HPIAR and HPIAW actas a single32-bitHPIA (single-HPIAmode) oras two separate32-bitHPIAs (dual-HPIAmode) fromthe perspectiveoftheHost.The CPU can accessHPIAW and HPIAR independently. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 169 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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6.28.3 HPI ElectricalData/Timing

Table6-99.Timing Requirements forHost-PortInterfaceCycles(1)(2) No. PARAMETER MIN MAX UNIT 1 tsu(SELV-HSTBL) Setuptime,selectsignals(3)validbeforeUHPI_HSTROBE low 5 ns 2 th(HSTBL-SELV) Holdtime,selectsignals(3)validafterUHPI_HSTROBE low 2 ns 3 tw(HSTBL) Pulseduration,UHPI_HSTROBE activelow 15 ns 4 tw(HSTBH) Pulseduration,UHPI_HSTROBE inactivehighbetween consecutiveaccesses 2M ns 9 tsu(SELV-HASL) Setuptime,selectssignalsvalidbeforeUHPI_HAS low 5 ns 10 th(HASL-SELV) Holdtime,selectsignalsvalidafterUHPI_HAS low 2 ns 11 tsu(HDV-HSTBH) Setuptime,hostdatavalidbeforeUHPI_HSTROBE high 5 ns 12 th(HSTBH-HDV) Holdtime,hostdatavalidafterUHPI_HSTROBE high 2 ns Holdtime,UHPI_HSTROBE highafterUHPI_HRDY low.UHPI_HSTROBE 13 th(HRDYL-HSTBH) shouldnotbe inactivateduntilUHPI_HRDY isactive(low);otherwise,HPI 2 ns writeswillnotcompleteproperly. 16 tsu(HASL-HSTBL) Setuptime,UHPI_HAS lowbeforeUHPI_HSTROBE low 2 ns 17 th(HSTBL-HASH) Holdtime,UHPI_HAS lowafterUHPI_HSTROBE low 2 ns (1) UHPI_HSTROBE referstothefollowinglogicaloperationon UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS. (2) M=SYSCLK2 period(CPU clockfrequency)/2inns. (3) Selectsignalsinclude:HCNTL[1:0],HR/W and HHWIL.

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-100.SwitchingCharacteristicsforHost-PortInterfaceCycles(1)(2)(3) No. PARAMETER MIN MAX UNIT ForHPI Write,HRDY can go high(not ready)fortheseHPI Writeconditions; otherwise,HRDY stayslow(ready): Case 1:Back-to-backHPIA writes(canbe eitherfirstorsecond half-word) Case 2:HPIA writefollowinga PREFETCH command (canbe eitherfirstorsecond half-word) Case 3:HPID writewhen FIFO isfullor flushing(canbe eitherfirstorsecond half-word) Case 4:HPIA writeand WriteFIFO not empty ForHPI Read, HRDY can go high(notDelaytime,HSTROBE lowto ready)fortheseHPI Read conditions:5 td(HSTBL-HRDYV) 10 nsHRDY valid Case 1:HPID read(withauto-increment) and datanotinRead FIFO (canonly happen tofirsthalf-wordofHPID access) Case 2:Firsthalf-wordaccessofHPID Read withoutauto-increment ForHPI Read, HRDY stayslow(ready)for theseHPI Read conditions: Case 1:HPID readwithauto-incrementand dataisalreadyinRead FIFO (appliesto eitherhalf-wordofHPID access) Case 2:HPID readwithoutauto-increment and dataisalreadyinRead FIFO (always appliestosecond half-wordofHPID access) Case 3:HPIC orHPIA read(appliesto eitherhalf-wordaccess) 5a td(HASL-HRDYV) Delaytime,HAS lowtoHRDY valid 10 ns 6 ten(HSTBL-HDLZ) Enabletime,HD drivenfromHSTROBE low 2 ns 7 td(HRDYL-HDV) Delaytime,HRDY lowtoHD valid 0 ns 8 toh(HSTBH-HDV) Outputholdtime,HD validafterHSTROBE high 1.5 ns 14 tdis(HSTBH-HDHZ) Disabletime,HD high-impedancefromHSTROBE high 10 ns ForHPI Read. Appliestoconditionswhere dataisalreadyresidinginHPID/FIFO: Case 1:HPIC orHPIA read Delaytime,HSTROBE lowtoHD Case 2:Firsthalf-wordofHPID readwith15 td(HSTBL-HDV) 15 nsvalid auto-incrementand dataisalreadyinRead FIFO Case 3:Second half-wordofHPID readwith orwithoutauto-increment ForHPI Write,HRDY can go high(not ready)fortheseHPI Writeconditions; otherwise,HRDY stayslow(ready): Case 1:HPID writewhen WriteFIFO isfullDelaytime,HSTROBE highto18 td(HSTBH-HRDYV) (canhappen toeitherhalf-word) 12 nsHRDY valid Case 2:HPIA write(canhappen toeither half-word) Case 3:HPID writewithoutauto-increment (onlyhappens tosecond half-word) (1) M=SYSCLK2 period(CPU clockfrequency)/2inns. (2) HSTROBE referstothefollowinglogicaloperationon HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. (3) By design,whenever HCS isdriveninactive(high),HPI willdriveHRDY active(low). Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 171 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION UHPI_HCS UHPI_HAS (D) UHPI_HCNTL[1:0] UHPI_HR/W UHPI_HHWIL UHPI_HSTROBE (A)(C) UHPI_HD[15:0] (output) UHPI_HRDY (B) 1st Half-Word 2nd Half-Word A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(HDS1 XOR HDS2)] OR UHPI_HCS. B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur. C. UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2 . UHPI_HCS timing requirements are reflected by parameters for UHPI_HSTROBE. D The diagram above assumes UHPI_HAS has been pulled high. AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Figure6-67.UHPI Read Timing (HAS Not Used, TiedHigh)

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ADVANCE□INFORMATION UHPI_HAS (A) UHPI_HCNTL[1:0] UHPI_HR/W UHPI_HHWIL UHPI_HSTROBE (B) UHPI_HCS UHPI_HD[15:0] (output) UHPI_HRDY 1st half-word 2nd half-word75a 815 10910 9 17 17 1616 AM1707 www.ti.com SPRS637 –FEBRUARY 2010 A. Forcorrectoperation,strobetheUHPI_HAS signalonlyonce perUHPI_HSTROBE activecycle. B. UHPI_HSTROBE refersto the followinglogicaloperationon UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS. Figure6-68.UHPI Read Timing (HAS Used) Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 173 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION UHPI_HAS (D) UHPI_HCNTL[1:0] UHPI_HR/W UHPI_HHWIL UHPI_HSTROBE (A)(C) UHPI_HCS UHPI_HD[15:0] (input) UHPI_HRDY (B) 2 1 21 1 2 1 2 3 4 3 11 12 1813 185 11 12 2nd Half-Word1st Half-Word A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(HDS1 XOR HDS2 )] OR UHPI_HCS . B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur. C. UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2. UHPI_HCS timing requirements are reflected by parameters for UHPI_HSTROBE. D The diagram above assumes UHPI_HAS has been pulled high. AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Figure6-69.UHPI WriteTiming (HAS Not Used, TiedHigh)

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ADVANCE□INFORMATION 1st half-word 2nd half-word 12111211 UHPI_HAS (A) UHPI_HCNTL[1:0] UHPI_HR/W UHPI_HHWIL UHPI_HSTROBE (B) UHPI_HCS UHPI_HD[15:0] (input) UHPI_HRDY 1717 16 16 AM1707 www.ti.com SPRS637 –FEBRUARY 2010 A. Forcorrectoperation,strobetheUHPI_HAS signalonlyonce perUHPI_HSTROBE activecycle. B. UHPI_HSTROBE refersto the followinglogicaloperationon UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS. Figure6-70.UHPI WriteTiming (HAS Used) Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 175 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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6.29 Power and Sleep Controller(PSC)

The Power and SleepControllers(PSC) areresponsibleformanaging transitionsofsystem power on/off, clockon/off,resets(deviceleveland module level).Itisused primarilytoprovidegranularpower control foron chipmodules (peripheralsand CPU). A PSC module consistsofa GlobalPSC (GPSC) and a setof LocalPSCs (LPSCs).The GPSC containsmemory mapped registers,PSC interrupts,a statemachine for each peripheral/moduleitcontrols.An LPSC isassociatedwitheverymodule thatiscontrolledby thePSC and providesclockand resetcontrol. The PSC includesthefollowingfeatures:

Providesa softwareinterfaceto: – Controlmodule clockenable/disable – Controlmodule reset – ControlCPU localreset
SupportsICEpickTAP Routerpower,clockand resetfeatures.Fordetailson ICEpickfeaturessee http://tiexpressdsp.com/wiki/index.php?title=ICEPICK. Table6-101.Power and Sleep Controller(PSC) Registers PSC0 PSC1 ACRONYM DESCRIPTION BYTE ADDRESS BYTE ADDRESS 0x01C1 0000 0x01E2 7000 REVID PeripheralRevisionand ClassInformationRegister 0x01C1 0018 0x01E2 7018 INTEVAL InterruptEvaluationRegister 0x01C1 0040 0x01E2 7040 MERRPR0 Module ErrorPendingRegister0 (module0-15) (PSC0) Module ErrorPendingRegister0 (module0-31) (PSC1) 0x01C1 0050 0x01E2 7050 MERRCR0 Module ErrorClearRegister0 (module0-15)(PSC0) Module ErrorClearRegister0 (module0-31)(PSC1) 0x01C1 0060 0x01E2 7060 PERRPR Power ErrorPendingRegister 0x01C1 0068 0x01E2 7068 PERRCR Power ErrorClearRegister 0x01C1 0120 0x01E2 7120 PTCMD Power Domain TransitionCommand Register 0x01C1 0128 0x01E2 7128 PTSTAT Power Domain TransitionStatusRegister 0x01C1 0200 0x01E2 7200 PDSTAT0 Power Domain 0 StatusRegister 0x01C1 0204 0x01E2 7204 PDSTAT1 Power Domain 1 StatusRegister 0x01C1 0300 0x01E2 7300 PDCTL0 Power Domain 0 ControlRegister 0x01C1 0304 0x01E2 7304 PDCTL1 Power Domain 1 ControlRegister 0x01C1 0400 0x01E2 7400 PDCFG0 Power Domain 0 ConfigurationRegister 0x01C1 0404 0x01E2 7404 PDCFG1 Power Domain 1 ConfigurationRegister 0x01C1 0800- 0x01E2 7800- MDSTAT0-MDSTAT15 Module Statusn Register(modules0-15)(PSC0) 0x01C1 083C 0x01E2 787C MDSTAT0-MDSTAT31 Module Statusn Register(modules0-31)(PSC1) 0x01C1 0A00- 0x01E2 7A00- MDCTL0-MDCTL15 Module Controln Register(modules0-15)(PSC0) 0x01C1 0A3C 0x01E2 7A7C MDCTL0-MDCTL31 Module Controln Register(modules0-31)(PSC1)

6.29.1 Power Domain and Module Topology

The deviceincludestwo PSC modules. Each PSC module controlsclockstatesforseveraloftheon chipmodules,controllersand interconnect components.Table6-102 and Table6-103 liststhesetofperipherals/modulesthatare controlledby the PSC, thepower domain theyareassociatedwith,theLPSC assignmentand thedefault(power-onreset) module states.See thedevice-specificdatamanual fortheperipheralsavailableon a givendevice.The module statesand terminologyaredefinedinSection6.29.1.1.

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-102.PSC0 DefaultModule Configuration LPSC Number Module Name Power Domain DefaultModule State Auto Sleep/Wake Only

0 EDMA3 ChannelController AlwaysON (PD0) SwRstDisable —

1 EDMA3 TransferController0 AlwaysON (PD0) SwRstDisable —

2 EDMA3 TransferController1 AlwaysON (PD0) SwRstDisable —

3 EMIFA (BR7) AlwaysON (PD0) SwRstDisable —

4 SPI 0 AlwaysON (PD0) SwRstDisable —

5 MMC/SD 0 AlwaysON (PD0) SwRstDisable —

6 ARM InterruptController AlwaysON (PD0) SwRstDisable —

7 ARM RAM/ROM AlwaysON (PD0) Enable Yes

9 UART 0 AlwaysON (PD0) SwRstDisable —

10 SCR0 (Br0,Br 1,Br 2,Br 8) AlwaysON (PD0) Enable Yes

11 SCR1 (Br4) AlwaysON (PD0) Enable Yes

12 SCR2 (Br3,Br 5,Br 6) AlwaysON (PD0) Enable Yes

13 PRUSS AlwaysON (PD0) SwRstDisable —

14 ARM AlwaysON (PD0) SwRstDisable —

15 - - - — Table6-103.PSC1 DefaultModule Configuration LPSC Number Module Name Power Domain DefaultModule State Auto Sleep/Wake Only

0 Not Used — — —

1 USB0 (USB2.0) AlwaysON (PD0) SwRstDisable — 2 USB1 (USB1.1) AlwaysON (PD0) SwRstDisable —

3 GPIO AlwaysON (PD0) SwRstDisable —

4 UHPI AlwaysON (PD0) SwRstDisable —

5 EMAC AlwaysON (PD0) SwRstDisable —

6 EMIFB (Br20) AlwaysON (PD0) SwRstDisable —

7 McASP0 (+ McASP0 FIFO) AlwaysON (PD0) SwRstDisable —

8 McASP1 (+ McASP1 FIFO) AlwaysON (PD0) SwRstDisable —

9 McASP2( + McASP2 FIFO) AlwaysON (PD0) SwRstDisable —

10 SPI 1 AlwaysON (PD0) SwRstDisable —

11 I2C 1 AlwaysON (PD0) SwRstDisable —

12 UART 1 AlwaysON (PD0) SwRstDisable —

13 UART 2 AlwaysON (PD0) SwRstDisable —

14-15 Not Used — — —

16 LCDC AlwaysON (PD0) SwRstDisable —

17 eHRPWM0/1/2 AlwaysON (PD0) SwRstDisable — 18-19 Not Used — — —

20 ECAP0/1/2 AlwaysON (PD0) SwRstDisable —

21 EQEP0/1 AlwaysON (PD0) SwRstDisable —

22-23 Not Used — — —

24 SCR8 (Br15) AlwaysON (PD0) Enable Yes

25 SCR7 (Br12) AlwaysON (PD0) Enable Yes

26 SCR12 (Br18) AlwaysON (PD0) Enable Yes

27-30 Not Used — — —

31 On-chipRAM (Br13) PD_SHRAM Enable Yes

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com 6.29.1.1Module States The PSC definesseveralpossiblestatesfora module.Thisstatesare essentiallya combinationofthe module resetassertedorde-assertedand module clockon/enabledoroff/disabled.The module statesare definedinTable6-104. Table6-104.Module States Module State Module Reset Module Clock Module StateDefinition Enable De-asserted On A module intheenablestatehas itsmodule resetde-assertedand ithas its clockon.Thisisthenormaloperationalstatefora givenmodule Disable De-asserted Off A module inthedisabledstatehas itsmodule resetde-assertedand ithas its module clockoff.Thisstateistypicallyused fordisablinga module clockto save power.The deviceisdesignedinfullstaticCMOS, so when you stopa module clock,itretainsthemodule’s state.When theclockisrestarted,the module resumes operatingfromthestoppingpoint. SyncReset Asserted On A module stateintheSyncResetstatehas itsmodule resetassertedand ithas itsclockon.Generally,softwareisnotexpectedtoinitiatethisstate SwRstDisable Asserted Off A module intheSwResetDisablestatehas itsmodule resetassertedand ithas itsclockdisabled.Afterinitialpower-on,severalmodules come up inthe SwRstDisablestate.Generally,softwareisnotexpectedtoinitiatethisstate AutoSleep De-asserted Off A module intheAutoSleepstatealsohas itsmodule resetde-assertedand its module clockdisabled,similartotheDisablestate.However thisisa special state,once a module isconfiguredinthisstateby software,itcan “automatically”transitionto“Enable”statewhenever thereisan internal read/writerequestmade toit,and afterservicingtherequestitwill “automatically”transitionintothesleepstate(withmodule resetrede-asserted and module clockdisabled),withoutany softwareintervention.The transition fromsleeptoenabledand back tosleepstatehas some cyclelatency associatedwithit.Itisnotenvisionedtouse thismode when peripheralsare fullyoperationaland moving data. AutoWake De-asserted Off A module intheAutoWake statealsohas itsmodule resetde-assertedand its module clockdisabled,similartotheDisablestate.However thisisa special state,once a module isconfiguredinthisstateby software,itwill “automatically”transitionto“Enable”statewhenever thereisan internal read/writerequestmade toit,and willremaininthe“Enabled”statefromthen on (withmodule resetrede-assertedand module clockon),withoutany softwareintervention.The transitionfromsleeptoenabledstatehas some cyclelatencyassociatedwithit.Itisnotenvisionedtouse thismode when peripheralsarefullyoperationaland moving data.

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010

6.30 Programmable Real-TimeUnitSubsystem (PRUSS)

The Programmable Real-TimeUnitSubsystem (PRUSS) consistsof

Two Programmable Real-TimeUnits(PRU0 and PRU1) and theirassociatedmemories
An InterruptController(INTC)forhandlingsystem interruptevents.The INTC alsosupportsposting eventsback tothedevicelevelhostCPU.
A SwitchedCentralResource (SCR) forconnectingthe variousinternaland externalmastersto the resourcesinsidethePRUSS. The two PRUs can operatecompletelyindependentlyor incoordinationwitheach other.The PRUs can alsowork incoordinationwiththedevicelevelhostCPU. Thisisdeterminedby thenatureoftheprogram which isloadedintothePRUs instructionmemory. Severaldifferentsignalingmechanisms are available between thetwo PRUs and thedevicelevelhostCPU. The PRUs are optimizedforperformingembedded tasksthatrequiremanipulationof packed memory mapped datastructures,handlingofsystemeventsthathave tightrealtimeconstraintsand interfacingwith systemsexternaltothedevice. The PRUSS comprisesvariousdistinctaddressableregions.Externallythesubsystem presentsa single 64Kbyterangeofaddresses.The internalinterconnectbus (alsocalledswitchedcentralresource,orSCR) of the PRUSS decodes accesses foreach of the individualregions.The PRUSS memory map is documented in Table 6-105 and in Table 6-106. Note thatthese two memory maps are implemented insidethePRUSS and arelocaltothecomponents ofthePRUSS. Table6-105.Programmable Real-TimeUnitSubsystem (PRUSS) LocalInstructionSpace Memory Map BYTE ADDRESS PRU0 PRU1 0x0000 0000 -0x0000 0FFF PRU0 InstructionRAM PRU1 InstructionRAM Table6-106.Programmable Real-TimeUnitSubsystem (PRUSS) LocalData Space Memory Map BYTE ADDRESS PRU0 PRU1 0x0000 0000 -0x0000 01FF Data RAM 0 (1) Data RAM 1 (1) 0x0000 0200 -0x0000 1FFF Reserved Reserved 0x0000 2000 -0x0000 21FF Data RAM 1 (1) Data RAM 0 (1) 0x0000 2200 -0x0000 3FFF Reserved Reserved 0x0000 4000 -0x0000 6FFF INTC Registers INTC Registers 0x0000 7000 -0x0000 73FF PRU0 ControlRegisters PRU0 ControlRegisters 0x0000 7400 -0x0000 77FF Reserved Reserved 0x0000 7800 -0x0000 7BFF PRU1 ControlRegisters PRU1 ControlRegisters 0x0000 7C00 -0xFFFF FFFF Reserved Reserved (1) Note thatPRU0 accessesData RAM 0 ataddress0x0000 0000,alsoPRU1 accessesData RAM 1 ataddress0x0000 0000.Data RAM0 isintendedtobe theprimarydatamemory forPRU0 and Data RAM1 isintendedtobe theprimarydatamemory forPRU1. However for passinginformationbetween PRUs, each PRU can accessthedataram ofthe‘other’PRU throughaddress0x0000 2000. The globalview ofthePRUSS internalmemories and controlportsisdocumented inTable6-107.The offsetaddresses of each regionare implemented insidethe PRUSS but the globaldevicememory mapping placesthePRUSS slaveportintheaddressrange0x01C3 0000-0x01C3 FFFF. The PRU0 and PRU1 can use eitherthelocalor globaladdressestoaccess theirinternalmemories,butusingthelocal addresseswillprovideaccesstimeseveralcyclesfasterthanusingtheglobaladdresses.Thisisbecause when accessingviatheglobaladdresstheaccess needs tobe routedthroughtheswitchfabricoutside PRUSS and back inthroughthePRUSS slaveport. Table6-107.Programmable Real-TimeUnitSubsystem (PRUSS) GlobalMemory Map BYTE ADDRESS REGION 0x01C3 0000 -0x01C3 01FF Data RAM 0 Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 179 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com Table6-107.Programmable Real-TimeUnitSubsystem (PRUSS) GlobalMemory Map (continued) BYTE ADDRESS REGION 0x01C3 0200 -0x01C3 1FFF Reserved 0x01C3 2000 -0x01C3 21FF Data RAM 1 0x01C3 2200 -0x01C3 3FFF Reserved 0x01C3 4000 -0x01C3 6FFF INTC Registers 0x01C3 7000 -0x01C3 73FF PRU0 ControlRegisters 0x01C3 7400 -0x01C3 77FF PRU0 Debug Registers 0x01C3 7800 -0x01C3 7BFF PRU1 ControlRegisters 0x01C3 7C00 -0x01C3 7FFF PRU1 Debug Registers 0x01C3 8000 -0x01C3 8FFF PRU0 InstructionRAM 0x01C3 9000 -0x01C3 BFFF Reserved 0x01C3 C000 -0x01C3 CFFF PRU1 InstructionRAM 0x01C3 D000 -0x01C3 FFFF Reserved Each ofthePRUs can access therestofthedevicememory (includingmemory mapped peripheraland configurationregisters)usingtheglobalmemory space addresses

6.30.1 PRUSS RegisterDescriptions

Table6-108.Programmable Real-TimeUnitSubsystem (PRUSS) Control/StatusRegisters PRU0 BYTE ADDRESS PRU1 BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01C3 7000 0x01C3 7800 CONTROL PRU ControlRegister 0x01C3 7004 0x01C3 7804 STATUS PRU StatusRegister 0x01C3 7008 0x01C3 7808 WAKEUP PRU Wakeup EnableRegister 0x01C3 700C 0x01C3 780C CYCLCNT PRU CycleCount 0x01C3 7010 0x01C3 7810 STALLCNT PRU StallCount PRU ConstantTableBlockIndex0x01C3 7020 0x01C3 7820 CONTABBLKIDX0 Register0 PRU ConstantTableProgrammable0x01C3 7028 0x01C3 7828 CONTABPROPTR0 PointerRegister0 PRU ConstantTableProgrammable0x01C3 702C 0x01C3 782C CONTABPROPTR1 PointerRegister1 PRU InternalGeneralPurpose0x01C37400 -0x01C3747C 0x01C3 7C00 -0x01C3 7C7C INTGPR0 – INTGPR31 Registers(forDebug) PRU InternalConstantsTable0x01C37480 -0x01C374FC 0x01C3 7C80 -0x01C3 7CFC INTCTER0 – INTCTER31 Registers(forDebug) Table6-109.Programmable Real-TimeUnitSubsystem InterruptController(PRUSS INTC) Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01C3 4000 REVID RevisionID Register 0x01C3 4004 CONTROL ControlRegister 0x01C3 4010 GLBLEN GlobalEnableRegister 0x01C3 401C GLBLNSTLVL GlobalNestingLevelRegister 0x01C3 4020 STATIDXSET System InterruptStatusIndexedSetRegister 0x01C3 4024 STATIDXCLR System InterruptStatusIndexedClearRegister 0x01C3 4028 ENIDXSET System InterruptEnableIndexedSetRegister 0x01C3 402C ENIDXCLR System InterruptEnableIndexedClearRegister 0x01C3 4034 HSTINTENIDXSET HostInterruptEnableIndexedSetRegister 0x01C3 4038 HSTINTENIDXCLR HostInterruptEnableIndexedClearRegister 0x01C3 4080 GLBLPRIIDX GlobalPrioritizedIndexRegister

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-109.Programmable Real-TimeUnitSubsystem InterruptController(PRUSS INTC) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01C3 4200 STATSETINT0 System InterruptStatusRaw/Set Register0 0x01C3 4204 STATSETINT1 System InterruptStatusRaw/Set Register1 0x01C3 4280 STATCLRINT0 System InterruptStatusEnabled/ClearRegister0 0x01C3 4284 STATCLRINT1 System InterruptStatusEnabled/ClearRegister1 0x01C3 4300 ENABLESET0 System InterruptEnableSetRegister0 0x01C3 4304 ENABLESET1 System InterruptEnableSetRegister1 0x01C3 4380 ENABLECLR0 System InterruptEnableClearRegister0 0x01C3 4384 ENABLECLR1 System InterruptEnableClearRegister1 0x01C3 4400 -0x01C3 4440 CHANMAP0 -CHANMAP15 ChannelMap Registers0-15 0x01C3 4800 -0x01C3 4808 HOSTMAP0 -HOSTMAP2 HostMap Register0-2 HOSTINTPRIIDX0 -0x01C3 4900 -0x01C3 4928 HostInterruptPrioritizedIndexRegisters0-9HOSTINTPRIIDX9 0x01C3 4D00 POLARITY0 System InterruptPolarityRegister0 0x01C3 4D04 POLARITY1 System InterruptPolarityRegister1 0x01C3 4D80 TYPE0 System InterruptType Register0 0x01C3 4D84 TYPE1 System InterruptType Register1 HOSTINTNSTLVL0-0x01C3 5100 -0x01C3 5128 HostInterruptNestingLevelRegisters0-9HOSTINTNSTLVL9 0x01C3 5500 HOSTINTEN HostInterruptEnableRegister Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 181 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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6.31 EmulationLogic

Thissectiondescribesthestepstouse a thirdpartydebugger.The debug capabilitiesand featuresfor ARM areas shown below. ForTI’s latestdebug and emulationinformationsee : http://tiexpressdsp.com/wiki/index.php?title=Category:Emulation ARM:

BasicDebug – ExecutionControl – System Visibility
Advanced Debug – GlobalStart – GlobalStop
Advanced System Control – Subsystem resetviadebug – Peripheralnotificationofdebug events – Cache-coherentdebug accesses
Program Trace – Program flowcorruption – Code coverage – Pathcoverage – Thread/interruptsynchronizationproblems
Data Trace – Memory corruption
TimingTrace – Profiling
AnalysisActions – Stopprogramexecution – Controltracestreams – Generatedebug interrupt – Benchmarkingwithcounters – Externaltriggergeneration – Debug statemachine statetransition – Combinationaland Sequentialeventgeneration
AnalysisEvents – Program eventdetection – Data eventdetection – ExternaltriggerDetection – System eventdetection(i.e.cache miss) – Debug statemachine statedetection
AnalysisConfiguration – Applicationaccess – Debugger access

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-110.ARM Debug Features Category Hardware Feature Availability Softwarebreakpoint Unlimited Up to14 HWBPs, including: 2 precise(1)HWBP insideARM corewhichareshared withwatchpoints.BasicDebug Hardware breakpoint 8 imprecise(1)HWBPs fromETM ’s addresscomparators, whicharesharedwithtracefunction,and can be used as watchpointtoo. 4 imprecise(1)HWBPs fromICECrusher. Up to6 watchpoints,including: 2 fromARM corewhichissharedwithHWBPs and can Watch point be associatedwitha data. 8 fromETM ’s addresscomparators,whichareshared withtracefunction,and HWBPs. 2 fromARM corewhichissharedwithHWBPs.Analysis Watch pointwithData 8 watchpointsfromETM can be associatedwitha data comparator,and ETM has total4 datacomparators. Counters/timers 3x32-bit(1cycle;2 event) ExternalEventTriggerIn 1 ExternalEventTriggerOut 1 Addressrangefortrace 4 Data qualificationfortrace 2 System eventsfortracecontrol 20 TraceControl Counters/Timersfortracecontrol 2x16-bit StateMachines/Sequencers 1x3-StateStateMachine Context/ThreadID Comparator 1 Independenttriggercontrolunits 12 CapturedepthPC 4k bytesETB On-chipTrace CapturedepthPC + Timing 4k bytesETBCapture Applicationaccessible Y (1) Precisehardwarebreakpointswillhalttheprocessorimmediatelypriortotheexecutionoftheselectedinstruction.Imprecisebreakpoints willhalttheprocessorsome number ofcyclesaftertheselectedinstructiondependingon deviceconditions. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 183 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

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6.31.1 JTAG PortDescription

The devicetargetdebug interfaceuses thefivestandardIEEE 1149.1(JTAG)signals(TRST, TCK, TMS, TDI,and TDO) ,a returnclock(RTCK) due totheclockingrequirementsoftheARM926EJ-S and EMU0 . TRST holdsthedebug and boundaryscan logicinresetwhen pulledlow (itsdefaultstate).SinceTRST has an internalpull-downresistor,thisensures thatat power up the devicefunctionsin itsnormal (non-test)operationmode ifTRST isnot connected.Otherwise,TRST shouldbe driveninactiveby the emulatoror boundary scan controller.Boundary scan testcannotbe performedwhilethe TRST pinis pulledlow. Table6-111.JTAG PortDescription PIN TYPE NAME DESCRIPTION When asserted(activelow)causesalltestand debug logicinthedevicetobe resetalongTRST I TestLogicReset withtheIEEE 1149.1interface Thisisthetestclockused todrivean IEEE 1149.1TAP statemachine and logic. TCK I TestClock Dependingon theemulatorattachedto,thisisa freerunningclockora gatedclock dependingon RTCK monitoring. SynchronizedTCK. Dependingon theemulatorattachedto,theJTAG signalsareclockedRTCK O ReturnedTestClock fromRTCK orRTCK ismonitoredby theemulatortogateTCK. TMS I TestMode Select DirectsthenextstateoftheIEEE 1149.1testaccessportstatemachine TDI I TestData Input Scan datainputtothedevice TDO O TestData Output Scan dataoutputofthedevice EMU0 I/O Emulation0 Channel0 trigger+ HSRTDX

6.31.2 Scan Chain ConfigurationParameters

Table6-112shows theTAP configurationdetailsrequiredtoconfiguretherouter/emulatorforthisdevice. Table6-112.JTAG PortDescription Router PortID DefaultTAP TAP Name Tap IR Length

17 No Reserved 38

18 No ARM926 4

19 No ETB 4

The routerisICEpickrevisionC and has a 6-bitIR length.

6.31.3 InitialScan Chain Configuration

The firstlevelofdebug interfacethatsees thescan controlleristheTAP routermodule.The debugger can configuretheTAP routerforseriallylinkingup to16 TAP controllersor individuallyscanningone of theTAP controllerswithoutdisruptingtheIR stateoftheotherTAPs. 6.31.3.1Adding TAPS totheScan Chain The TAP routermust be programmed toadd additionalTAPs tothescan chain.The followingJTAG scans must be completedtoadd theARM926EJ-S tothescan chain. A Power-On Reset (POR) or theJTAG Test-LogicReset stateconfigurestheTAP routertocontainonly therouter’s TAP.

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ADVANCE□INFORMATION TDO Router TDI StepsCLK TMS Router ARM926EJ-S/ETM AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Figure6-71.Adding ARM926EJ-S tothescan chain Pre-amble:The devicewhose datareachestheemulatorfirstislistedfirstintheboardconfigurationfile. Thisdeviceisa pre-ambleforalltheotherdevices.Thisdevicehas thelowestdeviceID. Post-amble:The devicewhose datareachestheemulatorlastislistedlastintheboardconfigurationfile. Thisdeviceisa post-ambleforalltheotherdevices.Thisdevicehas thehighestdeviceID.

Function:Update theJTAG preambleand post-amblecounts. – Parameter:The IR pre-amblecountis'0'. – Parameter:The IR post-amblecountis'0'. – Parameter:The DR pre-amblecountis'0'. – Parameter:The DR post-amblecountis'0'. – Parameter:The IR main countis'6'. – Parameter:The DR main countis'1'.
Function:Do a send-onlyJTAG IR/DR scan. – Parameter:The routetoJTAG shiftstateis'shortesttransition'. – Parameter:The JTAG shiftstateis'shift-ir'. – Parameter:The JTAG destinationstateis'pause-ir'. – Parameter:The bitlengthofthecommand is'6'. – Parameter:The send datavalueis'0x00000007'. – Parameter:The actualreceivedatais'discarded'.
Function:Do a send-onlyJTAG IR/DR scan. – Parameter:The routetoJTAG shiftstateis'shortesttransition'. – Parameter:The JTAG shiftstateis'shift-dr'. – Parameter:The JTAG destinationstateis'pause-dr'. – Parameter:The bitlengthofthecommand is'8'. – Parameter:The send datavalueis'0x00000089'. – Parameter:The actualreceivedatais'discarded'.
Function:Do a send-onlyJTAG IR/DR scan. – Parameter:The routetoJTAG shiftstateis'shortesttransition'. – Parameter:The JTAG shiftstateis'shift-ir'. – Parameter:The JTAG destinationstateis'pause-ir'. – Parameter:The bitlengthofthecommand is'6'. – Parameter:The send datavalueis'0x00000002'. – Parameter:The actualreceivedatais'discarded'.
Function:Embed theportaddressinnextcommand. – Parameter:The portaddressfieldis'0x0f000000'. – Parameter:The portaddressvalueis'3'. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 185 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION TDI Router ARM926EJ-S/ETM TDO StepsCLK TMS Router ARM926EJ-S/ETM ETB AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

Function:Do a send-onlyJTAG IR/DR scan. – Parameter:The routetoJTAG shiftstateis'shortesttransition'. – Parameter:The JTAG shiftstateis'shift-dr'. – Parameter:The JTAG destinationstateis'pause-dr'. – Parameter:The bitlengthofthecommand is'32'. – Parameter:The send datavalueis'0xa2002108'. – Parameter:The actualreceivedatais'discarded'.
Function:Do a send-onlyall-onesJTAG IR/DR scan. – Parameter:The JTAG shiftstateis'shift-ir'. – Parameter:The JTAG destinationstateis'run-test/idle'. – Parameter:The bitlengthofthecommand is'6'. – Parameter:The send datavalueis'all-ones'. – Parameter:The actualreceivedatais'discarded'.
Function:Waitfora minimum number ofTCLK pulses. – Parameter:The countofTCLK pulsesis'10'.
Function:Update theJTAG preambleand post-amblecounts. – Parameter:The IR pre-amblecountis'0'. – Parameter:The IR post-amblecountis'6'. – Parameter:The DR pre-amblecountis'0'. – Parameter:The DR post-amblecountis'1'. – Parameter:The IR main countis'4'. – Parameter:The DR main countis'1'. The initialscan chaincontainsonlythe TAP routermodule.The followingstepsmust be completedin ordertoadd ETB TAP tothescan chain. Figure6-72.Adding ETB tothescan chain
Function:Do a send-onlyJTAG IR/DR scan. – Parameter:The routetoJTAG shiftstateis'shortesttransition'. – Parameter:The JTAG shiftstateis'shift-ir'. – Parameter:The JTAG destinationstateis'pause-ir'. – Parameter:The bitlengthofthecommand is'6'. – Parameter:The send datavalueis'0x00000007'. – Parameter:The actualreceivedatais'discarded'.
Function:Do a send-onlyJTAG IR/DR scan. – Parameter:The routetoJTAG shiftstateis'shortesttransition'. – Parameter:The JTAG shiftstateis'shift-dr'. – Parameter:The JTAG destinationstateis'pause-dr'.

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010 – Parameter:The bitlengthofthecommand is'8'. – Parameter:The send datavalueis'0x00000089'. – Parameter:The actualreceivedatais'discarded'.

Function:Do a send-onlyJTAG IR/DR scan. – Parameter:The routetoJTAG shiftstateis'shortesttransition'. – Parameter:The JTAG shiftstateis'shift-ir'. – Parameter:The JTAG destinationstateis'pause-ir'. – Parameter:The bitlengthofthecommand is'6'. – Parameter:The send datavalueis'0x00000002'. – Parameter:The actualreceivedatais'discarded'.
Function:Embed theportaddressinnextcommand. – Parameter:The portaddressfieldis'0x0f000000'. – Parameter:The portaddressvalueis'3'.
Function:Do a send-onlyJTAG IR/DR scan. – Parameter:The routetoJTAG shiftstateis'shortesttransition'. – Parameter:The JTAG shiftstateis'shift-dr'. – Parameter:The JTAG destinationstateis'pause-dr'. – Parameter:The bitlengthofthecommand is'32'. – Parameter:The send datavalueis'0xa3302108'. – Parameter:The actualreceivedatais'discarded'.
Function:Do a send-onlyall-onesJTAG IR/DR scan. – Parameter:The JTAG shiftstateis'shift-ir'. – Parameter:The JTAG destinationstateis'run-test/idle'. – Parameter:The bitlengthofthecommand is'6'. – Parameter:The send datavalueis'all-ones'. – Parameter:The actualreceivedatais'discarded'.
Function:Waitfora minimum number ofTCLK pulses. – Parameter:The countofTCLK pulsesis'10'.
Function:Update theJTAG preambleand post-amblecounts. – Parameter:The IR pre-amblecountis'0'. – Parameter:The IR post-amblecountis'6+ 4'. – Parameter:The DR pre-amblecountis'0'. – Parameter:The DR post-amblecountis'1+ 1'. – Parameter:The IR main countis'4'. – Parameter:The DR main countis'1'. 6.31.4 JTAG 1149.1Boundary Scan Considerations To use boundaryscan,thefollowingsequence shouldbe followed:
Executea validresetsequence and exitreset
Waitatleast6000 OSCIN clockcycles
Enterboundaryscan mode usingtheJTAG pins No specificvalueisrequiredon the EMU0 pinforboundary scan testing.IfTRST isnot drivenby the boundaryscan toolortester,TRST shouldbe externallypulledhighduringboundaryscan testing. Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 187 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com 6.32 IEEE 1149.1JTAG The JTAG (1)interfaceisused forBSDL testingand emulationofthedevice. The devicerequiresthatboth TRST and RESET be assertedupon power up to be properlyinitialized. WhileRESET initializesthedevice,TRST initializesthedevice'semulationlogic.Both resetsarerequired forproperoperation. WhilebothTRST and RESET need tobe assertedupon power up,onlyRESET needs tobe releasedfor thedevicetobootproperly.TRST may be assertedindefinitelyfornormaloperation,keepingtheJTAG portinterfaceand device'semulationlogicintheresetstate. TRST onlyneeds tobe releasedwhen itisnecessarytouse a JTAG controllertodebug thedeviceor exercisethedevice'sboundaryscan functionality.Note:TRST issynchronousand must be clockedby TCK; otherwise,theboundaryscan logicmay notrespondas expectedafterTRST isasserted. RESET must be releasedonlyin orderforboundary-scanJTAG to read the variantfieldof IDCODE correctly.Otherboundary-scaninstructionswork correctlyindependentofcurrentstateofRESET. For maximum reliability,the deviceincludesan internalpulldown(IPD)on the TRST pinto ensure that TRST willalways be assertedupon power up and the device'sinternalemulationlogicwillalways be properlyinitialized. JTAG controllersfrom Texas InstrumentsactivelydriveTRST high.However, some third-partyJTAG controllersmay notdriveTRST highbutexpecttheuse ofa pullupresistoron TRST. When usingthistypeofJTAG controller,assertTRST toinitializethedeviceafterpowerup and externally driveTRST highbeforeattemptingany emulationorboundaryscan operations.

6.32.1 JTAG PeripheralRegisterDescription(s)– JTAG ID Register(DEVIDR0)

Table6-113.DEVIDR0 Register BYTE ADDRESS ACRONYM REGISTER DESCRIPTION COMMENTS 0x01C1 4018 DEVIDR0 JTAG IdentificationRegister Read-only.Provides32-bitJTAG ID ofthedevice. (1) IEEE Standard1149.1-1990Standard-Test-AccessPortand BoundaryScan Architecture. The JTAG ID registerisa read-onlyregisterthatidentifiestothecustomertheJTAG/Device ID.For the device,theJTAG ID registerresidesataddresslocation0x01C1 4018.The registerhex valueforeach siliconrevisionis:

0x8B7D F02F forsiliconrevision1.1
0x9B7D F02F forsiliconrevision2.0 For the actualregisterbitnames and theirassociatedbitfielddescriptions,see Figure6-73 and Table6-114. 31-28 27-12 11-1 0 VARIANT (4-Bit) PART NUMBER (16-Bit) MANUFACTURER (11-Bit) LSB R-xxxx R-1011 0111 1101 1111 R-0000 0010 111 R-1 LEGEND: R = Read, W = Write,n = valueatreset Figure6-73.JTAG ID (DEVIDR0) RegisterDescription-RegisterValue

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ADVANCE□INFORMATION TCK TDO RTCK 5 6 TDI/TMS/TRST AM1707 www.ti.com SPRS637 –FEBRUARY 2010 Table6-114.JTAG ID RegisterSelectionBitDescriptions BIT NAME DESCRIPTION 31:28 VARIANT Variant(4-Bit)value 27:12 PART NUMBER PartNumber (16-Bit)value 11-1 MANUFACTURER Manufacturer(11-Bit)value 0 LSB LSB. Thisbitisreadas a "1".

6.32.2 JTAG Test-PortElectricalData/Timing

Table6-115.Timing Requirements forJTAG TestPort(seeFigure6-74) No. PARAMETER MIN MAX UNIT 1 tc(TCK) Cycletime,TCK 40 ns 2 tw(TCKH) Pulseduration,TCK high 16 ns 3 tw(TCKL) Pulseduration,TCK low 16 ns 4 tc(RTCK) Cycletime,RTCK 40 ns 5 tw(RTCKH) Pulseduration,RTCK high 16 ns 6 tw(RTCKL) Pulseduration,RTCK low 16 ns 7 tsu(TDIV-RTCKH) Setuptime,TDI/TMS/TRST validbeforeRTCK high 4 ns 8 th(RTCKH-TDIV) Holdtime,TDI/TMS/TRST validafterRTCK high 4 ns Table6-116.SwitchingCharacteristicsOver Recommended OperatingConditionsforJTAG TestPort (seeFigure6-74) No. PARAMETER MIN MAX UNIT 9 td(RTCKL-TDOV) Delaytime,RTCK lowtoTDO valid 15 ns Figure6-74.JTAG Test-PortTiming Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 189 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION Seconds Minutes Hours Days Months Years Alarm Timer Alarm Interrupts Periodic Interrupts Counter 32□kHz Oscillator Compensation Week Days Oscillator RTC_XI XTAL RTC_XO AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

6.33 Real Time Clock (RTC)

The RTC providesa timereferencetoan applicationrunningon thedevice.The currentdateand timeis trackedina setofcounterregistersthatupdateonce persecond.The timecan be representedin12-hour or24-hourmode. The calendarand timeregistersarebufferedduringreadsand writesso thatupdatesdo notinterferewiththeaccuracyofthetimeand date. Alarms are availabletointerrupttheCPU ata particulartime,or atperiodictimeintervals,such as once perminuteoronce perday.Inaddition,theRTC can interrupttheCPU everytimethecalendarand time registersareupdated,oratprogrammableperiodicintervals. The real-timeclock(RTC) providesthefollowingfeatures:

100-yearcalendar(xx00toxx99)
Countsseconds,minutes,hours,day oftheweek,date,month,and yearwithleapyearcompensation
Binary-coded-decimal(BCD) representationoftime,calendar,and alarm
12-hourclockmode (withAM and PM) or24-hourclockmode
Alarminterrupt
Periodicinterrupt
SingleinterrupttotheCPU
Supportsexternal32.768-kHzcrystalorexternalclocksourceofthesame frequency
Separateisolatedpower supply Figure6-75shows a blockdiagramoftheRTC. Figure6-75.Real-TimeClock Block Diagram

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ADVANCE□INFORMATION XTAL 32.768 kHz RTC_X1 RTC_X0 RTC_VSS 32K OSC Real Time Clock (RTC) Module Isolated□RTC Power□Domain Switch□for□Device Core□Power Real□Time□Clock +1.2V CV DD RTC_CVDD AM1707 www.ti.com SPRS637 –FEBRUARY 2010

6.33.1 Clock Source

The clockreferencefortheRTC isan external32.768-kHzcrystaloran externalclocksourceofthesame frequency.The RTC alsohas a separatepower supplythatisisolatedfromtherestofthesystem.When theCPU and otherperipheralsare withoutpower,theRTC can remainpowered topreservethecurrent timeand calendarinformation. The sourcefortheRTC referenceclockmay be providedby a crystalorby an externalclocksource.The RTC has an internaloscillatorbuffertosupportdirectoperationwitha crystal.The crystalisconnected between pinsRTC_XI and RTC_XO. RTC_XI isthe inputto the on-chiposcillatorand RTC_XO isthe outputfrom theoscillatorback tothecrystal.A crystalwith70k-ohm max ESR isrecommended. Typical C1, C2 valuesare10-20pF. An external32.768-kHzclocksourcemay be used insteadofa crystal.Insuch a case,theclocksourceis connectedtoRTC_XI, and RTC_XO isleftunconnected. Ifthe RTC isnot used,the RTC_XI pinshouldbe staticheldhighor low and RTC_XO shouldbe left unconnected. Figure6-76.Clock Source Copyright© 2010,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 191 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

6.33.2 Registers

Table6-117liststhememory-mapped registersfortheRTC. See thedevice-specificdatamanual forthe memory addressoftheseregisters. Table6-117.Real-TimeClock (RTC) Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01C2 3000 SECOND Seconds Register 0x01C2 3004 MINUTE MinutesRegister 0x01C2 3008 HOUR Hours Register 0x01C2 300C DAY Day oftheMonth Register 0x01C2 3010 MONTH Month Register 0x01C2 3014 YEAR Year Register 0x01C2 3018 DOTW Day oftheWeek Register 0x01C2 3020 ALARMSECOND AlarmSeconds Register 0x01C2 3024 ALARMMINUTE AlarmMinutesRegister 0x01C2 3028 ALARMHOUR AlarmHours Register 0x01C2 302C ALARMDAY AlarmDays Register 0x01C2 3030 ALARMMONTH AlarmMonths Register 0x01C2 3034 ALARMYEAR AlarmYearsRegister 0x01C2 3040 CTRL ControlRegister 0x01C2 3044 STATUS StatusRegister 0x01C2 3048 INTERRUPT InterruptEnableRegister 0x01C2 304C COMPLSB Compensation(LSB)Register 0x01C2 3050 COMPMSB Compensation(MSB) Register 0x01C2 3054 OSC OscillatorRegister 0x01C2 3060 SCRATCH0 Scratch0 (General-Purpose)Register 0x01C2 3064 SCRATCH1 Scratch1 (General-Purpose)Register 0x01C2 3068 SCRATCH2 Scratch2 (General-Purpose)Register 0x01C2 306C KICK0 Kick0 (WriteProtect)Register 0x01C2 3070 KICK1 Kick1 (WriteProtect)Register

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010

7 Device and Documentation Support

7.1 Device Support

TI offersan extensivelineof developmenttoolsforthe deviceplatform,includingtoolsto evaluatethe performanceoftheprocessors,generatecode,developalgorithmimplementations,and fullyintegrateand debug softwareand hardwaremodules.The tool'ssupportdocumentationiselectronicallyavailablewithin theCode Composer Studio™ IntegratedDevelopmentEnvironment(IDE). The followingproductssupportdevelopmentofthedeviceapplications: SoftwareDevelopment Tools: Code Composer Studio™ IntegratedDevelopmentEnvironment(IDE):includingEditor C/C++/AssemblyCode Generation,and Debug plusadditionaldevelopmenttools Hardware Development Tools: ExtendedDevelopmentSystem (XDS ™ )Emulator For a completelistingofdevelopment-supporttoolsforthedevice,visittheTexas Instrumentsweb site on theWorldwideWeb athttp://www.ti.comuniformresourcelocator(URL).For informationon pricing and availability,contactthenearestTIfieldsalesofficeorauthorizeddistributor.

7.2 Documentation Support

The followingdocuments describethedevice.Copiesofthesedocuments areavailableon theInternetat ReferenceGuides SPRUGR6 AM1707 ARM MicroprocessorSystem ReferenceGuide SPRUFU0 AM17x/AM18x ARM MicroprocessorPeripheralsOverview ReferenceGuide Copyright© 2010,Texas InstrumentsIncorporated Deviceand DocumentationSupport 193 SubmitDocumentationFeedback ProductFolderLink(s):AM1707

ADVANCE□INFORMATION X AM1707 ( ) ZKB ( ) 3 PREFIX X = Experimental Device P = Prototype Device Blank = Production Device DEVICE SILICON REVISION 3 = 375 MHz 4 = 456 MHz Blank PACKAGE TYPE

256 Pin Plastic BGA, with Pb-free

Soldered Balls [Green] ZKB = DEVICE SPEED RANGE TEMPERATURE RANGE (JUNCTION) B = Silicon Revision 2.0 = 0°C to 90°C (Commercial Grade) = -40°C to 90°C (Industrial Grade)D A = -40°C to 105°C( Extended Grade) T = -40°C to 125°C( Automotive Grade) AM1707 SPRS637 –FEBRUARY 2010 www.ti.com

8 MechanicalPackaging and OrderableInformation

This sectiondescribesthe deviceorderablepartnumbers, packagingoptions,materials,thermaland mechanicalparameters.

8.1 Device and Development-Support Tool Nomenclature

Figure8-1providesa legendforreadingthedevice. Figure8-1.Device Nomenclature

8.2 Thermal Data forZKB

The followingtable(s)show the thermalresistancecharacteristicsfor the PBGA –ZKB mechanical package. Table8-1.Thermal ResistanceCharacteristics(PBGA Package) [ZKB] PARAMETER °C/W (1) °C/W (2) AIR FLOW (m/s)(3) R ΘJC Junction-to-case 12.8 13.5 N/A R ΘJB Junction-to-board 15.1 19.7 N/A R ΘJA Junction-to-freeair 24.5 33.8 0.00 21.9 30 0.50 21.1 28.7 1.00 R ΘJMA Junction-to-movingair 20.4 27.4 2.00 19.6 26 4.00 0.6 0.8 0.00 0.8 1 0.50 PsiJT Junction-to-packagetop 0.9 1.2 1.00 1.1 1.4 2.00 1.3 1.8 4.00 14.9 19.1 0.00 14.4 18.2 0.50 PsiJB Junction-to-board 14.4 18 1.00 14.3 17.7 2.00 14.1 17.4 4.00 (1) These measurements were conductedina JEDEC defined2S2P systemand willchange based on environmentas wellas application. Formore information,see theseEIA/JEDEC standards– EIA/JESD51-2,IntegratedCircuitsThermalTestMethod Environment Conditions-NaturalConvection(StillAir)and JESD51-7,HighEffectiveThermalConductivityTestBoard forLeaded SurfaceMount Packages.Power dissipationof1W and ambienttemp of70C assumed. PCB with2oz (70um)topand bottomcopperthicknessand 1.5oz(50um)innercopperthickness (2) Simulationdata,usingthesame model butwith1oz (35um)topand bottomcopperthicknessand 0.5oz(18um)innercopperthickness. Power dissipationof1W and ambienttemp of70C assumed. (3) m/s = meterspersecond

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ADVANCE□INFORMATION AM1707 www.ti.com SPRS637 –FEBRUARY 2010

8.3 MechanicalDrawings

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) XAM1707BZKB4 ACTIVE BGA ZKB 256 90 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 27-Feb-2010 Addendum-Page 1

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Product Information

PAM1707BZKBD4 specifications and overview.

Summary

AM1707 ARM Microprocessor

Description

AM1707 ARM Microprocessor

Source title PAM1707BZKBD4 Datasheet(PDF) - Texas Instruments

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