PAL20C1

PAL20X8 NSC | Alldatasheet

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J = . £ ZA National z Semiconductor a = . @| Programmable Array Logic (PAL®) Ly) . ry ‘¢ | 24-Pin Small PAL Family a = | General Description The 24-pin Small PAL family contains six popular PAL archi- | The Small PAL logic array has between 12 and 20 comple- tectures. The devices in the Small PAL family draw only mentary inputs and up to 10 combinatorial outputs generat- 1400 mA maximum supply current as compared to 210 mAin _ed by a single programmable AND-gate array with fixed OR- the 24-pin Medium PAL devices. These devices offer gate connections. The Small PAL family offers a variety of speeds as fast as 25 ns maximum propagation delay. Na- input/output combinations as shown in the Device Types tional Semiconductor's Schottky TTL process with titanium table below. Security fuses can be programmed to prevent tungsten fusible links provides high-speed user-programma- _ direct copying of proprietary logic patterns. ble replacements for conventional SSI/MSI logic with signif- icant chip-count reduction. Features Programmable logic devices provide convenient solutions m™ As fast as 25 ns maximum propagation delay for a wide variety of application-specific functions, including User-programmable replacement for TTL logic random logic, custom decoders, state machines, etc. BY w Large variety of JEDEC-compatible programming equip- programming fusible links to configure AND/OR gate con- ment available nections, the system designer can implement custom logic g Fylly supported by National PLANT™ development as convenient sum-of-products Boolean functions. System software prototyping and design iterations can be performed quickly " F - - using these off-the-shelf products. A large variety of pro- '™ Security fuse prevents direct copying of logic patterns gramming units and software makes design development and functional testing of PAL devices quick and easy. Device Types Block Diagram—PAL12L10 Device Dedicated Combinatorial Type inputs Outputs [+f | 24] Paats [4 [8 —id on = Paice [te | > patie |e | a) ee PAL2012 in De 7) Be . eee OD | Speed/Power Versions apa om foe me] 6 hd LE | eo | tec | too | toc | Oo >. Standard] PAL12L10 100 mA | To | PALI2L10A on 2 ” PAL20C1A = 30 ns Cor ial, fe = aE Li 2-48

Standard Series (pav12i10, PAL14L8, PAL16L6, PAL18L4, PAL20L2, PAL20C1) 2 i oororvrt—were —e>e>o>eES TOTS . ‘ 7) Absolute Maximum Ratings (note 1) 3 If Military/Aerospace specified devices are required, Output Current (ip) +100 mA 2 please contact the National Semiconductor Sales Storage Temperature ecto +1500 | O Office/Distributors for availability and specifications. Ambient Temperature 2 Supply Voltage (Vcc) (Note 2) —0.5to +7.0V with Power Applied -es'cto +1250 | Input Voltage (Notes 2 and 3) —15to +5.5V Junction Temperature -65Cto +1500 | 3 Off-State Output Voltage (Note 2) -1.5to +5.5V = Input Current (Note 2) —30.0 mA to + 5.0 mA Recommended Operating Conditions Military Commercial Symbol Parameter Units ee eee Max Te OperatingCase Temperate | | | as | | Te Electrical Characteristics over Recommended Operating Conditions (Note 4) symbol | Parameter Test Conditions [ win | typ [max | units Vi [towLevelinputvortagewvowes) | TT |v Via __[HighLevelinputVoltge Notes) | Pc TT Vic__| Input Clamp Voltage Voc = Min, | = —18 mA [| -os | -15[ v tit Low Level Input Current Voc = Max, V; = 0.4V |__| -o.02 | -0.25 | mA ti High Level Input Current Voc = Max, Vi = 2.4V | | [25 [pa 1, | Maximum input Curent Vo = Max,V, = 68V Ltt ma Vou | High Level Output Vottage | Vcc = Min y los Output Short-Circuit Current Voc = 5V, Vo = OV —70 | —190 | ma (Note 6) cc__ | Supply Current Voc = Max, Outputs Open |_| 60 | 100 | ma Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. Proper operation is not guaranteed outside the ‘specified recommended operating conditions. Note 2: Some device pins may be raised above these limits during programming operations according to the applicable specification. Note 3: It is recommended that precautions be taken to minimize electrostatic discharge when handling and testing this product. Pins 1 and 13 (DIP) are connected directly to the security fuses, and the security fuses may be damaged preventing subsequent programming and verification operations. Nate 4: All typical values are for Veg = 5.0V and Ta = 25°C. Note 5: These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. Note 6: To avoid Invalid readings in other parameter tests, its preferable to conduct the log test last. To minimize internal heating, only one output should be ‘shorted at a time with a maximum duration of 1.0 second each. Prolonged shorting of a high output may raise the chip temperature above normal and permanent damage may result. 2-49

& Standard Series (Pav12110, PAL14L8, PAL16L6, PAL18L4, PAL20L2, PAL20C1) (Continued)

2 Switching Characteristics over Recommended Operating Conditions

= [Mittary —[Commercian |

3 Smee ‘ne

a E [renew | [min | typ | mex | win [ typ | Max | 2 tep Input to Output | C, = 50 pF a ns N Test Load Test Waveform sv Propagation Delay INPUT wv ‘MIL/COM hook Ri = 560 v ‘OH OUTPUT = IN“PHASE Vy | Vr Reo hk ourPuT Vou. o R2 pL p= =H OUT OF PHASE You output vp Vy TL/L/e907-2 TUL/9997-3 Notes: Vy = 1.5V C, includes probe and jig capacitance. In the examples above, the phase relationships between inputs and outputs. have been chosen arbitrarily. Schematic of Inputs and Outputs EQUIVALENT INPUT TYPICAL OUTPUT Yee 0 © Yee 400 NOM. i ): 5 © OUTPUT = = TL/L/9897~4 2-60

Series A (PAL12L10A, PAL14L8A, PAL16L6A, PALI8L4A, PAL20L2A, PAL20C1A) a] Oe ooreeeeRPe__—arre GS . ” Absolute Maximum Ratings (note 1) 3 If Milltary/Aerospace specified devices are required, Ambient Temperature 2 please contact the National Semiconductor Sales with Power Applied -65'Ct0 +1256 | Office/Distributors for availability and specifications. Junction Temperature -escto+is0c | 2 Supply Voltage (Vcc) (Note 2) —0.5to +7.0V ESD Tolerance (Note 3) 1500V a Input Voltage (Note 2) -1.5to +5.5V Czap = 100 pF 3 Off-State Output Voltage (Note 2) —1.5to +5.5V Baar meter Body Model = _ ‘est Method: Human Body Model Input Current (Note 2) 30.0 mA to + 5.0 mA Test ification: NSC SOP-5-028 Output Current (Io) +100 mA s Storage Temperature —65°C to + 150°C Recommended Operating Conditions Symbol | reeme e E = Yoo Supply Voltage pas | 5 | ss | av [os | ses |v Te OperatingGaseTemperetwe | | | as | TTT oe Electrical Characteristics over Recommended Operating Conditions (Note 4) symbol] Parameter | Test Conditions [min | typ | max | units Vi [LowLevetinputvottge vores) | To | Vic Input Clamp Voltage Veo = Min, = —18 mA [| -oe | -15 | v he Low Level Input Current Voc = Max, Vi = 0.4V |__| -o.02 | -0.26 | ma im High Level Input Current Voc = Max, Vj = 2.4V | | [ss [na I Maximum Input Current Voc = Max, Vi = 5.5V [ [400 | pa Vor__| Low Level Output Vottage Voo=Mn[in=ema | [oa [os Tv Vou | High Level Output Voltage Voc = Min V lon= -3.2ma_| Com _| los Output Short-Circuit Current Voc = 5V, Vo = OV -70 mA (Note 6) tcc __| Supply Current Voc = Max, Outputs Open | [| «0 | 100 | ma Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. Proper operation is not guaranteed outside the specified recommended operating conditions. Note 2: Some device pins may be raised above these limits during programming operations according to the applicable specification. Note 3: It is recommended that precautions be taken to minimize electrostatic discharge when handling and testing this product. Pins 1 and 13 (DIP) are connected directly to the security fuses, and although the input circuitry can withstand the specified ESD conditions, the security fuses may be damaged preventing ‘subsequent programming and verification operations. Note 4: All typical values are for Voc = 5.0V and Ta = 25°C. Note 5: These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. Note 6: To avoid Invalid readings in other parameter tests, it is preferable to conduct the log test last. To minimize internal heating, only one output should be shorted at a time with a maximum duration of 1.0 second each. Prolonged shorting of a high output may raise the chip temperature above normal and permanent damage may result. 2-51

E Series A (PAL12L10A, PAL14L8A, PAL16L6A, PAL18L4A, PAL20L2A, PAL20C1A) (Continued) 2 | S| symbot Test Conditions Unita oO E [win [ tye | wax | min | typ | max | c tep Input to Output C, = 50 pF 12L10A, 14L8A, a 16L6A, 18L4A, ns 3 20L2A

2001 Py Pf ns

Ri = 560 ‘OH OUTPUT - IN-PHASE Vr | Ree tk ourPuT Vou C R2 tL IPH OUT OF PHASE Vou OUTPUT Ny Vy: = = ‘Yor TUs/9907-5 Tut/9987-6 Notes: Vr = 1.5V C, includes probe and jig capacitance. In the examples above, the phase relationships between inputs and outputs: have been chosen arbitrarily. Schematic of Inputs and Outputs EQUIVALENT INPUT TYPICAL OUTPUT Voc o o Yeo 400 NOM. ): = © ourPuT = = TL/L/9997~7 2-52

24-Pin Smail PAL Family Block Diagrams—DIP Connections 3 PAL12L10 PAL14L8 g ' pl ay | [28] Vog 1 2 cy] 128) Veg 2

1 BI =a Pere Lo nS) Er _ bn 3

1 ar ae [26] 0 ac) Lr <a }22| 26] 0 2 1 pl on pee 125} 0 an] og pee [25] 0 (6) on perp [4] 0 nc] on Pore [24] 0 1 om [et F=5>e-{ 13] 1231 0 1om [ef wo FRO] 31 0 ion on pee (191 0 in] on HD lis] 0 1 ca pe 1a] 0 1 pay fro} J Dofis} a) 0 1 pay [ia Deja} 171 0 13) = nal = ut GND [14] at, L_} felt GND [14] at L_| fe) 1 L*z PIN cman L*x PIN cam TLL/9997-8 TL/L/9967-9 PALI6L6 PAL18L4 1 2 on | [28] Voc 1 2 on | 128] Vee

1 BI oa re py 1 1 8 on Z_ a |

» 1 [af Re [25] 0 iow [ay —fa [25] 1 1 tel cH Poe (24) 0 1 18 cH =] [20] (24) 0 1 om Le] i). FFL? fig} 123) 0 1 om [ef wo =} ej 19] 123) 0 2 | 1 ogy cH Fj De-j16] 1193 0 1 oon Ls] ua= (9 1 112) [ro mall = felt 1 ay =a |__ Fe 3) 1 1 13) =a = tt 1 3) = - uo OND [14] at L_|} ta rt a GND [14] at L_| fs [ie] 1 L*2 PIN Tan] L*x PIN vm! TU/L/9907-10 TU/L/9987-11 2-53

—| 24-Pin Small PAL Family Block Diagrams—DIP Connections (continued) z PAL20L2 PAL20C1 a € or Ls] [ 24} 128) Voc 1 pl 28) Vee 5 a 4 Ba | 4 a 1 68 on LE (241 1 [6 on [20] 24) 1 f ney 2 1 12 =e rE 8] 1 1 ty a re {18} 1 1 ons fi] fe ut 1 ga [of rH ut L* PIN cmap! L = PIN cman] TULie0e7-12 Tuviewor-13 28-Lead PLCC Connection Conversion Diagram eo 8 5 & 24-PIN +o r — > - or PNP ic emo) GE) « bl LHS] [23 Ls] 1B [3] [25] loro iB [6] [24] IE] lor 0 ‘BE [2s] [3] o 28=LEAD PLCC we [a] (ToP VIEW) [22] ve OB Ei] 00rd Ce] Lo] [20] lor 0 1B) fy [ie] [a] 100 Ale « 6 ~~ eg =~ 9 8 g 5S 7 7~ ‘TL/L/9997-14 Note: For availability of old (NON-JEDEC) pinout, please contact your local National Semiconductor sales representative or distributor. 2-54

i or verifying operations. This feature prevents direct copying | 3 Functional Description ; of proprietary logic patterns. The security fuses should be | = The 24-pin Small PAL logic arrays consist of between 12 programmed only after programming and verifying all other | and 20 complementary input lines and either 16 or 20 prod- device fuses. 3 uct-term lines with a programmable fuse link at each inter- FA section (up to 720 fuses). The family consists of six device Design Development Su port = types with different numbers of combinatorial outputs. The ° P' P| 4 - R4 24-pin Small PAL Family Block Diagrams show the number A variety of software tools and programming hardware is 2 of product terms allocated to each output for each device. available to support the development of designs using PAL = All product terms allocated to each output connect into an products. Typical software packages accept Boolean logic | & OR-gate to produce the sum-of-products output logic fune- equations to define desired functions. Most are available to | tion. Tun on personal computers and generate JEDEC-compati- |“ i, , ble “fuse maps”. The industry-standard JEDEC format en- a unprogrammed wed {use Gstablishes a connection sures that the resulting fuse-map files can be down-loaded “or a ra) and ¢ or comple ving the foo into a variety of programming equipment. Many software Tonotos te conn tion A product one oat ‘9 (ox ical. Packages and programming units support a wide variety of " fection. A product term is satisfied (logical- programmable logic products as well. The PLANT software 'y true) while all of the input lines connected to it (via unpro- Package from National Semiconductor supports all pro- grammed fuses) are in the high logic state. Therefore, if grammable logic products available from National and is ful- both the true and complement of at least one array input is left connected to a product line, that product term ts always ly JEDEC-compatible. PLAN software also provides auto- held in the low logic state (which is the state of all product Irate oases en bared on the designer's Boolean terms in an unprogrammed device). Conversely, if all fuses , on a product tormewore panna the product term and Detailed logic diagrams showing all JEDEC fuse-map ad- the resulting logic function would be held in the high state. Grosses: 20 cating ea Sagroste fame a Fear your As wi any logic crete. unuse’ inputs to niente local National Semiconductor sales representative or dis- eV However ow switch Ape in uty or vccted toa tributor for a list of current software and programming sup- 'y to Veo » Swavcrung any input not cone: port tools available for these devices. Contact the National product term or logic function has no effect on its output Semiconductor Programmable Device Support Department logic state, if detailed specifications of PAL programming algorithms are needed. Security Fuse Security fuses are provided on all National PAL devices which, when programmed, inhibit any further programming

Ordering Information

Programmable Array Logic Family Number of Array Inputs Output Type: Ls C=Complementary R=Registered X= Exclusive-OR Registered P=Programmable Polarity Number of Outputs ‘Speed Version: No Symbol= 40 ns A =25ns Package Type: N=24-Pin Plastic DIP J=24=Pin Ceramic DIP V=28-Lead Plastic Chip Carrier Temperature Range: C=Commercial foe te beta! M=Mllitary (-55°C to +125°C! PAL12L10ANC quueeer 18 2-55

&| Logic Diagram PAL12L10 uo z DIP PIN NUMBERS INPUT LINE DIP PIN a PRODUCT LINE FIRST FUSE NUMBERS NUMBERS NUMBERS

3 Vea fr fo hy is ‘is ‘Wiz ‘ie za72 el Vog '

— C24 a 1 pean a z u—2 mena 23 2-48 iiNiouiomom omni a 2 120-28: mic an a

163144 Mn 20

216192 Fee PS 19

264 240: mo 18 312288. moo 7 8 sat | || 360 338: cnn te 16 408 324 Mn ne 15 "1 | [Fs olalal 6) a) sol i2l tal tel tal 20le: mS O79 11S 1817-19 2125 = TLIL/9907-16 Note: JEDEC Logic Array Fuse Number = Product Line First Fuse Number + Input Line Number. 2-56

n DIP PIN NUMBERS INPUT LINE DIP PIN 3 pene LINE FIRST FUSE NUMBERS NUMBERS NUMBERS Db 24 2

1 Pan nm

2 ba: HIM nt 23 oot TET TTT TTT 28 “RR EY 0 56-28 iliii0iai mM iil 22 140112: mn i 2 196 188: Mane 20

752224 Mn 19

42032: Mi nie 16 2 |

9 SHH Ill

we iii :

10 TMT 14

" ELLE Fs ol2talelsl tol 121 tal tel tal 20122] 24lzeI VS S7 9 1 131817 19.” 2423-2527 ~ TL/L/9997-17° (Note: JEDEC Logic Array Fuse Number = Product Line First Fuse Number + Input Line Number. 257

£| Logic Diagram PAL16L6 uu z ‘DIP PIN NUMBERS. INPUT LINE DIP PIN a PRODUCT LINE FIRST FUSE NUMBERS NUMBERS NUMBERS 5 [ I, 2.4.6 8 10 12 14 16 18 2022 2426 assoel Veg & 1315/7] 9711 p13 15 17 19 21]23 [25}27 [29131 24 wn 1 aan a . | N

2 Le | Cre 23

64 SEER EEE ee 021

192, SoS pER Ey O20

7 HHH | lll

148 EE ey O17

576 EEE HE O16

mre : 2——_ Oe ety atts ts Sy Ny “2r3s 9597 28 1 ~ ‘TL/L/9087-18 Note: JEDEC Logic Array Fuse Number = Product Line First Fuse Number + Input Line Number. 2-58

. . = Logic Diagram PAL18L4 2 DIP PIN NUMBERS INPUT LINE DIP PIN 9 PRODUCT LINE FIRST FUSE NUMBERS. NUMBERS NUMBERS rx} [ J, 264 6 8 10 1214 16 18 2922 24.26 2830 32341 Yoo. + = TPS [S]7 [9411 [13/15 17 p19 y21923 [25]27 [29/31 )33}35 24 4 1 pan a 2 "| 5 nn a a OO TT TT TT TT TTT mee EES Do 19

1 EC TC TTT a

437 PEEP Ee EEE EEE) 0-18

— TTT

2 TOO TT TL ay

sizes siinsrsnsrrmsismtatassssesisesie tists Dall pirmmsscassscscsacsemsmemseracstecste stress, HET TT 8 area SR < W TE FFE 13 AOS 57 alan 88 17 19 2125-2927 29 51 35585 ~ TL/L/9997-19 Note: JEDEC Logic Array Fuse Number = Product Line First Fuse Number + Input Line Number. 2-59

E| Logic Diagram PAL20L2 wu z ‘DIP PIN NUMBERS INPUT LINE — DIP PIN a PRODUCT LINE FIRST FUSE NUMBERS NUMBERS = NUMBERS = t, 2,4 6 8 10 1214 1618 2022 2426 2830 3234 s638<! Vege } £ VPS [SET [904 [13)15 [1719 (21123 125j27 129/51 13335 137}59 24 (77) 1 Pn a N S Poort ee 20 oI CO TEESE EEE}

80 RCEEEE EEE EEE

1600S EEE EEE EEE HEHE ey O19

720 EERE EEE ee Eee ee eee

4.00 S235 ERE EEE EEE EEE EEE EEE EEE EER

180 SORE EEE EEE EEO 18

1 LCT PI 13

O121 4161 Bl0l 121141 1611 8t 201221 241264 281501 321541 36138) ———_V35°7- 911 15.15 1719 2123 25.27 29.31 3335 3739 = T1/1/9997-20 Note: JEDEC Logic Array Fuse Number = Product Line First Fuse Number + Input Line Number. 2-60

s rm) ‘DIP PIN NUMBERS: INPUT LINE DIP PIN 3 PRODUCT LINE FIRST FUSE NUMBERS NUMBERS NUMBERS b J, 24.6 8 10 1214 1618 2022 24.26 2830 3234 3638 «/ Vege i =o TPS /S]7 [9 [11 [13p15 [17]19 21923 (25}27 129)31 |33/35 |37)39 24 > 1 pen aa

5 Peto eT 20

=z PT PTT Eee See ee eee ee See seeeeeeees seeeeseesessate 80: PEE Eee eee eee eee eet

160 OEE HEHEHE eee)

240 EEE Eee eee eee eee ee eet tet

280: o TTT 19

6 Roo ooo Da

SEER EERE EEE EEE EERE EERE EEE

4005 EEE EEE

480 OSE EEE EEE Eee eee >

560: EERE EERE EEE Eee Eee eee eet 600: oS TT TT 1" NTE {1 13 0121 4161 81101 121141 161181 201221 241261 281301 321341 36138! 12—_ 135-7914 1315 1719 2123 2527 2931 3335 3739 = TU/9907-21 Note: JEDEC Logic Array Fuse Number = Product Line First Fuse Number + Input Line Number. 2-61