PAL1016P8

PAL1016P8 NSC | Alldatasheet

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o i 2 . a

3 GA National PRELIMINARY

8 Semiconductor

o 2 | PAL10/10016P8-3 (DIP Only) < . a) 3ns ECL ASPECT™ Programmable Array Logic Oo ae w | General Description The PAL10/10016P8-3 is a member of the National Semi- product term. Each output function is provided with output conductor 28-pin high speed ECL PAL® family. This device __ polarity fuses. These fuses permit the designer to configure utilizes National Semiconductor's ASPECT (Advanced Sin- each output independently to produce either a logic high (by gle Poly Emitter Coupled Technology) process with a newly —_leaving the fuse intact) or a logic low (by programming the developed tungsten fuse technology to provide the highest- fuse) when the equation defining that output is satisfied. speed user-programmable replacements for conventional programming equipment and software make PAL design de- ECL SSI-MSI! logic with significant chip-count reduction. The velopment quick and easy. Programming is accomplished JEDEC fuse-map format and programming algorithm of this using TTL voltage levels and is therefore supported by in- device is compatible with those of all prior ECL PAL prod- dustry standard TTL PLD programmers. After programming ucts from National. and verifying the logic array, an additional security fuse may Programmable logic devices provide convenient solutions — be programmed to prevent direct copying of proprietary log- for a wide variety of applications—specific functions, includ- _ ic designs. ing random logic, custom decoders, state machines, etc. By programming fuse links to configure AND/OR gate connec- Features tions, the system Sesigner can implement custom oa @S wm High speed: tpep = 3 ns max Convenient sum-of-products Boolean functions. System pro- ig programmable replacement for ECL logic totyping and design iterations can be performed quickly us- ' ™ Both 100K and 10 KH I/O compatible versions ing these off-the shelf products. @ Eight output functions with programmable polarity The PAL10/10016P8-3 logic array has a total of 16 comple- im rove ? rogrammabili ‘on en fuses po mentary input pairs, 64 product terms and 8 programmable P Progt lity tungsten f polarity output functions. Each output function is the OR- ™ Security fuse to prevent direct copying sum of 8 product terms. Each product term is satisfied when | ™ Programmed on conventional TTL PLD programmers all array inputs which are connected to it (via intact fuses) ™ Fully supported by PLAN™ software are in the correct state as defined by the equation for that ™ Commercial and Military ranges Ordering Information Block Diagram Programmable Array Logic Family PAL10/10016P8-3 ECL I/O Compatibility: " 5 10 = ECL 10KH yo— 4 0 100 = ECL 100K 12 > Number of Array Inputs is 8 T> Da so Output Type: you P = Programmable Polarity yos 8 > >? ° | Number of Outputs 19 Speed Version: —3 = 3nstpp 110 8 > > yo a mm 28. N = 24-Pin Plastic 113 J. = 24-Pin Ceramic DIP ‘JD | >°- 70 “Note: For PLCC see PAL10/10016PE8-3 ad Temperature Range: is 8 i o— 18 0 C= Commercial: 116 > 0°C to + 75°C for 10KH 0°C to + 85°C for 100K yor 8 > L>°-» ° M4 = Extended (ny: vor —§5°C to + 125°C for 10KH O°C to + 125°C for 100K 122 U D> Dea yo PAL 100 16 P 8 -3 J C 8 TULto7I4—1 2-236

m . ‘ _ ° Absolute Maximum Ratings Output Current ; Soma | Temperature under Bias ESC to + 125°C Lead Temperature (Soldering, 10 Seconds) sore |p Storage Temperature Range 65°C to + 150°C ESD Tolerance TaD | - Czap = 100 pF 2 Vee Relative to Voc -7V to +0.5V Rzap = 15009 s Input Voltage Ver to +0.5V Test Method: Human Body Model o Test Specification: NSC SOP-5-028 : a Recommended Operating Conditions for commercial Range e oa symbol | Parameter in| typ | Max | Unite VEE Supply Voltage 40KH —5.46 5.2 4,94 v 100K —480 45 —4.20 T Operating Temperature (note) | tox | oo | |] | rook | oT es | Electrical Characteristics over Recommended Operating Conditions Output Load = 50? to —2.0V symbol | Parameter | Conditions [ta | win [tax | unite Vin High Level Input Voltage Guaranteed Input Voltage 40KH oc —1170 —840 High for All Inputs: +25°C -1130 —810 mv +75C —1070 735 | 100k | orcto rec | —i165 | xo | Vit Low Level Input Voltage Guaranteed Input Voltage oc —1950 —1480 Low for All Inputs 10KH +258C —1950 —1480 mv +758°C —1950 —1450 [ 100k | octo +e5c | —1810 | —1475 Vou High Level Output Voltage | Vin = Vi Max or Vi. Min oc -1020 | —840 10KH +25°C —980 -810 mv +75°C =920 | -735 Oto +85°C | — 1025 Vor Low Level Output Voltage | Vin = Vin Max or Vi. Min oc —1950 | —1630 10KH +25°C —1950 — 1630 mv +75°C ~ 1950 — 1600 Ii High Level Input Current | Vin = Vij Max toKH orc +75°C pA O°C to +85°C hie Low Level input Current Vin = Vi Min toKH oc 2 | +75°C pA OC to +85°C lee Supply Current Vee = Min O° to + 75°C All Inputs and Outputs Open mA i puts Open | 400K | O°Cto +85°C Note: Operating temperatures for circuits in J and N packages are specified as ambient temperatures (Ta) with circuits in a test socket or mounted on a Printed circuit board and transverse air flow greater than 500 linear fpm is maintained. 2-237

ry " " - & | Absolute Maximum Ratings Output Current 50 mA © | Temperature under Bias “55°C to +125°C Lead Temperature (Soldering, 10 Seconds) 300°C s Storage Temperature Range 65°C to + 150°C Ss ates oF TaD S| Vee Relative to Voc -7Vto +0.5V Rzap = 15009. | input vottage Vee to +0.5V Test Method: Human Body Model

4 Test Specification: NSC SOP-5-028

a @| Recommended Operating Conditions for Extended (Military) Range* w symbol [Parameter | win [typ | Max | Units Vee Supply Voltage 10KH 5.46 -5.2 4.94 v 100K — 4.80 4.5 —4.20 T Operating Temperature (Note) | soKH | 85 || tT ag Electrical Characteristics over Recommended Operating Conditions Output Load = 502 to —2.0V symbol | Parameter | Conaitions [te | min [ax | units Vie High Level Input Voltage | Guaranteed input Voltage | a4, —55°C —1250 | -930 High for All inputs +25°C —1130 -810 mv +125°C — 1000 —660 OG t0 +1256 Vit Low Level Input Voltage Guaranteed Input Voltage —55°C —1950 | —1480 Low for All Inputs 10KH + 25°C 1950 1480 mv +126°C -1950 | ~1420 100K | 0°Cto + 125°C = 1475 Vou High Level Output Voltage | Viy = Vin Max or Vj_ Min 55°C 1110 | 930 10KH +25°C —980 —810 mv +125°C —830 —660 O10 +1256 Voi Low Level Output Voltage | Vin = Vin Max or Vip Min —55°C —1950 | —1630 10KH +25°C -1950 | —1630 mv +125°C —1950 | —1570 took | orcto+126°¢ | 1810 | —1620 | hi High Level Input Current | Vin = Vin Max t0KH —55°C + 125°C pA 100K O°C to + 125°C | te Low Level Input Current | Vin = Vip Min t0KH 55°C +125°C HA 100K OC to + 125°C lee Supply Current Vee = Min 10KH | —55°C to +125°C All Inputs and Outputs Oj ~ 220 mA Inputs and Outputs Open | ro9K | oC to + 125°C Note: Operating temperatures for circuits in J and N packages are specified as ambient temperatures (Ta) with circuits in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. * Extended (Military) range available in J package only. 2-238

m . . 9 Switching Characteristics ec Over Recommended Operating Conditions, Output load: Ri, = 509 to —2.0V, CL = 5 pF to GND 3 crmtet | Pare | teenrss Teton ao ie ee tep Input to Output Measured at Threshold Points ns 3 (Note 1) = & Output Rise Time | Measured between | 025 | 125 | 025 | 125 [ns | 3 u Output FallTime | _20% and 80% Points | o2s [ 125 [ 025 | 125 [ns | © Note 1: All AC Measurements are to be made from Threshold Point. bed Vin = Threshold + 400 mV Vit = Threshold — 400 mv Vitin * Vitex [rat [temp] Vinwin | Yuwax | Thresmod [vw [Yu _| 10 kH 58°C —1250 —1480 —1365 —965 —1765 oc —1170 —1480 —1325 —925 —1725 25°C —1130 —1480 —1300 —900 —1700 75°C —1070 —1450 —1260 860 — 1660 125°C — 1000 —1420 —1210 —810 — 1610 Timing Measurements Test Load Vu Dout THRESHOLD INPUT _— a Vou’ THRESHOLD OUTPUT L You “2V = Tuunoria-2 Tuunorie-3 Connection Diagram Dual-In-Line Package 1 1 Ey Voc 1 2 23 1 1 3 2 1 vo 4 a vo oO 5 20 0 ‘vCcO 6 19 veco o 7 18 0 vo 8 7 vo i] 9 16 1 i) 10 1S 1 1 n 4 i) VEE 1 3 i) TULno7i4—4 Top View 2-239

& i products. Typical software packages accept Boolean logic S Functional Testing . equations to define desired functions. Most are available to S| _ As.with all field-programmable devices, the user of the ECL run on personal computers and generate JEDEC-compati- 8 | PAL devices provides the final Manufacturing step. While ble “fuse maps”. The industry-standard JEDEC format en- | National's PAL devices undergo extensive testing when sures that the resulting fuse-map files can be downloaded e they are manufactured, their logic function can be fully test- into a large variety of programming equipment. Many soft- =! | edonly after they have been programmed to the user's pat- ware packages and programming units support a large vari- < tern. ety of programmable logic products as well. The PLAN soft- a4 To ensure that the programmed PAL devices will operate ware package from National Semiconductor supports all oO properly in your system, National Semiconductor (along with Programmable logic products available from National and is ua most other manufacturers of PAL devices) strongly recom- fully JEDEC-compatible. PLAN software also provides auto- mends that devices be functionally tested before being in- matic device selection based on the designer’s Boolean stalled in your system. Even though the number of post-pro- logic equations. gramming functional failures is small, testing the logic func- A detailed logic diagram showing all JEDEC fuse-map ad- tion of the PAL devices before they reach system assembly dresses for the PAL10/10016P8-3 is provided for direct will save board debugging and rework costs. For more infor- map editing and diagnostic purposes. For a list of current mation about the functional testing of PAL devices, please software and programming support tools available for these refer to National Semiconductor's Application Note #351 devices, please contact your local National Semiconductor and the Programmable Logic Design Guide. sales representative or distributor. If detailed specifications of the ECL PAL programming algorithm are needed, please Design Development Support contact the National Semiconductor Programmable Device A variety of software tools and programming hardware is ‘Support Department. available to support the development of designs using PAL Programmer Support Advin Systems Sailor PAL 8.40 Data I/O Unisite 40 v2.20 Digelec Model 860 VA-3.2 International Microsystems ECL-2 Logical Devices Allpro 1.446 Palpro 2x V4.0 SMS ‘Sprint Plus V3.25 Stag Microsystems ZL30A V31 2-240

m . 5 9° Logic Diagram—PAL1016P8-3/PAL10016P8-3 r z INPUT LINE NUMBER—>O 2 4 6 8B 10 12 14 16 18 2022 24 26 28 30 ore 173 [5/7 [9)t4 [13]15 17 [19 [21] 23 )25)27 429131 3 2 a iy CHASES 22 Ss > om qa = COT Teo 2048 vu PRODUCT LINE 0 SEE a oes ee 21 ° FIRST CELL NUMBER 64 SR Se ) > é 96 [EEE > 128 eee

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