PACS1284 | DigiCamel IC Datasheet

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PACS1284 CALMIRCO | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 7

Technical content

Features

Single chip IEEE 1284 parallel port termination 28-pin QSOP package, smallest physical solution 17 terminating lines in a single package In-system ESD protection to ±8KV, HBM In-system ESD protection to ±4KV per IEC 61000-4-2 Protects downstream devices to 30V Lead-free version available

Applications

ECP/EPP Parallel Port termination PC Peripherals Notebook and Desktop computers Engineering Workstations and Servers Product Description California Micro Devices’ PACS1284 Parallel Port Ter- mination Network provides a complete integrated solu- tion for the entire IEEE 1284 interface in a single QSOP package. To support the bi-directional transfer data rates of enhanced high-speed parallel ports, the IEEE 1284 Standard recommends a combined termination/pull-up filter network between the driver/receiver and the cable at both ends of the parallel port interface. In addition, government EMC compatibility requirements impose strict filtering requirements on the parallel port. The California Micro Devices PACS1284 addresses all these requirements by providing a seventeen-line IEEE 1284-compliant network in a thin film integrated circuit. The device provides a complete parallel port termina- tion solution for space critical applications by integrat- ing a total of 60 discrete components. In addition, all the I/O pins are ESD protected for contact discharges up to ±4KV per the Human Body Model (HBM), with the output pins having the highest probability of ESD pulse exposure protected to ±8KV (HBM), thereby providing the necessary robustness for the port’s application environment. The PACS1284 is manufactured in a 28-pin QSOP package and is available with optional lead-free finish- ing. Electrical Schematic PACS1284-02: R1 = 2.2kΩ R2 = 33Ω C = 220pF PACS1284-04: R1 = 4.7kΩ R2 = 33Ω C = 180pF C C C C C C C C C C C C C C C C C R3 = 2.2kΩ R3 = 4.7kΩ

Ordering Information

Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. PIN DESCRIPTIONS PINS PIN NAME

DESCRIPTION

1, 2, 27 Cap-filtered; R1 Pull-up IEEE 1284 signals which require no series termination; pull-up is R1 value. 8, 10, 12, 15, 28 Cap-filtered; R3 Pull-up IEEE 1284 signals which require no series termination; pull-up is R3 value. 3-7, 9,11, 13,14 SuperChip Side Series-terminated IEEE 1284 signals on the Super I/O Chip side which require series termination. 16-19, 21, 23-26 Connector Side Series-terminated IEEE 1284 signals on the Parallel Port Connector side which require series termination. VCC Supply rail for the device GND Ground reference for the device PACKAGE / PINOUT DIAGRAM Note: This drawing is not to scale. 28-pin QSOP SUPERCHIP SIDE SERIES-TERMINATED SUPERCHIP SIDE SERIES-TERMINATED SUPERCHIP SIDE SERIES-TERMINATED CAP-FILTERED; R3 PULL-UP SUPERCHIP SIDE SERIES-TERMINATED CAP-FILTERED; R3 PULL-UP SUPERCHIP SIDE SERIES-TERMINATED CAP-FILTERED; R3 PULL-UP CAP-FILTERED; R1 PULL-UP CAP-FILTERED; R1 PULL-UP SUPERCHIP SIDE SERIES-TERMINATED SUPERCHIP SIDE SERIES-TERMINATED CAP-FILTERED; R1 PULL-UP CONNECTOR SIDE SERIES-TERMINATED CONNECTOR SIDE SERIES-TERMINATED CONNECTOR SIDE SERIES-TERMINATED CONNECTOR SIDE SERIES-TERMINATED GND CONNECTOR SIDE SERIES-TERMINATED VCC CONNECTOR SIDE SERIES-TERMINATED CONNECTOR SIDE SERIES-TERMINATED CONNECTOR SIDE SERIES-TERMINATED CAP-FILTERED; R3 PULL-UP CONNECTOR SIDE SERIES-TERMINATED CAP-FILTERED; R3 PULL-UP SUPERCHIP SIDE SERIES-TERMINATED SUPERCHIP SIDE SERIES-TERMINATED STANDARD VALUES Product R1 (Ω) R2 (Ω) R3 (Ω) C (pF) PACS1284-02 2.2k 2.2k 220 PACS1284-04 4.7k 4.7k 180 PART NUMBERING INFORMATION Pins Package Standard FInish Lead-free Finish Ordering Part Number1 Part Marking Ordering Part Number1 Part Marking QSOP PACS1284-02Q PACS128402Q PACS1284-02QR PACS128402QR QSOP PACS1284-04Q PACS128404Q PACS1284-04QR PACS128404QR

© 2004 California Micro Devices Corp. All rights reserved. 06/07/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲Tel: 408.263.3214 Fax: 408.263.7846 www.calmicro.com PACS1284 Specifications Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified. Note 2: Guaranteed by design. Note 3: ESD contact discharge between pin 22 (GND) and pins 1, 2, 8, 10, 12, 15, 16, 17, 18, 19, 21, 23, 24, 25, 26, 27, & 28 (one at a time, all other I/O pins open), pin 20=5V; pin 22=GND ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS VCC Voltage 6.0 V Input Voltage Range, no clamping -6.0 to 6.0 V Storage Temperature Range -65 to +150 Power Dissipation per Resistor 100 mW Package Power Dissipation 1.00 W STANDARD OPERATING CONDITIONS PARAMETER RATING UNITS VCC Voltage 5.0 V Operating Temperature 0 to +70 ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS TOLR Absolute Resistance Tolerance (R1, R2, R3) Measured at TA=25°C ±10 TOLC Absolute Capacitance Tolerance Measured at 1MHz, 2.5VDC, TA=25°C ±20 ILEAK Leakage current to GND Measured at 5.0VDC, TA=25°C µA VESD Peak Discharge Voltage at any I/O Per MIL-STD-883, Method 3015 (HBM); CDischarge=100pF; RDischarge=1.5KΩ; Notes 2,3 kV VESD In-System ESD Protection Per MIL-STD-883, Method 3015 (HBM); CDischarge=100pF; RDischarge=1.5KΩ; Notes 2,3 kV VESD In-System ESD Protection Per IEC 61000-4-2 Level 2; CDischarge=150pF; RDischarge=330Ω; Notes 2,3 kV VCL Clamping voltage under ESD discharge ESD applied to connector pin, mea- sured at corresponding input pin; +8kV discharge, Human Body Model Note 2 ±30 V

Application Information

Termination Considerations The IEEE 1284 specification requires both termination and EMI filtering on a total of 17 signal lines. Control and Status lines (8 in total) only require a pull-up resis- tor and a filter capacitor. The Data lines and Strobe also require a series termination resistor in addition to the pull-up resistors and filter capacitors. See Table 1, in conjunction with the schematic diagram on page 1. Interfacing to IEEE 1284 Connectors IEEE 1284 defines three interface connectors:

1284 A is a 25-pin DB series connector which is

the de facto PC standard for the host connection. 1284 B is a 36-pin, 0.085 inch centerline connector used on the peripheral device. 1284 C is a new 36-pin, 0.050 inch centerline con- nector which can be used for both host and periph- eral. Figure 2A shows a possible hook-up between the 1284-A connector on a PC motherboard and the PACS1284, illustrating how the pin configuration of the PACS1284 allows for easy interconnect between the two. The dotted I/O signals of the PACS1284 will typically be connected to a Super I/O chip on the motherboard. Figure 2B shows a possible hook-up between the 1284-B connector on a peripheral and the PACS1284. Figure 2C shows a possible hook-up between the 1284-C connector and the PACS1284. Figure 2. Example Connections of IEEE 1284 Connectors with PACS1284

© 2004 California Micro Devices Corp. All rights reserved. 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.calmicro.com 06/07/04 PACS1284 Application Information (continued) Table 2 provides the IEEE 1284 signal assignments for the three connectors, and example PACS1284 pin con- nections. When connecting a 1284-A host to a 1284-B periph- eral, the “Peripheral Logic High” signal is not used. Similarly, when a 1284-A host is connected to a 1284- C peripheral, the “Peripheral Logic High” and “Host Logic High” are not used. These two signals are optionally used to detect a “Power Off” or “Cable Dis- connect” state for host and peripheral, respectively. Table 2: IEEE 1284 Connector Pinouts and PACS1284 Connection Guidelines PACS1284 PIN TYPE 1284-A 25-PIN DSUB 1284-B 36-PIN CHAMP 1284-C 36-PIN HIGH DENSITY SIGNAL PIN SIGNAL PIN SIGNAL PIN P-Port conn. side, series-terminated (16-19, 21, or 23-26) STROBE STROBE STROBE P-Port conn. side, series-terminated (16-19, 21, or 23-26) Data 1 Data 1 Data 1 P-Port conn. side, series-terminated (16-19, 21, or 23-26) Data 2 Data 2 Data 2 P-Port conn. side, series-terminated (16-19, 21, or 23-26) Data 3 Data 3 Data 3 P-Port conn. side, series-terminated (16-19, 21, or 23-26) Data 4 Data 4 Data 4 P-Port conn. side, series-terminated (16-19, 21, or 23-26) Data 5 Data 5 Data 5 P-Port conn. side, series-terminated (16-19, 21, or 23-26) Data 6 Data 6 Data 6 P-Port conn. side, series-terminated (16-19, 21, or 23-26) Data 7 Data 7 Data 7 P-Port conn. side, series-terminated (16-19, 21, or 23-26) Data 8 Data 8 Data 8 Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) ACK ACK ACK Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) BUSY BUSY BUSY Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) PError PError PError Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) Select Select Select Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) AUTOFD AUTOFD AUTOFD Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) FAULT FAULT FAULT Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) INIT INIT INIT Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) Selectin Selectin Selectin Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Not Defined Ground Not Defined Ground Not Defined Ground Not Defined Ground Logic Ground Ground Chassis GND Not Required Peripheral Logic Host Logic High

© 2004 California Micro Devices Corp. All rights reserved. 06/07/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲Tel: 408.263.3214 Fax: 408.263.7846 www.calmicro.com PACS1284 Mechanical Details QSOP Mechanical Specifications: PACS1284 devices are packaged in 28-pin QSOP packages. Dimensions are presented below. For complete information on the QSOP-28 package, see the California Micro Devices QSOP Package Infor- mation document. * This is an approximate amount which may vary. Package Dimensions for QSOP-28 PACKAGE DIMENSIONS Package QSOP (JEDEC name is SSOP) Pins Dimensions Millimeters Inches Min Max Min Max A 1.35 1.75 0.053 0.069 0.10 0.25 0.004 0.010 B 0.20 0.30 0.008 0.012 C 0.18 0.25 0.007 0.010 D 9.80 9.98 0.386 0.393 E 3.81 3.98 0.150 0.157 e

0.64 BSC

0.025 BSC

H 5.79 6.20 0.228 0.244 L 0.40 1.27 0.016 0.050 # per tube 50 pieces* # per tape and reel 2500 pieces Controlling Dimensions: inches Mechanical Package Diagrams E D H TOP VIEW L END VIEW C e B A SEATING PLANE SIDE VIEW Pin 1 Marking

Product Information

PACS1284 specifications and overview.

Summary

P/ACTIVE IEEE 1284 ECP/EPP TERMINATION NETWORK

Description

P/ACTIVE IEEE 1284 ECP/EPP TERMINATION NETWORK

Source title PACS1284 Datasheet(PDF) - California Micro Devices Corp

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