PACDT CALMIRCO | Alldatasheet
Document overview
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Technical content
Features
- Minimal ground bounce, crosstalk Stable 1% absolute tolerance elements 16 terminating lines per QSOP package Saves board space and reduces assembly cost Product Description High speed logic devices like HSTL (High Speed Transceiver Logic) demand unique, high speed bus terminations. The dual Thévenin termination network provides 16 terminating channels per package, and optimizes signal integrity by reducing reflections and ringing. The terminations are available in a range of standard values and are ideal for use in HSTL busses. As seen in the schematic, R1 is typically tied to V CC and serves as a pull-up resistor, while R2 functions as a pull- down resistor and is tied to ground (or the most negative supply voltage). In addition, the equivalent Thévenin
Applications
HSTL termination Thévenin termination ECL, TTL termination C1611100 resistance (R1 in parallel with R2) should match the impedance of the trace. Ground-bounce and crosstalk are virtually eliminated using a proprietary lead-frame which includes four direct ground connections to the die substrate, as well as four double-bonded connections to V CC, for a total of 8 commons. In addition, the resistors are trimmed to a tight absolute tolerance of 1% which provides tight impedance-matching and results in greatly reduced reflections. This unique proprietary design provides optimal signal integrity. SCHEMATI C CONFI GURATION VCC 123 4 23 22 21 17 20 19 18 16 15 14 13 1110 12 GND 47 94 94 001 50 100 100 002 56 112 112 003 68 136 136 004 CODER2 (Ω)R1(Ω)BUS IMPEDANCE (Ω) STANDARD PART ORDERIN G INF ORMATI ON Packa ge Orderin g Part Numbe r R Code Pin Style T ubes Tape & Reel Part Markin g 001 24 QSOP PAC001DTFQ/T PAC001DTFQ/R PAC001DTFQ 002 24 QSOP PAC002DTFQ/T PAC002DTFQ/R PAC002DTFQ 003 24 QSOP PAC003DTFQ/T PAC003DTFQ/R PAC003DTFQ 004 24 QSOP PAC004DTFQ/T PAC004DTFQ/R PAC004DTFQ STANDARD VAL UES Absolute Tolerance (R1 & R2) ±1% T CR ±100ppm Operating Temperature Range 0˚C to 70˚C Power Rating/Resistor 100mW Crosstalk (see Test Circuit) 30mV TYP Package 24 Pin QSOP
©2000 California Micro Devices Corp. All rights reserved. 11/19/2000 215 Topaz Street, Milpitas, California 95035 /G20 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com PACDT Degrees C Percent of Rated Power 0 70 125 150 100 L C D E H H Be A POWER DERATIN G CURVE MECHANI CAL SPECIFI CATIONS Lead Plating Tin-Lead L ead Material Copper Allo y Lead Coplanarity 0.004" (0.102mm) Substrate Material Silicon Body Material Molded Epoxy Flammability UL94V-0 PACKAGE DIMENSIONS , POWER DISSIPATION & ORDERING INFORMATIO N Package QSOP Pin s #1 6 20 24 28 mm inches mm inches mm inches mm inches MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX P D @ 70˚C 0 .75W 1.00W 1.00W 1.00W #/tube 99 pcs 56 pcs 56 pcs 56 pcs #/tape & reel 2,500 pcs 2,500 pcs 2,500 pcs 2,500 pcs A B C D E e H L