DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 17
Technical content
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715 www.protekanalog.com PA5322 100dB, 24-Bit, 192 kHz Stereo Audio CODEC 95248 Rev.0. 01/10 NOT FOR USE IN LIFE SUPPORT SYSTEMS
FEATURES
ADC and DAC: 100 dB dynamic range –90 dB THD 8 kHz to 200 kHz sampling frequency I 2S, left justified and right ju stified audio data format, 16- 24 bits 128, 192, 256, 384, 512, 768 and 1024 MCLK to LRCK ratios Independent ADC and DAC sampling frequencies and clocks Advanced multi-bit delta-sigma with low sensitivity to clock jitter Single power supply from 3V to 5.5V Hardware mode or SPI or 2-wire uC interface ADC: 4-to-1 MUX for analog inputs Direct 2 V RMS analog input ADC PGA from 11.5 dB to –11.5 dB in 0.5 dB per step Digital attenuation from 6.5 dB to 89.5 dB in 0.5 dB per step Optional high pass filter to remove analog DC offset DAC: Digital volume control from 0 dB to 120 dB attenuation in 0.5 dB per step, with soft ramp and zero crossing transition De-emphasis filter for 32, 44.1 and 48 kHz sampling frequencies Selectable fast and slow roll-off filters 95 dB dynamic range -85 dB THD+N Up to 200 kHz sampling frequency I 2S audio data format, 16-24 bits Single power supply 4.5 V to 5.5V
APPLICATIONS
DVD recorder Personal video recorder LCD and digital TVs Car audio AV receiver GENERAL DESCRIPTION PA5322 is a low cost high performance stereo audio CODEC. PA5322 performs stereo digital to analog conversion and analog to digital conversion continuously from 8 kHz to 200 kHz sampling frequency. PA5322 is ideal for high performance cost sensitive consumer audio applications. PA5322 can accept I²S; left justified and right justified serial audio data formats up to 24-bit word length. ADC and DAC operate on independent sampling frequencies and clocks. The device uses advanced multi-bit (∆-∑) delta-sigma modulation technique to convert data between digital and analog. The multi-bit (∆-∑) delta-sigma modulators makes the device with low sensitivity to clock jitter and low out of band noise. PA5322 can operate either in the hardware mod or the software mode. In the hardware mode, pin M0, M1, M2 and M3 set the operation of the device. In the software mode, PA5322 provides SPI or 2-wire micro-controller interfaces to configure its operations. BLOCK DIAGRAM
ORDERING INFORMATION
Temperature Range Package Part Number -40 to 85 °C SSOP-28 PA5322-T7 95248 ADCLRCK ADCSCLK ADCSDOUT/M3 ADCMCLK ADC Clock Manager Input MUX/MIX PGA ADC Serial Port µC Interface DAC Clock Manager DSP Output Amp Low Pass Filter Multilevel Sigma Delta DAC DAC Serial Port DACMCLK AIN3L/R AIN4L/R AIN2L/R 5KΩ AIN1L/R D ACLRCK DACSCLK DACSDIN AOUTL AOUTR 5KΩ Multilevel Sigma Delta ADC DSP CDATA/M1 CCLK/M2 CE/MO
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715 www.protekanalog.com PA5322 100dB, 24-Bit, 192 kHz Stereo Audio CODEC 95248 Rev.0. 01/10 NOT FOR USE IN LIFE SUPPORT SYSTEMS PIN CONFIGURATION PIN DESCRIPTIONS Pin Pin No. Pin Description ADC Pin. AIN1L/R 20, 19 Analog input 1 left and right channels AIN2L/R 23, 18 Analog input 2 left and right channels AIN3L/R 24, 17 Analog input 3 left and right channels AIN4L/R 25, 16 Analog input 4 left and right channels ADCMCLK 9 ADC master clock ADCSDOUT/M3 10 ADC PCM serial data output ADCLRCK 5 ADC PCM serial data left and right channel frame clock ADCSCLK 6 ADC PCM serial data bit clock DACMCLK 4 DAC master clock DACSDIN 1 DAC PCM serial data input DACLRCK 2 DAC PCM serial data left and right channel frame clock DACSCLK 3 DAC PCM serial data bit clock AOUTL/R 28, 27 DAC analog output left and right channels MUTE 14 Mute pin, active when detect 8K zero input in both left and right channels or users choose to mute the DAC DAC Pin. CE/M0 13 SPI uC interface chip select or 2-wire AD0 CCLK/M2 11 SPI or 2-wire (I2C compatible) uC interface clock CDATA/M1 12 SPI or 2-wire (I2C compatible) uC interface data Micro-Controller Pin or Hardware Mode Pin. VDDD/GNDD 7, 8 Digital power supply VDDA/GNDA 22, 21 Analog power supply ADCREFP/DACREFP 15, 26 Analog filtering pins AIN4L AOUTL VDDA DACREFP AOUTR GNDA ADCREFP AIN4R AIN2L AIN3L AIN1R AIN1L AIN3R AIN2R ADCMCLK ADCLRCK VDDD ADCSDOUT/M3 DACLRCK ADCSCLK GNDD DACSDIN MUTE DACSCLK CE/M0 CDATA/M1 CCLK/M2 DACMCLK 14 15
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715 www.protekanalog.com PA5322 100dB, 24-Bit, 192 kHz Stereo Audio CODEC 95248 Rev.0. 01/10 NOT FOR USE IN LIFE SUPPORT SYSTEMS In hardware mode, the mode pins function as follows: Pin Pin No. Pin Description M3 10 External pull-up (47k resistor) – ADC and DAC I2S serial data format External pull-down (47k resistor) – ADC and DAC LJ serial data format M2 11 0 – no de-emphasis 1 – 44.1 kHz de-emphasis filter on M1:M0 12, 13 00 – select AIN1 01 – select AIN2 10 – select AIN3 11 – select AIN4 ABSOLUTE MAXIMUM RATINGS Input Voltage ………………… MIN GND-0.3V MAX V DD+0.3V Operating Temperature………………..MIN -40°C MAX +85°C Storage Temperature…………………MIN -65°C MAX +150°C Note: Continuous operation at or beyond these conditions may permanently damage the device. RECOMMENDED OPERATING CONDITIONS Analog Supply Voltage ………………… MIN 3.0V MAX 5.5V Digital Supply Voltage ………………… MIN 3.0V MAX 5.5V ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS Test conditions are as the following unless otherwise specify: VDDA=+5.0V, VDDD=+5.0V, GNDA=0V, GNDD=0V, Ambient temperature=+25C, Fs=48 KHz, 96 KHz or 192 KHz, MCLK/LRCK=256. PARAMETER MIN TYP MAX UNIT ADC Performance Dynamic Range (Note 1) 85 95 100 dB THD+N -90 -86 -80 dB Channel Separation (1KHz) 80 85 90 dB Signal to Noise ratio 85 95 100 dB Inter-channel Gain Mismatch 0.1 dB Gain Error ±5 % Filter Frequency Response – Single Speed Pass-band 0 0.4535 Fs Stop-band 0.5465 Fs Pass-band Ripple ±0.05 dB Stop-band Attenuation 70 dB Filter Frequency Response – Double Speed Pass-band 0 0.4167 Fs Stop-band 0.5833 Fs Pass-band Ripple ±0.005 dB Stop-band Attenuation 70 dB Filter Frequency Response – Quad Speed Pass-band 0 0.2083 Fs Stop-band 0.7917 Fs Pass-band Ripple ±0.005 dB
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715 www.protekanalog.com PA5322 100dB, 24-Bit, 192 kHz Stereo Audio CODEC 95248 Rev.0. 01/10 NOT FOR USE IN LIFE SUPPORT SYSTEMS Stop-band Attenuation 70 dB Analog Input Full Scale Input Level (Note 2) 2*(VDDA/5) Vrms Input Impedance 10 KΩ Note 1. The value is measured used A-weighted filter. If not use, the result will decrease 2-3 dB. 2. PA5322 allows direct 2 VRMS inputs if external 5 K resistors are used in serial with the analog input pins. 1 VRMS inputs can directly apply to the analog input pins. DAC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS Test conditions are as the following unless otherwise specify: VDDA=+5.0V, VDDD=+5.0V, GNDA=0V, GNDD=0V, Ambient temperature=+25C, Fs=48 KHz, 96 KHz or 192 KHz, MCLK/LRCK=256. PARAMETER MIN TYP MAX UNIT DAC Performance Dynamic Range (Note 1) 85 98 100 dB THD+N -90 -82 -75 dB Channel Separation (1KHz) 80 85 90 dB Signal to Noise ratio 85 97 100 dB Inter-channel Gain Mismatch 0.05 dB Filter Frequency Response – Single Speed, Fast Roll-off Filter Pass-band 0 0.4535 Fs Stop-band 0.5465 Fs Pass-band Ripple ±0.05 dB Stop-band Attenuation 53 dB Filter Frequency Response – Double Speed, Fast Roll-off Filter Pass-band 0 0.4167 Fs Stop-band 0.5833 Fs Pass-band Ripple ±0.005 dB Stop-band Attenuation 56 dB Filter Frequency Response – Quad Speed, Fast Roll-off Filter Pass-band 0 0.2083 Fs Stop-band 0.7917 Fs Pass-band Ripple ±0.006 dB Stop-band Attenuation 50 dB Filter Frequency Response – Single Speed, Slow Roll-off Filter Pass-band 0 0.4167 Fs Stop-band 0.5833 Fs Pass-band Ripple ±0.05 dB Stop-band Attenuation 65 dB Filter Frequency Response – Double Speed, Slow Roll-off Filter Pass-band 0 0.2083 Fs Stop-band 0.7917 Fs Pass-band Ripple ±0.005 dB Stop-band Attenuation 85 dB Filter Frequency Response – Quad Speed, Slow Roll-off Filter
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715 www.protekanalog.com PA5322 100dB, 24-Bit, 192 kHz Stereo Audio CODEC 95248 Rev.0. 01/10 NOT FOR USE IN LIFE SUPPORT SYSTEMS Pass-band 0 0.1042 Fs Stop-band 0.8958 Fs Pass-band Ripple ±0.005 dB Stop-band Attenuation 55 dB De-emphasis Error at 1 KHz (Single Speed Mode Only) Fs = 32KHz Fs = 44.1KHz Fs = 48KHz 0.002 0.013 0.0009 dB Analog Output Full Scale Output Level 0.7*VDDA Vpp Output Impedance 120 Ω Load Resistance 2 KΩ Load Capacitance 100 PF Note 1. The value is measured used A-weighted filter. DC CHARACTERISTICS AND SPECIFICATIONS PARAMETER MIN TYP MAX UNIT Normal Operation Mode VDDD=VDDA=5.0V: VDDD Current VDDA Current VDDD=VDDA=3.3V: VDDD Current VDDA Current mA Power Down Mode VDDD=VDDA=5.0V: VDDD Current VDDA Current VDDD=VDDA=3.3V: VDDD Current VDDA Current TBD TBD TBD TBD mA Digital Voltage Level Input High-level Voltage 2.0 V Input Low-level Voltage 0.8 V Output High-level Voltage VDDD V Output Low-level Voltage 0 V Mute Pin Drive Capability 3.0 mA SERIAL AUDIO PORT SWITCHING SPECIFICATIONS PARAMETER Symbol MIN MAX UNIT MCLK frequency 51.2 MHz MCLK duty cycle 40 60 % LRCK frequency 200 KHz LRCK duty cycle 40 60 % SCLK frequency 26 MHz SCLK pulse width low TSCLKL 15 ns SCLK Pulse width high TSCLKH 15 ns
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715 www.protekanalog.com PA5322 100dB, 24-Bit, 192 kHz Stereo Audio CODEC 95248 Rev.0. 01/10 NOT FOR USE IN LIFE SUPPORT SYSTEMS SCLK falling to LRCK edge TSLR –10 10 ns SCLK falling to SDOUT valid TSDO 0 ns SDIN valid to SCLK rising setup time T SDIS 10 ns SCLK rising to SDIN hold time TSDIH 10 ns Serial Audio Port Timing SERIAL CONTROL PORT SWITCHING SPECIFICATIONS PARAMETER Symbol MIN MAX UNIT SPI Mode SPI_CLK clock frequency 10 MHz SPI_CLK edge to SPI_CSn falling TSPICS 5 ns SPI_CSn High Time Between transmissions TSPISH 500 ns SPI_CSn falling to SPI_CLK edge TSPISC 10 ns SPI_CLK low time TSPICL 45 ns SPI_CLK high time TSPICH 45 ns SPI_DIN to SPI_CLK rising setup time TSPIDS 10 ns SPI_CLK rising to DATA hold time TSPIDH 15 ns 2-wire Mode SCL Clock Frequency FSCL 100 KHz Bus Free Time Between Transmissions TTWID 4.7 us Start Condition Hold Time TTWSTH 4.0 us Clock Low time TTWCL 4.0 us Clock High Time TTWCH 4.0 us Setup Time for Repeated Start Condition TTWSTS 4.7 us SDA Hold Time from SCL Falling TTWDH 0.1 us SDA Setup time to SCL Rising TTWDS 100 ns Rise Time of SCL TTWR 25 us Fall Time SCL TTWF 25 ns LRCK Input SLCK Input SDOUT SDIN tslr tsdo tsclkh tsclkw tsdis tsdih tsclkl
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715 www.protekanalog.com PA5322 100dB, 24-Bit, 192 kHz Stereo Audio CODEC 95248 Rev.0. 01/10 NOT FOR USE IN LIFE SUPPORT SYSTEMS 5KΩ 5KΩ 5KΩ 5KΩ 5KΩ 5KΩ 5KΩ 5KΩ VDDD 0.1µF 10µF 47µH 7 VDDD GNDD
14 MUTE
A OUTL AOUTR DACREFP AIN4L AIN3L AIN2L AIN1L AIN1R AIN2R AIN3R AIN4R ADCREFP GNDA VDDA ANALOG RIGHT INPUTS ANALOG LEFT INPUTS 0.1µF10µF 47µH 4.7µF 4.7µF 4.7µF 4.7µF VDDA 0.1µF 10µF 4.7µF 4.7µF 4.7µF 4.7µF 0.1µF10µF Vout L/R TO EXTERNAL LPE SPI_DIN SPI_CLK SPI_CSn TSPICS TSPISC TSPIDS TSPIDH TSPICH TSPICL TSPISH Serial Control Port SPI Timing S P SDA SCL TTWSTS TTWSTH TTWCH TTWCL TTWDH TTWDS TTWF TTWR S TTWID Serial Control Port 2-wire Timing RECOMMENDED APPLICATION CIRCUIT
or quad speed modes. The ranges of the sampling frequency in these three modes are listed in Table1. address 0x07) set the speed mode. detection so ADC and DAC sampling frequencies can be completely independent. Table 1. Sampling Frequency and CLK/LRCK Ration each speed mode are also listed in Table1. The device always detects MCLK/LRCK ratio automatically. mode to the software mode, set SCPEn bit of Chip Control register (RAM address 0x00) to 1. and pins M1 and pin M0 select one of the four ADC analog inputs. Please refer to PIN DESCRIPTIONS section for detail settings. ramp feature can be turned off by setting ClickFree bit of DAC Control 1 register (RAM address 0x06) to 0. ADCLRCK, and DAC can power down by stopping DACMCLK or DACLRCK. configure the device through writing to internal configuration registers. SPI_CSn, SPI_CLK and SPI_DIN. In 2-wire mode, pin CE, CCLK and CDATA function as AD0, SCL and SDA. To select SPI mode, apply high to low transition signal to CE pin. Otherwise the device will operate in 2-wire interface mode. allow the external master SPI controller to access the internal registers, and thus control the operations of chip. data transfer, the SPI_DIN line carries data from the master to the slave; SPI_CSn is generated by the master to select PA5322. selected. Each write procedure contains 3 words, i.e. Chip Address plus R/W bit, internal register address and internal register data. word is transferred firstly. The transfer rate can be up to 10M bps.
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715 www.protekanalog.com PA5322 100dB, 24-Bit, 192 kHz Stereo Audio CODEC 95248 Rev.0. 01/10 NOT FOR USE IN LIFE SUPPORT SYSTEMS Chip Address 7 bits - 0010000 SPI_DIN SPI_CLK SPI_CSn Wb 567 8 91 4 1 5 1 6 17 22 23 RAM 8 bits Register Data 8 bits RAM = Register Address Mapping Figure1. SPI Configuration Interface Timing Diagram 2-WIRE 2-wire interface is a bi-directional serial bus that uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. The timing diagram for data transfer of this interface is given in Figure 2. Data are transmitted synchronously to SCL clock on the SDA line on a byte-by-byte basis. Each bit in a byte is sampled during SCL high with MSB bit being transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull the SDA low. The transfer rate of this interface can be up to 100k bps. 1-7 8 9 1-7 8 9 1-7 8 S P SDA SCL START ADDRESS R/W ACK DATA ACK DATA STOP Figure2. Complete Data Transfer 2-wire Interface A master controller initiates the transmission by sending a “start” signal, which is defined as a high-to-low transition at SDA while SCL is high. The first byte transferred is the slave address. It is a seven-bit chip address followed by a RW bit. The chip address must be 001000x, where x equals AD0 (pin CE). The RW bit indicates the slave data transfer direction. Once an acknowledge bit is received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified by the RW bit. The master can terminate the communication by generating a “stop” signal, which is defined as a low-to-high transition at SDA while SCL is high. In 2-wire interface mode, the registers can be written and read. The formats of “write” and “read” instructions are shown in Table 2 and Table 3. Please note that, to read data from a register, you must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the register. There are no acknowledge bit after data to be written or read, this is the only difference from the I2C protocol. Table 2 Write Data to Register in 2-wire Interface Mode Chip Address R/W Regist er Address Data to be written
001000 AD0 0 ACK RAM ACK DATA
Table 3 Read Data from Register in 2-wire Interface Mode Chip Address R/W Register Address
001000 AD0 0 ACK RAM
Chip Address R/W Data to be read
001000 AD0 1 ACK DATA
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715 www.protekanalog.com PA5322 100dB, 24-Bit, 192 kHz Stereo Audio CODEC 95248 Rev.0. 01/10 NOT FOR USE IN LIFE SUPPORT SYSTEMS CONFIGURATION REGISTER DEFINITION SPI and 2-wire configuration interface share the same registers because there is only one interface active at any time. There are total of 11 user programmable 8-bit registers in this device. These registers control the operations of ADC and DAC. External master controller can access these registers by using the slave address specified in RAM (Register Address Map) register as shown in Table 2. Table 2 Bit Content of Register Address Map Bit Name Bit Description RAM Address 7:0 The address of the register to be accessed: 0x00 – Chip Control (default) 0x01 – ADC Control 1 0x02 – ADC Control 2 0x03 – ADC Mute Control 0x04 – ADC Left Gain Control 0x05 – ADC Right Gain Control 0x06 – DAC Control 1 0x07 – DAC Control 2 0x08 – DAC Mute Control 0x09 – DAC Left Volume Control 0x0a – DAC Right Volume Control Chip Control – 0x00 Bit Name Bit Description SCPEn 7 0 – hardware mode (default) 1 – software (control port) mode Reserved 6:5 Reserved ADCPDN 4 0 – normal (default) 1 – ADC low power mode Reserved 3 Reserved DACPDN 2 0 – normal (default) 1 – DAC low power mode Reserved 1:0 Reserved ADC Control 1 – 0x01 Bit Name Bit Description AINMIX 7:3 00000 – AIN1 input to ADC (default) xxx1 – AIN1 input ADC xx1x – AIN2 input ADC x1xx – AIN3 input ADC 1xxx – AIN4 input ADC HPF 2 0 – ADC HPF enable (default) 1 – ADC HPF disable Reserved 1:0 Reserved ADC Control 2 – 0x02 Bit Name Bit Description ADCSampleRate 7:6 00 – ADC speed mode auto detect (default) 01 –single speed mode 10 –double speed mode 11 –quad speed mode ADCSPDataMode 5:3 000 – Left just ified, up to 24 bit data
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715 www.protekanalog.com PA5322 100dB, 24-Bit, 192 kHz Stereo Audio CODEC 95248 Rev.0. 01/10 NOT FOR USE IN LIFE SUPPORT SYSTEMS 001 – I2S, up to 24 bit data (default) 010 – Right justified, 16 bit data 011 – Reserved 100 – Reserved 101 – Right justified, 24 bit data 110 – Reserved 111 – Reserved SCLKRatio 2:1 00 – 32 01 – 48 10 – 64 (default) 11 – 128 Reserved 0 Reserved ADC Mute Control – 0x03 Bit Name Bit Description ADCMute 7 0 – normal (default) 1 – mute ADC digital output Reserved 6 Reserved ADCRampRate 5:4 These bits define ADC gain control ramp rate: 00 – 0.5 dB per 4 LRCK (default) 01 – 0.5 dB per 8 LRCK 10 – 0.5 dB per 16 LRCK 11 – 0.5 dB per 32 LRCK ADCL=R 3 0 – normal (default) 1 – both channel gain control is set by ADC Left Gain Control register ADCSoftRamp 2 ADC soft ramp at mute or gain change: 0 – Disabled 1 – Enabled (default) ADCZeroCrs 1 ADC mute or gain change at zero crossing signal level to minimize audible noise 0 – Disabled 1 – Enabled (default) Reserved 0 Reserved ADC Left Gain Control – 0x04 Bit Name Bit Description ADCGainL 7:0 1110 1000 – 6.0 dB gain (PGA) 1110 1001 – 6.5 dB gain (PGA) 1110 1010 – 7.0 dB gain (PGA) 1110 1011 – 7.5 dB gain (PGA) 1110 1100 – 8.0 dB gain (PGA) 1110 1101 – 8.5 dB gain (PGA) 1110 1110 – 9.0 dB gain (PGA) 1110 1111 – 9.5 dB gain (PGA) 1111 0000 – 10.0 dB gain (PGA) 1111 0001 – 10.5 dB gain (PGA) 1111 0010 – 11.0 dB gain (PGA) 1111 0011 – 11.5 dB gain (PGA) 1111 0100 – 6.0 dB attenuation (PGA) 1111 0101 – 5.5 dB attenuation (PGA) 1111 0110 – 5.0 dB attenuation (PGA) 1111 0111 – 4.5 dB attenuation (PGA) 1111 1000 – 4.0 dB attenuation (PGA) 1111 1001 – 3.5 dB attenuation (PGA) 1111 1010 – 3.0 dB attenuation (PGA)
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715 www.protekanalog.com PA5322 100dB, 24-Bit, 192 kHz Stereo Audio CODEC 95248 Rev.0. 01/10 NOT FOR USE IN LIFE SUPPORT SYSTEMS 1111 1011 – 2.5 dB attenuation (PGA) 1111 1100 – 2.0 dB attenuation (PGA) 1111 1101 – 1.5 dB attenuation (PGA) 1111 1110 – 1.0 dB attenuation (PGA) 1111 1111 – 0.5 dB attenuation (PGA) 0000 0000 – no gain or attenuation (default) 0000 0001 – 0.5 dB gain (PGA) 0000 0010 – 1.0 dB gain (PGA) 0000 0011 – 1.5 dB gain (PGA) 0000 0100 – 2.0 dB gain (PGA) 0000 0101 – 2.5 dB gain (PGA) 0000 0110 – 3.0 dB gain (PGA) 0000 0111 – 3.5 dB gain (PGA) 0000 1000 – 4.0 dB gain (PGA) 0000 1001 – 4.5 dB gain (PGA) 0000 1010 – 5.0 dB gain (PGA) 0000 1011 – 5.5 dB gain (PGA) 0000 1100 – 6.0 dB gain (PGA) 0000 1101 – 11.5 dB attenuation (PGA) 0000 1110 – 11.0 dB attenuation (PGA) 0000 1111 – 10.5 dB attenuation (PGA) 0001 0000 – 10.0 dB attenuation (PGA) 0001 0001 – 9.5 dB attenuation (PGA) 0001 0010 – 9.0 dB attenuation (PGA) 0001 0011 – 8.5 dB attenuation (PGA) 0001 0100 – 8.0 dB attenuation (PGA) 0001 0101 – 7.5 dB attenuation (PGA) 0001 0110 – 7.0 dB attenuation (PGA) 0001 0111 – 6.5 dB attenuation (PGA) 0001 1000 – 6.0 dB attenuation (PGA) 0001 1001 – 6.5 dB attenuation (6 dB PGA + digital attenuation) 0001 1010 – 7.0 dB attenuation (6 dB PGA + digital attenuation) …….. 1011 1111 – 89.5 dB attenuation (6 dB PGA + digital attenuation) ADC Right Gain Control – 0x05 Bit Name Bit Description ADCGainR 7:0 Same as ADCGainL settings for ADC right channel DAC Control 1 – 0x06 Bit Name Bit Description Reserved 7:6 Reserved ClickFree 5 0 – disable pop noise suppression power up and down 1 – enable pop noise suppression power up and down (default) SlowFilter 4 0 – fast filter roll off (default) 1 – slow filter roll off InvL InvR 3:2 0 – DAC analog output no phase inversion (default) 1 – DAC analog output 180 degree phase inversion Reserved 1:0 Reserved DAC Control 2 – 0x07 Bit Name Bit Description DACSampleRate 7:6 00 – DAC speed mode auto detect (default) 01 – single speed mode 10 – double speed mode 11 – quad speed mode DACSPDataMode 5:3 000 – Left justified, up to 24 bit data
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715 www.protekanalog.com PA5322 100dB, 24-Bit, 192 kHz Stereo Audio CODEC 95248 Rev.0. 01/10 NOT FOR USE IN LIFE SUPPORT SYSTEMS 001 – I2S, up to 24 bit data (default) 010 – Right justified, 16 bit data 011 – Reserved 100 – Reserved 101 – Right justified, 24 bit data 110 – Reserved 111 – Reserved DeEmphasisMode 2:1 00 – De-empha sis filter disabled (default) 01 – De-emphasis filter for Fs=32 KHz 10 – De-emphasis filter for Fs=44.1 KHz 11 – De-emphasis filter for Fs=48 KHz Reserved 0 Reserved DAC Mute Control – 0x08 Bit Name Bit Description DACMute 7 0 – un-mute analog outpu ts for both channels (default) 1 – mute analog outputs for both channels DACRampRate 6 These bits define volume control ramp rate: 00 – 0.5 dB per 4 LRCK (default) 01 – 0.5 dB per 8 LRCK 10 – 0.5 dB per 16 LRCK 11 – 0.5 dB per 32 LRCK AutoMute 5 Auto mute function: long period of zero inputs (8k audio samples) will mute the analog output. Any single non-zero input will un-mute. 0 – disable 1 – enable (default) DACL=R 4 0 – normal (default) 1 – both channel volume control is set by Left Volume Control register DACSoftRamp 3 Soft ramp at mute and volume change: 0 – Disabled 1 – Enabled (default) DACZeroCrs 1 Mute or volume change at zero cr ossing signal level to minimize audible noise 0 – Disabled 1 – Enabled (default) Reserved 0 Reserved DAC Left Volume Control – 0x09 Bit Name Bit Description DACVolumeL 7:0 Digital volume control setting attenuates the signal in 0.5 dB incremental from 0 to –120 dB. Max setting is –120 dB. 0000 0000 – no attenuation (default) 0000 0001 – 0.5 dB attenuation 0000 0010 – 1.0 dB attenuation 0000 0011 – 1.5 dB attenuation …….. DAC Right Volume Control – 0x0a Bit Name Bit Description DACVolumeR 7:0 Same as DACVolumeL settings for DAC right channel Digital Audio Interface The device provides three formats of serial audio data interface to the input of the DAC or output from the ADC through LRCK, SCLK and SDIN/SDOUT pins. The three formats are I2S, left justified and right justified. In the hardware mode, the formats are selected through pin M3.
(SDIN/SDOUT), SCLK and LRCK with the three formats is shown below through Figure 3 to Figure 5.
1 SCLK
Figure 3. I Figure 4. Left Justified Audio Data Format up to 24-bit Figure 5. Right Justified Audio Data Format up to 24-bit PA5322 allows direct 2 VRMS inputs if external 5 K resistors are used in serial with the analog input pins. Please refer to Figure 6. VRMS inputs can directly apply to the analog input pins. analog input pins to achieve mixing effects. Figure 6. ADC Left and Right Inputs independent control of left and right channel gains.
0x03). This feature minimizes the audible click and “zipper” noise as the gain values change. outputs go up gradually at the same rate set by DACRampRate bits. Please refer to Figure 7. The fade in and fade out feature can be set or disabled by DACSoftRamp bit in the same register. Figure 7. Fade In/Out Diagram detect long stream of zero input data.
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715 www.protekanalog.com PA5322 100dB, 24-Bit, 192 kHz Stereo Audio CODEC 95248 Rev.0. 01/10 NOT FOR USE IN LIFE SUPPORT SYSTEMS PACKAGE DIMENSIONS AND MEASUREMENTS 28-pin SSOP Outline Dimensions
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715 www.protekanalog.com PA5322 100dB, 24-Bit, 192 kHz Stereo Audio CODEC 95248 Rev.0. 01/10 NOT FOR USE IN LIFE SUPPORT SYSTEMS Life Support Policy PROTEK ANALOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF PROTEK DEVICES.