PA3427 UTC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 7
Technical content
UNISONIC TECHNOLOGIES CO., LTD PA3427 Preliminary CMOS IC www.unisonic.com.tw 1 of 7 Copyright © 2009 Unisonic Technologies Co., Ltd QW-R502-357.a 2W STEREO AUDIO AMPLIFIER DESCRIPTION The UTC PA3427 is a stereo audio speaker operated on a single 5V supply. It is capable of deliver ing 2W of output power per channel in Bridge-Tied Load mode into 4Ω load with less than 1% THD+N. Two terminals (GAIN0 and GAIN1) can configure and control the amplifier gain. In order to simplif y the design of audio system in the notebook application, the two m odes of Bridge-Tied Load (BTL) and Single-End (SE) mode drive the speakers and headphone respectively. The UTC PA3427 supports two input paths to choose two different amplitude AC signals through setting HP/ LINE pin. The UTC PA3427 is suitable for applications, such as stereo power amplifiers of notebooks or desktop computers, and multimedia monitors. FEATURES * Depop circuitry integrated * BTL gain: 6dB, 10dB, 15.6dB, 21.6dB SE gain: 4.1dB * Output power (THD+N:1%, supply voltage:5V) − 2.0W into a 4Ω load − 1.2W into a 8Ω load * With two mode :BTL and SE * Stereo input multiplexer * Fully differential input * Build-in gain control * PC-Beep input function * Thermal shutdown protection * Halogen Free HTSSOP-24 ORDERING INFORMATION Ordering Number Package Packing PA3427G -N24-R HTSSOP-24 Tape Reel PA3427G -N24-T HTSSOP-24 Tube
PA3427 Preliminary CMOS IC UNISONIC TECHNOLOGIES CO., LTD 2 of 7 www.unisonic.com.tw Q W - R 5 0 2 - 3 5 7 . a PIN CONFIGURATION GND/HS GAIN0 GAIN1 LOUT+ LLINEIN LPHIN PVDD RIN LOUT- LIN
24 GND/HS
14 PC-BEEP
13 GND/HS
PIN DESCRIPTION PIN NO PIN NAME I/O DESCRIPTION 1,12,13,24 GND/HS Gr ound, directly connected to thermal pad.
2 GAIN0 I Bit 0 of gain control
3 GAIN1 I Bit 1 of gain control
4 L OUT+ O Positive output for Left channel in BTL mode, + output in SE mode. 5 LLINEIN I Line input for left channel, selected when HP/ LINE pin is held low. 6 LHPIN I Left channel headphone input, selected when HP/LINE pin is held high. 7,18 PV DD I Supply voltage 8 R IN I Differential input for Right channel. AC ground for single-ended inputs. 9 L OUT- O Negative output for Left channel, and high impedance in SE mode. 10 L IN I Differential input for Left channel. AC ground for single-ended inputs.
11 BYPASS Tap to voltage divider for internal mid-supply bias generator
14 PC-BEEP I The input for PC-BEEP mode. PC-BEEP is enabled when at least eight continuous > 1-VPP (peak to peak) square waves is input to PC-BEEP pin. 15 SE/ BTL I Hold low for BTL mode, hold high for SE mode.
16 R OUT- O negative output for Right channel
17 HP/ LINE I MUX control input, hold high to select headphone inputs (6, 20), hold low
to select line inputs (5, 23).
19 V DD Analog V DD supply voltage
20 RHPIN I Right channel headphone input, selected when HP/ LINE pin is held high. 21 R OUT+ O Positive output for right channel in BTL mode, positive output in SE mode. 22 SHUTDOWN I In shutdown mode when held low, expect PC-BEEP remains active. 23 RLINEIN I Line input for Right channel, selected when HP/ LINE pin is held low.
PA3427 Preliminary CMOS IC UNISONIC TECHNOLOGIES CO., LTD 3 of 7 www.unisonic.com.tw Q W - R 5 0 2 - 3 5 7 . a BLOCK DIAGRAM
PA3427 Preliminary CMOS IC UNISONIC TECHNOLOGIES CO., LTD 4 of 7 www.unisonic.com.tw Q W - R 5 0 2 - 3 5 7 . a ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATINGS UNIT Supply Voltage V DD 6 V Power Dissipation (Ta=25°C) P D 2.7 W Junction Temperature T J 150 °C Operating Temperature T OPR -40 ~ +85 °C Storage Temperature T STG -65 ~ +150 °C Note: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. ELECTRICAL CHARACTERISTICS (unless otherwise specified) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DC ELECTRICAL CHARACTERISTICS (Ta=25°C) Supply voltage V DD 4.5 5 5.5 V High-Level Input Voltage V IH SE/ BTL , HP/ LINE , SHUTDOWN GAIN0, GAIN1 2 V Low-Level Input Voltage V IL SE/ BTL , HP/ LINE , SHUTDOWN GAIN0, GAIN1 0.8 V DC Differential Output Voltage V O(DIFF) V DD= 5V,Gain = 2V/V 5 50 mV VDD= 5V, Stereo BTL 7.5 13 mA Supply Current in Mute Mode I DD VDD= 5V, Stereo SE 4 7 mA IDD in Shutdown Mode I SD V DD= 5V 160 300 µA AC ELECTRICAL CHARACTERISTICS (Ta=25°C, VDD = 5.0V, RL = 4Ω) THD =1%, BTL, RL= 4Ω, G=-2V/V 2 W THD =1%, BTL, RL= 8Ω, G=-2V/V 1.25 W THD =10%, BTL, RL= 4Ω, G=-2V/V 2.5 W THD =10%, BTL,RL= 8Ω, G=-2V/V 1.6 W Output Power (Note) P OUT THD = 0.1%, SE,RL= 32Ω 85 mW POUT= 1.6W, BTL,RL= 4Ω,G=-2V/V 100 m% POUT= 1W, BTL, RL= 8Ω,G=-2V/V 60 m% POUT= 75mW, SE, RL= 32Ω 80 m% Total Harmonic Distortion Plus Noise THD+N VIN = 1V, RL= 10kΩ,SE 30 m% Max Output Power Bandwidth B W THD = 5% >15 kHz Power Supply Rejection PSRR F=1kHz,BTL,G=-2V/V, C BYP=1µF 68 dB Channel-to-Channel Output Separation f = 1kHz 80 dB Line/HP Input Separation 80 dB BTL Attenuation (SE mode) 85 dB Signal-to-Noise Ratio SNR P OUT= 500mW, BTL, G=2V/V 90 dB Output Noise Voltage E N BTL,G=2V/V, A Weighted filter 45 µVrms Note: Output power is measured at the output terminals of the IC at 1kHz.
PA3427 Preliminary CMOS IC UNISONIC TECHNOLOGIES CO., LTD 5 of 7 www.unisonic.com.tw Q W - R 5 0 2 - 3 5 7 . a TYPICAL APPLICATION CIRCUIT GND SHUTDOWN 22 VDD 19 PVDD 7.18 1, 12, 13, 24 LOUT- 3 LOUT+ 4 ROUT- 16 ROUT+ 21 Right MUX RLINEIN RHPIN 1µF 1µF Right Linein Negative Differential Input Right Hpin Negative Differential Input RIN 1µF Right Hpin/Linein Positive Differential Input 1µFPC-BEEP Input Signal PC-Beep14 BYPASS11 2.2µF GAIN0 GAIN1 SE/BTL HP/LINE 0.1µF LLINEIN LHPIN LIN 1µF 1µF Left Linein Negative Differential Input Left Hpin Negative Differential Input Left Hpin/Linein Positive Differential Input 1µF 220µF VDD 220µF 1µF 10µF 100K 100K Gain/ MUX Control Depop Circuitry Power Management PC-Beep Left MUX Application Circuit Using Differential Inputs Note: 1µF ceramic capacitor must be placed much closely to the IC. For filtering lower frequency noise signals, a larger electrolytic capacitor of 10µF or greater should be placed as close as possible to the audio power amplifier.
PA3427 Preliminary CMOS IC UNISONIC TECHNOLOGIES CO., LTD 6 of 7 www.unisonic.com.tw Q W - R 5 0 2 - 3 5 7 . a TYPICAL APPLICATION CIRCUIT(Cont.) Application Circuit Using Single-Ended Inputs Note: 1µF ceramic capacitor should be placed as close as po ssible to the IC to filter the higher-frequency noise.
PA3427 Preliminary CMOS IC UNISONIC TECHNOLOGIES CO., LTD 7 of 7 www.unisonic.com.tw Q W - R 5 0 2 - 3 5 7 . a APPLICATION INFORMATION 1. Shutdown Mode Operating INPUT AMPLIFIER HP/ LINE SE/ BTL SHUTDOWN INPUT OUTPUT X X L X MUTE L L H LINE BTL L H H LINE SE H L H HEADPHONE BTL H H H HEADPHONE SE X: Don’t care L: Low H: High 2. Gain setting (VS Gain0, Gain1 and R I, SE/BTL) Gain setting is determined by GAIN0 and GAIN1. The gains listed in the next table are realized by changing the taps on the input resistors inside the amplifier which will cause the internal input impedance(R I) to be dependent on the gain setting as we can see listed in the next table. AV(dB) GAIN0 GAIN1 SE/ BTL R I (kΩ) 6 0 0 0 90 10 0 1 0 70 15.6 1 0 0 45 21.6 1 1 0 30
4.1 X X 1 -
X: Don’t care UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.