STP90NF03L_05 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuit
  • 4 Package mechanical data
  • 5 Revision history

N-channel 30V - 0.0056Ω -90A TO-220/I2PAK Low gate charge STripFET™ Power MOSFET General features ■ Optimal RDS(on) x Qg trade-off ■ Conduction losses reduced ■ Switching losses reduced

Description

This application specific Power Mosfet is the third generation of STMicroelectronics unique “Single Feature Size™” strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance.

Applications

■ Switching application Internal schematic diagram Type VDSS (@Tjmax) RDS(on) ID STP90NF03L 30V <0.0065 Ω 90A STP90NF03L-1 30V <0.0065 Ω 90A TO-220 I2PAK 1 2 3 Order codes Part number Marking Package Packaging STP90NF03L P90NF03L TO-220 Tube STB90NF03L-1 B90NF03L I 2PAK Tube

1 Electrical ratings

Table 1. Absolute maximum ratings

  1. Pulse width limited by safe operating area

Table 2. Thermal data

2 Electrical characteristics

Table 3. On/off states Table 4. Dynamic

  1. Pulsed: pulse duration=300µs, duty cycle 1.5%

Table 5. Switching times

Table 6. Source drain diode

  1. Pulse width limited by safe operating area
  2. Pulsed: pulse duration=300µs, duty cycle 1.5%

2.1 Electrical characteri stics (curves)

Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance

3 Test circuit

Figure 12. Switching times test circuit for Figure 13. Gate charge test circuit Figure 14. Test circuit for inductive load Figure 15. Unclamped Inductive load test Figure 16. Unclamped inductive wavefo rm Figure 17. Switching time waveform

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com

DIM. mm. inch A 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 D 15.25 15.75 0.60 0.620 E 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 F 1.23 1.32 0.048 0.052 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.094 0.107 L 13 14 0.511 0.551 L1 3.50 3.93 0.137 0.154 L20 16.40 0.645 L30 28.90 1.137 øP 3.75 3.85 0.147 0.151 Q 2.65 2.95 0.104 0.116 TO-220 MECHANICAL DATA

DIM. mm. inch A 4.40 4.60 0.173 0.181 A1 2.40 2.72 0.094 0.107 b 0.61 0.88 0.024 0.034 b1 1.14 1.70 0.044 0.066 c 0.49 0.70 0.019 0.027 c2 1.23 1.32 0.048 0.052 D 8.95 9.35 0.352 0.368 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 E 10 10.40 0.393 0.410 L 13 14 0.511 0.551 L1 3.50 3.93 0.137 0.154 L2 1.27 1.40 0.050 0.055 TO-262 (I2PAK) MECHANICAL DATA

5 Revision history

Table 7. Revision history