P9038

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Document overview

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• PDF pages: 18

Technical content

Features

• 4.5V to 6.9V input operating voltage range, supporting:
• USB or AC adapter
• USB dedicated charger port (DCP) detection
• WPC-1.2.2 compliant for A5 or A11-type coils
• Integrated, high-efficiency power stage with low RDS(ON)
• Integrated foreign object detection & current sense
• Excellent EMI performance eliminates need for EMI filter
• Supports up to 8W power transfer to the receiver
• Demodulates and Decodes Communication Packets from WPC-compliant Receivers
• I2C Interface for EEPROM access
• Programmable input over-voltage protection
• Programmable soft start
• Current limit and over-temperature protection
• -40° to +85°C temperature range
• 7 x 7 mm 56-VFQFPN package

Applications

• Furniture
• PC peripherals
• Rugged electronic gear
• Small appliances
• Battery-powered electronics

Description

The P9038 is a WPC-compliant Wireless Power Transmitter for A5 and A11 designs operating from 5V supplies conforming with WPC Specification 1.2.2. Operating in the WPC-compliant mode, the integrated full-bridge inverter supports 8W power transfer utilizing the P902x Receiver family, and ensures efficient switching with EMI/RFI emissions that are better than the requirements of the WPC specification. To safeguard the device and the system under fault conditions, the P9038 offers resistor programmable Foreign Object Detection, built-in Over-Current protection, and programmable Over-Voltage / Over-Temperature protection. This transmitter is extremely easy to use and provides a complete WPC-compliant solution with minimum external parts count, requiring significantly less board space and lower total solution cost than competing products. The P9038 is available in a compact 7 x 7 mm VFQFPN package, and it is rated for -40° to +85°C temperature range. Typical Application Circuit LDO5V LDO2P5V ADAPTOR DM DP WP P9038 LCTX VSNS_AVG IN SCL SDA REG_IN EN RESET LDO2P5V_IN GND RESET CIN CIN LDO5V LDO2P5V GPIO_0 - GPIO_6 CLDO5V COUT CLDO2P5V VO GPIO_6 SW1 BST1 CBST1 BST2 CSW2 SW2 CSW1 CBST2 GATE VBUS_SNS ISNSP_IN ISNSN_IN ISNS_AVG INV5V_IN DP DM CHPF CISNS_1 ISNS HPF CISNS_AVG OVP_SEL SHIELD1 SHIELD2 CVSNS_AVG GPIO_1 EEPROM RSHLD =10MO RGATE CGATE VSS VCC WP SCL SDA RSNS RFILT_P RFILT_N CFILT_N CFILT_P CFILT_CM EN

©2016 Integrated Device Technology, Inc. 2 P9038 August 1, 2016 Absolute Maximum Ratings Stresses above the ratings listed below (Table 1 and Table 2) can cause permanent damage to the P9038. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Table 1: Absolute Maximum Ratings Summary. (All voltages are referred to ground.) Table 2: Package Thermal Information 1,2,3 NOTES: 1. The maximum power dissipation is PD(MAX) = (TJ(MAX) - TA) / ΘJA where TJ(MAX) is 125°C. Exceeding the maximum allowable power dissipation will result in excessive die temperature, and the device will enter thermal shutdown. 2. This thermal rating was calculated on JEDEC 51 standard 4-layer board with dimensions 3" x 4.5" in still air conditions. 3. Actual thermal resistance is affected by PCB size, solder joint quality, layer count, copper thickness, air flow, altitude, and other unlisted variables. Table 3: ESD Information Pins Rating Units VBUS_SNS -0.3 to 27 V EN, IN, REG_IN, SW1, SW2, ISNSN_IN, ISNSP_IN -0.3 to 12.5 V GPIO_6:0, SCL, SDA, RESET, DP, DM, NC, NC1, NC2, NC3, SHIELD2, LDO5V, LDO2P5V_IN, INV5V_IN, VFOD_SNS, ISNS, HPF, OVP_SEL, ISNS_V -0.3 to 5.5 V BST1, BST2 -0.3 to SW+6 V GATE -0.3 to REG_IN+6 V GND, REFGND, PGND1, PGND2 +0.3 V SHIELD1 -0.3 to 8 V LDO2P5V -0.3 to 2.75 V Symbol Description Rating (VFQFPN) Units ΘJA Thermal Resistance Junction to Ambient 25.5 C/W ΘJC Thermal Resistance Junction to Case 8.6 C/W ΘJB Thermal Resistance Junction to Board 2.4 C/W TJ Operating Junction Temperature -40 to +125 C TA Ambient Operating Temperature -40 to +85 C TSTG Storage Temperature -55 to +150 C TLEAD Lead Temperature (soldering, 10s) +300 C Test Model Pins Ratings Units HBM All pins ±2000 V CDM All pins ±500 V

P9038 August 1, 2016 3 ©2016 Integrated Device Technology, Inc. Electrical Specifications Table Table 4: Device Characteristics VIN = 5V, EN = 0V, CIN = 40μF, Coil = A11, CS = 400nF, TA = -40° to +85°C, unless otherwise noted. Typical values are at 25°C. Symbol Description Con ditions Min Typ Max Units Input Supplies & UVLO VBUS Input Operating Range VBUS_MIN to OVP_Max 4.5 6.9 V IIN_REGIN Standby Input Current (no ping) After power-up sequence complete. No coil, no switching at SW1, SW2, LDO5V, LDO2P5V. REG_IN = 6.9V 81 2 m A Standby Input Current (pinging) After power-up sequence complete. Average including pinging. 15 mA Sleep Mode Input Current EN= REG_IN = 6.9V 600 uA IIN_VBUS_SNS VBUS_SNS Input Current VBUS_SNS = 6.9V 1 mA VREGIN_UVLO REGIN Under-Voltage Protection Trip Points Rising 4.1 V Falling 3.4 V Hysteresis 150 mV Full Bridge PWM Generators F SW Switching Frequency 110 205 kHz FSW LSB Switching Frequency Step Size 12.5 ns Duty4 Duty Cycle V REG = 4.5V-6.9V 10 50 90 % Full Bridge Inverter IHS_OCP_RNG Over-Current Protection Trip Point Range VIN = 5V, cycle-by-cycle protection, programmable range 31 5 A IHS_OCP_ACC Over-Current Protection Trip Point Accuracy VIN = 5V, OCP Setting = 5A -20 20 % Input OVP , Inrush Control, and Current Limit VBUS_OVP VBUS Over-Voltage Protection Trip Point VBUS rising, OVP_SEL pin grounded 6.7 7.15 V VBUS rising, OVP_SEL pin 220k 5% to GND 5.8 6.3 V VBUS rising, OVP_SEL pin floating 7.3 7.85 V Hysteresis 200 mV VREG_OVP REG_IN Over-Voltage Protection Trip Point VREG_IN rising 9.3 9.8 V TGATE_RISE GATE Voltage Rise Time VBUS = 5V, Gate cap = 4nF VGATE = 1V to VIN+4V 3.6 ms DGATE_FALL Delay from input OVP to GATE Voltage Pull-down VGATE Pull down Time, Gate cap = 4nF VGATE = VIN+4V to VIN 400 ns IGATE_LKG GATE Leakage VBUS_SNS = 0V, REG_IN = 5V, VGATE = 10V -1 +1 µA Input Average Current Sense

©2016 Integrated Device Technology, Inc. 4 P9038 August 1, 2016 ISENIR Input Range ISNSP_IN, ISNSN_IN REGIN -0.3V - REGIN +0.15V V ISENACC Current Sense Accuracy VREGIN = 4.5 to 7.2V, ISENSR = 1.5A, Note 1 +/- 3 % LDO2P5V3 VIN VIN VIN VIN VIN VIN VIN VOUT VOUT VOUT VOUT VOUT VOUT VOUT IOUT_MAX IOUT_MAX IOUT_MAX IOUT_MAX IOUT_MAX IOUT_MAX IOUT_MAX LDO5V3 VIN Input Voltage 4.5 6.9 V VOUT Output Voltage I LOAD = 10mA, REG_IN = 5.5 5 V IOUT_MAX Maximum Output Current 10 mA Thermal Shutdown TSD Thermal Shutdown Threshold Rising 140 °C Threshold Falling 110 °C EN VIH 1.1 V VIL 0.3 V IEN EN Input Current V EN = 6.9V 25 μA General Purpose Inputs / Outputs (GPIO) 5 VIH Input Threshold High 3.5 V VIL Input Threshold Low 1.5 V ILKG Input Leakage -1 +1 µA VOH Output Logic High I OH = -8mA 4 V VOL Output Logic Low I OL = 8mA 0.5 V RESET V IH Input Threshold High 3.5 V VIL Input Threshold Low 1.5 V ILKG Input Leakage -1 +1 µA DP/DM CHARGER DETECTION VDP_SRC VDM_SRC DP and DM Voltage Source 0.6 V DP and DM Voltage Source Output Source Current VDP or VDM between 0.5V and 0.7V 250 µA DP and DM Voltage Source Output Sink Current VDP or VDM at 2.2V 500 µA IDP_SINK IDM_SINK Current Sink 25 100 175 µA IDP_SRC Current Source 7 13 µA VDAT_REF Data Detect Voltage 0.25 0.4 V VDP/DM_LGCHI Logic High 2.0 V Symbol Description Con ditions Min Typ Max Units

P9038 August 1, 2016 5 ©2016 Integrated Device Technology, Inc. NOTES: 1. 10m 1% or better sense resistor is required to meet the FOD specification 2. This current is the sum of the input currents for REG_IN, IN, ISNSP_IN, ISNSN_IN, and EN_B. 3. 3.For internal use - do not externally load. 4. Guaranteed by Design. 5. Any of the GPIO pins is capable of sourcing 8mA. The GPIO connected to the ADC have a max operating input voltage of 2.4V to prevent saturation of the ADC. VDP/DM_LGCLO Logic Low 0.8 V RDP_DWN Pull-down Resistance 14.25 19.5 24.8 k CI Input Capacitance Dm pin, Switch Open 4.5 5 pF Dp pin, Switch Open 4.5 5 pF IILK Input Leakage Dm pin, Switch Open V = 5.0 -1 +1 μA Dp pin, Switch Open V = 5.0 -1+ 1 μA SCL, SDA (I2C Interface) fSCL_MSTR1 fSCL_MSTR1 fSCL_MSTR1 fSCL_MSTR1 fSCL_MSTR1 fSCL_MSTR1 fSCL_MSTR1 fSCL_MSTR2 fSCL_MSTR2 fSCL_MSTR2 fSCL_MSTR2 fSCL_MSTR2 fSCL_MSTR2 fSCL_MSTR2 fSCL_SLV Clock Frequency P9038 as Slave 0 400 kHz tHD,STA Hold Time (Repeated) for START Condition 0.6 µs tHD:DAT Data Hold Time I 2C-bus Devices 10 ns tLOW Clock Low Period 1.3 µs tHIGH Clock High Period 0.6 µs tSU:STA Set-up Time for Repeated START Condition 100 ns tBUF Bus Free Time between STOP and START Condition 1.3 µs C B Capacitive Load for each Bus Line 100 pF CBIN SCL, SDA Input Capacitance5 5p F VIL Input Threshold Low 0.4 V VIH Input Threshold High 1.4 V ILKG Input Leakage Current V = 0V & 5V -1.0 1.0 µA VOL Output Logic Low (SDA) I = 2mA 0.25 V Symbol Description Con ditions Min Typ Max Units

Figure 1. System Efficiency vs. Load Circuit Measured using the P9025AC-R-EVK V1.0 (receiver) and P9038-R-EVK V1.0 (transmitter) reference boards.

P9038 August 1, 2016 7 ©2016 Integrated Device Technology, Inc. Pin Configuration Pin Descriptions Pin # Name Type Function 1 GND I Signal Ground Connection. 2 NC – Do not connect. Internally connected. 3 GPIO6 I/O General Purpose Input/Output. 4 GPIO5 I/O General Purpose Input/Output. 5 GPIO4 I/O General Purpose Input/Output. 6 GPIO3 I/O General Purpose Input/Output. 7 GPIO2 I/O General Purpose Input/Output. 8 GPIO1 I/O General Purpose Input/Output. 9 GPIO0 I/O General Purpose Input/Output.

10 SCL I I

2C Clock. 11 SDA I/O I 2C Data. 12 DP I/O USB Data Positive Input. If not used, the pin can be floating. 13 DM I/O USB Data Negative Input. If not used, the pin can be floating. 14 RESET I Active-high Rese t Pin. Connect a 47KΩ to GND or tie directly to GND if not used. 15 VBUS_SNS I VBUS OVP sense point & provides bias for OVP circuitry. GPIO6 NC GND GND SW1 BST1 PGND1 EN REFGND REG_IN LDO2P5V_IN LDO2P5V IN IN GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 SCL SDA RESET VSNS_AVG ISNS_AVG PGND1 PGND1 DP DM LDO5V ISNSP_IN ISNSN_IN GATE PGND1 SW1 SW1 SW1 IN IN SW2 SW2 SW2 SW2 PGND2 PGND2 PGND2 BST2 PGND2 18171615 19 20 21 22 23 24 25 26 27 28 53545556 52 51 50 49 48 47 46 45 44 43 ISNS GND HPF SHIELD2 SHIELD1 VBUS_SNS INV5V_IN OVP_SEL EPAD

©2016 Integrated Device Technology, Inc. 8 P9038 August 1, 2016 16 EN I Active-low Enable Pin. Connect a 47K Ω to GND or tie directly to GND if chip is always enabled. 17 REFGND PWR Signal Ground Connection. Connect to AGND. 18 REG_IN I Input Voltage for the internal 5V linear regul ator. Connect a 1µF capacitor from this pin to GND. 19 LDO5V O 5V LDO Output. Connect a 1µF Capacitor from this pin to GND. 20 LOD2P5V O 2.5V LDO Output. Connect a 1µF Capacitor from this pin to GND. 21 LDO2P5_IN PWR Input Voltage for the internal 2.5V linear regulator. This pin must be connected to LDO5V (pin 19). 22 INV5V_IN PWR Input power to the internal driver circui try. Connect a 1µF capacitor from this pin to GND. 23 OVP_SEL I Input over-voltage protecti on selection. When connected to GND, the nominal OVP threshold is set to 7.15V. When floating, 7.85V. Connecting the pin through a 220KΩ resistor to GND sets the OVP to 6.3V. 24 VSNS_AVG I Input voltage sense averaging pin. Conn ect a 6.8nF capacitor from this pin to AGND. 25 BST2 I Bootstrap pin for SW2 Bridge Node. Connect a 0.1uF capacitor from this pin to SW2 pin. 26,27,28,29 PGND2 GND Power Ground. 30,31,32,33 SW2 O H-Bridge Switch Node 2. 34,35,36,37 IN I Power Supply Input Vo ltage. Connect two 22µF capacitors from the pins to GND. 38,39,40,41 SW1 O H-Bridge Switch Node 1. 42,43,44,45 PGND1 GND Power Ground. 46 BST1 I Bootstrap pin for SW1 Bridge Node. Connect a 0.1uF capacitor from this pin to SW1 pin. 47 GATE O Output gate driver for the external FET. Connect a 6.8nF capacitor in parallel with 10MΩ from this pin to GND to configure soft-start. 48 ISNS_AVG I Input current sense averaging pin. Connect a 1nF capacitor from this pin to AGND. 49 ISNSN_IN I Input Current Sens e amplifier inverting Input. 50 ISNSP_IN I Input Current Sense amplifier non-inverting Input. 51 SHIELD1 O Shield output to guard DC voltage on HPF pin. Connect a 10M Ω resistor to GND. 52 HPF I High Pass Filter Input for Demodulator. Connect to an external high pass filter. 53 SHIELD2 O Shield output to guard DC volt age on HPF pin. Leave this pin floating. 54 GND I Signal Ground Connection. 55 ISNS O Coil current sense output, connec ted to external demodulation circuit. 56 GND I Signal Ground Connection. EP EP GND Exposed Pad. Connect to GND. Pin # Name Type Function

P9038 August 1, 2016 9 ©2016 Integrated Device Technology, Inc. Block Diagram Foreign Object Detection VBUS_SNS GATE OVP_SEL DIGITAL LDO2P5V REG_IN LDO5V SW1 SW2 BST2 BST1 PGND1 IN PGND2 SCL SDA RESET EPAD REFGND HPF ISNS DP DM RAM ROM INV5V_IN SHIELD1GPIO[6:0] SHIELD2 ISNSP_IN ISNSN_IN ISNS_AVG VBUS OVP & Inrush Control VSNS_AVG MCU ADC & Telemetry Demodulator Communication Bias & Reference Generators GPIO USB DPDM I/O I2C I/O Full Bridge Inverter EN

transmitter with a magnetic attraction. pins are both high and fast switching. REG_IN, a 1µF in parallel with 0.1µF capacitors are sufficient. power pins and power ground (PGND). described in subsequent sections of this document. Figure 2. Input Voltage Support Range (UVLO) The P9038 incorporates an integrated full-bridge inverter. internal MOSFETs are controlled.

27 V transient on the V

on the REG_IN and IN pins of the IC.

4.5 V Min

P9038 August 1, 2016 11 ©2016 Integrated Device Technology, Inc. The P9038 monitors the VBUS_SNS pin for over-voltage conditions and shuts off the OVP MOSFET to implement over-voltage protection. This OVP threshold can be configured via a single pin as shown in Table 6. Table 6: V BUS OVP Threshold Selection A secondary over voltage protection with a 9.5V threshold is implemented on REG_IN for cases where the OVP MOSFET is not used. If the REG_IN threshold is exceeded, the P9038 is disabled until the REG_IN voltage drops below 8V. Demodulation Power transfer from the P9038 to a WPC-compliant wireless power receiver, such as P9025AC-R, is controlled by the receiver. Communication packets are superimposed on the power link between the two devices, and are demodulated by the P9038. Further information about the WPC communication protocol can be found at the WPC website. Communication can be made more robust by running traces from Shield1 and Shield2 along both sides of the HPF trace. Analog-to-Digital Converter [ADC] The ADC is the main functional block which the MCU uses for IC operation, including Foreign Object Detection. The ADC also digitizes several internal and external voltages and currents for overall system control and improved demodulation functionality. USB DP/DM Functionality The P9038 implements USB D+/D- detection derived from the BCS1.2 specification. This determines whether the USB power source is a Standard Port (such as from a computer) or a dedicated USB power supply Charger Port. When a Charger Port is detected, the P9038 will set its GPIO-5 pin to a logic-high state to indicate power is from a Charger Port. This information may be used for any purpose, but has no direct effect on the actual operation of the P9038. Operation of the P9038 follows the commonly accepted practice in wireless charging to draw as much power as the source will allow. A Charger Port will provide its rated output, which is usually greater than the normal 500mA limit that could be typically expected from a Standard Port. Foreign Object Detection and Input Over-current Protection The P9038 makes precision measurements of the input voltage and input current, which are sampled by the internal ADC and processed in firmware for WPC 1.2.2 Foreign Object Detection [FOD] compliance. Two external pins, ISNS_AVG and VSNS_AVG, are provided for filtering the input current sense and input voltage sense signals respectively. The input current sense signal is generated differentially from the ISNSP_IN and ISNSN_IN pins. This input current sense signal is filtered by an internal 50k output resistor combined with an external capacitor on the ISNS_AVG pin. Input voltage measurements are also filtered by an internal 33k output resistor on the VSNS_AVG pin combined with an external capacitor on the VSNS_AVG pin. It is recommended to follow approximately the filter time constants used on the VSNS_AVG and ISNS_AVG signals as shown in the reference design to insure time alignment of the resulting measurements and accurate power calculation for FOD and other purposes. External Chip Reset and EN The P9038 can be externally reset by pulling the RESET pin to a logic high (above the VIH level). The RESET pin is a dedicated high-impedance active-high digital input, and its effect is similar to the automatic power-up reset function. Because of the internal low voltage monitoring/ reset scheme, the use of the external RESET pin is not mandatory. When RESET is HIGH, the micro-controller's registers are set to the default configuration. When the RESET pin is released to a LOW, the micro-controller starts loading and executing the firmware from the program memory. If the particular application requires the P9038 to be disabled, this can be accomplished with the EN pin. When the EN pin is pulled high, the device is shuts off and placed in a very low current condition.When EN is connected to logic LOW, the device will become active, and the micro-controller starts loading and executing the firmware from the program memory. The current into EN is approximately equal to: or close to zero if V(EN) is less than 2V. OVP_SEL Pin Connection OVP threshold 220kΩ to ground 6.3V Grounded 7.15V Floating 7.85V IEN VEN 2–

©2016 Integrated Device Technology, Inc. 12 P9038 August 1, 2016 System Overview For complete details of the WPC wireless power systems, refer to the WPC specifications and other materials at http://www.wirelesspowerconsortium.com. The P9038 requires a minimum number of external components for proper operation. The provided reference design schematic and Bill-of-Materials component list enable a fully WPC "Qi Compliant" system. In addition to providing required LED indications, this system also provides optional buzzer indications (that could be used with an external piezoelectric buzzer device), and an thermistor over-temperature limit function and optional buzzer indications that are available to drive an external piezeoelectric buzzer device. I2C Communication The P9038 includes an I2C block which can support either I2C Master or I2C Slave operation. After power-on-reset (POR), the P9038 will initially acts as an I2C Master for the purpose of downloading firmware from an external memory device, such as an EEPROM. The I 2C Master mode on the P9038 does not support multi-master mode, and it is important for system designers to avoid any bus master conflict until the P9038 has finished any firmware uploading and has released control of the bus as I 2C Master. After firmware downloaded from external memory is complete, and when the P9038 begins normal operation, the P9038 is configured by the standard firmware to be exclusively in I 2C Slave mode. For maximum flexibility, the P9038 tries to communicate with the first address on the EEPROM at 300kHz. If no acknowledge bit (ACK) is received, communication is attempted at the other addresses at 100kHz. If no EEPROM is present in the system, the P9038 will attempt to execute firmware from its internal ROM memory. EEPROM The P9038 EVK supports an external EEPROM memory chip, pre-programmed with a standard operating firmware that is automatically loaded when 5V power is applied. The P9038 uses I 2C master address 0x52 to access the EEPROM. The P9038 slave address is 0x39. If the standard firmware is not suitable for the application, custom EEPROM or internal factory programmed ROM configurations are possible. Please contact IDT Sales for more information regarding non-standard solution options. Overview of Standard GPIO Usage There are 7 GPIO's on the P9038 transmitter IC. All GPIOs are configured as inputs during the power-on startup process. Firmware will then reconfigure the GPIO as follows:

• GPIO-0: This pin is not used in the standard firmware and is configured as active-low output during normal operation.
• GPIO-1: This pin is used to dynamically manage the optimum configuration of the external communication demodulation circuit.
• GPIO-2: This pin is connected to an external thermistor circuit which is used by P9038 to determine an external over-temperature condition
• GPIO-3: During power-on, this pin is sampled by the internal ADC to determine the resistor option setting for the LED mode. In normal operation, this pin is configured as an output to drive the Green LED indication functions (see Table 10).
• GPIO-4: During power-on, this pin is sampled by the internal ADC to determine the resistor option setting for adjusting the FOD offset value. In normal operation, this pin is configured as an output to drive the optional external piezoelectric buzzer function.
• GPIO-5: This pin is configured as an output to indicate the result of the USB D+/D- port type detection. If the USB port type is a Charger Port, then the output will be set to active-high. Otherwise, the output is set to active-low
• GPIO-6: This pin is configured as an output to drive the Red LED functions (see Table 7). Table 7 lists how the red and green LEDs can be used to display information about the P9038's operating modes. This table also specifies how to configure the GPIO-3 optioning resistors to select the desired LED mode.

P9038 August 1, 2016 13 ©2016 Integrated Device Technology, Inc. one time during power-on to determine the LED configuration. value must be limited to not greater than 1Vdc. Figure 3. P9038 LED Resistor Optioning Note 1 - Voltage div ider on GPIO3 should use 1% resistors w ith parallel impedance approx imately 20k-50k. Note 2 - LED Select v oltage should be w ithin ±3% of listed v alue.

©2016 Integrated Device Technology, Inc. 14 P9038 August 1, 2016 Buzzer Function An optional buzzer feature is supported on GPIO4 which is able to drive directly a piezoelectric type transducer without amplification. As shown on the reference schematic, a series current limiting resistor should be included if a buzzer device is included. The buzzer signal is approximately a 2kHz square wave, and it is recommended to use a buzzer with a 2kHz resonant frequency for best results. Buzzer Action: Power Transfer Indication The P9038 supports audible notification when the device operation successfully reaches the Power Transfer state. The duration of the Power Transfer indication sound is approximately 200ms. Buzzer Action: Charge Complete Indication The P9038 supports audible notification when the receiver sends a "Charge Complete" during the power transfer state. If "Charge Complete" is sent as the very first packet before being in the power transfer state, there is no buzzer indication for this case. The duration of the “Charge Complete” indication sound is approximately 200ms. WPC TX-A5 and A11 Coils The P9038 SW output pins are connected to a series-resonance circuit comprised of a WPC Type-A5 or A11 coil and a series resonant capacitor, as shown on the reference design schematic. The coil serves as the primary winding in a loosely-coupled transformer, the secondary of which is the coil connected to the power receiver The power transmitter coil is mounted on a ferrite shield per the WPC specifications. Either a ground plane or grounded copper shielding can be added beneath the ferrite shield for a reduction in radiated electrical field emissions. The coil ground plane should be connected to the P9038 ground plane by a single trace. Resonance Capacitors The resonance capacitors must be C0G type dielectric and have a DC rating of at least 50V. The highest-efficiency combination is four 100nF in parallel to achieve the lowest ESR. PCB Layout Considerations For optimum device performance and lowest output phase noise, IDT recommends that customers copy the reference layout used in the P9038-R-EVK reference kit. More information and layout files can be found at: http://www.idt.com/P9038-R-EVK. Additional layout guidelines can be found in application note, AN-894 P9038 Layout Guidelines. Users are encouraged to read this document prior to starting a board design. Thermal Overload Protection The P9038 integrates thermal overload shutdown circuitry to prevent damage resulting from excessive thermal stress that may be encountered under fault conditions. This circuitry will shut down and reset the P9038 if the die temperature exceeds 140°C. To enable the best performance, it is important to ensure that the heat generated by the P9038 is dissipated into the PCB and then carried away into the environment. The package exposed pad must be soldered to the PCB, with multiple vias evenly distributed under the exposed pad and exiting the bottom side of the PCB. This improves heat flow away from the package and minimizes package thermal gradients. Special Notes Note 1: Unopened Dry Packaged Parts have a one year shelf life. Note 2: The HIC indicator card for newly opened Dry Packaged Parts should be checked. If there is any moisture content, the parts must be baked for minimum of 8 hours at 125°C within 24 hours of the assembly re-flow process.

P9038 August 1, 2016 15 ©2016 Integrated Device Technology, Inc. Reference Schematic (P9038-R-EVK) The reference schematic bill-of-materials can be found in the P9038-R-EVK reference board manual. DD CC BB AA LEDA LEDB Integrated Device Technology, Inc. THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY TO Integrated Device Technology, Inc. (IDT). USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION OF AN OFFICER OF IDT IS EXPRESSLY FORBIDDEN DO NOT MODIFY THE VOLTAGE SPECIFICATION OF CAPACITORS: C13,C18,C17,C15,C19,C20,C29,C30 P9038-R-EVK V1.1 OPTIONAL FOD Tuning Resistors Tx COIL SCL WP SDA ISNS LDO5V LDO2P5V GPIO0 GPIO5 GPIO4 GPIO2 GPIO3 RESET Title SizeDocument Number Rev Date: Sheetof 305-PD-15-02601 P9038-R-EVK V1.1 B

22 Wednesday, July 15, 2015

Date: Sheetof 305-PD-15-02601 P9038-R-EVK V1.1 B Date: Sheetof 305-PD-15-02601 P9038-R-EVK V1.1 B 6.8nF C11 6.8nF IO5 C27 0.1uF R11 15K IO4 C310.1uF C24 1uF 0402 P9038 SW2_b31 PGND2_a26 SW2_d33 SW2_c32 GPIO45 IN_a 34 IN_b 35 GPIO63 NC2 GPIO54 GPIO18 GPIO09 DP 12 PGND2_d29 SW2_a30 PGND2_b27 SCL 10 GPIO36 SDA 11 GPIO27 PGND2_c28 PGND1_a42 BST225 IN_c 36 IN_d 37 SW1_a38 SW1_b39 SW1_c40 DM 13 RESET14 VBUS_SNS15 EN 16 REFGND17 REG_IN 18 LDO5V19 LDO2P5V20 LDO2P5V_IN21 INV5V_IN22 OVP_SEL23 VSNS_AVG24 BST146 PGND1_d45 PGND1_c44 SW1_d41 PGND1_b43 GATE 47 ISNS_AVG48 ISNSN_IN 49 GND_a1 ISNSP_IN 50 SHIELD151 HPF52 SHIELD253 GND_c54 ISNS55 GND_b56 EPAD57 C26 1uF 0402 6.8nF C12 3.3nF 6.8nF C10 0.1uF R18 NP R27 C22 1uF R23 4.7K 6.8nF R20 NP C20 100nF1206 50V GND FDC88781 R17 1.5K R833 GND1 C30 100nF1206 50V R26 THER 1 2 /EN IO3 24AA64T-I/MNY VSS4A2 3 A0 1 A1 2VCC8 WP7 SCL6 SDA5 EPAD 0.1uF R24 4.7K WP C13 10uF IO0 C14 22nF C18 0.1uF LDO5V CDSU400B 0603 GREEN C29 100nF1206 50V R22 47K C15 10uF R10 10K R12 4.7K 6.8nF 6.5uH R25 10K C28 22nF IO2 C16 3.3nF 3.3nF 1nF C23 0.1uF C17 10uF HPFC 1nF 0.01 C21 0.1uF 10M SLD SLD VCC ID GND usb_micro_ab 5 6 C19 100nF1206 50V 22nF SCL R13 47K RED SDA R16 NP R14 4.7K RESET R19 10K

©2016 Integrated Device Technology, Inc. 16 P9038 August 1, 2016

P9038 August 1, 2016 17 ©2016 Integrated Device Technology, Inc.

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright ©2016 Integrated Device Technology, Inc.. All rights reserved. Corporate Headquarters

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Ordering Information

Revision History

Part/Order Number Marking Package Shipping Packaging Ambient Temperature P9038-RNDGI P9038-RNDGI 7 x 7 mm 56-VFQFPN Tray -40° to +85°C P9038-RNDGI8 P9038-RNDGI 7 x 7 mm 56-VFQFPN Tape and Reel -40° to +85°C Date Description of Change August 19, 2015 Initial release.