P9030-0NTGI8

P9030-0NTGI8 IDT | Alldatasheet

Document overview

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Technical content

Features

 Single-Chip 5W Solution for Wireless Power Consortium (WPC)-compliant power transmitter design A1  Conforms to WPC specification version 1.1 specifications  19±1V Operating Input Voltage  Integrated Half-Bridge Inverter  Closed-Loop Power Transfer Control between Base Station and Mobile Device  Demodulates and Decodes WPC-Compliant Message Packets  5V Regulated DC/DC Converter  Integrated RESET Function  Proprietary Back –Channel Communication  I2C Interface  Open-Drain LED Indicator Outputs  Over-Temperature/Voltage/Current Protection  Security and encryption up to 64 bits  Foreign Object Detection (FOD) for safety

Applications

 WPC-Compliant Wireless Charging Base Stations Package: 6x6-48 TQFN (See page 27) Ordering Information (See page 28)

Description

The IDTP9030 is a highly -integrated single -chip WPC -compliant wireless power transmitter IC for power transmitter design A1. The device operates with a 19V (±1V) adapter , and supplies an integrated half-bridge in verter for DC/AC conversion. It controls the transferred power by modulating the switching frequency of the half -bridge inverter from 110kHz to 205kHz at a fixed 50% duty cycle specified by the WPC specification for an “A1” transmitter. It contains logic circuits required to demodulate and decode WPC-compliant message packets sent by the mobile device to adjust the transferred power. The IDTP9030 is an intelligent device that periodically pings the area surrounding the base station to detect a mobile device for charging while minimizing idle power. Once the mobile device is detected and authenticated, the IDTP9030 continuously monitors all communications from the mobile device, and adjusts the transmitted power accordingly by varying the switching frequency of the half-bridge inverter. The IDTP9030 fea tures a proprietary back -channel communication mode which enables the device to communicate to IDT’s wirele ss power receiver solutions (e.g. IDTP9020). This feature enables additional layers of capabilities relative to standard WPC requirements. This device also features optional security and encryptions to securely authenticate the receiver before transferring power. This feature is available when an IDTP9020 is used for the receiver. The device includes over -temperature/voltage/current protection and a Foreign Object Detection (FOD) method to protect the base station and mobile device from overheating in the presence of a metallic foreign object. It manages fault conditions associated with power transfer and controls status LEDs to indicate operating modes. Typical Application Circuit Mobile Device Receiver Output Load Control System Power Pick-Up Comm Cont Mod Sensing Control Out PWR Base Station Transmitter(s) Input Power Control System Power Generation Comm Cont DeMod IN PWR Sensing Control Induction Load Reflection Comm Control Wireless Interface

Revision 1.0.2 2 © 2012 Integrated Device Technology, Inc. Figure 1. IDTP9030 Simplified Application Schematic Note 1: NPO/C0G-type ceramic capacitor. Note 2: For PCB layout, use single-point reference (“star” ground), refer to design schematic in Figure 15).

Revision 1.0.2 3 © 2012 Integrated Device Technology, Inc. cause permanent damage to the device. Functional operation of the IDTP9030 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions for extended periods may affect long-term reliability. Table 1. Absolute Maximum Ratings Summary. All voltages are referred to ground, unless otherwise noted. Table 2. Package Thermal Information result in excessive die temperature, and the device will enter thermal shutdown. Note 2: This thermal rating was calculated on JEDEC 51 standard 4-layer board with dimensions 3” x 4.5” in still air conditions. Note 3: Actual thermal resistance is affected by PCB size, solder joint quality, layer count, copper thickness, air flow, altitude, and other unlisted variables. (PTH) vias, from top to bottom sides of the PCB, is recommended for improving the overall thermal performance. Note 5: If the voltage at VIN is less than 24V, limit the voltages on , LX, SW to V(VIN)+0.3V and the voltage on BST to V(VIN)+5V.

Revision 1.0.2 4 © 2012 Integrated Device Technology, Inc. Table 3. ESD Information

Revision 1.0.2 5 © 2012 Integrated Device Technology, Inc. Figure 2. IDTP9030 Internal Functional Block Diagram

Revision 1.0.2 6 © 2012 Integrated Device Technology, Inc.

ELECTRICAL CHARACTERISTICS

= RESET = 0V, IN = REG_I N = BUCK5VT_IN = 19V. T A = -40 to +85 C, unless otherwise noted. Typical values are at 25C, unless otherwise noted. Table 4. Device Characteristics After power-up sequence complete.

Revision 1.0.2 7 © 2012 Integrated Device Technology, Inc. IDTP9030 Product Datasheet = RESET = 0V, IN = REG_IN = BUCK5VT_IN = 19V. T A = -40 to +85 C, unless otherwise noted. Typical values are at 25C, unless otherwise noted. Table 5. Device Characteristics, Continued

Revision 1.0.2 8 © 2012 Integrated Device Technology, Inc. = RESET = 0V, IN = REG_IN = BUCK5VT_IN = 19V. T A = -40 to +85 C, unless otherwise noted. Typical values are at 25C, unless otherwise noted. Table 6. Device Characteristics, Continued Note 1: BUCK5VT_IN, IN, REG_IN. These pins must be connected together at all times. Note 2: This current is the sum of the input currents for IN, REG_IN and BUCK5VT_IN. and Table 6 WPC “Qi” Compliance Bill of Materials. Note 5: Guaranteed by design.

Revision 1.0.2 9 © 2012 Integrated Device Technology, Inc.

Revision 1.0.2 10 © 2012 Integrated Device Technology, Inc. Table 7. IDTP9030 NTG48 Package Pin Functions by Pin Number ()

1 GPIO_6 I/O General purpose input/output 6

2 GPIO_5 I/O General purpose input/output 5

3 GPIO_4 I/O General purpose input/output 4

4 GPIO_3 I/O General purpose input/output 3

5 GPIO_2 I/O General purpose input/output 2

6 GPIO_1 I/O General purpose input/output 1

7 GPIO_0 I/O General purpose input/output 0

8 SCL I/O I2C clock

9 SDA I/O I2C data

10 XTAL/CLK_IN I Crystal or clock input. If not used, must be connected to GND. 11 XTAL/CLK_OUT O Crystal or clock output. If not used, must be left unconnected. and LDO5V, and a 100kΩ resistor to G D. pulled high. Tie to GND for stand-alone operation. 14 REFGND - Signal ground connection. Must be connected to AGND. connected to pins 37, 38, and 39. 16 LDO5V2 O A 1µF ceramic capacitor must be connected between this pin and GND. 17 LDO2P5V2 O 2.5V LDO output. A 1µF ceramic capacitor must be connected between this pin and GND. capacitor must be connected between this pin and GND. 19 BUCK5VT2 I Power and digital supply input to internal circuitry.

Revision 1.0.2 11 © 2012 Integrated Device Technology, Inc. 20 BST I Bootstrap pin for BUCK converter top switch gate drive supply. 21 AGND - Analog ground connection. Connect to signal ground. Must be connected to REFGND. 22 DGND - Digital ground connection. Must be connected to GND. 23 NC NC Not internally connected. this pin and PGND.. This pin must be connected to pins 37, 38, and 39. 25 BUCK5VT_SNS I Buck regulator feedback. Connect to the high side of the buck converter output capacitor. 26 LX O Switch Node of BUCK converter. Connects to one of the inductor’s terminals. 27 VOSNS I TX-A1 coil voltage sense input. 31 NC NC Not internally connected.

33 SW O

35 SW O

36 NC NC Not internally connected.

37 IN1 I

three pins (37, 38, 39) in parallel.

38 IN1 I

39 IN1 I

40 ISNS O ISNS output signal

Revision 1.0.2 12 © 2012 Integrated Device Technology, Inc.

41 HPF I High pass filter input

42 NC Internal connection, must be connected to GND.

43 GND - Ground

44 NC Internal connection, must be connected to GND. 45 NC Internal connection, must be connected to GND. 46 NC Internal connection, must be connected to GND. 47 NC Internal connection, must be connected to GND. 48 NC Internal connection, do not connect. performance, solder to a large copper pad embedded with a pattern of plated through -hole vias. Note 1: IN, REG_IN, BUCK5VT_IN. These pins must be connected together at all times. and Table 6 WPC “Qi” Compliance Bill of Materials.

Revision 1.0.2 14 © 2012 Integrated Device Technology, Inc. Figure 6. IDTP9030/IDTP9020 Simplified Systems Application Diagram

Revision 1.0.2 18 © 2012 Integrated Device Technology, Inc. In this phase, the IDT P9030 operates in a low power mode to determine if a potential receiver has been placed on the coil surface prior to the PING state. Twice a second, the IDT P9030 applies a brief ac signal to its coil and listens for a response. PING PHASE In this phase, the IDTP9030 applies a power signal at 175 kHz with a fixed 50% duty cycle and attempts to establish a communication link with a mobile device. Required packet(s) in PING: 1. Signal strength packet (0x01) The m obile device must send a Signal Strength Packet within a time period specified by the WPC , otherwise the power signal is terminated and the process repeats. The mobile device calculates the Signal S trength Packet value, which is an unsigned integer value between 0 -255, based on this formula: where U is a monitored variable (i.e. rectified voltage/current/power) and U max is a maximum value of that monitored variable expected during the digital ping phase at 175 kHz. If the IDTP9030 does not detect the start bit of the header byte of the Signal Strength P acket during the Ping Phase , it removes the power signal after a delay . If a signal strength packet is received, the IDT P9030 goes to the Identification and Configuration Phase. If t he IDT P9030 does not move to the Identification and Configuration Phase after receiving the signal strength packet, or if a packet othe r than a signal strength packet is received, then power is terminated. IDENTIFICATION AND CONFIGURATION (ID & Config) In this phase, the IDT P9030 tries to identify the mobile device and collects configuration information. Required packet(s) in ID & Config: 1. Identification packet (0x71) 2. Extended Identification packet (0x81)* 3. Configuration packet (0x51) * If Ext bit of 0x71 packet is set to 1. Also, the IDT P9030 must correctly receive the following sequence of packets without changing the operating point (175 kHz @ 50% duty cycle): 1. Identification Packet (0x71) 2. Extented Identification (0x81) 3. Up to 7 optional configuration Packe ts from the following set: a. Power Control Hold -Off Packet (0x06) b. Proprietary Packet (0x18 – 0xF2) c. Reserved Packet 4. Configuration Packet (0x51) If the IDTP9030 does not detect the start bit of the header byte of the next Packet in the sequence within a WPC - specified time after receiving the stop bit of the checksum byte of the preceding Signal Strength Packet, then the Power Signal is removed within after a delay . If a correct control packet in the above sequence is received late, or if control packets that ar e not in the sequence are received, the IDTP9030 removes the Power Signal after a delay. POWER TRANSFER PHASE In this phase, the IDT P9030 adapts the power transfer to the receiver based on control data it receives in control error packets. Required packet(s) in Power Transfer: 1. Control Error Packet (0x03) 2. Rectified Power Packet (0x04) For this purpose, the IDT P9030 may receive zero or more of the following Packets: 1. Control Error Packet (0x03) 2. Rectified Power Packet (0x04) 3. Charge Status Packet (0x05) 4. End Power Transfer Packet (0x02) 5. Any Proprietary Packet 6. Any reserved Packets If the IDTP9030 does not correctly receive the first Control Error Packet in time, it removes the Power Signal after a delay. Because Control Error Packets come at a regular interval, th e IDT P9030 expects a new Control Error Packet after receiving the stop bit of the checksum byte of the preceding Control Error Packet. If that does not

Revision 1.0.2 19 © 2012 Integrated Device Technology, Inc. IDTP9030 Product Datasheet happen, then the IDT P9030 removes the Power Signal. Similary, the IDT P9030 must receive a Rectified Powe r Packet within a WPC -specified time after receiving the stop bit of the checksum byte of the Configuration Packet (which was received earlier in the identification and configuration phase). Otherwise, it removes the Power Signal. Upon receiving a Control Error value, the IDT P9030 makes adjustments to its operating point after a delay to enable the Primary Coi l current to stabilize again after communication. If the IDTP9030 correctly receives a Packet that does not comply with the sequence, then it removes the Power Signal. FOREIGN OBJECT DETECTION (FOD) In addition to over -temperature protection, the IDT P9030 employs a proprietary FOD technique for safety which detects foreign objects placed on the base station. The FOD algorithm is multi -layered and issue s warnings depending on the severity of the warning. The FOD warning comes on during the PING phase indicating the presence of a smaller object and larger object respectively. The FOD warning is asserted during the Power Transfer phase, indicating presenc e of a foreign object. With this warning ON, the I DTP9030 stops power transfer, goes back to the PING phase, and stays there until the surface is cleared and the process starts over again.

Revision 1.0.2 20 © 2012 Integrated Device Technology, Inc.

2 VCC

Figure 15. IDTP9030 WPC “Qi” Compliance Schematic (See IDTP9030 valuation Kit User Manual for complete details)

Revision 1.0.2 21 © 2012 Integrated Device Technology, Inc. Table 6. IDTP9030 WPC “Qi” Compliance Bill of Materials

Revision 1.0.2 22 © 2012 Integrated Device Technology, Inc. attempted at the other addresses at 300kHz. conditions, and FOD warnings; see table 7. options for different buzzer configurations. development, and are currently not defined. charging and some possible fault conditions. Power Trans fer and Charge Complete state information. Figure 16. IDTP9030 LED Resistor Options. Blink Slow: 1s ON, 1s OFF, repeat. 800ms of silence corresponds with the LED being off.

Revision 1.0.2 23 © 2012 Integrated Device Technology, Inc. Table 7 – IDTP9030 LED Resistor Optioning (Not all options supported, shaded rows are for future development) . Standby Power Transfer Charge Complete Fault Condition LED1- Green ON BLINK SLOW ON OFF OFF LED2- Red ON OFF OFF ON BLINK FAST LED1- Green ON BLINK SLOW ON OFF OFF LED2- Red ON OFF OFF ON BLINK FAST LED1- Green ON BLINK SLOW ON OFF OFF LED2- Red ON OFF OFF ON BLINK FAST LED1- Green ON BLINK SLOW ON OFF OFF LED2- Red ON OFF OFF ON BLINK FAST LED1- Green ON BLINK SLOW ON OFF OFF LED2- Red ON OFF OFF ON BLINK FAST LED1- Green OFF BLINK SLOW ON OFF OFF LED2- Red OFF OFF OFF ON BLINK FAST LED1- Green OFF BLINK SLOW ON OFF OFF LED2- Red OFF OFF OFF ON BLINK FAST LED1- Green OFF BLINK SLOW ON OFF OFF LED2- Red OFF OFF OFF ON BLINK FAST LED1- Green OFF BLINK SLOW ON OFF OFF LED2- Red OFF OFF OFF ON BLINK FAST LED1- Green OFF BLINK SLOW ON OFF OFF LED2- Red OFF OFF OFF ON BLINK FAST R1-R8 are created using combination of two 1% resistors. Designates Future Option Pull Down Standby LEDs OFF plus Standby LEDs ON

9 Standby LEDs OFF plus

Operational StatusLED Control Option LED Select Resistor Value Description LED #/ Color Buzzer Function An optional buzzer feature is supported on GPIO4. The default configuration is an “AC” buzzer . The signal is created by toggli ng GPIO4 active -high/active-low at a 2KHz frequency. Buzzer Action: Power Transfer Indication The IDTP9030 supports audible notification when the device operation successfully reaches the Power Transfer state. The duration of the power transfer indic ation sound is 400ms. The latency between reaching the Power Transfer state and sounding the buzzer does not exceed 500ms. Additionally, the buzzer sound is concurrent within ±250ms of any change to the LED configuration indicating the start of power transfer. Buzzer Action: No Power Transfer due to Foreign Object Detected (FOD) When a major FOD situation is detected such that , for safety reasons, power transfer is not initiated, or that power transfer is terminated, the buzzer is sounded in a repeating sequence: For 30 seconds: 400ms ON, 800ms OFF, repeat Next 30 seconds: Off/silence (but no change to LED on/off patterns) The pattern is repeated while the error condition exists The buzzer is synchronized with the FOD LED such that the 400ms on tone corresponds with the Red LED illumination and 800ms off (no sound) corresponds with Red LED being off. Decoupling/Bulk Capacitors As with any high -performance mixed -signal IC, the IDTP9030 must be isolated from the system power supply noise to perform optimally. A decoupling capacitor of 0.1μF must be connected between each power supply and the PCB ground plane as close to these pins as possible. For optimum device performance, the decoupling capacitor must be mounted on the component side of the PCB. Avoid the use of vias in the decouplin g circuit. Additionally, medium value capacitors in the 22μF range must be used at the VIN input to minimize ripple current and voltage droop due to the large current requirements of the resonant half Half -Bridge driver . At least four 22μF

Revision 1.0.2 24 © 2012 Integrated Device Technology, Inc. capacitors must be used close to the IN pins of the device. Since the operating voltage is 18V to 20V, the value of the capacitors will decrease due to voltage derating characteristics. For example, a 22μF X7R 25V capacitor’s value is actually 6μF when operating at 20V. There must also be an 82μF to 100μF bulk capacitor connected at the node where the input voltage to the board is applied. A 25V Oscon -type or aluminum electrolytic must be connected between the input supply and ground as shown in Figure 20. Oscon capacitors have much lower ESR than aluminum electrolytic capacitors and will reduce voltage ripple. ADC Considerations The GPIO pins are connected internally to a successive approximation ADC with a multiplexed input. The GPIO pins that are connected to the AD C have limited input range, so attention must be paid to the maximum VIN (2.5V). 0.01μF decoupling capacitors can be added to the GPIO inputs to minimize noise. WPC TX-A1 Coil The SW pin connects to a series -resonance circuit comprising a WPC Type -A1 coil (~ 24H) and a s eries resonant capacitor (~100nF), as shown in Figures 8 and 9. The inductor serves as the primary coil in a loosely - coupled transformer, the secondary of which is the inductor connected to the power receiver (IDTP9020 or another receiver). The TX-A1 power transmitter coil is mounted on a ferrite shield to reduce EMI. The coil assembly can be mounted next to the IDTP9030. Either ground plane or grounded copper shielding can be added beneath the ferrite shield for added reduction in radiated electrical field emissions. The coil ground plane/shield must be connected to the IDTP9030 ground plane by a single trace. Resonance Capacitors The resonance capacitors must be C0 G type dielectric and have a DC rating to 250V. The highest -efficiency combination is three 33nF in parallel to get the lowest ESR. Using a single 100nF or two 47nF capacitors is also an option. The part numbers are shown in Table 6. Buck Converter The input capacitors (C IN) must be connected directly between the power VIN and power PGND pins. The output capacitor (C OUT) and power ground must be connected together to minimize any DC regulation errors caused by ground potential differences. The bootstrap pin requires a small capacitor; c onnect a 47nF bootstrap capacitor rated above 25V between the BST pin and the LX pin. The output -sense connection to the f eedback pins must be separ ated from any power trace. Connect the output- sense trace as close as possible to the load point to avoid additional load regulation errors. Sensing through a high- current load trace will degrade DC load regulation. The power traces, including PGND traces, the SW or OUT traces and the VIN trace must be kept short, direct and wide to allow large current flow. The inductor connection to the SW or OUT pins must be as short as possible. Use several via pads when routing between layers. LDOs Input Capacitor The input capacitors must be located as physically close as possible to the power pin ( LDO2P5V_IN) and power ground (GND). Ceramic capacitors are recommended for their higher current operation and small profile. Also, ceramic capacitors are inherently more capable than are tantalum capacitors to withstand input current surges from low impedance sources such as batteries used in portable devices. Typically, 10V - or 16V -rated capacitors are required. The recommended external components are shown in Table 10. Output Capacitor For proper load voltage regulation and operational stability, a capacitor is req uired on the output of each LDO (LDO2P5V and LDO5V) . The output capacitor must be placed as close to the device and power (PGND) pins as possible. Since the LDOs have been designed to function with very low ESR capacitors, a ceramic capacitor is recommended for best performance. PCB Layout Considerations - For optimum device performance and lowest output phase noise, the following guid elines must be observed. Please contac t IDT for Gerber files that contain the recommended board layout. - As for all switching power supplies, especially those providing high current and using high switching frequencies, layout is an important design step . If layout is not carefully done, the regulator could show

Revision 1.0.2 25 © 2012 Integrated Device Technology, Inc. instability as well as EMI problems. Therefore, use wide and short traces for high current paths. - The 0.1μF decoupling capacitors must be mounted on the component side of the board as close to the VDD pin as possible. Do not use vias between decoupling capacitors and VDD pins. Keep PCB traces to each VDD pin and to ground vias as short as possible. - To optimize board layout, place all components on the same side of the board and limit the use of vias. Route other signal traces away from the IDTP9030 . For example, use keepouts for signal traces routing on inner and bottom layers underneath the device. - The NQG48 6.0 mm x 6x0 mm x 75mm 48L package has an inner thermal pad which requires blind assembly. It is recommended that a more active flux solder paste be used such as Alpha OM -350 solder paste from Cookson Electronics (http://www.cooksonsemi.com). Please contact IDT for Gerber files that contain recomme nded solder stencil design. - The package center e xposed pad (EP) must be reliably soldered directly to the PCB. The center land pad on the PCB (set 1:1 with EP) must also be tied to the board ground plane, primarily to maximize thermal performance in the a pplication. The g round connection is best achi eved using a matrix of PTH vias embedded in the PCB center land pad for the NTG48. The PTH vias perform as thermal conduits to the ground plane (thermally, a heat spreader) as well as to the solder side of the board. There, these thermal vias embed in a copper fill having the same dimensions as the center land pad on the component side. Recommendations for the via finished hole -size and array pi tch are 0.3mm to 0.33mm and 1.3mm, respectively. - Layout and PCB d esign have a significant influence on the power dissipation capabilities of power management ICs. This is due to the fact that the surface mount packages used with these devices rely heavily on ther mally conductive traces or pads to transfer heat away from the package. Appropriate PC layout techniques must then be used to remove the heat due to device power dissipation. The following general guidelines will be helpful in designing a board layout for lowest thermal resistance: 1. PC board traces with large cros s sectional areas remove more heat. For optimum results, use large area PCB patterns with wide and heavy (2 oz.) copper traces, placed on the top layer of the PCB. 2. In cases where maximum heat dissipation is required, use double -sided copper planes connected with multiple vias. 3. Thermal vias are needed to provide a thermal path to the inner and/or bottom layers of the PCB to remove the heat generated by device power dissipation. 4. Where possible, increase the thermally conducting surface area(s) openly exposed to moving air, so that heat can be removed by convection (or forced air flow, if available). 5. Do not use solder mask or place silkscreen on the heat -dissipating traces/pads, as they increase the net thermal resistance of the mounted IC package. Power Dissipation/Thermal Requirements The IDTP9030 is offered in a TQFN-48L package. The maximum pow er dissipation capability is 2 W, limited by the die’s specified maximum operating junction temperature, Tj, of 125 °C. The junction temperature rise s with the device power dissipation based on the package thermal resistance. The package offers a typical thermal resistance, junction to ambient ( JA), of 31 °C/W when the PCB layout and surrounding devices are optimized as described in the PCB Layout Considerations section . The techniques as noted in the PCB Layout section need to be followed when designing the printed circuit board layout, as well a s the placement of the IDTP9030 IC package in proximity to other heat generating devices in a given application design. The am bient temperature around the power IC will also have an effect on the thermal limits of an application. The main factors influencing θ JA (in the order of decreasing influence) are PCB characteristics, die/package attach thermal pad size, and internal package construction. Board designers should keep in mind that the package thermal metric θJA is impacted by the characteristics of the PCB itself upon which the TQFN is mounted. For example, in a still air environment, as is often the case, a significant amo unt of the heat that is generated (60 - 85%) sinks into the PCB. Changing the design or configuration of the PCB changes impacts the overall thermal resistivity and, thus , the board’s heat sinking efficiency.

Revision 1.0.2 26 © 2012 Integrated Device Technology, Inc. Implementation of integrated circuits in low -profile and fine-pitch surface -mount packages typically requires special attention to power dissipation. Many system - dependant issues such as thermal coupling, airflow, added heat sinks, and convection surfaces, and the presence of other heat -generating components, affect the power-dissipation limits of a given component. Three basic approaches for enhancing thermal performance are listed below: 1. Improving the power dissipation capability of the PCB design 2. Improving the thermal coupling of the component to the PCB 3. Introducing airflow into the system First, the maximum power dissipation for a given situation must be calculated: PD(MAX) = (TJ(MAX) - TA)/θJA Where: PD(MAX) = Maximum Power Dissipation (W) θJA = Package Thermal Resistance (°C/W) TJ(MAX) = Maximum Device Junction Temperature (°C) TA = Ambient Temperature (°C) The maximum recommended junction temperature ( TJ(MAX)) for the IDTP9030 device is 150°C. The thermal resistance of the 48 -pin NQG package (NGQ48 ) is optimally θJA=30°C/W. Operation is specified to a maximum steady - state ambient temperature (T A) of 85 °C. Therefore, the maximum recommended power dissipation is: PD(Max) = (150°C - 85°C) / 30°C/W 2 Watt Thermal Overload Protection The IDTP9030 integrates thermal overload shutdown circuitry to prevent damage resulting from excessive thermal stress that may be encountered under fa ult conditions. This circuitry will shut down or reset the device if the die temperature exceeds 140 °C. To allow the maximum load current on each regulator and resonant transmitter, and to prevent thermal overload, it is important to ensure that the heat generated by the IDTP9030 is dissipated into the PCB. The packa ge exposed paddle must be soldered to the PCB, with multiple vias evenly distributed under the exposed paddle and exiting the bottom side of the PCB. This improves heat flow away from the package and minimizes package thermal gradients. Special Notes Note 1: Unopened Dry Packaged Parts have a one year shelf life. Note 2: The HIC indicator card for newly opened Dry Packaged Parts should be checked . If there is any moisture content, the parts must be baked for minimum of 8 hours at 125˚C within 24 hours of the assembly reflow process.

Revision 1.0.2 27 © 2012 Integrated Device Technology, Inc. PACKAGE OUTLINE DRAWING POD IN BOTTOM VIEW POD IN SIDE VIEW C0.35 DAP SIZE 4.5x4.5 DO NOT SCALE DRAWING PKP APPROVALS DRAWN CHECKED XX± XXX± DECIMAL .030 .05 12/04/09 SIZE C ANGULAR DATE ±1° TITLE UNLESS SPECIFIED TOLERANCES SHEET OF1 NT/NTG48 PACKAGE OUTLINE 6.0 x 6.0 mm BODY 0.4 mm PITCH TQFN PSC-4294 DRAWING No. REV PHONE: (408) 284-8200 DI T FAX: (408) 284-3572www.IDT.com VALLEY ROAD. SAN JOSE,

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affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an expre ss, written agreement by IDT. property of IDT or their respective third party owners. © Copyright 2012. All rights reserved. Table 8. Ordering Summary NUMBER MARKING PACKAGE AMBIENT TEMP.