P9028AC

Integrated Device Techn...

Dual-Mode WPC/PMA 5 Watt Wireless Power Receiver IC

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P9028AC IDT | Alldatasheet

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PDF pages: 38

Technical content

Features

 Single Chip Receiver (Rx) Solution  WPC v1.1.2 Compliant  PMA v1, v3 Pre-Release Compatible with Options  Advanced WPC v1.1.2 Foreign Object Detection (FOD)  Programmable FOD setting via external resistor and I2C registers  Programmable current limit via external resistor  Integrated Full-Bridge Synchronous Rectifier  Integrated 5V @ 1A LDO Regulator Output  Closed-loop power transfer control between TX and RX  I2C interface provides VRECT, Iout and switching frequency values  Open-Drain LED Indicator Output  Over-Temperature/Voltage/Current Protection

Applications

 WPC-Compliant and PMA-Compatible Wireless Chargers for Mobile Applications.  Cellular Mobile Phones  Tablets, DSC, DVC and Handhelds Introduction The P9028AC is an integrated single-chip, dual-mode WPC v1.1.2-compliant and PMA v1.0-compatible, wireless power receiver IC with advanced WPC v1.1.2 Foreign Object Detection (FOD). The device operates with an AC power signal from a resonant tank and converts it into a regulated 5V output voltage, which can be used to supply power to a mobile application. It includes a high efficiency Synchronous Full Bridge Rectifier and 5V tracking LDO output stage. The P9028AC dual-mode operation automatically detects the transmitter type and initiates either WPC or PMA AC modulation communication protocols with optimal efficiency. The device includes the control circuit required to modulate the load to transmit WPC-compliant or PMA-compatible message packets to the base station. It uses minimal external components to reduce overall solution area. The P9028AC employs advanced programmable WPC FOD techniques to detect foreign metallic objects placed on the transmitter base station derived from a transmitted and received power transfer algorithm. The P9028AC is available in a 36 ball 3mm X 3mm WLCSP or 32 pin 5mm X 5mm TQFN package. Typical Application Circuit Packages: WLCSP-36 6x6 balls (3.06mm x 2.9mm) (See page 33) TQFN-32 5x5mm (See page 35) Ordering information: (See page 38)

Revision 1.0.3 3 © 2015 Integrated Device Technology, Inc. Table 1. Absolute Maximum Ratings Summary. Table 2. Package Thermal Information.1,2,3,4 result in excessive die temperature, and the device will enter thermal shutdown. Note 2: This thermal rating was calculated on JEDEC 51 standard 4-layer board with dimensions 3” x 4.5” in still air conditions. Note 3: Actual thermal resistance is affected by PCB size, solder joint quality, layer count, copper thickness, air flow, altitude, and other unlisted variables. the 7 thermal balls to internal/external ground planes from top to bottom sides of the PCB, is recommended for improving the overall thermal performance. Table 3. ESD Information.

Revision 1.0.3 4 © 2015 Integrated Device Technology, Inc. VRECT=6V, COUT=1uF, CVRECT=20uF, VENഥ=0V, TA = 0C to 85C, unless otherwise noted. Typical values are at 25°C, unless otherwise noted. Table 4. Device Characteristics.

Revision 1.0.3 5 © 2015 Integrated Device Technology, Inc. VRECT=6V, COUT=1uF, CVRECT=20uF, VENഥ=0V, TA = 0C to 85C, unless otherwise noted. Typical values are at 25°C, unless otherwise noted. Table 4. Device Characteristics (Continued). Note 1: Guaranteed by design. Not 100% tested in production. Note 2: Guaranteed by design/simulation data.

Revision 1.0.3 10 © 2015 Integrated Device Technology, Inc. Table 5. WLCSP Pin Descriptions. (EOC) command will be sent. This pin has an internal pull down resistor. pin has an internal pull down resistor. B1 VRECT_B1 O Output of the full-wave rectifier. sets the current limit of the 5V LDO. EOC signal. This pin has an internal pull down resistor. thermal performance or to other pins to facilitate routing. C4 FOD2 I Foreign object detection 2 offset adjustment. D3 DNC1 DNC DO NOT connect to this pin, it is internally connected. This pin must be left floating. D4 ACM1 I AC Modulation input 1. E1 BST2 O Bootstrap output for high-side rectifier FET 2. E2 BST1 O Bootstrap output for high-side rectifier FET 1. E4 SCL I I 2C clock port. If not used, connect to ground. E5 ACM2 I AC Modulation input 2. E6 PGND1 - Power ground for modulation FETs. OC, OV, or OT event has occurred. and ground. Must be left unloaded. F4 AGND - Analog ground connection. F5 SDA I/O I 2C data port. If not used, connect to ground. F6 FOD1 I Foreign object detection 1 to select internal FOD1 settings.

Revision 1.0.3 12 © 2015 Integrated Device Technology, Inc. Table 6. TQFN Pin Descriptions. 2 DNC1 DNC DO NOT connect to this pin, it is internally connected. This pin must be left floating. 3 DNC2 DNC DO NOT connect to this pin, it is internally connected. This pin must be left floating. 4 BST2 O Bootstrap output for high-side rectifier FET 2. 5 BST1 O Bootstrap output for high-side rectifier FET 1. 6 AC1 I AC1 input to the Internal full-wave rectifier. 7 VRECT O Output of the full-wave rectifier. current limit of the 5V LDO. 9 SNS I LDO output sense pin. Connect to the OUT pin (TQFN only).

10 CHG_END/CS100 I

sent. This pin has an internal pull down resistor. or to improve thermal performance. or to improve thermal performance. mode when pulled high. This pin is pulled low inside the chip.

15 TEOP I

signal. This pin has an internal pull down resistor. or to improve thermal performance. 17 CLAMP2 I AC clamp input 2. 18 PGND2 - Power ground for the AC clamp FETs. 19 CLAMP1 I AC clamp input 1.

20 FOD2 I FOD2 adjustment

21 ACM1 I AC Modulation input 1. 22 PGND1 - Power ground for the full-wave rectifier. 23 ACM2 I AC Modulation input 2. or to improve thermal performance.

25 FOD1 I Select FOD settings

26 SDA I/O I 2C data port. If not used, connect to ground. 27 SCL I I 2C clock port. If not used, connect to ground. 28 AGND - Analog ground connection. ground. Must be left unloaded.

Revision 1.0.3 13 © 2015 Integrated Device Technology, Inc. Table 6. TQFN Pin Descriptions (Continued). 30 AC2 I AC2 input to the Internal full-wave rectifier. 31 PGND - Power ground for the full-wave rectifier. 32 STATതതതതതത O Status output. A low condition indi cates that power is being transferred.

Revision 1.0.3 15 © 2015 Integrated Device Technology, Inc. DESCRIPTION OF THE WIRELESS POWER CHARGING SYSTEM A wireless power charging system has a base station with one or more transmitters that make power available via DC-to-AC inverter(s) and transmit the power over a strongly-coupled inductor pair to a receiver in a mobile device. A WPC 1 transmitter may be a free-positioning or magnetically-guided type. PMA 2 supports only the magnetically-guided configuration. A free-positioning type of transmitter has one coil or an array of coils that gives limited spatial freedom to the end-user, whereas a magnetically-guided type of transmitter helps the end-user align the receiver to the transmitter with a magnetic attraction. The amount of power transferred to the mobile device is controlled by the receiver. The receiver sends communication packets to the transmitter to increase power, decrease power, or maintain the power level. The bit rate for RX-to-TX communication link is 2-kbps for WPC compliant receivers and variable for PMA compatible receivers. The communication is purely digital and communication 1’s and 0’s ride on top of the power link that exists between the two coils. THEORY OF OPERATION The P9028AC is a highly-integrated wireless power receiver IC for mobile devices. The device can transfer up to 5W from a wireless transmi tter to a load (e.g., a battery charger) in either WPC or PMA (Dual-mode) using near- field magnetic induction. Dual-mode operation is achieved using a single RX coil with fixed inductance for both WPC and PMA AC modulation for maximum efficiency. Note 1 - Refer to the WPC specification at http://www.wirelesspowerconsortium.com/ for the most current information. Note 2 – PMA members can download the most current PMA Receiver Interoperability Specification at http://www.powermatters.org. OVERVIEW The simplified internal block diagram of the P9028AC is shown in Figure 9. An external inductor and capacitor transfers energy from the transmitter's coil through the P9028AC's AC1 and AC2 pins to be full-wave-rectified and stored on a capacitor connected to VRECT. Until the voltage across the capacitor exceeds the threshold of the VIN_UVLO block, the rectific ation is performed by the body diodes of the Synchronous Full Bridge Rectifier FETs. After the internal biasing circuit is enabled, the Driver and Control block operates the MOSFET switches in the rectifier for increased efficiency. An internal ADC monitors the voltage at VRECT and the load current, the P9028AC sends instructions to the wireless power transmitter to increase or decrease the amount of power transferred or to terminate power transmission based on these readings. The voltage at the output of the 5V low- drop-out regulator and the internal temperature are also monitored to ensure proper operation. POWER CONTROL The voltage at VRECT and the current through the rectifier are sampled periodically and digitized by the ADC. The digital equivalents of the voltage and current are supplied to the internal control logic, which decides whether the loading conditions on VRECT indicate that a change in the operating point is required. If the load is heavy enough to bring the voltage at VRECT below its target, the transmitter is instructed to move its frequency lower, closer to resonance. If the voltage at VRECT is higher than its target, the transmitter is instructed to increase its frequency. To maximize efficiency, the voltage at VRECT is programmed to decrease as the LDO’s load current increases. WPC MODE CHARACTERISTICS STARTUP When a mobile device containing the P9028AC is placed on a WPC “Qi” charging pad, it responds to the transmitter’s “ping” signal by rectifying the AC power from the transmitter and storing it on a capacitor connected to VRECT. During the “ping” phase, the rectifier provides about 5V at the VRECT pin. An internal capacitor-less linear voltage regulator provides the supply voltage for the digital section to enable WPC communication. To increase the reliability of the communication, an internal load of about 15mA is connected to VRECT until the external load is large enough to support communication.

Revision 1.0.3 16 © 2015 Integrated Device Technology, Inc. The control loop of the P9028AC adjusts the rectifier voltage to 7V by sending error packets to the transmitter before it enables the 5V LDO. The LDO is enabled when the power transfer mode is initiated and the voltage at VRECT, the output of the full- wave synchronous rectifier, is 7V. The enable pin of the P9028AC can be asserted to shut down the LDO and send an “end power transfer” communication packet to the transmitter. POWER TRANSFER Once the “identification and configuration” phase is completed, the transmitter in itiates the power transfer mode. The P9028AC control circuit measures the rectifier voltage and sends error packets to the transmitter to adjust the rectifier voltage to the level required to maximize the efficiency of the linear regulator. SYNCHRONOUS RECTIFIER The efficiency of the full-bridge rectifier in the P9028AC is increased by implementing it as a synchronous rectifier. The rectifier comprises four self-driven switches that work in a full synchronous mode of operation when the load is higher than 300 mA. Below that threshold, the rectifier works in half-synchronous rectification mode. At power-up, when the voltage is below the UVLO threshold, the rectifier works by using the body diodes associated with the NMOS transistors. Charge pumps are used to drive the high-side NMOS switches. ADVANCED FOREIGN OBJECT DETECTION (FOD) WPC MODE When metallic objects are exposed to an alternating magnetic field, eddy currents cause such objects to heat up. Examples of parasitic metal objects as such are coins, keys, paperclips, etc. The amount of heating depends on the amplitude and frequency of the magnetic field coupled, as well as on the characteristics of the object such as its resistivity, size, and shape. In a wireless power transfer system, the heating manifests itself as a power loss, and therefore a reduced power transfer efficiency. Moreover, if no appropriate measures are taken, the heating could lead to unsafe situations if the objects reach high temperatures. WPC-compliant power transmitters and receivers need to also compensate for the power loss due to parasitic metals—i.e. metals that are neither part of the power transmitter, nor of the power receiver, but which dissipate power from magnetic field coupling during power transfer. The power transmitter uses both an input power and received power method to detect susceptible metallic objects near the interface surface. This method relies on Analog Ping and does not involve waking up the power receiver and starting digital communications. Typically zero or more Analog Pings precede Digital Pinging, which the power transmitter executes in an attempt to communicate with a possible receiver client device. The P9028AC employs advanced FOD techniques to detect foreign objects placed on the transmitter base station. The FOD algorithm includes values that are programmable through either the I 2C interface or OTP (One Time Programmable) bits. Programmability is necessary so that the FOD settings can be optimized to match the power transfer characteristics of each particular WPC system to include the power losses of the Tx and Rx coils, battery, shielding and case materials under no load to full load conditions. The values are based on the comparison of the received power against a reference power curve so that any foreign object can be sensed when the received power is different than the expected system power. The I 2C interface FOD option has 1 volatile setting that can accommodate the power transfer characteristics of one system . The OTP option has up to 10 non-volatile value settings for up to ten different systems. The 10 programmed OTP settings are externally selected through the FOD1 setting resistor value (see Figure 16 and 17) which selects the settings chosen for the particular system. A further enhancement is selected by the FOD2 offset resistor which adds a -300 to +300mW power offset to the values selected by the FOD1 resistor. There are three available options to set the advanced FOD programming and testing: Option 1: IDT completes all the FOD system tests and programming. Option 2: IDT completes the programming only with information provided by customer. Option 3: The customer performs the FOD system tests and programming. Please contact IDT for application note #814A which contains a detailed description of the advanced FOD programming and options available.

Revision 1.0.3 17 © 2015 Integrated Device Technology, Inc. to ground through the above mentioned internal FETs. which causes the Tx to Rx gain to decrease dramatically. Table 7. VRECT target range. Over-Voltage or Over-Temperature event has occured. See Electrical Specifications for threshold levels. floating, the device is active. the system and/or charging circuitry.

Revision 1.0.3 19 © 2015 Integrated Device Technology, Inc. proceeds to the power transfer phase. modulation capacitors are shown in Figure 14. Figure 14. Modulation components. system with a specific coil type.

Revision 1.0.3 20 © 2015 Integrated Device Technology, Inc. transmitter is waiting to detect any new, detectable object. Transfer, and End-of-Charge (EOC). Figure 15. Simplified PMA-State Machine. Table 8. Receiver Power Transfer Operation. recognized by the transmitter as a PMA capable device. the transmitter to receiver begins. wave synchronous rectifier, is more than 5.6V. until the transmitter removes the power.

Revision 1.0.3 21 © 2015 Integrated Device Technology, Inc. APPLICATIONS INFORMATION EXTERNAL COMPONENTS The P9028AC requires a minimum number of external components for proper operation, as indicated in Figure 16, 17 and 18 as well as Table 9, 10 and 11. LDO Input Capacitor (VRECT Capacitors) The LDO input capacitors (VRECT capacitors) should be located as close as possible to the VRECT pins, and ground (PGND). Ceramic capacitors are recommended for their lower ESR and small profile. See Figure 17 and Table 10 for values and type of capacitor. VDD Capacitor The P9028AC has an internal LDO regulator that must have a capacitor connected from the VDD pin to GND. This capacitor should be as close as possible to the VDD pin with a close GND connection. See Figure 17, 18 and Table 10, 11 for values and type of capacitor. Output Capacitor The output capacitor connection to the ground pin (PGND) should be made as short as practical for maximum device performance. Since the LDO has been designed to function with very low ESR capacitors, a ceramic capacitor is recommended for best performance. For better transient response increase the total amount of output capacitance. For 1A load steps, an output capacitance of at least 10µF is recommended. PCB LAYOUT CONSIDERATIONS - For optimum device performance and lowest output phase noise, the following guidelines should be observed. Please contact IDT Inc. for Gerber files that contain the recommended board layout and application note AN883, “P9028AC Layout Guidelines”. - An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Signal tr aces not related to the P9028AC should be routed away from the IC as much as possible to avoid blocking thermal dissipation paths from the IC to the PCB. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. - Layout and PCB design have a significant influence on the power dissipation capabilities of power management ICs because the surface mount packages used with these devices rely heavily on thermally conductive traces or pads to transfer heat away from the package. Appropriate PC layout techniques should be used to remove the heat due to device power dissipation. - The following general guidelines will be helpful in designing a board layout for lowest thermal resistance: 1. PC board traces with large cross-sectional areas remove more heat. For optimum results, use large-area PCB patterns with wide copper traces, placed on the uppermost side of the PCB. 2. In cases where maximum heat dissipation is required, use double-sided copper planes connected with multiple vias. 3. Thermal vias are needed to provide a thermal path to inner and/or bottom layers of the PCB to remove the heat generated by device power dissipation. POWER DISSIPATION AND THERMAL REQUIREMENTS The P9028AC is offered in a QFN-32 package which has a maximum power dissipation capability of about 1.9W and in a WLCSP package, the maximum power dissipation of which is determined by the number of thermal vias between the package and the printed circuit board. The maximum power dissipation of both packages is defined by the die’s specified maximum operating junction temperature, T J, of 125 °C. The junction temperature rises when the heat generated by the device’s power dissipation goes through the package thermal resistance. The QFN package offers a typical thermal resistance, junction to ambient ( Θ JA), of 35 OC/W when the PCB layout and surrounding devices are optimized as described in the PCB Layout Considerations section. The WLCSP package has a typical Θ JA of 70ºC/W with 7 thermal vias and 144 ºC/W with no thermal vias. Clearly, maximizing the thermal vias is highly recommended. The techniques as noted in the PCB layout section must be followed when designing the printed circuit board layout, as well as the placement of the P9028AC IC package in proximity to other heat-

Revision 1.0.3 22 © 2015 Integrated Device Technology, Inc. generating devices in a given application design. The ambient temperature around the power IC will also have an effect on the thermal limits of an application. The main factors influencing ΘJA (in the order of decreasing influence) are PCB characteristics, Die/package attach thermal pad size (QFN), thermal vias (WLCSP), and internal package construction. Board designers should keep in mind that the package thermal metric Θ JA is impacted by the characteristics of the PCB itself upon which the IC is mounted. For example, in a still-air environment, as is often the case, a significant amount of the heat generated (~85%) is absorbed by the PCB. Changing the design or configuration of the PCB changes the overall thermal resistivity and, thus, the board’s heat- sinking efficiency. The use of integrated circuits in low-profile and fine-pitch surface-mount packages requires special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat- generating components, affect the power-dissipation limits of a given component. Three basic approaches for enhancing thermal performance are listed below: 1. Improving the power dissipation capability of the PCB design 2. Improving the thermal coupling of the component to the PCB 3. Introducing airflow into the system First, the maximum power dissipation for a given situation should be calculated: P D(MAX) = (TJ(MAX) - TA)/θJA In which PD(MAX) = Maximum Power Dissipation θJA = Package Thermal Resistance (°C/W) TJ(MAX) = Maximum Device Junction Temperature (°C) TA = Ambient Temperature (°C) The maximum recommended junction temperature (T J(MAX)) for the P9028AC device is 125°C. The thermal resistance of the 32-pin QFN package (NBG32) is nominally θJA=35°C/W. Operation is specified to a maximum steady- state ambient temperature (T A) of 85°C. Therefore, the maximum recommended power dissipation is: PD(Max) = (125°C - 85°C) / 35°C/W ؆1.14 Watt. The thermal resistance for the WLCSP package (AWG36) is nominally θJA=70°C/W with 7 thermal vias, the maximum recommended power dissipation is: PD(Max) = (125°C - 85°C) / 70°C/W ؆0.57 Watt All the above-mentioned thermal resistances are the values found when the ICs are mounted on a standard board of the dimensions and characteristics specified by the JEDEC 51 standard. THERMAL OVERLOAD PROTECTION The P9028AC integrates thermal overload shutdown circuitry to prevent damage resulting from excessive thermal stress that may be encountered under fault conditions. This circuitry will shut down or reset the device if the die temperature exceeds 150°C. To allow the maximum load current on each regulator and the synchronous rectifier, and to prevent thermal overload, it is important to ensure that the heat generated by the P9028AC is dissipated into the PCB. End of Charge (EOC) In the event of thermal shutdown (150°C), EN, CHG_END or TEOP pins assertion the device turns off the LDO and continually sends End Of Power (EOP) packets in WPC or End Of Charge (EOC) in PMA until the transmitter removes the power and the rectifier voltage on the receiver side drops below the UVLO threshold. NC pins that are indicated as “Not Internally Connected” should be soldered to the PCB ground plane to improve thermal performance with multiple vias exiting the bottom side of the PCB. This improves heat flow away from the package and minimizes package thermal gradients. DNC pins that are indicated as “Internally connected” MUST BE LEFT FLOATING. Special Notes Note 1: Unopened Dry Packaged Parts have a one year shelf life. Note 2: The HIC indicator card for newly-opened Dry Packaged Parts should be checked. If there is any moisture content, the parts must be baked for a minimum of 8 hours at 125˚C within 24 hours of the assembly reflow process.

22 C MOD1, CMOD2 100nF

32 C CLAMP1, CCLAMP2 470nF

42 C BST1, CBST2 10nF

52 C OUT, C1 10F

61 C RECT 30F

71 C D 1800pf

82 C S 400nF

Note 1 – Contact the factory for suitable coil recommendations.

Revision 1.0.3 28 © 2015 Integrated Device Technology, Inc. The P9028AC has a one-time programmable I2C address that is set to default 0X25h. Table 12. READ Registers - VRECT voltage: VRECT=5 X ADC1<12:1> = [ADC1<12:1>] X 5 X [1.8V/2 0x41 REG1 3 RESERVED. R RESERVED. 0x41 REG1 2 RESERVED. R RESERVED. 0x41 REG1 1 RESERVED. R RESERVED. 0x41 REG1 0 RESERVED. R RESERVED.

Revision 1.0.3 29 © 2015 Integrated Device Technology, Inc. Table 13. READ Registers - Iout current: IOUT is read directly from IOUT = ADC2<12:1> = [ADC1<12:1>] X [1.8A/212]. 0X43 REG3 3 RESERVED. R RESERVED. 0X43 REG3 2 RESERVED. R RESERVED. 0X43 REG3 1 RESERVED. R RESERVED. 0x43 REG3 0 RESERVED. R RESERVED.

Revision 1.0.3 30 © 2015 Integrated Device Technology, Inc. Table 14. READ Registers - Frequency: ൌ 0X44 REG4 7 FREQ<10> R Frequency value (10 bits). 0X44 REG4 6 FREQ<9> R Frequency value (10 bits). 0X44 REG4 5 FREQ<8> R Frequency value (10 bits). 0X44 REG4 4 FREQ<7> R Frequency value (10 bits). 0X44 REG4 3 FREQ<6> R Frequency value (10 bits). 0X44 REG4 2 FREQ<5> R Frequency value (10 bits). 0X44 REG4 1 FREQ<4> R Frequency value (10 bits). 0X44 REG4 0 FREQ<3> R Frequency value (10 bits). 0X45 REG5 7 FREQ<2> R Frequency value (10 bits). 0X45 REG5 6 FREQ<1> R Frequency value (10 bits). 0X45 REG5 5 RESERVED. R RESERVED. 0X45 REG5 4 RESERVED. R RESERVED. 0X45 REG5 3 RESERVED. R RESERVED. 0X45 REG5 2 RESERVED. R RESERVED. 0X45 REG5 1 RESERVED. R RESERVED. 0X45 REG5 0 RESERVED. R RESERVED.

Revision 1.0.3 31 © 2015 Integrated Device Technology, Inc. Table 15. READ Registers – Miscellaneous functions. 1: LDO current limit exceeded. 0X47 REG7 0 RESERVED. R RESERVED. 0X48 REG8 7 CHARGE_COMPLETE R 0: No meaning. 0X48 REG8 6 RESERVED. R RESERVED. 0X48 REG8 5 RESERVED. R RESERVED. 0X48 REG8 4 RESERVED. R RESERVED. 0X48 REG8 3 RESERVED. R RESERVED. 0X48 REG8 2 RESERVED. R RESERVED. 0x54 REG20 [7:0] WPC_ID_B0 R Read OTP26 content. 0x55 REG21 [7:0] WPC_ID_B1 R Read OTP27 content. 0x56 REG22 [7:0] WPC_ID_B2 R Read OTP28 content. 0x57 REG23 [7:0] WPC_ID_B3 R Read OTP29 content. 0x58 REG24 [7:0] WPC_ID_B4 R Read OTP30 content. 0x59 REG25 [7:0] WPC_ID_B5 R Read OTP31 content. 0x5A REG26 [7:0] WPC_ID_B6 R Read OTP32 content. 0x5B REG27 [7:0] PMA_RXID_PRE R Read OTP33 content. 0x5C REG28 [7:0] PMA_RXID_MSG R Read OTP34 content. 0x5D REG29 [7:0] PMA_RXID_CER R Read OTP35 content. 0x5E REG30 [7:0] PMA_RXID_B0 R Read OTP36 content. 0x5F REG31 [7:0] PMA_RXID_B1 R Read OTP37 content. 0x60 REG32 [7:0] PMA_RXID_B2 R Read OTP38 content. 0x61 REG33 [7:0] PMA_RXID_B3 R Read OTP39 content. 0x62 REG34 [7:0] PMA_RXID_B4 R Read OTP40 content. 0x63 REG35 [7:0] PMA_RXID_B5 R Read OTP41 content. 0x64 REG36 [7:0] PMA_RXID_CRCB0 R Read OTP42 content. 0x65 REG37 [7:0] PMA_RXID_CRCB1 R Read OTP43 content.

REVISION HISTORY

1.0.0 Initial release

1.0.1 Page 23: Corrected TEOP pin name. Page 41: Removed TS pin register descriptions. 1.0.2 Page 3: Added Note: For the WLCSP (AWG36) package, connecting the 7 thermal balls to internal/external ground planes from top to bottom sides of the PCB, is recommended for improving the overall thermal performance. Page 23: Corrected part number P9028AC Page 29: Added information to the sentence. The thermal resistance for the WLCSP package (AWG36) is nominally θ JA=70°C/W with 7 thermal vias, the maximum recommended power dissipation is: 1.0.3 Pages 24, 25, 26, 27: Added 30k (R6) resistor from VRECT pin to ground to schematic and BOM. Resistor is needed to pass PMA3 certification, ping detection test. Added TQFN schematic and BOM.

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Product Information

P9028AC specifications and overview.

Summary

Dual-Mode WPC/PMA 5 Watt Wireless Power Receiver IC

Description

Dual-Mode WPC/PMA 5 Watt Wireless Power Receiver IC

Source title P9028AC Datasheet(PDF) - Integrated Device Technology

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