Microcontroller

P89V662

NXP Semiconductors

8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI Rev. 03-10 November 2008

Manufacturer: NXP Semiconductors

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Technical content

General description The P89V660/662/664 are 80C51 microcontrollers with 16 kB/32 kB/64 kB ﬂash and 512 B/1 kB/2 kB of data RAM. These devices are designed to be drop-in and software compatible replacements for the P89C660/662/664 devices. Both the In-System Programming (ISP) and In-Application Programming (IAP) boot codes are upward compatible. Additional features of the P89V660/662/664 devices when compared to the P89C660/662/664 devices are the inclusion of a secondary 100 kHz byte-wide I 2C-bus interface, an SPI interface, four addition I/O pins (Port 4), and the ability to erase code memory in 128-byte pages. The IAP capability combined with the 128-byte page size allows for efﬁcient use of the code memory for non-volatile data storage. 2. Features

2.1 Principal features

n Dual 100 kHz byte-wide I2C-bus interfaces n 128-byte page erase for efﬁcient use of code memory as non-volatile data storage n 0 MHz to 40 MHz operating frequency in 12x mode, 20 MHz in 6x mode n 16 kB/32 kB/64 kB of on-chip ﬂash user code memory with ISP and IAP n 512 B/1 kB/2 kB RAM n SPI (Serial Peripheral Interface) and enhanced UART n PCA (Programmable Counter Array) with PWM and Capture/Compare functions n Three 16-bit timers/counters n Four 8-bit I/O ports, one 4-bit I/O port n WatchDog Timer (WDT)

2.2 Additional features

n 30 ms page erase, 150 ms block erase n Support for 6-clock (default) or 12-clock mode selection via ISP or parallel programmer n PLCC44 and TQFP44 packages n Ten interrupt sources with four priority levels n Second DPTR register n Low EMI mode (ALE inhibit) n Power-down mode with external interrupt wake-up P89V660/662/664 8-bit 80C51 5 V low power 16 kB/32 kB/64 kB ﬂash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI Rev. 03 — 10 November 2008 Product data sheet

2.3 Comparison to the P89C660/662/664 devices

present on the P89C660/662/664 devices. n Dual I2C-bus interfaces. The P89V660/662/664 devices have two I2C-bus interfaces. The P89C660/662/664 devices have one. devices could only be switched using parallel programmer mode. Table 1. Ordering information

3.1 Ordering options

Table 2. Ordering options

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 4 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI 5. Pinning information

5.1 Pinning

Fig 2. PLCC44 pin conﬁguration P89V660/662/664 P1[5]/CEX2 P0[4]/AD4 P1[6]/SCL P0[5]/AD5 P1[7]/SDA P0[6]/AD6 RST P0[7]/AD7 P3[0]/RXD P4[1]/SDA_1/MISO P3[1]/TXD P2[7]/A15 P3[4]/T0/CEX3 P2[6]/A14 P3[5]/T1/CEX4 P2[5]/A13 P1[4]/CEX1 P1[3]/CEX0 XTAL2 P1[2]/ECI XTAL1 P1[1]/T2EX V SS P1[0]/T2 P4[0]/SCL_1/SCK P4[2]/MOSI P2[0]/A8 V DD P2[1]/A9 P0[0]/AD0 P2[2]/A10 P0[1]/AD1 P2[3]/A11 P0[2]/AD2 P2[4]/A12 P0[3]/AD3 002aab909 EA ALE/PROG PSEN P3[6]/WR P3[7]/RD P3[3]/INT1 P3[2]/INT0 P4[3]/SS

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 5 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI Fig 3. TQFP44 pin conﬁguration P89V660/662/664 P1[5]/CEX2 P0[4]/AD4 P1[6]/SCL P0[5]/AD5 P1[7]/SDA P0[6]/AD6 RST P0[7]/AD7 P3[0]/RXD P4[1]/SDA_1/MISO P3[1]/TXD P2[7]/A15 P3[4]/T0/CEX3 P2[6]/A14 P3[5]/T1/CEX4 P2[5]/A13 P1[4]/CEX1 P1[3]/CEX0 XTAL2 P1[2]/ECI XTAL1 P1[1]/T2EX V SS P1[0]/T2 P4[0]/SCL_1/SCK P4[2]/MOSI P2[0]/A8 V DD P2[1]/A9 P0[0]/AD0 P2[2]/A10 P0[1]/AD1 P2[3]/A11 P0[2]/AD2 P2[4]/A12 P0[3]/AD3 002aab910 EA ALE/PROG PSEN P3[6]/WR P3[7]/RD P3[3]/INT1 P3[2]/INT0 P4[3]/SS

5.2 Pin description

Table 3. Pin description P0[0] to P0[7] I/O Port 0:Port 0 is an 8-bit open-drain bidirectional I/O port. strong internal pull-ups when making the transition to ‘1’s. External pull-ups are required as a general purpose I/O port. I/O AD0 — Address/data bit 0. I/O AD1 — Address/data bit 1. I/O AD2 — Address/data bit 2. I/O AD3 — Address/data bit 3. I/O AD4 — Address/data bit 4. I/O AD5 — Address/data bit 5. I/O AD6 — Address/data bit 6. I/O AD7 — Address/data bit 7. pull-ups. P1[5], P1[6], P1[7] have high current drive of 16 mA. I/O CEX0 — Capture/compare external I/O for PCA Module 0.

IL) because of the internal pull-ups. Table 3. Pin description …continued

I INT0 — External interrupt 0 input. I T0 — External count input to Timer/Counter 0. I/O CEX3 — Capture/compare external I/O for PCA Module 3. O RD — External data memory read strobe. IL) because of the internal pull-ups. this pin for two machine cycles will reset the device.

modes other than normal working mode. The solution is to add a pull-up resistor of 3 kΩ to 50 kΩ to VDD , e.g., for ALE pin. [2] For 6-clock mode, ALE is emitted at1⁄3 of crystal frequency. the internal clock generator circuits. XTAL2 14 20 O Crystal 2: Output from the inverting oscillator ampliﬁer.

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 10 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI 6. Functional description

6.1 Special function registers

Remark: SFR accesses are restricted in the following ways:

User mustnot attempt to access any SFR locations not deﬁned.
Accesses to any deﬁned SFR locations must be strictly for the functions for the SFRs.
SFR bits labeled ‘-’, ‘0’ or ‘1’ canonly be written and read as follows: – ‘-’ Unless otherwise speciﬁed,must be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives. – ‘0’must be written with ‘0’, and will return a ‘0’ when read. – ‘1’must be written with ‘1’, and will return a ‘1’ when read.

**Table 4. Special function registers* indicates Special Function Registers (SFRs) that are bit addressable.**

Table 4. Special function registers

indicates Special Function Registers (SFRs) that are bit addressable.

purposes in future derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read.

indicates Special Function Registers (SFRs) that are bit addressable.

6.2 Memory organization

DATA

128 B of internal data memory space (00H:7FH) accessed via direct or indirect

IDATA Indirect Data. 256 B of internal data memory space (00H:FFH) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 B immediately above it.
SFR Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.
XDATA ‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the DPTR, R0, or R1. The P89V660/662/664 have 256/768/1792 B of on-chip XDATA memory.
CODE 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89V660/662/664 have 16/32/64 kB of on-chip Code memory.

6.2.1 Expanded data RAM addressing

The P89V660/662/664 have 512 B/1 kB/2 kB of RAM. SeeFigure4. ﬁrst bytes of external memory (addresses 000H to 0FFH/2FFH/6FFH). instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. With EXTRAM = 1, the expanded RAM can be accessed as in the following example. Table 5. AUXR - Auxiliary register (address 8EH) bit allocation

P3[6] and P3[7] as write and read timing signals. When EXTRAM = 0, MOVX @Ri and MOVX @DPTR will be similar to the standard 8051. Table 6. AUXR - Auxiliary register (address 8EH) bit description 7 to 2 - Reserved for future use. Should be set to ‘0’ by user programs. accesses internal XRAM with address speciﬁed in MOVX instruction. targets external data memory by default. active only during a MOVX or MOVC. Table 7. External data memoryRD, WR with EXTRAM bit

6.2.2 Dual data pointers

The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1 determines which of the two data pointers is accessed. When DPS = 0, DPTR0 is selected; when DPS = 1, DPTR1 is selected. Quickly switching between the two data pointers can be accomplished by a single INC instruction on AUXR1 (see Figure5). Fig 4. Internal and external data memory structure 000H 2FFH 00H FFH UPPER 128 B INTERNAL RAM LOWER 128 B INTERNAL RAM (INDIRECT AND DIRECT ADDRESSING) (INDIRECT ADDRESSING) (DIRECT ADDRESSING) SPECIAL FUNCTION REGISTERS (SFRs)80H FFH FFFFH 000H EXTERNAL DATA MEMORY EXTERNAL DATA MEMORY 2FFH 0000H EXTRAM = 0 EXTRAM = 1 EXPANDED RAM 0300H (INDIRECT ADDRESSING) (INDIRECT ADDRESSING) (INDIRECT ADDRESSING) FFFFH 80H 7FH 002aaa517 EXPANDED RAM 768 B

6.2.3 Reset

the contents of the on-chip RAM during power-up are indeterminate. capacitor and to VSS through an 8.2 kΩ resistor as shown inFigure6. condition. The POF ﬂag will remain active until cleared by software. the high byte of the address and 00H as the low byte. Table 8. AUXR1 - Auxiliary register 1 (address A2H) bit allocation Table 9. AUXR1 - Auxiliary register 1 (address A2H) bit description 7 to 4 - Reserved for future use. Should be set to ‘0’ by user programs. 3 GF2 General purpose user-deﬁned ﬂag. incrementing AUXR1, without interfering with other bits in the register. 1 - Reserved for future use. Should be set to ‘0’ by user programs. program. See text for details.

6.3 Flash memory

6.3.1 Flash organization

The P89V660/662/664 program memory consists of a 16/32/64 kB block for user code. The ﬂash can be read or written in bytes and can be erased in 128 pages. A chip erase function will erase the entire user code memory and its associated security bits. There are three methods of erasing or programming the ﬂash memory that may be used. First, the ﬂash may be programmed or erased in the end-user application by calling LOW-state routines through a common IAP entry point. Second, the on-chip ISP bootloader may be invoked. This ISP bootloader will, in turn, call LOW-state routines through the same common entry point that can be used by the end-user application. Third, the ﬂash may be programmed or erased using the parallel method by using a commercially available EPROM programmer which supports this device.

6.3.2 Features

Flash internal program memory with 128-byte page erase.
Internal Boot block, containing LOW-state IAP routines available to user code.
Boot vector allows user-provided ﬂash loader code to reside anywhere in the ﬂash memory space, providing ﬂexibility to the user.
Default loader providing ISP via the serial port, located in upper end of program memory.
Programming and erase over the full operating voltage range.
Read/Programming/Erase using ISP/IAP .
Programming with industry-standard commercial programmers.
10000 typical erase/program cycles for each byte.
100 year minimum data retention. Fig 6. Power-on reset circuit 002aaa543 VDD VDD 8.2 kΩ RST XTAL2 XTAL1 C 1 C 2 10 µF

6.3.3 Boot block

disabled on-the-ﬂy so that the upper 1 kB of user code is available to the user’s program.

6.3.4 Power-on reset code execution

boot loader entry point to perform ISP functions.

6.3.5 Hardware activation of the bootloader

execution of the user’s application code beginning at address 0000H.

6.3.6 ISP

be available to interface your application to an external circuit in order to use this feature.

6.3.7 Using ISP

Table 10. Default boot vector values and ISP entry points

record types will be added to indicate either commands or data for the ISP facility. Table 11. ISP hex record formats

00 Program User Code Memory

01 End of File (EOF), no operation

03 Miscellaneous Write Functions

04 Display Device Data or Blank Check

05 Miscellaneous Read Functions

06 Direct Load of Baud Rate

6.3.8 IAP method

Table 12. IAP function calls

6.4 I2C-bus interface

Bidirectional data transfer between masters and slaves Erase Status bit and Boot vectorInput parameters: R1 = 04H or 84H (WDT feed) DPL = don’t care DPH = don’t care Return parameter(s): ACC = 00 = pass A C C=! 0 0=f a i l Program Security bits Input parameters: R1 = 05H or 85H (WDT feed) DPL = 00H = security bit 1 DPL = 01H = security bit 2 DPL = 02H = security bit 3 Return parameter(s): ACC = 00 = pass A C C=! 0 0=f a i l Program Status bit, Boot vector, 6x/12x bit Input parameters: R1 = 06H or 86H (WDT feed) DPL = 00H = program Status bit DPL = 01H = program Boot vector DPL = 02H = 6x/12x bit ACC = Boot vector value to program Return parameter(s): ACC = 00 = pass A C C=! 0 0=f a i l Read Security bits, Status bit, Boot vector Input parameters: ACC = 07H or 87H (WDT feed) DPL = 00H = security bits DPL = 01H = Status bit DPL = 02H = Boot vector Return parameter(s): ACC = 00 SoftICE S/N-match 0 SB 0 DBL_CLK Erase page Input parameters: R1 = 08H or 88H (WDT feed) DPH = page address high byte DPL = page address low byte Return parameter(s): ACC = 00 = pass ACC = !00 = fail

Multimaster bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer
The I2C-bus may be used for test and diagnostic purposes A typical I2C-bus conﬁguration is shown inFigure7. Depending on the state of the direction bit (R/W), two types of data transfers are possible on the I2C-bus:
Data transfer from a master transmitter to a slave receiver. The ﬁrst byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte.
Data transfer from a slave transmitter to a master receiver. The ﬁrst byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows the data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a ‘not acknowledge’ is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the I 2C-bus will not be released. The P89V660/662/664 device provides two byte-oriented I2C-bus interfaces. For simplicity, the description in this text is written for the primary interface. However, unless otherwise noted, the description applies to the secondary I 2C-bus interface with consideration given to the SFR’s addresses for the secondary interface. Please note that the secondary I 2C-bus interface uses quasi-bidirectional I/O pins instead of open-drain pins. The interface has four operation modes: Master Transmitter mode, Master Receiver mode, Slave Transmitter mode and Slave Receiver mode The P89V660/662/664 CPU interfaces with the I 2C-bus through four Special Function Registers (SFRs): S1CON (primary I2C-bus Control Register), S1DAT (primary I2C-bus Data Register), S1STA (primary I2C-bus Status Register), and the S1ADR (primary I2C-bus Slave Address Register). Fig 7. I2C-bus conﬁguration OTHER DEVICE WITH I2C-BUS INTERFACE SDA SCL R puR pu OTHER DEVICE WITH I2C-BUS INTERFACE P1[7]/SDA P1[6]/SCL P89V660/662/664 I2C-bus 002aab911

6.4.1 I2C-bus data register

data is located at the MSB of S1DAT.

6.4.2 I2C-bus slave address register

general call bit. When this bit is set, the general call address (00H) is recognized.

6.4.3 I2C-bus control register

condition when it is already in master mode. condition in master mode, or recovering from an error condition in slave mode. internal STOP condition will be generated, but it is not transmitted to the bus. Table 13. I2C-bus slave address register (S1ADR - address DBH) bit allocation Table 14. I

Table 15. I2C-bus control register (S1CON - address D8H) bit allocation Table 16. I2C-bus control register (S1CON - address D8H) bit description 7,1,0 CR2:0 SCL clock selection. See Table17.

The ‘own slave address’ has been received.
The general call address has been received while the general call bit (GC) in S1ADR is set.
A data byte has been received while the I

2C-bus interface is in the Master Receiver mode.

A data byte has been received while the I2C-bus interface is in the addressed Slave Receiver
A data byte has been received while the I2C-bus interface is in the Master Receiver mode.
A data byte has been received while the I2C-bus interface is in the addressed Slave Receiver

software by writing 0 to this bit. Receiver mode. The STO ﬂag is cleared by hardware automatically.

6 ENS1 I

Table 17. I2C-bus clock rates

6 MHz 12 MHZ 6 MHz 12 MHz 6X 12X

6.4.4 I2C-bus status register

set. Refer toTable22 toTable25 for details.

6.4.5 I2C-bus operation modes

6.4.5.1 Master transmitter mode

slave mode. STA, STO, and SI bits must be cleared to 0. Table 17. I Table 18. I2C-bus status register (S1STA - address D9H) bit allocation Table 19. I 7:3 SC[4:0] I2C-bus Status code. 2:0 - Reserved, are always set to 0. Table 20. I2C-bus control register (S1CON - address D8H)

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 29 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI The I2C-bus will enter Master Transmitter mode by setting the STA bit. The I2C-bus logic will send the START condition as soon as the bus is free. After the START condition is transmitted, the SI bit is set, and the status code in S1STA should be 08H. This status code must be used to vector to an interrupt service routine where the user should load the slave address to S1DAT and data direction bit (SLA+W). The SI bit must be cleared before the data transfer can continue. When the slave address and R/W bit have been transmitted and an acknowledgment bit has been received, the SI bit is set again, and the possible status codes are 18H, 20H, or 38H for the master mode or 68H, 78H, or 0B0H if the slave mode was enabled (setting AA = Logic 1). The appropriate action to be taken for each of these status codes is shown in Table22.

6.4.5.2 Master receiver mode

In the Master Receiver mode, data is received from a slave transmitter. The transfer started in the same manner as in the Master Transmitter mode. When the START condition has been transmitted, the interrupt service routine must load the slave address and the data direction bit to I 2C-bus Data Register (S1DAT). The SI bit must be cleared before the data transfer can continue. When the slave address and data direction bit have been transmitted and an acknowledge bit has been received, the SI bit is set, and the Status Register will show the status code. For master mode, the possible status codes are 40H, 48H, or 38H. For slave mode, the possible status codes are 68H, 78H, or B0H. Refer to Table24 for details. After a repeated START condition, I2C-bus may switch to the Master Transmitter mode. Fig 8. Format in the Master Transmitter mode S R/W A DATA DATA data transferred (n Bytes + acknowledge) A A/A Pslave address logic 0 = write logic 1 = read from master to slave from slave to master A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) S = START condition P = STOP condition 002aaa929 Fig 9. Format of Master Receiver mode S R Aslave address logic 0 = write logic 1 = read from master to slave from slave to master A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) S = START condition 002aaa930 DATA DATA data transferred (n Bytes + acknowledge) A A P

6.4.5.3 Slave receiver mode

STO and SI are cleared to 0. Table25 for the status codes and actions.

6.4.5.4 Slave transmitter mode

Fig 10. A Master Receiver switches to Master Transmitter after sending Repeated Start. Table 21. I2C-bus control register (S1CON - address D8H)

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 31 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI STOP conditions are recognized as the beginning and end of a serial transfer. In a given application, the I2C-bus may operate as a master and as a slave. In the slave mode, the I2C-bus hardware looks for its own slave address and the general call address. If one of these addresses is detected, an interrupt is requested. When the microcontrollers wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. If bus arbitration is lost in the master mode, the I 2C-bus switches to the slave mode immediately and can detect its own slave address in the same serial transfer. Fig 12. Format of slave transmitter mode S R Aslave address logic 0 = write logic 1 = read from master to slave from slave to master A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) S = START condition P = STOP condition 002aaa933 DATA DATA data transferred (n Bytes + acknowledge) A A P

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 32 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI Fig 13. I2C-bus serial interface block diagram INTERNAL BUS 002aab912 ADDRESS REGISTER COMPARATOR SHIFT REGISTER I2ADR ACK BIT COUNTER/ ARBITRATION AND SYNC LOGIC I2DAT TIMING AND CONTROL LOGIC SERIAL CLOCK GENERATOR CCLK interrupt INPUT FILTER OUTPUT STAGE INPUT FILTER OUTPUT STAGE P1[7] P1[7]/SDA P1[6]/SCL P1[6] timer 1 overflow CONTROL REGISTERS AND SCL DUTY CYCLE REGISTERS I2CON I2SCLH I2SCLL STATUS DECODERstatus bus STATUS REGISTER I2STAT

Table 22. Master transmitter mode

Table 23. Master Receiver mode

0000 Data byte will be received; NOT ACK

0001 Data byte will be received; ACK bit

100x Repeated START will be transmitted.

Read data byte or100x Repeated START will be transmitted. Table 24. Slave Receiver mode

0001 Switched to not addressed SLA

1000 Switched to not addressed SLA

will be recognized if S1ADR.0 = 1.

will be recognized if S1ADR.0 = 1. Table 25. Slave transmitter mode and ACK bit will be received. and ACK bit will be received.

6.5 Timers/counters 0 and 1

either as timers or event counters (seeTable26 andTable27). 1⁄6 of the oscillator frequency. will be recognized if S1ADR.0 = 1. will be recognized if S1ADR.0 = 1. will be recognized if S1ADR.0 = 1. will be recognized if S1ADR.0 = 1.

Timer 0 and Timer 1 have four operating modes from which to select. Table 26. TMOD - Timer/Counter mode control register (address 89H) bit allocation Table 27. TMOD - Timer/Counter mode control register (address 89H) bit description cleared, Timer 1 is enabled when the TR1 control bit is set. from CCLK). Set for Counter operation (input from T1 input pin). 5 T1M1 Mode select for Timer 1.

4 T1M0

cleared, Timer 0 is enabled when the TR0 control bit is set. from CCLK). Set for Counter operation (input from T0 input pin). 1 T0M1 Mode Select for Timer 0.

0 T0M0

Table 28. TMOD - Timer/Counter mode control register (address 89H) M1/M0 operating 0 0 0 8048 timer ‘TLx’ serves as 5-bit prescaler.

6.5.1 Mode 0

Counter with a ﬁxed divide-by-32 prescaler.Figure14 shows Mode 0 operation. timer only controlled by Timer 1 control bits. 1 1 3 (Timer 1) Timer/Counter 1 stopped. Table 29. TCON - Timer/Counter control register (address 88H) bit allocation Table 30. TCON - Timer/Counter control register (address 88H) bit description 7 TF1 Timer 1 overﬂow ﬂag. Set by hardware on Timer/Counter overﬂow. 5 TF0 Timer 0 overﬂow ﬂag. Set by hardware on Timer/Counter overﬂow. is processed, or by software. edge/LOW-state that triggers external interrupt 1. is processed, or by software. edge/LOW-state that triggers external interrupt 0.

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 41 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI In this mode, the Timer register is conﬁgured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt ﬂag TFn. The count input is enabled to the Timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer to be controlled by external inputINTn, to facilitate pulse width measurements). TRn is a control bit in the Special Function Register TCON (Figure5). The GATE bit is in the TMOD register. The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3 bits of TLn are indeterminate and should be ignored. Setting the run ﬂag (TRn) does not clear the registers. Mode 0 operation is the same for Timer 0 and Timer 1 (see Figure14). There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

6.5.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn) are used. See Figure15.

6.5.3 Mode 2

Mode 2 conﬁgures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown inFigure16. Overﬂow from TLn not only sets TFn, but also reloads TLn with the contents of THn, which must be preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer 0 and Timer 1. Fig 14. Timer/Counter 0 or 1 in Mode 0 (13-bit counter) 002aaa519 osc/6 Tn pin TRn TnGate INTn pin C/T = 0 C/T = 1 TLn (5-bits) THn (8-bits) TFn control overflow interrupt Fig 15. Timer/Counter 0 or 1 in Mode 1 (16-bit counter) 002aaa520 osc/6 Tn pin TRn TnGate INTn pin C/T = 0 C/T = 1 TLn (8-bits) THn (8-bits) TFn control overflow interrupt

6.5.4 Mode 3

When timer 1 is in Mode 3 it is stopped (holds its count). The effect is the same as setting T R 1=0 . Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for Mode 3 and Timer 0 is shown inFigure17. TL0 uses the Timer 0 control bits: T0C/T, T0GATE, TR0,INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the ‘Timer 1’ interrupt. Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode 3, the P89V660/662/664 can look like it has an additional Timer. Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3. It can still be used by the serial port as a baud rate generator, or in any application not requiring an interrupt.6.6 Timer 2 Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/ T2 in the special function register T2CON. Timer 2 has four operating modes: Capture, Auto-reload (up or down counting), Clock-out, and Baud Rate Generator which are selected according to Table31 using T2CON (Table32 and Table33) and T2MOD (Table34 andTable35). Fig 16. Timer/Counter 0 or 1 in Mode 2 (8-bit auto-reload) 002aaa521 osc/6 Tn pin TRn TnGate INTn pin TLn (8-bits) THn (8-bits) TFn control overflow reload interrupt C/T = 0 C/T = 1 Fig 17. Timer/Counter 0 Mode 3 (two 8-bit counters) 002aaa522 osc/2 TR1 TR0 TnGate INT0 pin TL0 (8-bits) TF0 control overflow interrupt TH0 (8-bits) TF1 control overflow interrupt osc/6 T0 pin C/T = 0 C/T = 1

Table 31. Timer 2 operating mode

0011 Programmable Clock-Out

1 X 1 0 Baud rate generator

Table 32. T2CON - Timer/Counter 2 control register (address C8H) bit allocation Table 33. T2CON - Timer/Counter 2 control register (address C8H) bit description

7 TF2 Timer 2 overﬂow ﬂag set by a Timer 2 overﬂow and must be cleared by

Timer 2 is in Clock-out mode.

6 EXF2 Timer 2 external ﬂag is set when Timer 2 is in capture, reload or baud

Timer 2 interrupt routine. EXF2 must be cleared by software. causes Timer 1 overﬂow to be used for the receive clock. causes Timer 1 overﬂows to be used for the transmit clock. 2 TR2 Start/stop control for Timer 2. A logic ‘1’ enables the timer to run. ignored and the timer is forced to auto-reload on Timer 2 overﬂow. Table 34. T2MOD - Timer 2 mode control register (address C9H) bit allocation

6.6.1 Capture mode

upon overﬂowing sets bit TF2, the Timer 2 overﬂow bit. The capture mode is illustrated inFigure18. determine which event caused the interrupt. interrupt is signalled it has to be serviced before new capture event on T2EX pin occurs. previously reported interrupt. Table 35. T2MOD - Timer 2 mode control register (address C9H) bit description 7 to 2 - Reserved for future use. Should be set to ‘0’ by user programs.

6.6.2 Auto-reload mode (up or down-counter)

In the 16-bit auto-reload mode, Timer 2 can be conﬁgured as either a timer or counter (via C/T2 in T2CON), then programmed to count up or down. The counting direction is determined by bit DCEN (Down-counter Enable) which is located in the T2MOD register (see Table34 andTable35). When reset is applied, DCEN = 0 and Timer 2 will default to counting up. If the DCEN bit is set, Timer 2 can count up or down depending on the value of the T2EX pin. Figure19 shows Timer 2 counting up automatically (DCEN = 0). In this mode, there are two options selected by bit EXEN2 in T2CON register. If EXEN2 = 0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overﬂow Flag) bit upon overﬂow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software means. Auto reload frequency when Timer 2 is counting up can be determined from this formula: (1) Where SupplyFrequency is either f osc (C/T2 = 0) or frequency of signal on T2 pin (C/T2 = 1). If EXEN2 = 1, a 16-bit reload can be triggered either by an overﬂow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 is ‘1’. Microcontroller’s hardware will need three consecutive machine cycles in order to recognize falling edge on T2EX and set EXF2 = 1: in the ﬁrst machine cycle pin T2EX has to be sampled as ‘1’; in the second machine cycle it has to be sampled as ‘0’, and in the third machine cycle EXF2 will be set to ‘1’. Fig 19. Timer 2 in Auto-reload mode (DCEN = 0) 002aaa524 OSC ‚6 T2 pin C/T2 = 0 C/T2 = 1 TL2 (8-bits) TH2 (8-bits) TF2 control reload TR2 timer 2 interrupt EXF2 RCAP2L RCAP2H control EXEN2 transition detector T2EX pin SupplyFrequency

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 46 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI InFigure20, DCEN = 1 and Timer 2 is enabled to count up or down. This mode allows pin T2EX to control the direction of count. When a logic ‘1’ is applied at pin T2EX Timer 2 will count up. Timer 2 will overﬂow at 0FFFFH and set the TF2 ﬂag, which can then generate an interrupt, if the interrupt is enabled. This timer overﬂow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2. When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underﬂow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underﬂow sets the TF2 ﬂag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2. The external ﬂag EXF2 toggles when Timer 2 underﬂows or overﬂows. This EXF2 bit can be used as a 17th bit of resolution if needed.

6.6.3 Programmable clock-out

A 50 % duty cycle clock can be programmed to come out on pin T2 (P1[0]). This pin, besides being a regular I/O pin, has two additional functions. It can be programmed: 1. To input the external clock for Timer/Counter 2, or 2. To output a 50 % duty cycle clock ranging from 122 Hz to 8 MHz at a 16 MHz operating frequency. To conﬁgure the Timer/Counter 2 as a clock generator, bit C/ T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in Equation2: (2) Where (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. In the Clock-Out mode Timer 2 rollovers will not generate an interrupt. This is similar to when it is used as a baud rate generator. Fig 20. Timer 2 in Auto Reload mode (DCEN = 1) 002aaa525 TL2 (8-bits) TH2 (8-bits) TF2 EXF2 underflow timer 2 interrupt RCAP2L RCAP2H FFH FFH overflow (down-counting reload value) (up-counting reload value) count direction 1 = up 0 = down T2EX pin toggle OSC ÷6 T2 pin C/T2 = 0 C/T2 = 1 control TR2 OscillatorFrequency

6.6.4 Baud rate generator mode

Bits TCLK and/or RCLK in T2CON allow the UART) transmit and receive baud rates to be derived from either Timer 1 or Timer 2 (SeeSection6.7 for details). When TCLK = 0, Timer 1 is used as the UART transmit baud rate generator. When TCLK = 1, Timer 2 is used as the UART transmit baud rate generator. RCLK has the same effect for the UART receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates – Timer 1 or Timer 2. Figure21 shows Timer 2 in baud rate generator mode: The baud rate generation mode is like the auto-reload mode, when a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in modes 1 and 3 are determined by Timer 2’s overﬂow rate given below: Modes 1 and 3 Baud Rates = Timer 2 Overﬂow Rate / 16 The timer can be conﬁgured for either ‘timer’ or ‘counter’ operation. In many applications, it is conﬁgured for ‘timer' operation (C/ T2 = 0). Timer operation is different for Timer 2 when it is being used as a baud rate generator. Usually, as a timer it would increment every machine cycle (i.e.,1⁄6 the oscillator frequency). As a baud rate generator, it increments at the oscillator frequency. Thus the baud rate formula is as follows: Modes 1 and 3 Baud Rates = (3) Where: (RCAP2H, RCAP2L) = The content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. The Timer 2 as a baud rate generator mode is valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the Fig 21. Timer 2 in Baud Rate Generator mode 002aaa526 TX/RX baud rate timer 2 interrupt OSC ÷2 T2 pin C/T2 = 0 C/T2 = 1 TL2 (8-bits) TH2 (8-bits) control TR2 EXF2 RCAP2L RCAP2H control EXEN2 transition detector T2EX pin reload OscillatorFrequency

before accessing the Timer 2 or RCAP2 registers. rates and how they can be obtained from Timer 2.

6.6.5 Summary of baud rate equations

6.7 UARTs

UART include Framing Error detection, and automatic address recognition. Table 36. Timer 2 generated commonly used baud rates

600 Bd 12 MHz FB 1E

220 Bd 12 MHz F2 AF

600 Bd 6 MHz FD 8F

220 Bd 6 MHz F9 57

6.7.1 Mode 0

transmitted or received, LSB ﬁrst. The baud rate is ﬁxed at1⁄6 of the CPU clock frequency. whether it sends or receives data on RXD line.

6.7.2 Mode 1

6.7.3 Mode 2

6.7.4 Mode 3

Table 37. SCON - Serial port control register (address 98H) bit allocation Table 38. SCON - Serial port control register (address 98H) bit description

6 SM1 With SM0, deﬁnes the serial port mode (see

5 SM2 Enables the multiprocessor communication feature in Modes 2 and 3. software to disable reception.

6.7.5 Framing error

6.7.6 More about UART mode 1

boundaries of the incoming bit times. register, and reception of the rest of the frame will proceed. (b) Either SM2 = 0, or the received stop bit = 1.

6.7.7 More about UART modes 2 and 3

Reception is performed in the same manner as in mode 1. transmission. Must be cleared by software. modes. (See SM2 for exceptions). Must be cleared by software. Table 39. SCON - Serial port control register (address 98H) SM0/SM1 mode deﬁnition

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 51 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the ﬁnal shift pulse is generated: (a) RI = 0, and (b) Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the ﬁrst 8 data bits go into SBUF .

6.7.8 Multiprocessor communications

UART modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received or transmitted. When data is received, the 9th bit is stored in RB8. The UART can be programmed so that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. One way to use this feature in multiprocessor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it ﬁrst sends out an address byte which identiﬁes the target slave. An address byte differs from a data byte in a way that the 9th bit is ‘1’ in an address byte and ‘0’ in the data byte. With SM2 = 1, no slave will be interrupted by a data byte, i.e. the received 9th bit is ‘0’. However, an address byte having the 9th bit set to ‘1’ will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed or not. The addressed slave will clear its SM2 bit and prepare to receive the data (still 9 bits long) that follow. The slaves that weren’t being addressed leave their SM2 bits set and go on about their business, ignoring the subsequent data bytes. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit, although this is better done with the Framing Error ﬂag. When UART receives data in mode 1 and SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.

6.7.9 Automatic address recognition

Automatic address recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled for the UART by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt ﬂag (RI) will be automatically set when the received byte contains either the ‘Given’ address or the ‘Broadcast' address. The 9 bit mode requires that the 9th information bit is a ‘1’ to indicate that the received information is an address and not data. Using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special function registers are used to deﬁne the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to deﬁne which bits in the SADDR are to be used and which bits are ‘don’t care’. The SADEN mask can be logically ANDed with the SADDR to create the Given address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. This device uses the methods presented in Figure22 to determine if a Given or Broadcast address has been received or not.

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 52 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI The following examples will help to show the versatility of this scheme. Example 1, slave 0: (4) Example 2, slave 1: (5) In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a ‘0’ in bit 0 and it ignores bit 1. Slave 1 requires a ‘0’ in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a ‘0’ in bit 1. A unique address for slave 1 would be 1100 0001 since a ‘1’ in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit0=0( f o rs l a v e0 )a n db i t1=0( f o rs l a v e1 ) .Thus, both could be addressed with 1100 0000. Fig 22. Schemes used by the UART to detect ‘given’ and ‘broadcast’ addresses when multiprocessor communications is enabled 002aaa527 rx_byte(7) saddr(7) saden(7) rx_byte(0) saddr(0) given_address_match logic used by UART to detect 'given address' in received data saddr(7) saden(7) rx_byte(7) saddr(0) saden(0) rx_byte(0) broadcast_address_match logic used by UART to detect 'given address' in received data saden(0) SADDR = 1100 0000 SADEN = 1111 1101 SADDR = 1100 0000 SADEN = 1111 1110

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 53 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Example 1, slave 0: (6) Example 2, slave 1: (7) Example 2, slave 2: (8) In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit1=0 and it can be uniquely addressed by 1110 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are treated as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR and SADEN are loaded with 0s. This produces a given address of all ‘don’t cares’ as well as a Broadcast address of all ‘don’t cares'. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature.

6.8 Serial Peripheral Interface (SPI)

6.8.1 SPI features

Master or slave operation
10 MHz bit frequency (max)
LSB ﬁrst or MSB ﬁrst data transfer
Four programmable bit rates
End of transmission (SPIF)
Write collision ﬂag protection (WCOL)
Wake-up from Idle mode (slave mode only)

6.8.2 SPI description

The serial peripheral interface allows high-speed synchronous data transfer between the P89V660/662/664 and peripheral devices or between several P89V660/662/664 devices. Figure23 shows the correspondence between master and slave SPI devices. The SCK SADDR = 1100 0000 SADEN = 1111 1001 SADDR = 1110 0000 SADEN = 1111 1010 SADDR = 1100 0000 SADEN = 1111 1100

the SPI Interrupt Enable bit (SPIE) and the SPI interrupt enable bit, ES3, are both set. pin can also be used as an input port pin. show the four possible combinations of these two bits. Table 40. SPCR - SPI control register (address D5H) bit allocation Table 41. SPCR - SPI control register (address D5H) bit description 7 SPIE If both SPIE and ES3 are set to one, SPI interrupts are enabled. 6 SPEN SPI enable bit. When set enables SPI. 4 MSTR Master/slave select. 1 = master mode, 0 = slave mode.

clock; 0 = shift triggered on the leading edge of the clock. Table 42. SPCR - SPI control register (address D5H) clock rate selection Table 43. SPSR - SPI status register (address AAH) bit allocation Table 44. SPSR - SPI status register (address AAH) bit description 7 SPIF SPI interrupt ﬂag. Upon completion of data transfer, this bit is set to ‘1’. data transfer. This bit is cleared by software. 5 to 0 - Reserved for future use. Should be set to ‘0’ by user programs.

6.9 Watchdog timer

The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer Reset (WDTRST) SFR. The WDT is disabled at reset. To enable the WDT, the user must write 01EH and 0E1H, in sequence, to the WDTRST SFR. When the WDT is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT, except through a reset (either hardware reset or a WDT overﬂow reset). When the WDT overﬂows, it will drive an output reset HIGH pulse at the RST pin. When the WDT is enabled (and thus running) the user needs to reset it by writing 01EH and 0E1H, in sequence, to the WDTRST SFR to avoid WDT overﬂow. The 14-bit counter reaches overﬂow when it reaches 16383 (3FFFH) and this will reset the device. The WDT’s counter cannot be read or written. When the WDT overﬂows it will generate a output pulse at the reset pin with a duration of 98 oscillator periods in 6 clock mode or 196 oscillator periods in 12 clock mode.

6.10 PCA

The PCA includes a special 16-bit Timer that has ﬁve 16-bit capture/compare modules associated with it. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. Each module has a pin associated with it. Module 0 is connected to CEX0, module 1 to CEX1, etc. Registers CH and CL contain current value of the free running up counting 16-bit PCA timer. The PCA timer is a common time base for all ﬁve modules and can be programmed to run at: 1⁄6 the oscillator frequency,1⁄2 the oscillator frequency, the Timer 0 overﬂow, or the input on the ECI pin (P1[2]). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (see Table45 and Table46). Fig 25. SPI transfer format with CPHA = 1 002aaa530 MSB SCK cycle # (for reference) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from master) MISO (from slave) SS (to slave) 12345678 M S B 654321 L S B 4 3 2 1 LSB

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 57 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI In the CMOD SFR there are three additional bits associated with the PCA. They are CIDL which allows the PCA to stop during Idle mode, WDTE which enables or disables the Watchdog function on module 4, and ECF which when set causes an interrupt and the PCA overﬂow ﬂag CF (in the CCON SFR) to be set when the PCA timer overﬂows. The watchdog timer function is implemented in module 4 of PCA. The CCON SFR contains the run control bit for the PCA (CR) and the ﬂags for the PCA timer (CF) and each module (CCF4:0). To run the PCA the CR bit (CCON.6) must be set by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when the PCA counter overﬂows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. Bits 0 through 4 of the CCON register are the ﬂags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These ﬂags can only be cleared by software. All the modules share one interrupt vector. The PCA interrupt system is shown in Figure27. Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. The registers contain the bits that control the mode that each module will operate in. The ECCF bit (from CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module) enables the CCFn ﬂag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module (see Figure27). PWM (CCAPMn.1) enables the pulse width modulation mode. The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module’s capture/compare register. The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module’s capture/compare register. Fig 26. PCA MODULE0 PCA TIMER/COUNTER P1[3]/CEX0 MODULE1 P1[4]/CEX1 MODULE2 P1[5]/CEX2 MODULE3 P3[4]/T0/CEX3 MODULE4 P3[5]/T1/CEX4 time base for PCA modules Module functions: - 16-bit capture - 16-bit timer - 16-bit high speed output - 8-bit PWM - watchdog timer (module 4 only) 16 bits 16 bits 002aab913

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 58 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output. Fig 27. PCA interrupt system 002aab914 PCA TIMER/COUNTER MODULE0 CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 MODULE1 MODULE2 MODULE3 MODULE4 ECF ECCFn IEN0.6 EC IEN0.7 EA CCAPMn.0CMOD.0 CCON (C0h) to interrupt priority decoderTable 45. CMOD - PCA counter mode register (address C1H) bit allocation Not bit addressable; Reset value: 00H Bit 7 6 5 4 3 2 1 0 Symbol CIDL WDTE - - - CPS1 CPS0 ECF

Table 46. CMOD - PCA counter mode register (address C1H) bit description

7 CIDL Counter Idle Control: CIDL = 0 programs the PCA Counter to continue

6 WDTE WatchDog Timer Enable: WDTE = 0 disables watchdog timer function

on module 4. WDTE = 1 enables it. 5 to 3 - Reserved for future use. Should be set to ‘0’ by user programs.

0 ECF PCA Enable Counter Overﬂow Interrupt: ECF = 1 enables CF bit in

CCON to generate an interrupt. ECF = 0 disables that function. Table 47. CMOD - PCA counter mode register (address C1H) count pulse select Table 48. CCON - PCA counter control register (address 0C0H) bit allocation Table 49. CCON - PCA counter control register (address 0C0H) bit description either hardware or software but can only be cleared by software. on. Must be cleared by software to turn the PCA counter off. 5 - Reserved for future use. Should be set to ‘0’ by user programs. capture occurs. Must be cleared by software. capture occurs. Must be cleared by software. capture occurs. Must be cleared by software. capture occurs. Must be cleared by software. capture occurs. Must be cleared by software.

6.10.1 PCA capture mode

capture registers (CCAPnL and CCAPnH). Table 50. CCAPMn - PCA modules compare/capture register (address CCAPM0 0C2H, Table 51. CCAPMn - PCA modules compare/capture register (address CCAPM0 0C2H, 7 - Reserved for future use. Should be set to ‘0’ by user programs. 6 ECOMn Enable Comparator. ECOMn = 1 enables the comparator function. 5 CAPPn Capture Positive, CAPPn = 1 enables positive edge capture. 4 CAPNn Capture Negative, CAPNn = 1 enables negative edge capture. module’s compare/capture register causes the CEXn pin to toggle. used as a pulse width modulated output. CCON register to generate an interrupt. Table 52. PCA module modes (CCAPMn register)

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 61 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated. 6.10.2 16-bit software timer mode The PCA modules can be used as software timers (Figure29) by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module’s capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set. Fig 28. PCA capture mode 002aab915 CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 CCON (C0h) PCA interrupt PCA timer/counter - ECOMn 0 000 CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4 (C2h to C6h) CH CL CCAPnH CCAPnL capture (to CCFn) CEXn

6.10.3 High-speed output mode

In this mode (Figure30) the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must be set. Fig 29. PCA compare mode 002aab916 CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 CCON (C0h) PCA interrupt - ECOMn 00 100 CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4 (C2h to C6h) 16-BIT COMPARATOR PCA timer/counter CH CL match (to CCFn) CCAPnH CCAPnL enable write to CCAPnH write to CCAPnL reset

6.10.4 Pulse width modulator mode

All of the PCA modules can be used as PWM outputs (Figure31). Output frequency depends on the source for the PCA timer. All of the modules will have the same frequency of output because they all share one and only PCA timer. The duty cycle of each module is independently variable using the module’s capture register CCAPnL. When the value of the PCA CL SFR is less than the Fig 30. PCA high-speed output mode 002aab917 toggle CEXn CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 CCON (C0h) PCA interrupt - ECOMn 00 100 CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4 (C2h to C6h) 16-BIT COMPARATOR PCA timer/counter CH CL match (to CCFn) CCAPnH CCAPnL enable write to CCAPnH write to CCAPnL reset Fig 31. PCA PWM mode 002aab918 - ECOMn 01 0 001 1 CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4 (C2h to C6h) CCAPnL 8-BIT COMPARATOR PCA timer/counter CCAPnH CL enable CEXn CL < CCAPnL CL ‡ CCAPnL

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 64 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI value in the module’s CCAPnL SFR the output will be low, when it is equal to or greater than the output will be high. When CL overﬂows from FF to 00, CCAPnL is reloaded with the value in CCAPnH. This allows updating the PWM without glitches. The PWM and ECOM bits in the module’s CCAPMn register must be set to enable the PWM mode.

6.10.5 PCA watchdog timer

An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a Watchdog. However, this module can still be used for other modes if the Watchdog is not needed. Figure31 shows a diagram of how the Watchdog works. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. user’s software then must periodically change (CCAP4H,CCAP4L) to keep a match from occurring with the PCA timer (CH,CL). This code is given in the WATCHDOG routine shown above. In order to hold off the reset, the user has three options: 1. Periodically change the compare value so it will never match the PCA timer. 2. Periodically change the PCA timer value so it will never match the compare values. 3. Disable the Watchdog by clearing the WDTE bit before a match occurs and then re-enable it. The ﬁrst two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base forall modules; changing the time base for other modules would not be a good idea. Thus, in most applications the ﬁrst solution is the best option. ;CALL the following WATCHDOG subroutine periodically. CLR EA ;Hold off interrupts MOV CCAP4L,#00 ;Next compare value is within 255 counts of current PCA timer value MOV CCAP4H,CH SETB EA ;Re-enable interrupts RET This routine should not be part of an interrupt service routine, because if the program counter goes astray and gets stuck in an inﬁnite loop, interrupts will still be serviced and the Watchdog will keep getting reset. Thus, the purpose of the Watchdog would be defeated. Instead, call this subroutine from the main program within 2 16 count of the PCA timer.

6.11 Security bits

from being read by unauthorized parties in Parallel Programmer mode and ISP mode. disabled from fetching code bytes from internal code memory.

6.12 Interrupt priority and polling sequence

Table 53. Security bit functions programming, except to program other security bits or a chip erase. 2 Read protect. When programmed inhibits reading of user code memory. instructions from external code memory. Table 54. Interrupt polling sequence

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 66 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI Fig 32. Interrupt structure 002aab919 highest priority interrupt interrupt polling sequence INT0 IE and IEA registers IP/IPH/IPA/IPAH registers individual enables global disable IE0 IT0 lowest priority interrupt SPIE SPIF TF0 INT1 TF1 CF ECF CCFn ECCFn RI TI TF2 EXF2 I2C-bus (primary) I2C-bus (secondary) IE1 IT1

Table 55. IEN0 - Interrupt enable register 0 (address A8H) bit allocation Table 56. IEN0 - Interrupt enable register 0 (address A8H) bit description

7 EA Interrupt Enable Bit: EA = 1 interrupt(s) can be serviced, EA = 0

interrupt servicing disabled. 6 EC PCA Interrupt Enable bit.

5 ES1 I

2C-bus Interrupt Enable (primary).

4 ES0 Serial Port Interrupt Enable

3 ET1 Timer 1 Overﬂow Interrupt Enable. 2 EX1 External Interrupt 1 Enable. 1 ET0 Timer 0 Overﬂow Interrupt Enable. 0 EX0 External Interrupt 0 Enable. Table 57. IEN1 - Interrupt enable register 1 (address E8H) bit allocation Table 58. IEN1 - Interrupt enable register 1 (address E8H) bit description 7 to 3 - Reserved for future use. Should be set to ‘0’ by user programs.

1 ES2 I

2C-bus Interrupt Enable (secondary). 0 ET2 Timer 2 Interrupt Enable. Table 59. IP0 - Interrupt priority 0 low register (address B8H) bit allocation Table 60. IP0 - Interrupt priority 0 low register (address B8H) bit description 7 PT2 Timer 2 Interrupt Priority Low Bit. 6 PPC PCA Interrupt Priority Low Bit.

5 PS1 I

2C-bus Interrupt Priority Low Bit. 4 PS0 Serial Port Interrupt Priority Low Bit. 3 PT1 Timer 1 Interrupt Priority Low Bit. 2 PX1 External Interrupt 1 Priority Low Bit. 1 PT0 Timer 0 Interrupt Priority Low Bit. 0 PX0 External Interrupt 0 Priority Low Bit.

6.13 Power-saving modes

consumption is critical. The two modes are idle and power-down, seeTable67. Table 61. IP0H - Interrupt priority 0 high register (address B7H) bit allocation Table 62. IP0H - Interrupt priority 0 high register (address B7H) bit description 7 PT2H Timer 2 Interrupt Priority High Bit. 6 PPCH PCA Interrupt Priority High Bit.

5 PS1H I

2C-bus Interrupt Priority High Bit (primary). 4 PS0H Serial Port Interrupt Priority High Bit. 3 PT1H Timer 1 Interrupt Priority High Bit. 2 PX1H External Interrupt 1 Priority High Bit. 1 PT0H Timer 0 Interrupt Priority High Bit. 0 PX0H External Interrupt 0 Priority High Bit. Table 63. IP1 - Interrupt priority 1 register (address 91H) bit allocation Table 64. IP1 - Interrupt priority 1 register (address 91H) bit description 7 to 2 - Reserved for future use. Should be set to ‘0’ by user programs. 1 PS3 SPI Interrupt Priority Low Bit.

0 PS2 I

2C-bus Interrupt Priority 1 Low Bit (secondary). Table 65. IP1H - Interrupt priority 1 high register (address 92H) bit allocation Table 66. IP1H - Interrupt priority 1 high register (address 92H) bit description 7 to 2 - Reserved for future use. Should be set to ‘0’ by user programs. 1 PS3H SPI Interrupt Priority High Bit.

0 PS2H I

2C-bus Interrupt Priority High Bit (secondary).

6.13.1 Idle mode

mode. A hardware reset starts the device similar to a power-on reset.

6.13.2 Power-down mode

Power-down mode. A hardware reset starts the device similar to power-on reset. Table 67. Power-saving modes device similar to a power-on reset. LOW-state during power-down. similar to a power-on reset.

6.14 System clock and clock options

6.14.1 Clock input options and recommended capacitor values for the oscillator

ampliﬁer (XTAL1, XTAL2), which can be conﬁgured for use as an on-chip oscillator.

6.14.2 Clock doubling option

clocks per machine cycle mode by ﬂash programming of the 6x/12x bit. Table 68. Recommended values for C1 and C2 by crystal type

Table 69. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Table 70. Static characteristics

[1] This parameter is measured only for initial qualiﬁcation and after a design or process change that could affect this parameter. qualify ALE with a Schmitt trigger, or use an address latch with a Schmitt trigger STROBE input. PSEN = 100 pF , load capacitance for all other outputs = 80 pF . the address bits are stabilizing. maximum value when VI is approximately 2 V. [7] Pin capacitance is characterized but not tested.EA = 25 pF (max). Table 70. Static characteristics …continued

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 73 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI (1) Maximum active IDD (2) Maximum idle IDD (3) Typical active IDD (4) Typical idle IDD Fig 35. IDD vs. frequency internal clock frequency (MHz) 0 40302010 002aaa813 IDD (mA) (1) (2) (3) (4)

[2] Calculated values are for 6-clock mode only. Table 71. Dynamic characteristics

9.1 Explanation of symbols

Each timing symbol has 5 characters. The ﬁrst character is always a ‘T’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A — Address C — Clock D — Input data H — Logic level HIGH I — Instruction (program memory contents) L — Logic level LOW or ALE P — PSEN Q — Output data R — RD signal T — Time V — Valid W — WR signal X — No longer a valid logic level Z — High impedance (Float) Example: tAVLL = Address valid to ALE LOW time tLLPL = ALE LOW toPSEN LOW time Fig 36. External program memory read cycle 002aaa548 port 2 PSEN ALE A0 to A7 tLLAX tPLAZ tPXIZ tLLPL tAVIV tAVLL tLLIV tPLIV tPLPH INSTR IN A8 to A15 A8 to A15 A0 to A7port 0 tPXIX tPXAV tLHLL

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 76 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI Fig 37. External data memory read cycle ALE PSEN port 0 port 2 RD A0 to A7 from RI to DPL DATA IN A0 to A7 from PCL INSTR IN P2.0 to P2.7 or A8 to A15 from DPH A0 to A15 from PCH tLLDV 002aaa549 tWHLH tAVDV tLLWL tAVLL tAVWL tRLRH tRLDV tLLAX tRHDZ tRHDX tRLAZ Fig 38. External data memory write cycle 002aaa550 port 2 port 0 WR PSEN ALE tLHLL P2[7:0] or A8 to A15 from DPH A0 to A7 from RI or DPL DATA OUT INSTR IN tAVLL tAVWL tLLWL tLLAX tWLWH tQVWH tWHQX tWHLH A8 to A15 from PCH A0 to A7 from PCL

Table 72. External clock drive

40 MHz Variable

Table 73. Serial port timing

[1] At 100 kb/s. All other bit rates, this value is inversely proportional to the bit rate of 100 kb/s. [2] Determined by the external bus capacitance and pull-up resistor. This must be < 1µs. [3] Spikes on SDA and SCL with a duration less than 3Tcy(clk) will be ﬁltered out. Max capacitance on SDA and SCL = 400 pF . Table 74. I2C-bus interface timing (12-clock mode)

Table 75. SPI interface timing

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 80 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI Fig 42. SPI master timing (CPHA = 0) TSPICYC tSPICLKH tSPICLKH tSPICLKL tSPICLKL master LSB/MSB outmaster MSB/LSB out tSPIDHtSPIDSU tSPIF tSPIOH tSPIDV tSPIRtSPIDV tSPIF tSPIR tSPIF tSPIR SS SPICLK (CPOL = 0) (output) 002aaa908 SPICLK (CPOL = 1) (output) MISO (input) MOSI (output) LSB/MSB inMSB/LSB in Fig 43. SPI master timing (CPHA = 1) TSPICYC tSPICLKL tSPICLKL tSPICLKH tSPICLKH master LSB/MSB outmaster MSB/LSB out tSPIDHtSPIDSU tSPIF tSPIOH tSPIDV tSPIDV tSPIR tSPIDV tSPIF tSPIF tSPIR tSPIR SS SPICLK (CPOL = 0) (output) 002aaa909 SPICLK (CPOL = 1) (output) MISO (input) MOSI (output) LSB/MSB inMSB/LSB in

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 81 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI Fig 44. SPI slave timing (CPHA = 0) TSPICYC tSPICLKH tSPICLKH tSPICLKL tSPICLKL tSPILEAD tSPILAG tSPIDSU tSPIDH tSPIDHtSPIDSU tSPIDSU tSPIR tSPIA tSPIOH tSPIDIS tSPIR slave MSB/LSB out MSB/LSB in LSB/MSB in slave LSB/MSB out tSPIDV tSPIOH tSPIOH tSPIDV tSPIR tSPIR tSPIF tSPIF SS SPICLK (CPOL = 0) (input) 002aaa910 SPICLK (CPOL = 1) (input) MISO (output) MOSI (input) not defined Fig 45. SPI slave timing (CPHA = 1) 002aaa911 TSPICYC tSPICLKH tSPICLKH tSPICLKLtSPILEAD tSPICLKL tSPILAG tSPIDSU tSPIDSU tSPIDSUtSPIDH tSPIDH tSPIR tSPIR tSPIR tSPIA tSPIOH tSPIOH tSPIOH tSPIDIS slave MSB/LSB outnot defined MSB/LSB in LSB/MSB in slave LSB/MSB out tSPIDV tSPIDV tSPIDV tSPIRtSPIF tSPIF SS SPICLK (CPOL = 0) (input) SPICLK (CPOL = 1) (input) MISO (output) MOSI (input)

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 82 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI Fig 46. Test load example All other pins disconnected Fig 47. IDD test condition, active mode All other pins disconnected Fig 48. IDD test condition, Idle mode 002aaa555 to DUT to tester C L 002aaa556 VDD VDD VDD EARST XTAL2(n.c.)clock signal XTAL1 VSS IDD VDD DUT 002aaa557 VDD VDD VDD EARST XTAL2(n.c.)clock signal XTAL1 VSS IDD DUT

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 83 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI All other pins disconnected Fig 49. IDD test condition, Power-down mode 002aaa558 VDDVDD = 2 V VDD EARST XTAL2(n.c.) XTAL1 VSS IDD VDD DUT

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 84 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI 10. Package outline Fig 50. Package outline SOT376-1 (TQFP44) UNIT A max. A 1 A 2 A 3 bp cE (1) eH E LL p Zywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.2 0.15 0.05 1.05 0.95 0.25 0.45 0.30 0.18 0.12 10.1 9.9 0.8 12.15 11.85 1.2 0.8 o o0.2 0.10.21 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT376-1 137E08 MS-026 00-01-19 02-03-14 D (1) (1)(1) 10.1 9.9 H D 12.15 11.85 EZ 1.2 0.8 D bp e E B DH bp EH v M B D ZD A Z E e v M A 33 23 q A 1 A Lp detail X L (A )3A 2 X y c w M w M 0 2.5 5 mm scale TQFP44: plastic thin quad flat package; 44 leads; body 10 x 10 x 1.0 mm SOT376-1 pin 1 index

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 85 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI Fig 51. Package outline SOT187-2 (PLCC44) UNIT A A 1 min. A 4 max. bp ey wv b REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 4.57 4.19 0.51 3.05 0.53 0.33 0.021 0.013 16.66 16.51 1.27 17.65 17.40 2.16 45o 0.18 0.10.18 DIMENSIONS (mm dimensions are derived from the original inch dimensions) Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. SOT187-2 D (1) E(1) 16.66 16.51 H D H E 17.65 17.40 ZD (1) max. ZE(1) max. 2.16 0.81 0.66 k 1.22 1.07 0.180 0.165 0.02 0.12 A 3 0.25 0.01 0.656 0.650 0.05 0.695 Lp 1.44 1.02 0.057 0.040 0.656 0.650 0.695 0.685 eD eE 16.00 14.99 0.63 0.59 16.00 14.99 0.63 0.59 0.0850.032 0.026 0.048 0.042 2939 71 7 detail X (A )3 bp w M A 1 A A 4 Lp b k Xy e E B DH Ee EH v M B D Z D A Z E e v M A pin 1 index 112E10 MS-018 EDR-7319 0 5 10 mm scale 99-12-27 01-11-14 inches PLCC44: plastic leaded chip carrier; 44 leads SOT187-2 De

Table 76. Acronym list

Table 77. Revision history

Section 2.2 “Additional features”: corrected 6-clock/12-clock mode information. P89V660_662_664_2 20080129 Product data sheet - P89V660_662_664_1 P89V660_662_664_1 20070502 Product data sheet - -

P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 88 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI 13. Legal information

13.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

13.2 Deﬁnitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

13.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

13.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I 2C-bus — logo is a trademark of NXP B.V. 14. Contact information For more information, please visit:http://www.nxp.com For sales ofﬁce addresses, please send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 November 2008 Document identifier: P89V660_662_664_3 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 15. Contents 2.3 Comparison to the P89C660/662/664 devices . 2 6.4 I

6.14.1 Clock input options and recommended capacitor

Product Information

P89V662 specifications and overview.

Summary

8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI Rev. 03-10 November 2008

Description

8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI Rev. 03-10 November 2008

Source title P89V662 Datasheet(PDF) - NXP Semiconductors

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