Microcontroller

P89V51RC2FN

NXP Semiconductors

8-bit 80C51 5 V low power 16/32/64 kB flash microcontroller with 1 kB RAM Rev. 05-12 November 2009

Manufacturer: NXP Semiconductors

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General description The P89V51RB2/RC2/RD2 are 80C51 microcontrollers with 16/32/64 kB ﬂash and 1024 B of data RAM. A key feature of the P89V51RB2/RC2/RD2 is its X2 mode option. The design engineer can choose to run the application with the conventional 80C51 clock rate (12 clocks per machine cycle) or select the X2 mode (six clocks per machine cycle) to achieve twice the throughput at the same clock frequency. Another way to beneﬁt from this feature is to keep the same performance by reducing the clock frequency by half, thus dramatically reducing the EMI. The ﬂash program memory supports both parallel programming and in serial ISP . Parallel programming mode offers gang-programming at high speed, reducing programming costs and time to market. ISP allows a device to be reprogrammed in the end product under software control. The capability to ﬁeld/update the application ﬁrmware makes a wide range of applications possible. The P89V51RB2/RC2/RD2 is also capable of IAP , allowing the ﬂash program memory to be reconﬁgured even while the application is running. 2. Features n 80C51 CPU n 5 V operating voltage from 0 MHz to 40 MHz n 16/32/64 kB of on-chip ﬂash user code memory with ISP and IAP n Supports 12-clock (default) or 6-clock mode selection via software or ISP n SPI and enhanced UART n PCA with PWM and capture/compare functions n Four 8-bit I/O ports with three high-current port 1 pins (16 mA each) n Three 16-bit timers/counters n Programmable watchdog timer n Eight interrupt sources with four priority levels n Second DPTR register n Low EMI mode (ALE inhibit) n TTL- and CMOS-compatible logic levels P89V51RB2/RC2/RD2 8-bit 80C51 5 V low power 16/32/64 kB ﬂash microcontroller with 1 kB RAM Rev. 05 — 12 November 2009 Product data sheet

3.1 Ordering options

Table 1. Ordering information Table 2. Ordering options

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 3 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core 4. Block diagram Fig 1. Block diagram HIGH PERFORMANCE 80C51 CPU 16/32/64 kB CODE FLASH 1 kB DATA RAM OSCILLATOR internal bus CRYSTAL OR RESONATOR 002aac772 UART PORT 2 SPI TIMER 2 TIMER 0 TIMER 1 PCA PROGRAMMABLE COUNTER ARRAY WATCHDOG TIMER XTAL1 XTAL2 PORT 3P3[7:0] P2[7:0] PORT 1P1[7:0] PORT 0P0[7:0] CEX[4:0] TXD RXD T2EX SPICLK MOSI MISO SS P89V51RB2/RC2/RD2

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 4 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core 5. Pinning information

5.1 Pinning

Fig 2. PLCC44 pin conﬁguration P89V51RB2FA P89V51RC2FA P89V51RD2FA P1.5/MOSI/CEX2 P0.4/AD4 P1.6/MISO/CEX3 P0.5/AD5 P1.7/SPICLK/CEX4 P0.6/AD6 RST P0.7/AD7 P3.0/RXD n.c. P3.1/TXD P2.7/A15 P3.4/T0 P2.6/A14 P3.5/T1 P2.5/A13 P1.4/SS/CEX1 P1.3/CEX0 XTAL2 P1.2/ECI XTAL1 P1.1/T2EX V SS P1.0/T2 n.c. n.c. P2.0/A8 V DD P2.1/A9 P0.0/AD0 P2.2/A10 P0.1/AD1 P2.3/A11 P0.2/AD2 P2.4/A12 P0.3/AD3 002aaa810 EA ALE/PROG PSEN P3.6/WR P3.7/RD P3.3/INT1 P3.2/INT0 n.c.

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 5 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Fig 3. DIP40 pin conﬁguration Fig 4. TQFP44 pin conﬁguration P89V51RB2FN P89V51RC2FN P89V51RD2BN P89V51RD2FN P1.0/T2 V DD P1.1/T2EX P0.0/AD0 P1.2/ECI P0.1/AD1 P1.3/CEX0 P0.2/AD2 P1.4/SS/CEX1 P0.3/AD3 P1.5/MOSI/CEX2 P0.4/AD4 P1.6/MISO/CEX3 P0.5/AD5 P1.7/SPICLK/CEX4 P0.6/AD6 RST P0.7/AD7 P3.0/RXD EA P3.1/TXD ALE/PROG P3.2/INT0 PSEN P3.3/INT1 P2.7/A15 P3.4/T0 P2.6/A14 P3.5/T1 P2.5/A13 P3.6/WR P2.4/A12 P3.7/RD P2.3/A11 XTAL2 P2.2/A10 XTAL1 P2.1/A9 V SS P2.0/A8 002aaa811 P89V51RB2BBC P89V51RC2FBC P89V51RD2FBC P1.5/MOSI/CEX2 P0.4/AD4 P1.6/MISO/CEX3 P0.5/AD5 P1.7/SPICLK/CEX4 P0.6/AD6 RST P0.7/AD7 P3.0/RXD n.c. P3.1/TXD P2.7/A15 P3.4/T0 P2.6/A14 P3.5/T1 P2.5/A13 P1.4/SS/CEX1 P1.3/CEX0 XTAL2 P1.2/ECI XTAL1 P1.1/T2EX V SS P1.0/T2 n.c. n.c. P2.0/A8 V DD P2.1/A9 P0.0/AD0 P2.2/A10 P0.1/AD1 P2.3/A11 P0.2/AD2 P2.4/A12 P0.3/AD3 002aaa812 EA ALE/PROG PSEN P3.6/WR P3.7/RD P3.3/INT1 P3.2/INT0 n.c.

5.2 Pin description

Table 3. P89V51RB2/RC2/RD2 pin description P0.0 to P0.7 I/O Port 0:Port 0 is an 8-bit open drain bidirectional I/O port. the code bytes during the external host mode veriﬁcation. or as a general purpose I/O port. I/O AD0 — Address/data bit 0. I/O AD1 — Address/data bit 1. I/O AD2 — Address/data bit 2. I/O AD3 — Address/data bit 3. I/O AD4 — Address/data bit 4. I/O AD5 — Address/data bit 5. I/O AD6 — Address/data bit 6. I/O AD7 — Address/data bit 7.

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. I/O CEX0 — Capture/compare external I/O for PCA Module 0. I SS — Slave port select input for SPI. I/O CEX1 — Capture/compare external I/O for PCA Module 1. I/O MOSI — Master Output Slave Input for SPI. I/O CEX2 — Capture/compare external I/O for PCA Module 2. I/O MISO — Master Input Slave Output for SPI. I/O CEX3 — Capture/compare external I/O for PCA Module 3. I/O SPICLK — Serial clock input/output for SPI. I/O CEX4 — Capture/compare external I/O for PCA Module 4.

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. external host mode programming and veriﬁcation. I INT0 — External interrupt 0 input. I INT1 — External interrupt 1 input. I T0 — External count input to Timer/counter 0. I T1 — External count input to Timer/counter 1. O WR — External data memory write strobe. O RD — External data memory read strobe.

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. modes other than normal working mode. The solution is to add a pull-up resistor of 3 kΩ to 50 kΩ to VDD , e.g., for ALE pin. [2] For 6-clock mode, ALE is emitted at1⁄3 of crystal frequency. memory. However, if AO is set to ‘1’, ALE is disabled. input to the internal clock generator circuits. XTAL2 18 14 20 O Crystal 2: Output from the inverting oscillator ampliﬁer. Table 3. P89V51RB2/RC2/RD2 pin description …continued

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 10 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core 6. Functional description

6.1 Special function registers

Remark: SFR accesses are restricted in the following ways:

User mustnot attempt to access any SFR locations not deﬁned.
Accesses to any deﬁned SFR locations must be strictly for the functions for the SFRs.
SFR bits labeled ‘-’, ‘0’ or ‘1’ canonly be written and read as follows: – ‘-’ Unless otherwise speciﬁed,must be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives. – ‘0’must be written with ‘0’, and will return a ‘0’ when read. – ‘1’must be written with ‘1’, and will return a ‘1’ when read.

6.2 Memory organization

The device has separate address spaces for program and data memory.

6.2.1 Flash program memory bank selection

when executing user code within the address range 0000H to 1FFFH.

6.2.2 Power-on reset code execution

however, the contents of the on-chip RAM during power up are indeterminate. exceed 1 ms and the oscillator start-up time does not exceed 10 ms. Table 5. Code memory bank selection

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 15 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core to work during initial power up, before the voltage reaches the brownout detection level. The POF ﬂag in the PCON register is set to indicate an initial power up condition. The POF ﬂag will remain active until cleared by software. Following a power-on or external reset the P89V51RB2/RC2/RD2 will force the SWR and BSEL bits (FCF[1:0]) = 00. This causes the boot block to be mapped into the lower 8 kB of code memory and the device will execute the ISP code in the boot block and attempt to autobaud to the host. If the autobaud is successful the device will remain in ISP mode. If, after approximately 400 ms, the autobaud is unsuccessful the boot block code will check to see if the SoftICE ﬂag is set (from a previous programming operation). If the SoftICE ﬂag is set the device will enter SoftICE mode. If the SoftICE ﬂag is cleared, the boot code will execute a software reset causing the device to execute the user code from block 0 starting at address 0000H. Note that an external reset applied to the RST pin has the same effect as a power-on reset.

6.2.3 Software reset

A software reset is executed by changing the SWR bit (FCF .1) from ‘0’ to ‘1’. A software reset will reset the program counter to address 0000H and force both the SWR and BSEL bits (FCF[1:0]) = 10. This will result in the lower 8 kB of the user code memory being mapped into the user code memory space. Thus the user's code will be executed starting at address 0000H. A software reset will not change WDTC.2 or RAM data. Other SFRs will be set to their reset values.

6.2.4 Brownout detect reset

The device includes a brownout detection circuit to protect the system from severe supply voltage ﬂuctuations. The P89V51RB2/RC2/RD2's brownout detection threshold is 2.35 V. When V DD drops below this voltage threshold, the brownout detect triggers the circuit to generate a brownout interrupt but the CPU still runs until the supplied voltage returns to the brownout detection voltage V BOD . The default operation for a brownout detection is to cause a processor reset. Fig 5. Power-on reset circuit 002aaa543 VDD VDD 8.2 kΩ RST XTAL2 XTAL1 C 1 C 2 10 µF

6.2.5 Watchdog reset

8 kB of user code memory space. This results in the code memory bank selections as shown.

6.2.6 Data RAM memory

6.2.7 Expanded data RAM addressing

memor y structure” on page 19.

The lower 128 B of RAM (00H to 7FH) are directly and indirectly addressable.
The higher 128 B of RAM (80H to FFH) are indirectly addressable.
The special function registers (80H to FFH) are directly addressable only.
The expanded RAM of 768 B (00H to 2FFH) is indirectly addressable by the move

Table 4 “Special function registers” on page 11). Table 6. Effects of reset sources on bank selection BSEL = 00 then uses boot code.

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. written to RAM location 90H rather than port 1. occupies the ﬁrst 768 B of external memory (addresses 000H to 2FFH). instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. With EXTRAM = 0, the expanded RAM can be accessed as in the following example. Table 7. AUXR - Auxiliary register (address 8EH) bit allocation Table 8. AUXR - Auxiliary register (address 8EH) bit description 7 to 2 - Reserved for future use. Should be set to ‘0’ by user programs. external data memory by default. active only during a MOVX or MOVC.

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. as write and read timing signals. When EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 8051. [1] Access limited to ERAM address within OSPI to 0FFH; cannot access 100H to 02FFH. Table 9. External data memoryRD, WR with EXTRAM bit[1]

6.2.8 Dual data pointers

The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1 determines which of the two data pointers is accessed. When DPS = 0, DPTR0 is selected; when DPS = 1, DPTR1 is selected. Quickly switching between the two data pointers can be accomplished by a single INC instruction on AUXR1 (see Figure7). Fig 6. Internal and external data memory structure 000H 2FFH 00H FFH UPPER 128 B INTERNAL RAM LOWER 128 B INTERNAL RAM (INDIRECT AND DIRECT ADDRESSING) (INDIRECT ADDRESSING) (DIRECT ADDRESSING) SPECIAL FUNCTION REGISTERS (SFRs)80H FFH FFFFH 000H EXTERNAL DATA MEMORY EXTERNAL DATA MEMORY 2FFH 0000H EXTRAM = 0 EXTRAM = 1 EXPANDED RAM 0300H (INDIRECT ADDRESSING) (INDIRECT ADDRESSING) (INDIRECT ADDRESSING) FFFFH 80H 7FH 002aaa517 EXPANDED RAM 768 B

6.3 Flash memory IAP

6.3.1 Flash organization

end-user application by calling low-level routines through a common entry point (IAP). using a commercially available EPROM programmer which supports this device.

6.3.2 Boot block (block 1)

operations include erase user code, program user code, program security bits, etc. Table 10. AUXR1 - Auxiliary register 1 (address A2H) bit allocation Table 11. AUXR1 - Auxiliary register 1 (address A2H) bit description 7 to 4 - Reserved for future use. Should be set to ‘0’ by user programs. 3 GF2 General purpose user-deﬁned ﬂag. incrementing AUXR1, without interfering with other bits in the register. 1 - Reserved for future use. Should be set to ‘0’ by user programs. program. See text for details.

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 21 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core A chip-erase operation can be performed using a commercially available parallel programer. This operation will erase the contents of this boot block and it will be necessary for the user to reprogram this boot block (block 1) with the NXP-provided ISP/IAP code in order to use the ISP or IAP capabilities of this device. Go to http://www.nxp.com/support for questions or to obtain the hex ﬁle for this device.

6.3.3 ISP

ISP is performed without removing the microcontroller from the system. The ISP facility consists of a series of internal hardware resources coupled with internal ﬁrmware to facilitate remote programming of the P89V51RB2/RC2/RD2 through the serial port. This ﬁrmware is provided by NXP and embedded within each P89V51RB2/RC2/RD2 device. The NXP ISP facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The ISP function uses ﬁve pins (V DD , VSS , TXD, RXD, and RST). Only a small connector needs to be available to interface your application to an external circuit in order to use this feature.

6.3.4 Using ISP

The ISP feature allows for a wide range of baud rates to be used in your application, independent of the oscillator frequency. It is also adaptable to a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the P89V51RB2/RC2/RD2 to establish the baud rate. The ISP ﬁrmware provides auto-echo of received characters. Once baud rate initialization has been performed, the ISP ﬁrmware will only accept Intel Hex-type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below: :NNAAAARRDD..DDCC<crlf> In the Intel Hex record, the ‘NN’ represents the number of data bytes in the record. The P89V51RB2/RC2/RD2 will accept up to 32 data bytes. The ‘AAAA’ string represents the address of the ﬁrst byte in the record. If there are zero bytes in the record, this ﬁeld is often set to 0000. The ‘RR’ string indicates the record type. A record type of ‘00’ is a data record. A record type of ‘01’ indicates the end-of-ﬁle mark. In this application, additional record types will be added to indicate either commands or data for the ISP facility. The maximum number of data bytes in a record is limited to 32 (decimal). ISP commands are summarized in Table12. As a record is received by the P89V51RB2/RC2/RD2, the information in the record is stored internally and a checksum calculation is performed. The operation indicated by the record type is not performed until the entire record has been received. Should an error occur in the checksum, the P89V51RB2/RC2/RD2 will send an ‘X’ out the serial port indicating a checksum error. If the checksum calculation is found to match the checksum in the record, then the command will be executed. In most cases, successful reception of the record will be indicated by transmitting a ‘.’ character out the serial port.

00 Program User Code Memory

01 End of File (EOF), no operation

02 Set SoftICE mode

code memory, erase device serial number.

03 Miscellaneous Write Functions

04 Display Device Data or Blank Check

05 Miscellaneous Read Functions

06 Direct Load of Baud Rate

07 Reset serial number, erase user code, clear SoftICE mode

08 Verify serial number

6.3.5 Using the serial number

entered, the serial number length is evaluated to determine if the serial number is in use. addition, the ‘reset serial number’ record will also erase all user code.

6.3.6 IAP method

09 Write serial number

6.4 Timers/counters 0 and 1

either as timers or event counters (seeTable14 andTable15). 1⁄6 of the oscillator frequency. Timer 0 and Timer 1 have four operating modes from which to select.

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Table 14. TMOD - Timer/counter mode control register (address 89H) bit allocation Table 15. TMOD - Timer/counter mode control register (address 89H) bit description enabled whenever ‘TRx’ control bit is set. Table 16. TMOD - Timer/counter mode control register (address 89H) M1/M0 operating timer only controlled by Timer 1 control bits. 1 1 3 (Timer 1) Timer/counter 1 stopped. Table 17. TCON - Timer/counter control register (address 88H) bit allocation Table 18. TCON - Timer/counter control register (address 88H) bit description 7 TF1 Timer 1 overﬂow ﬂag. Set by hardware on Timer/counter overﬂow. 5 TF0 Timer 0 overﬂow ﬂag. Set by hardware on Timer/counter overﬂow.

6.4.1 Mode 0

Counter with a ﬁxed divide-by-32 prescaler.Figure8 shows mode 0 operation. different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

6.4.2 Mode 1

edge/low level that triggers external interrupt 1. edge/low level that triggers external interrupt 0.

6.4.3 Mode 2

Mode 2 conﬁgures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown inFigure10. Overﬂow from TLn not only sets TFn, but also reloads TLn with the contents of THn, which must be preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer 0 and Timer 1.

6.4.4 Mode 3

When timer 1 is in mode 3 it is stopped (holds its count). The effect is the same as setting T R 1=0 . Timer 0 in mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for mode 3 and Timer 0 is shown in Figure11. TL0 uses the Timer 0 control bits: T0C/T, T0GATE, TR0,INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the ‘Timer 1’ interrupt. Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in mode 3, the P89V51RB2/RC2/RD2 can look like it has an additional Timer. Note: When Timer 0 is in mode 3, Timer 1 can be turned on and off by switching it into and out of its own mode 3. It can still be used by the serial port as a baud rate generator, or in any application not requiring an interrupt. Fig 9. Timer/counter 0 or 1 in mode 1 (16-bit counter) 002aaa520 osc/6 Tn pin TRn TnGate INTn pin C/T = 0 C/T = 1 TLn (8-bits) THn (8-bits) TFn control overflow interrupt Fig 10. Timer/counter 0 or 1 in mode 2 (8-bit auto-reload) 002aaa521 osc/6 Tn pin TRn TnGate INTn pin TLn (8-bits) THn (8-bits) TFn control overflow reload interrupt C/T = 0 C/T = 1

6.5 Timer 2

Table21) and T2MOD (Table22 andTable23). Table 19. Timer 2 operating mode

1 X 1 0 baud rate generator

Table 20. T2CON - Timer/counter 2 control register (address C8H) bit allocation Table 21. T2CON - Timer/counter 2 control register (address C8H) bit description

7 TF2 Timer 2 overﬂow ﬂag set by a Timer 2 overﬂow and must be cleared by

Timer 2 is in Clock-out mode.

6 EXF2 Timer 2 external ﬂag is set when Timer 2 is in capture, reload or

causes Timer 1 overﬂow to be used for the receive clock.

6.5.1 Capture mode

upon overﬂowing sets bit TF2, the Timer 2 overﬂow bit. The capture mode is illustrated inFigure12. causes Timer 1 overﬂows to be used for the transmit clock. 2 TR2 Start/stop control for Timer 2. A logic ‘1’ enables the timer to run. ignored and the timer is forced to auto-reload on Timer 2 overﬂow. Table 22. T2MOD - Timer 2 mode control register (address C9H) bit allocation Table 23. T2MOD - Timer 2 mode control register (address C9H) bit description 7 to 2 - Reserved for future use. Should be set to ‘0’ by user programs.

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 33 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IEN0 register). If EXEN2 = 1, Timer 2 operates as described above, but with the added feature that a 1-to-0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 overﬂow interrupt). The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt. There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2 pin transitions or f osc / 6 pulses. Since once loaded contents of RCAP2L and RCAP2H registers are not protected, once Timer2 interrupt is signalled it has to be serviced before new capture event on T2EX pin occurs. Otherwise, the next falling edge on T2EX pin will initiate reload of the current value from TL2 and TH2 to RCAP2L and RCAP2H and consequently corrupt their content related to previously reported interrupt.

6.5.2 Auto-reload mode (up or down counter)

In the 16-bit auto-reload mode, Timer 2 can be conﬁgured as either a timer or counter (via T2 in T2CON), then programmed to count up or down. The counting direction is determined by bit DCEN (Down Counter Enable) which is located in the T2MOD register (see Table22 andTable23). When reset is applied, DCEN = 0 and Timer 2 will default to counting up. If the DCEN bit is set, Timer 2 can count up or down depending on the value of the T2EX pin. Figure13 shows Timer 2 counting up automatically (DCEN = 0). Fig 12. Timer 2 in Capture mode 002aaa523 OSC ÷6 T2 pin C/T2 = 0 C/T2 = 1 TL2 (8-bits) TH2 (8-bits) TF2 control capture TR2 timer 2 interrupt EXF2 RCAP2L RCAP2H control EXEN2 transition detector T2EX pin

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 34 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core In this mode, there are two options selected by bit EXEN2 in T2CON register. If EXEN2 = 0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overﬂow Flag) bit upon overﬂow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software means. Auto reload frequency when Timer 2 is counting up can be determined from this formula: (1) Where SupplyFrequency is either f osc (C/T2 = 0) or frequency of signal on T2 pin (C/T2 = 1). If EXEN2 = 1, a 16-bit reload can be triggered either by an overﬂow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 is ‘1’. Microcontroller’s hardware will need three consecutive machine cycles in order to recognize falling edge on T2EX and set EXF2 = 1: in the ﬁrst machine cycle pin T2EX has to be sampled as ‘1’; in the second machine cycle it has to be sampled as ‘0’, and in the third machine cycle EXF2 will be set to ‘1’. In Figure14, DCEN = 1 and Timer 2 is enabled to count up or down. This mode allows pin T2EX to control the direction of count. When a logic ‘1’ is applied at pin T2EX Timer 2 will count up. Timer 2 will overﬂow at 0FFFFH and set the TF2 ﬂag, which can then generate an interrupt, if the interrupt is enabled. This timer overﬂow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2. Fig 13. Timer 2 in auto-reload mode (DCEN = 0) 002aaa524 OSC ‚6 T2 pin C/T2 = 0 C/T2 = 1 TL2 (8-bits) TH2 (8-bits) TF2 control reload TR2 timer 2 interrupt EXF2 RCAP2L RCAP2H control EXEN2 transition detector T2EX pin SupplyFrequency

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 35 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underﬂow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underﬂow sets the TF2 ﬂag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2. The external ﬂag EXF2 toggles when Timer 2 underﬂows or overﬂows. This EXF2 bit can be used as a 17th bit of resolution if needed.

6.5.3 Programmable clock-out

A 50 % duty cycle clock can be programmed to come out on pin T2 (P1.0). This pin, besides being a regular I/O pin, has two additional functions. It can be programmed: 1. To input the external clock for Timer/counter 2, or 2. To output a 50 % duty cycle clock ranging from 122 Hz to 8 MHz at a 16 MHz operating frequency. To conﬁgure the Timer/counter 2 as a clock generator, bit C/ T2 (in T2CON) must be cleared and bit T2OE in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in Equation2: (2) Where (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator.

6.5.4 Baud rate generator mode

Bits TCLK and/or RCLK in T2CON allow the UART) transmit and receive baud rates to be derived from either Timer 1 or Timer 2 (See Section 6.6 “UAR Ts” on page 37 for details). When TCLK = 0, Timer 1 is used as the UART transmit baud rate generator. When Fig 14. Timer 2 in Auto Reload mode (DCEN = 1) 002aaa525 TL2 (8-bits) TH2 (8-bits) TF2 EXF2 underflow timer 2 interrupt RCAP2L RCAP2H FFH FFH overflow (down-counting reload value) (up-counting reload value) count direction 1 = up 0 = down T2EX pin toggle OSC ÷6 T2 pin C/T2 = 0 C/T2 = 1 control TR2 OscillatorFrequency

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 36 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core TCLK = 1, Timer 2 is used as the UART transmit baud rate generator. RCLK has the same effect for the UART receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates – Timer 1 or Timer 2. Figure15 shows Timer 2 in baud rate generator mode: The baud rate generation mode is like the auto-reload mode, when a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in modes 1 and 3 are determined by Timer 2’s overﬂow rate given below: Modes 1 and 3 baud rates = Timer 2 Overﬂow Rate / 16 The timer can be conﬁgured for either ‘timer’ or ‘counter’ operation. In many applications, it is conﬁgured for ‘timer' operation (C/ T2 = 0). Timer operation is different for Timer 2 when it is being used as a baud rate generator. Usually, as a timer it would increment every machine cycle (i.e.,1⁄6 the oscillator frequency). As a baud rate generator, it increments at the oscillator frequency. Thus the baud rate formula is as follows: Modes 1 and 3 baud rates = (3) n = 32 in X1 mode, 16 in X2 mode Where: (RCAP2H, RCAP2L) = The content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. The Timer 2 as a baud rate generator mode is valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode. Also if the EXEN2 (T2 external enable ﬂag) is set, a 1-to-0 transition in T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 external ﬂag) but will Fig 15. Timer 2 in Baud Rate Generator mode 002aaa526 TX/RX baud rate timer 2 interrupt OSC ÷2 T2 pin C/T2 = 0 C/T2 = 1 TL2 (8-bits) TH2 (8-bits) control TR2 EXF2 RCAP2L RCAP2H control EXEN2 transition detector T2EX pin reload OscillatorFrequency

6.5.5 Summary of baud rate equations

6.6 UARTs

UART include Framing Error detection, and automatic address recognition.

6.6.1 Mode 0

1⁄6 of the CPU clock frequency. whether it sends or receives data on RXD line. Table 24. Timer 2 generated commonly used baud rates

600 Bd 12 MHz FB 1E

220 Bd 12 MHz F2 AF

600 Bd 6 MHz FD 8F

220 Bd 6 MHz F9 57

6.6.2 Mode 1

6.6.3 Mode 2

6.6.4 Mode 3

Table 25. SCON - Serial port control register (address 98H) bit allocation Table 26. SCON - Serial port control register (address 98H) bit description

6 SM1 With SM0, deﬁnes the serial port mode (see

5 SM2 Enables the multiprocessor communication feature in modes 2 and 3. software to disable reception.

6.6.5 Framing error

6.6.6 More about UART mode 1

boundaries of the incoming bit times. register, and reception of the rest of the frame will proceed. (b) either SM2 = 0, or the received stop bit = 1.

6.6.7 More about UART modes 2 and 3

Reception is performed in the same manner as in mode 1. transmission. Must be cleared by software. modes. (See SM2 for exceptions). Must be cleared by software. Table 27. SCON - Serial port control register (address 98H) SM0/SM1 mode deﬁnition

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 40 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the ﬁnal shift pulse is generated: (a) RI = 0, and (b) either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the ﬁrst 8 data bits go into SBUF .

6.6.8 Multiprocessor communications

UART modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received or transmitted. When data is received, the 9th bit is stored in RB8. The UART can be programmed so that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. One way to use this feature in multiprocessor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it ﬁrst sends out an address byte which identiﬁes the target slave. An address byte differs from a data byte in a way that the 9th bit is ‘1’ in an address byte and ‘0’ in the data byte. With SM2 = 1, no slave will be interrupted by a data byte, i.e. the received 9th bit is ‘0’. However, an address byte having the 9th bit set to ‘1’ will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed or not. The addressed slave will clear its SM2 bit and prepare to receive the data (still 9 bits long) that follow. The slaves that weren’t being addressed leave their SM2 bits set and go on about their business, ignoring the subsequent data bytes. SM2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit, although this is better done with the Framing Error ﬂag. When UART receives data in mode 1 and SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.

6.6.9 Automatic address recognition

Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled for the UART by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt ﬂag (RI) will be automatically set when the received byte contains either the ‘Given’ address or the ‘Broadcast' address. The 9 bit mode requires that the 9th information bit is a ‘1’ to indicate that the received information is an address and not data. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two Special Function Registers are used to deﬁne the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to deﬁne which bits in the SADDR are to be used and which bits are ‘don’t care’. The SADEN mask can be logically ANDed with the SADDR to create the ‘Given’ address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. This device uses the methods presented in Figure16 to determine if a ‘Given’ or ‘Broadcast’ address has been received or not.

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 41 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core The following examples will help to show the versatility of this scheme. Example 1, slave 0: (4) Example 2, slave 1: (5) In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a ‘0’ in bit 0 and it ignores bit 1. Slave 1 requires a ‘0’ in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a ‘0’ in bit 1. A unique address for slave 1 would be 1100 0001 since a ‘1’ in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit0=0( f o rs l a v e0 )a n db i t1=0( f o rs l a v e1 ) .Thus, both could be addressed with 1100 0000. Fig 16. Schemes used by the UART to detect ‘given’ and ‘broadcast’ addresses when multiprocessor communications is enabled 002aaa527 rx_byte(7) saddr(7) saden(7) rx_byte(0) saddr(0) given_address_match logic used by UART to detect 'given address' in received data saddr(7) saden(7) rx_byte(7) saddr(0) saden(0) rx_byte(0) broadcast_address_match logic used by UART to detect 'given address' in received data saden(0) SADDR = 1100 0000 SADEN = 1111 1101 SADDR = 1100 0000 SADEN = 1111 1110

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 42 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Example 1, slave 0: (6) Example 2, slave 1: (7) Example 3, slave 2: (8) In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit1=0 and it can be uniquely addressed by 1110 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are treated as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR and SADEN are loaded with 0s. This produces a given address of all ‘don’t cares’ as well as a Broadcast address of all ‘don’t cares'. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature.

6.7 SPI

6.7.1 SPI features

Master or slave operation
10 MHz bit frequency (max)
LSB ﬁrst or MSB ﬁrst data transfer
Four programmable bit rates
End of transmission (SPIF)
Write collision ﬂag protection (WCOL)
Wake-up from Idle mode (slave mode only)

6.7.2 SPI description

The SPI allows high-speed synchronous data transfer between the P89V51RB2/RC2/RD2 and peripheral devices or between several P89V51RB2/RC2/RD2 devices. Figure17 shows the correspondence between master and slave SPI devices. The SPICLK pin is the SADDR = 1100 0000 SADEN = 1111 1001 SADDR = 1110 0000 SADEN = 1111 1010 SADDR = 1100 0000 SADEN = 1111 1100

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. active and the MOSI/P1[5] port can also be used as an input port pin. show the four possible combinations of these two bits. Table 28. SPCR - SPI control register (address D5H) bit allocation Table 29. SPCR - SPI control register (address D5H) bit description 7 SPIE If both SPIE and ES are set to one, SPI interrupts are enabled. 6 SPE SPI enable bit. When set enables SPI. 4 MSTR Master/slave select. 1 = master mode, 0 = slave mode. 0 = SPICLK is low when idle (active HIGH).

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. clock; 0 = shift triggered on the leading edge of the clock. Table 30. SPCR - SPI control register (address D5H) clock rate selection Table 31. SPSR - SPI status register (address AAH) bit allocation Table 32. SPSR - SPI status register (address AAH) bit description 7 SPIF SPI interrupt ﬂag. Upon completion of data transfer, this bit is set to ‘1’. data transfer. This bit is cleared by software. 5 to 0 - Reserved for future use. Should be set to ‘0’ by user programs.

6.8 Watchdog timer

The device offers a programmable Watchdog Timer (WDT) for fail safe protection against software deadlock and automatic recovery. To protect the system against software deadlock, the user software must refresh the WDT within a user-deﬁned time period. If the software fails to do this periodical refresh, an internal hardware reset will be initiated if enabled (WDRE = 1). The software can be designed such that the WDT times out if the program does not work properly. The WDT in the device uses the system clock (XTAL1) as its time base. So strictly speaking, it is a Watchdog counter rather than a WDT. The WDT register will increment every 344064 crystal clocks. The upper 8-bits of the time base register (WDTD) are used as the reload register of the WDT. The WDTS ﬂag bit is set by WDT overﬂow and is not changed by WDT reset. User software can clear WDTS by writing ‘1' to it. Figure20 provides a block diagram of the WDT. Two SFRs (WDTC and WDTD) control WDT operation. During Idle mode, WDT operation is temporarily suspended, and resumes upon an interrupt exit from idle. The time-out period of the WDT is calculated as follows: Period = (255− WDTD) × 344064× 1/f CLK(XTAL1) where WDTD is the value loaded into the WDTD register and fosc is the oscillator frequency. Fig 19. SPI transfer format with CPHA = 1 002aaa530 MSB SPICLK cycle # (for reference) SPICLK (CPOL = 0) SPICLK (CPOL = 1) MOSI (from master) MISO (from slave) SS (to slave) 12345678 M S B 654321 L S B 4 3 2 1 LSB Fig 20. Block diagram of programmable WDT 002aaa531 WDT UPPER BYTE WDT reset internal reset 344064 clksCLK (XTAL1) external reset WDTC COUNTER WDTD

6.9 PCA

modes: rising and/or falling edge capture, software timer, high-speed output, or PWM. Table 33. WDTC - Watchdog control register (address COH) bit allocation Table 34. WDTC - Watchdog control register (address COH) bit description 7 to 5 - Reserved for future use. Should be set to ‘0’ by user programs. Watchdog reset will drive the reset pin active for 32 clocks.

2 WDTS Watchdog timer reset ﬂag, when set indicates that a WDT reset

occurred. Reset in software. 1 WDT Watchdog timer refresh. Set by software to force a WDT reset.

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 47 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core In the CMOD SFR there are three additional bits associated with the PCA. They are CIDL which allows the PCA to stop during Idle mode, WDTE which enables or disables the Watchdog function on module 4, and ECF which when set causes an interrupt and the PCA overﬂow ﬂag CF (in the CCON SFR) to be set when the PCA timer overﬂows. The watchdog timer function is implemented in module 4 of PCA. The CCON SFR contains the run control bit for the PCA (CR) and the ﬂags for the PCA timer (CF) and each module (CCF4:0). To run the PCA the CR bit (CCON.6) must be set by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when the PCA counter overﬂows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. Bits 0 through 4 of the CCON register are the ﬂags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These ﬂags can only be cleared by software. All the modules share one interrupt vector. The PCA interrupt system is shown in Figure22. Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. The registers contain the bits that control the mode that each module will operate in. The ECCF bit (from CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module) enables the CCFn ﬂag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module (see Figure22). PWM (CCAPMn.1) enables the pulse width modulation mode. The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module’s capture/compare register. The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module’s capture/compare register. The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output.

7 CIDL Counter Idle Control: CIDL = 0 programs the PCA Counter to continue

6 WDTE Watchdog Timer Enable: WDTE = 0 disables watchdog timer function

on module 4. WDTE = 1 enables it. 5 to 3 - Reserved for future use. Should be set to ‘0’ by user programs.

0 ECF PCA Enable Counter Overﬂow Interrupt: ECF = 1 enables CF bit in

CCON to generate an interrupt. ECF = 0 disables that function.

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Table 37. CMOD - PCA counter mode register (address D9H) count pulse select Table 38. CCON - PCA counter control register (address 0D8H) bit allocation Table 39. CCON - PCA counter control register (address 0D8H) bit description either hardware or software but can only be cleared by software. on. Must be cleared by software to turn the PCA counter off. 5 - Reserved for future use. Should be set to ‘0’ by user programs. capture occurs. Must be cleared by software. capture occurs. Must be cleared by software. capture occurs. Must be cleared by software. capture occurs. Must be cleared by software. capture occurs. Must be cleared by software. Table 40. CCAPMn - PCA modules compare/capture register (address CCAPM0 0DAH, Table 41. CCAPMn - PCA modules compare/capture register (address CCAPM0 0DAH, 7 - Reserved for future use. Should be set to ‘0’ by user programs. 6 ECOMn Enable Comparator. ECOMn = 1 enables the comparator function. 5 CAPPn Capture Positive, CAPPn = 1 enables positive edge capture. 4 CAPNn Capture Negative, CAPNn = 1 enables negative edge capture.

6.9.1 PCA capture mode

capture registers (CCAPnL and CCAPnH). module’s compare/capture register causes the CEXn pin to toggle. used as a pulse width modulated output. CCON register to generate an interrupt. Table 42. PCA module modes (CCAPMn register)

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 51 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated. 6.9.2 16-bit software timer mode The PCA modules can be used as software timers (Figure24) by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module’s capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set. Fig 23. PCA capture mode 002aaa538 CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 CCON (D8H) PCA interrupt PCA timer/counter - ECOMn 0 000 CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4 (DAH to DEH) CH CL CCAPnH CCAPnL capture (to CCFn) CEXn

6.9.3 High-speed output mode

In this mode (Figure25) the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must be set. Fig 24. PCA compare mode 002aaa539 CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 CCON (D8H) PCA interrupt - ECOMn 00 100 CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4 (DAH to DEH) 16-BIT COMPARATOR PCA timer/counter CH CL match (to CCFn) CCAPnH CCAPnL enable write to CCAPnH write to CCAPnL reset

6.9.4 PWM mode

All of the PCA modules can be used as PWM outputs (Figure26). Output frequency depends on the source for the PCA timer. All of the modules will have the same frequency of output because they all share one and only PCA timer. The duty cycle of each module is independently variable using the module’s capture register CCAPnL. When the value of the PCA CL SFR is less than the Fig 25. PCA high-speed output mode 002aaa540 toggle CEXn CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 CCON (D8H) PCA interrupt - ECOMn 00 100 CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4 (DAH to DEH) 16-BIT COMPARATOR PCA timer/counter CH CL match (to CCFn) CCAPnH CCAPnL enable write to CCAPnH write to CCAPnL reset Fig 26. PCA PWM mode 002aaa541 - ECOMn 01 0 001 1 CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4 (DAH to DEH) CCAPnL 8-BIT COMPARATOR PCA timer/counter CCAPnH CL enable CEXn CL < CCAPnL CL ≥ CCAPnL

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 54 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core value in the module’s CCAPnL SFR the output will be low, when it is equal to or greater than the output will be high. When CL overﬂows from FF to 00, CCAPnL is reloaded with the value in CCAPnH. This allows updating the PWM without glitches. The PWM and ECOM bits in the module’s CCAPMn register must be set to enable the PWM mode.

6.9.5 PCA watchdog timer

An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a Watchdog. However, this module can still be used for other modes if the Watchdog is not needed. Figure26 shows a diagram of how the Watchdog works. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. User’s software then must periodically change (CCAP4H,CCAP4L) to keep a match from occurring with the PCA timer (CH,CL). This code is given in the WATCHDOG routine shown above. In order to hold off the reset, the user has three options: 1. Periodically change the compare value so it will never match the PCA timer. 2. Periodically change the PCA timer value so it will never match the compare values. 3. Disable the Watchdog by clearing the WDTE bit before a match occurs and then re-enable it. The ﬁrst two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base forall modules; changing the time base for other modules would not be a good idea. Thus, in most applications the ﬁrst solution is the best option. ;CALL the following WATCHDOG subroutine periodically. CLR EA ;Hold off interrupts MOV CCAP4L,#00 ;Next compare value is within 255 counts of current PCA timer value MOV CCAP4H,CH SETB EA ;Re-enable interrupts RET This routine should not be part of an interrupt service routine, because if the program counter goes astray and gets stuck in an inﬁnite loop, interrupts will still be serviced and the Watchdog will keep getting reset. Thus, the purpose of the Watchdog would be defeated. Instead, call this subroutine from the main program within 2 16 count of the PCA timer.

6.10 Security bit

programmer should prompt the user and program a serial number into the device.

6.11 Interrupt priority and polling sequence

Table 43. Interrupt polling sequence

7 EA Interrupt Enable Bit: EA = 1 interrupt(s) can be serviced, EA = 0

interrupt servicing disabled. 6 EC PCA Interrupt Enable bit. 5 ET2 Timer 2 Interrupt Enable. 4 ES Serial Port Interrupt Enable. 3 ET1 Timer 1 Overﬂow Interrupt Enable. 2 EX1 External Interrupt 1 Enable. 1 ET0 Timer 0 Overﬂow Interrupt Enable. 0 EX0 External Interrupt 0 Enable. Table 46. IEN1 - Interrupt enable register 1 (address E8H) bit allocation Table 47. IEN1 - Interrupt enable register 1 (address E8H) bit description 7 to 4 - Reserved for future use. Should be set to ‘0’ by user programs. 3 EBO Brownout Interrupt Enable. 1 = enable, 0 = disable. 2 to 0 - Reserved for future use. Should be set to ‘0’ by user programs. Table 48. IP0 - Interrupt priority 0 low register (address B8H) bit allocation Table 49. IP0 - Interrupt priority 0 low register (address B8H) bit description 7 - Reserved for future use. Should be set to ‘0’ by user programs. 6 PPC PCA interrupt priority LOW bit. 5 PT2 Timer 2 interrupt priority LOW bit. 4 PS Serial Port interrupt priority LOW bit. 3 PT1 Timer 1 interrupt priority LOW bit. 2 PX1 External interrupt 1 priority LOW bit. 1 PT0 Timer 0 interrupt priority LOW bit. 0 PX0 External interrupt 0 priority LOW bit. Table 50. IP0H - Interrupt priority 0 high register (address B7H) bit allocation

6.12 Power-saving modes

consumption is critical. The two modes are Idle and Power-down, seeTable56.

6.12.1 Idle mode

Table 51. IP0H - Interrupt priority 0 high register (address B7H) bit description 7 - Reserved for future use. Should be set to ‘0’ by user programs. 6 PPCH PCA interrupt priority HIGH bit. 5 PT2H Timer 2 interrupt priority HIGH bit. 4 PSH Serial Port interrupt priority HIGH bit. 3 PT1H Timer 1 interrupt priority HIGH bit. 2 PX1H External interrupt 1 priority HIGH bit. 1 PT0H Timer 0 interrupt priority HIGH bit. 0 PX0H External interrupt 0 priority HIGH bit. Table 52. IP1 - Interrupt priority 1 register (address F8H) bit allocation Table 53. IP1 - Interrupt priority 1 register (address F8H) bit description 7 to 5 - Reserved for future use. Should be set to ‘0’ by user programs. 4 PBO Brownout interrupt priority bit. 3 to 0 - Reserved for future use. Should be set to ‘0’ by user programs. Table 54. IP1H - Interrupt priority 1 high register (address F7H) bit allocation Table 55. IP1H - Interrupt priority 1 high register (address F7H) bit description 7 to 5 - Reserved for future use. Should be set to ‘0’ by user programs. 4 PBOH Brownout interrupt priority bit. 3 to 0 - Reserved for future use. Should be set to ‘0’ by user programs.

6.12.2 Power-down mode

Power-down mode. A hardware reset starts the device similar to power-on reset. stabilize (normally less than 10 ms). Table 56. Power-saving modes LOW level during power -down. device similar to a power-on reset.

6.13 System clock and clock options

6.13.1 Clock input options and recommended capacitor values for oscillator

ampliﬁer (XTAL1, XTAL2), which can be conﬁgured for use as an on-chip oscillator. Oscillator Circuit Design Considerations application note.

6.13.2 Clock doubling option

set, the EDC bit in FST register will indicate 6-clock mode. consideration must be taken. Also note that the crystal output (XTAL2) will not be doubled. Table 57. Recommended values for C1 and C2 by crystal type

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Table 58. Clock doubling features Table 59. FST - Flash status register (address B6) bit allocation Table 60. FST - Flash status register (address B6) bit description 7 - Reserved for future use. Should be set to ‘0’ by user programs. 5 to 4 - Reserved for future use. Should be set to ‘0’ by user programs. 2 to 0 - Reserved for future use. Should be set to ‘0’ by user programs.

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. [1] This parameter is measured only for initial qualiﬁcation and after a design or process change that could affect this parameter. qualify ALE with a Schmitt trigger, or use an address latch with a Schmitt trigger STROBE input. PSEN = 100 pF , load capacitance for all other outputs = 80 pF . the address bits are stabilizing. maximum value when VI is approximately 2 V. [7] Pin capacitance is characterized but not tested.EA = 25 pF (max). Table 62. Static characteristics …continued

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 64 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core (1) Maximum active IDD (2) Maximum idle IDD (3) Typical active IDD (4) Typical idle IDD Fig 30. IDD vs. frequency internal clock frequency (MHz) 0 40302010 002aaa813 IDD (mA) (1) (2) (3) (4)

9.1 Explanation of symbols

Each timing symbol has 5 characters. The ﬁrst character is always a ‘T’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A — Address C — Clock D — Input data H — Logic level HIGH I — Instruction (program memory contents) L — Logic level LOW or ALE P — PSEN Q — Output data R — RD signal T — Time V — Valid W — WR signal X — No longer a valid logic level Z — High impedance (Float) Example: tAVLL = Address valid to ALE LOW time tLLPL = ALE LOW toPSEN LOW time Fig 31. External program memory read cycle 002aaa548 port 2 PSEN ALE A0 to A7 tLLAX tPLAZ tPXIZ tLLPL tAVIV tAVLL tLLIV tPLIV tPLPH INSTR IN A8 to A15 A8 to A15 A0 to A7port 0 tPXIX tPXAV tLHLL

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 67 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Fig 32. External data memory read cycle ALE PSEN port 0 port 2 RD A0 to A7 from RI to DPL DATA IN A0 to A7 from PCL INSTR IN P2.0 to P2.7 or A8 to A15 from DPH A0 to A15 from PCH tLLDV 002aaa549 tWHLH tAVDV tLLWL tAVLL tAVWL tRLRH tRLDV tLLAX tRHDZ tRHDX tRLAZ Fig 33. External data memory write cycle 002aaa550 port 2 port 0 WR PSEN ALE tLHLL P2[7:0] or A8 to A15 from DPH A0 to A7 from RI or DPL DATA OUT INSTR IN tAVLL tAVWL tLLWL tLLAX tWLWH tQVWH tWHQX tWHLH A8 to A15 from PCH A0 to A7 from PCL

40 MHz Variable

Table 65. Serial port timing

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 70 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Fig 36. SPI master timing (CPHA = 0) TSPICYC tSPICLKH tSPICLKH tSPICLKL tSPICLKL master LSB/MSB outmaster MSB/LSB out tSPIDHtSPIDSU tSPIF tSPIOH tSPIDV tSPIR tSPIDV tSPIF tSPIR tSPIF tSPIR SS SPICLK (CPOL = 0) (output) 002aaa908 SPICLK (CPOL = 1) (output) MISO (input) MOSI (output) LSB/MSB inMSB/LSB in Fig 37. SPI master timing (CPHA = 1) TSPICYC tSPICLKL tSPICLKL tSPICLKH tSPICLKH master LSB/MSB outmaster MSB/LSB out tSPIDHtSPIDSU tSPIF tSPIOH tSPIDV tSPIR tSPIDV tSPIF tSPIF tSPIR tSPIR SS SPICLK (CPOL = 0) (output) 002aaa909 SPICLK (CPOL = 1) (output) MISO (input) MOSI (output) LSB/MSB inMSB/LSB in

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 71 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Fig 38. SPI slave timing (CPHA = 0) TSPICYC tSPICLKH tSPICLKH tSPICLKL tSPICLKL tSPILEAD tSPILAG tSPIDSU tSPIDH tSPIDHtSPIDSU tSPIDSU tSPIF tSPIA tSPIOH tSPIDIS tSPIR slave MSB/LSB out MSB/LSB in LSB/MSB in slave LSB/MSB out tSPIDV tSPIOH tSPIOH tSPIDV tSPIR tSPIR tSPIF tSPIF SS SPICLK (CPOL = 0) (input) 002aaa910 SPICLK (CPOL = 1) (input) MISO (output) MOSI (input) not defined Fig 39. SPI slave timing (CPHA = 1) 002aaa911 TSPICYC tSPICLKH tSPICLKH tSPICLKLtSPILEAD tSPICLKL tSPILAG tSPIDSU tSPIDSUtSPIDH tSPIDH tSPIF tSPIR tSPIR tSPIA tSPIOH tSPIOH tSPIOH tSPIDIS slave MSB/LSB outnot defined MSB/LSB in LSB/MSB in slave LSB/MSB out tSPIDV tSPIDV tSPIDV tSPIRtSPIF tSPIF SS SPICLK (CPOL = 0) (input) SPICLK (CPOL = 1) (input) MISO (output) MOSI (input)

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 72 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Fig 40. Test load example All other pins disconnected Fig 41. IDD test condition, Active mode All other pins disconnected Fig 42. IDD test condition, Idle mode 002aaa555 to DUT to tester C L 002aaa556 VDD VDD VDD EARST XTAL2(n.c.)clock signal XTAL1 VSS IDD VDD DUT 002aaa557 VDD VDD VDD EARST XTAL2(n.c.)clock signal XTAL1 VSS IDD DUT

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 73 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core All other pins disconnected Fig 43. IDD test condition, Power-down mode 002aaa558 VDDVDD = 2 V VDD EARST XTAL2(n.c.) XTAL1 VSS IDD VDD DUT

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 74 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core 10. Package outline Fig 44. SOT129-1 (DIP40) package outline UNIT A max. 1 2 b1 cD E e M HL REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches DIMENSIONS (inch dimensions are derived from the original mm dimensions) SOT129-1 99-12-27 03-02-13 A min. A max. b Z max.wM Ee1 1.70 1.14 0.53 0.38 0.36 0.23 52.5 51.5 14.1 13.7 3.60 15.24 17.42 15.90 2.254.7 0.51 4 0.067 0.045 0.021 0.015 0.014 0.009 2.067 2.028 0.56 0.54 0.14 0.60 0.69 051G08 MO-015 SC-511-40 M H c (e )1 M E A L seating plane w M e D A 2 Z b E pin 1 index 0 5 10 mm scale Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. (1)(1)(1) DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 75 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Fig 45. SOT376-1 (TQFP44) package outline UNIT A max. A 1 A 2 A 3 bp cE (1) eH E LL p Zywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.2 0.15 0.05 1.05 0.95 0.25 0.45 0.30 0.18 0.12 10.1 9.9 0.8 12.15 11.85 1.2 0.8 o o0.2 0.10.21 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT376-1 137E08 MS-026 00-01-19 02-03-14 D (1) (1)(1) 10.1 9.9 H D 12.15 11.85 EZ 1.2 0.8 D bp e E B DH bp EH v M B D ZD A Z E e v M A 33 23 q A 1 A Lp detail X L (A )3A 2 X y c w M w M 0 2.5 5 mm scale TQFP44: plastic thin quad flat package; 44 leads; body 10 x 10 x 1.0 mm SOT376-1 pin 1 index

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 76 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Fig 46. SOT187-2 (PLCC44) package outline UNIT A A 1 min. A 4 max. bp ey wv b REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 4.57 4.19 0.51 3.05 0.53 0.33 0.021 0.013 16.66 16.51 1.27 17.65 17.40 2.16 45o 0.18 0.10.18 DIMENSIONS (mm dimensions are derived from the original inch dimensions) Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. SOT187-2 D (1) E(1) 16.66 16.51 H D H E 17.65 17.40 ZD (1) max. ZE(1) max. 2.16 0.81 0.66 k 1.22 1.07 0.180 0.165 0.02 0.12 A 3 0.25 0.01 0.656 0.650 0.05 0.695 Lp 1.44 1.02 0.057 0.040 0.656 0.650 0.695 0.685 eD eE 16.00 14.99 0.63 0.59 16.00 14.99 0.63 0.59 0.0850.032 0.026 0.048 0.042 2939 71 7 detail X (A )3 bp w M A 1 A A 4 Lp b k Xy e E B DH Ee EH v M B D Z D A Z E e v M A pin 1 index 112E10 MS-018 EDR-7319 0 5 10 mm scale 99-12-27 01-11-14 inches PLCC44: plastic leaded chip carrier; 44 leads SOT187-2 De

Table37: Changed 2nd row, fosc / 6 to fosc / 2.
Table62: Changed 12 MHz max values for IDD(oper) and IDD(idle).
Table3: Removed sentence “However, Security lock level 4 will disableEA...” fromEA pin description.
Changed SCK to SPICLK throughout data sheet.
Table3: Changed SCK to SPICLK and updated pin description. P89V51RB2_RC2_RD2_4 20070501 Product data sheet - P89V51RB2_RC2_RD2-03 P89V51RB2_RC2_RD2-03 20041202 Product data - P89V51RB2_RC2_RD2-02 P89V51RD2-02 20041011 Product data - P89V51RD2-01 P89V51RD2-01 20040301 Product data - -

P89V51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 November 2009 79 of 80 NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core 13. Legal information

13.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

13.2 Deﬁnitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

13.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control —This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.

13.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit:http://www.nxp.com For sales ofﬁce addresses, please send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 November 2009 Document identifier: P89V51RB2_RC2_RD2_5 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 15. Contents

6.13.1 Clock input options and recommended

Product Information

P89V51RC2FN specifications and overview.

Summary

8-bit 80C51 5 V low power 16/32/64 kB flash microcontroller with 1 kB RAM Rev. 05-12 November 2009

Description

8-bit 80C51 5 V low power 16/32/64 kB flash microcontroller with 1 kB RAM Rev. 05-12 November 2009

Source title P89V51RC2FN Datasheet(PDF) - NXP Semiconductors

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