Microcontroller

P89LPC933

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs Rev. 07-26 November 2008

Manufacturer: NXP Semiconductors

Document: 75 Pages / 366Kb

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Technical content

General description The P89LPC933/934/935/936 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC933/934/935/936 in order to reduce component count, board space, and system cost. 2. Features

2.1 Principal features

n 4 kB/8 kB/16 kB byte-erasable ﬂash code memory organized into 1 kB/2 kB sectors and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. n 256-byte RAM data memory. Both the P89LPC935 and P89LPC936 also include a 512-byte auxiliary on-chip RAM. n 512-byte customer data EEPROM on chip allows serialization of devices, storage of setup parameters, etc. (P89LPC935/936). n Dual 4-input multiplexed 8-bit A/D converters/DAC outputs (P89LPC935/936, single A/D on P89LPC933/934).Two analog comparators with selectable inputs and reference source. n Two 16-bit counter/timers (each may be conﬁgured to toggle a port output upon timer overﬂow or to become a PWM output) and a 23-bit system timer that can also be used as an RTC. n Enhanced UART with fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 kHz byte-wide I 2C-bus communication port and SPI communication port. n Capture/Compare Unit (CCU) provides PWM, input capture, and output compare functions (P89LPC935/936). n High-accuracy internal RC oscillator option allows operation without external oscillator components.The RC oscillator option is selectable and ﬁne tunable. n 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V). n 28-pin TSSOP , PLCC, and HVQFN packages with 23 I/O pins minimum and up to 26 I/O pins while using on-chip oscillator and reset options. P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable ﬂash with 8-bit ADCs Rev. 07 — 26 November 2008 Product data sheet

P89LPC933_934_935_936_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 26 November 2008 2 of 75 NXP Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core

2.2 Additional features

n A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI. n Serial ﬂash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. n Serial ﬂash In-System Programming (ISP) allows coding while the device is mounted in the end application. n In-Application Programming (IAP) of the ﬂash code memory. This allows changing the code in a running application. n Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from eight values. n Low voltage reset (brownout detect) allows a graceful system shutdown when power fails. May optionally be conﬁgured as an interrupt. n Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical power-down current is 1µA (total power-down with voltage comparators disabled). n Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available. n Conﬁgurable on-chip oscillator with frequency range options selected by user programmed ﬂash conﬁguration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz. n Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function. n Programmable port output conﬁguration options: quasi-bidirectional, open drain, push-pull, input-only. n Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. n LED drive capability (20 mA) on all port pins. A maximum limit is speciﬁed for the entire chip. n Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. n Only power and ground connections are required to operate the P89LPC933/934/935/936 when internal reset option is selected. n Four interrupt priority levels. n Eight keypad interrupt inputs, plus two additional external interrupt inputs. n Schmitt trigger port inputs. n Second data pointer. n Emulation support.

Product comparison overview

features please seeSection 2 “Features”.

4.1 Ordering options

Table 1. Product comparison overview Table 2. Ordering information Table 3. Ordering options

P89LPC933_934_935_936_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 26 November 2008 4 of 75 NXP Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core 5. Block diagram Fig 1. Block diagram ACCELERATED 2-CLOCK 80C51 CPU 4 kb/8 kB/16 kB CODE FLASH 256-BYTE DATA RAM PORT 2 CONFIGURABLE I/Os PORT 1 CONFIGURABLE I/Os PORT 0 CONFIGURABLE I/Os KEYPAD INTERRUPT PROGRAMMABLE OSCILLATOR DIVIDER CPU clock CONFIGURABLE OSCILLATOR ON-CHIP RC OSCILLATOR internal bus CRYSTAL OR RESONATOR POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) 002aab070 UART ANALOG COMPARATORS 512-BYTE AUXILIARY RAM I2C-BUS 512-BYTE DATA EEPROM (P89LPC935/936) PORT 3 CONFIGURABLE I/Os CCU (CAPTURE/ COMPARE UNIT) (P89LPC935/936) P89LPC933/934/935/936 WATCHDOG TIMER AND OSCILLATOR TIMER 0 TIMER 1 REAL-TIME CLOCK/ SYSTEM TIMER SPI ADC1/DAC1 ADC0/DAC0 (P89LPC935/936) P3[1:0] P2[7:0] P1[7:0] P0[7:0] TXD RXD SCL SDA CMP2 CIN2B CIN2A CMP1 CIN1A CIN1B OCA OCB OCC OCD ICA AD10 AD11 AD12 AD13 DAC1 AD00 AD01 AD02 AD03 DAC1 ICB SPICLK MOSI MISO SS

P89LPC933_934_935_936_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 26 November 2008 5 of 75 NXP Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core 6. Pinning information

6.1 Pinning

Fig 2. P89LPC933/934 TSSOP28 pin conﬁguration Fig 3. P89LPC935/936 TSSOP28 pin conﬁguration P89LPC933HDH P89LPC933FDH P89LPC934FDH 002aab071 P2.7 P2.6 P0.1/CIN2B/KBI1/AD10 P0.2/CIN2A/KBI2/AD11 P0.3/CIN1B/KBI3/AD12 P0.4/CIN1A/KBI4/DAC1/AD13 P0.5/CMPREF/KBI5 V DD P0.6/CMP1/KBI6 P0.7/T1/KBI7 P1.0/TXD P1.1/RXD P2.5/SPICLK P2.4/SS P2.0/DAC0 P2.1 P0.0/CMP2/KBI0 P1.7 P1.6 P1.5/RST V SS P3.1/XTAL1 P3.0/XTAL2/CLKOUT P1.4/INT1 P1.3/INT0/SDA P1.2/T0/SCL P2.2/MOSI P2.3/MISO P89LPC935FDH P89LPC936FDH 002aab072 P2.0/ICB/DAC0/AD03 P2.1/OCD/AD02 P0.0/CMP2/KBI0/AD01 P1.7/OCC/AD00 P1.6/OCB P1.5/RST VSS P3.1/XTAL1 P3.0/XTAL2/CLKOUT P1.4/INT1 P1.3/INT0/SDA P1.2/T0/SCL P2.2/MOSI P2.3/MISO P2.7/ICA P2.6/OCA P0.1/CIN2B/KBI1/AD10 P0.2/CIN2A/KBI2/AD11 P0.3/CIN1B/KBI3/AD12 P0.4/CIN1A/KBI4/DAC1/AD13 P0.5/CMPREF/KBI5 V DD P0.6/CMP1/KBI6 P0.7/T1/KBI7 P1.0/TXD P1.1/RXD P2.5/SPICLK P2.4/SS

P89LPC933_934_935_936_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 26 November 2008 6 of 75 NXP Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core Fig 4. P89LPC935 PLCC28 pin conﬁguration Fig 5. P89LPC935 HVQFN28 pin conﬁguration P89LPC935FA 002aab074 P1.6/OCB P1.5/RST VSS P3.1/XTAL1 P3.0/XTAL2/CLKOUT P1.4/INT1 P1.3/INT0/SDA P1.7/OCC/AD00 P0.0/CMP2/KBI0/AD01 P2.1/OCD/AD02 P2.0/ICB/DAC0/AD03 P2.7/ICA P2.6/OCA P0.1/CIN2B/KBI1/AD10 P0.2/CIN2A/KBI2/AD11 P0.3/CIN1B/KBI3/AD12 P0.4/CIN1A/KBI4/DAC1/AD13 P0.5/CMPREF/KBI5 V DD P0.6/CMP1/KBI6 P0.7/T1/KBI7 P1.2/T0/SCL P2.2/MOSI P2.3/MISO P2.4/SS P2.5/SPICLK P1.1/RXD P1.0/TXD 002aab076 P89LPC935FHN Transparent top view 7 15 6 16 5 17 4 18 3 19 2 20 1 21 terminal 1 index area P1.7/OCC/AD00 P2.7/ICA P2.1/OCD/AD02 P2.0/ICB/DAC0/AD03 P0.0/CMP2/KBI0/AD01 P2.6/OCA P0.1/CIN2B/KBI1/AD10 P2.4/SS P2.2/MOSI P2.3/MISO P1.2/T0/SCL P2.5/SPICLK P1.0/TXD P1.1/RXD P1.4/INT1 P1.3/INT0/SDA P3.0/XTAL2/CLKOUT P3.1/XTAL1 VSS P1.5/RST P1.6/OCB P0.6/CMP1/KBI6 P0.7/T1/KBI7 P0.5/CMPREF/KBI5 VDD P0.4/CIN1A/KBI4/DAC1/AD13 P0.3/CIN1B/KBI3/AD12 P0.2/CIN2A/KBI2/AD11

6.2 Pin description

Table 4. Pin description P0.0 to P0.7 I/O Port 0:Port 0 is an 8-bit I/O port with a user-conﬁgurable output type. and Table 11 “Static characteristics” for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt trigger inputs. O CMP2 — Comparator 2 output. I CIN2B — Comparator 2 positive input B. I AD10 — ADC1 channel 0 analog input. I CIN2A — Comparator 2 positive input A. I AD11 — ADC1 channel 1 analog input. I CIN1B — Comparator 1 positive input B. I AD12 — ADC1 channel 2 analog input. I CIN1A — Comparator 1 positive input A. O DAC1 — Digital-to-analog converter output 1. I AD13 — ADC1 channel 3 analog input. I CMPREF — Comparator reference (negative) input. O CMP1 — Comparator 1 output. I/O T1 — Timer/counter 1 external count input or overﬂow output.

P1.3 are open drain when used as outputs. P1.5 is input only. All pins have Schmitt trigger inputs. O TXD — Transmitter output for the serial port. I RXD — Receiver input for the serial port. P1.2/T0/SCL 12 8 I/O P1.2 — Port 1 bit 2 (open-drain when used as output). 2C serial clock input/output. 11 7 I/O P1.3 — Port 1 bit 3 (open-drain when used as output). I INT0 — External interrupt 0 input. I/O SDA — I2C serial data input/output. P1.5/RST 6 2 I P1.5 — Port 1 bit 5 (input only). I RST — External reset input during power-on or if selected via UCFG1.

12 MHz, in some applications, an external brownout detect circuit

minimum speciﬁed operating voltage. Table 4. Pin description …continued

P2.0 to P2.7 I/O Port 2: Port 2 is an 8-bit I/O port with a user-conﬁgurable output type. and Table 11 “Static characteristics” for details. All pins have Schmitt trigger inputs. I DAC0 — Digital-to-analog converter output. output; when conﬁgured as slave, this pin is input. conﬁgured as slave, this pin is input.

P3.0 to P3.1 I/O Port 3: Port 3 is a 2-bit I/O port with a user-conﬁgurable output type. and Table 11 “Static characteristics” for details. All pins have Schmitt trigger inputs. option is selected via the ﬂash conﬁguration. used to generate clock source for the RTC/system timer. SS 73I Ground: 0 V reference. well as Idle and Power-down modes.

P89LPC933_934_935_936_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 26 November 2008 11 of 75 NXP Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core 7. Logic symbols Fig 6. P89LPC933/934 logic symbol VDD VSS PORT 0 PORT 3 TXD RXD INT0 INT1 RST SCL SDA 002aab077 CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF CMP1 XTAL2 XTAL1 KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI6 KBI7 DAC1 DAC0 MOSI MISO SS SPICLK AD10 AD11 AD12 AD13 PORT 1 PORT 2 P89LPC933 P89LPC934 CLKOUT Fig 7. P89LPC935/936 logic symbol VDD VSS PORT 0 PORT 3 TXD RXD INT0 INT1 RST SCL SDA 002aab078 CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF CMP1 XTAL2 XTAL1 KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI6 KBI7 DAC1 MOSI MISO SS SPICLK AD10 AD11 AD12 AD13 AD01 PORT 1 PORT 2 P89LPC935 P89LPC936 OCB OCC ICB OCD OCA ICA AD00 AD03 AD02 DAC0CLKOUT

P89LPC933_934_935_936_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 26 November 2008 12 of 75 NXP Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core 8. Functional description Remark: Please refer to the P89LPC933/934/935/936 User manualfor a more detailed functional description.

8.1 Special function registers

Remark: SFR accesses are restricted in the following ways:

User mustnot attempt to access any SFR locations not deﬁned.
Accesses to any deﬁned SFR locations must be strictly for the functions for the SFRs.
SFR bits labeled ‘-’, logic 0 or logic 1 canonly be written and read as follows: – ‘-’ Unless otherwise speciﬁed,must be written with logic 0, but can return any value when read (even if it was written with logic 0). It is a reserved bit and may be used in future derivatives. – Logic 0must be written with logic 0, and will return a logic 0 when read. – Logic 1must be written with logic 1, and will return a logic 1 when read.

**Table 5. Special function registers - P89LPC933/934* indicates SFRs that are bit addressable.**

Program ﬂash control (Write) E4H FMCMD. Table 5. Special function registers - P89LPC933/934

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

purposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. [3] All ports are in input only (high-impedance) state after power-up. [5] The only reset source that affects these SFRs is power-on reset. [6] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [7] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF .

indicates SFRs that are bit addressable.

**Table 6. Special function registers - P89LPC935/936* indicates SFRs that are bit addressable.**

Program ﬂash control (Write) E4H FMCMD. Table 6. Special function registers - P89LPC935/936

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

purposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read. [2] All ports are in input only (high-impedance) state after power-up. [3] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. [5] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF . [6] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [7] The only reset source that affects these SFRs is power-on reset. TPCR2H Prescaler control register high CBH - - - - - - TPCR2H. TPCR2L Prescaler control register low CAH TPCR2L.

indicates SFRs that are bit addressable.

P89LPC933_934_935_936_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 26 November 2008 24 of 75 NXP Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core

8.2 Enhanced CPU

The P89LPC933/934/935/936 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

8.3 Clocks

8.3.1 Clock deﬁnitions

The P89LPC933/934/935/936 device has several internal clocks as deﬁned below: OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources (seeFigure8) and can also be optionally divided to a slower frequency (see Section 8.8 “CCLK modiﬁcation: DIVM register”). Remark: fosc is deﬁned as the OSCCLK frequency. CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles). RCCLK — The internal 7.373 MHz RC oscillator output. PCLK — Clock for the various peripheral devices and is CCLK ⁄2.

8.3.2 CPU clock (OSCCLK)

The P89LPC933/934/935/936 provides several user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are conﬁgured when the ﬂash is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source. The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 18 MHz.

8.3.3 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this conﬁguration.

8.3.4 Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this conﬁguration.

8.3.5 High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this conﬁguration.

8.3.6 Clock output

The P89LPC933/934/935/936 supports a user-selectable clock output function on the XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, watchdog oscillator,

P89LPC933_934_935_936_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 26 November 2008 25 of 75 NXP Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core external clock input on X1) and if the RTC is not using the crystal oscillator as its clock source. This allows external devices to synchronize to the P89LPC933/934/935/936. This output is enabled by the ENCLK bit in the TRIM register. The frequency of this clock output is 1⁄2 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power.

8.4 On-chip RC oscillator option

The P89LPC933/934/935/936 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7.373 MHz± 1 % at room temperature. End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies.

8.5 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.

8.6 External clock input option

In this conﬁguration, the processor clock is derived from an external source driving the P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2 pin may be used as a standard port pin or a clock output.When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until V DD has reached its speciﬁed level. When system power is removed VDD will fall below the minimum speciﬁed operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V DD falls below the minimum speciﬁed operating voltage.

P89LPC933_934_935_936_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 26 November 2008 26 of 75 NXP Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core Fig 8. Block diagram of oscillator control 002aab079 RTC ADC1 ADC0 (P89LPC935/936) CPU WDT DIVM CCLK UART OSCCLK I2C-BUS PCLK TIMER 0 AND TIMER 1 HIGH FREQUENCY MEDIUM FREQUENCY LOW FREQUENCY XTAL1 XTAL2 RC OSCILLATOR WATCHDOG OSCILLATOR (7.3728 MHz ±1 %) PCLK RCCLK SPI CCU (P89LPC935/936) 32 × PLL(400 kHz +30 % −20 %)

P89LPC933_934_935_936_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 26 November 2008 27 of 75 NXP Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core

8.7 CCLK wake-up delay

The P89LPC933/934/935/936 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus 60µst o1 0 0µs. If the clock source is either the internal RC oscillator, watchdog oscillator, or external clock, the delay is 224 OSCCLK cycles plus 60µst o1 0 0µs.

8.8 CCLK modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.

8.9 Low power select

The P89LPC933/934/935/936 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

8.10 Memory organization

The various P89LPC933/934/935/936 memory spaces are as follows:

DATA 128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area.
IDATA Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.
SFR Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.
XDATA (P89LPC935/936) ‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the SPTR, R0, or R1. All or part of this space could be implemented on-chip. The P89LPC935/936 has 512 bytes of on-chip XDATA memory.

CODE 64 kB of code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC933/934/935/936 have 4 KB/8 kB/16 kB of on-chip Code memory. The P89LPC935/936 also has 512 bytes of on-chip data EEPROM that is accessed via SFRs (see Section 8.27 “Data EEPROM (P89LPC935/936)”).

8.11 Data RAM arrangement

The 768 bytes of on-chip RAM are organized as shown inTable7.

8.12 Interrupts

EEPROM write/ADC completion. disable bit, EA, which disables all interrupts.

8.12.1 External interrupt inputs

Table 7. On-chip data memory usages

P89LPC933_934_935_936_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 26 November 2008 29 of 75 NXP Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core These external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit IT1 or IT0 in register TCON. In edge-triggered mode, if successive samples of theINTn pin show a HIGH in one cycle and a LOW in the next cycle, the interrupt request ﬂag IEn in TCON is set, causing an interrupt request. If an external interrupt is enabled when the P89LPC933/934/935/936 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section 8.15 “Pow er reduction modes” for details. (1) See Section 8.19 “CCU (P89LPC935/936)” (2) P89LPC935/936 Fig 9. Interrupt sources, interrupt enables, and power-down wake-up sources 002aab081 IE0 EX0 IE1 EX1 BOF EBO KBIF EKBI interrupt to CPU wake-up (if in power-down) EWDRT CMF2 CMF1 EC EA (IE0.7) TF1 ET1 TI & RI/RI ES/ESR TI EST SI EI2C SPIF ESPI RTCF ERTC (RTCCON.1) WDOVF TF0 ET0 any CCU interrupt(1) ECCU ENADCI0 (2) ADCI0 (2) ENADCI1 ADCI1 ENBI0(2) BNDI0 (2) ENBI1 BNDI1 EEIF(2) EADEE (P89LPC935) EAD (P89LPC933/934)

8.13 I/O ports

The P89LPC933/934/935/936 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. [1] Required for operation above 12 MHz.

8.13.1 Port conﬁgurations

port select the output type for each port pin. RST) can only be an input and cannot be conﬁgured.

P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be conﬁgured to be either input-only or

8.13.1.1 Quasi-bidirectional output conﬁguration

the quasi-bidirectional output that serve different purposes. quasi-bidirectional mode is discouraged.

8.13.1.2 Open-drain output conﬁguration

Table 8. Number of I/O pins available

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8.13.1.3 Input-only conﬁguration

The input-only port conﬁguration has no output drivers. It is a Schmitt trigger input that also has a glitch suppression circuit.

8.13.1.4 Push-pull output conﬁguration

The push-pull output conﬁguration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output. A push-pull port pin has a Schmitt trigger input that also has a glitch suppression circuit.

8.13.2 Port 0 analog functions

The P89LPC933/934/935/936 incorporates two Analog Comparators. In order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port output into the Input-Only (high-impedance) mode. Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5. On any reset, PT0AD[1:5] defaults to logic 0s to enable digital functions.

8.13.3 Additional port features

After power-up, all pins are in Input-Only mode. Remark: Please note that this is different from the LPC76x series of devices.

After power-up, all I/O pins except P1.5, may be conﬁgured by software.
Pin P1.5 is input only. Pins P1.2 and P1.3 and are conﬁgurable for either input-only or open-drain. Every output on the P89LPC933/934/935/936 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to Table 11 “Static characteristics” for detailed speciﬁcations. All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.

8.14 Power monitoring functions

The P89LPC933/934/935/936 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on detect and brownout detect.

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8.14.1 Brownout detection

The brownout detect function determines if the power supply voltage drops below a certain level. The default operation is for a brownout detection to cause a processor reset, however it may alternatively be conﬁgured to generate an interrupt. Brownout detection may be enabled or disabled in software. If brownout detection is enabled the brownout condition occurs when V DD falls below the brownout trip voltage, Vbo (seeTable11 “Staticcharacteristics”), and is negated when VDD rises above Vbo. If the P89LPC933/934/935/936 device is to operate with a power supply that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from operating. For correct activation of brownout detect, the V DD rise and fall times must be observed. Please seeTable 11 “Static characteristics” for speciﬁcations.

8.14.2 Power-on detection

The power-on detect has a function similar to the brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. The POF ﬂag in the RSTSRC register is set to indicate an initial power-up condition. The POF ﬂag will remain set until cleared by software.

8.15 Power reduction modes

The P89LPC933/934/935/936 supports three different power reduction modes. These modes are Idle mode, Power-down mode, and total Power-down mode.

8.15.1 Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode.

8.15.2 Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC933/934/935/936 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the RAM keep-alive voltage V RAM . This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after VDD has been lowered to VDDR , therefore it is highly recommended to wake-up the processor via reset in this case. VDD must be raised to within the operating range before the Power-down mode is exited. Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during power-down. These include: brownout detect, watchdog timer, Comparators (note that Comparators can be powered-down separately), and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled.

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8.15.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during power-down, there will be high power consumption. Please use an external low frequency clock to achieve low power with the RTC running during power-down.

8.16 Reset

The P1.5/RST pin can function as either a LOW-active reset input or as a digital input, P1.5. The Reset Pin Enable (RPE) bit in UCFG1, when set to logic 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin. Remark: During a power-up sequence, the RPE selection is overridden and this pin will always functions as a reset input.An external circuit connected to this pin should not hold this pin LOW during a power-on sequence as this will keep the device in reset. After power-up this input will function either as an external reset input or as a digital input as deﬁned by the RPE bit. Only a power-up reset will temporarily override the selection deﬁned by RPE bit. Other sources of reset will not override the RPE bit. Reset can be triggered from the following sources:

External reset pin (during power-up or if user conﬁgured via UCFG1).
Power-on detect.
Brownout detect.
Watchdog timer.
Software reset.
UART break character detect reset. For every reset source, there is a ﬂag in the reset register, RSTSRC. The user can read this register to determine the most recent reset source. These ﬂag bits can be cleared in software by writing a logic 0 to the corresponding bit. More than one ﬂag bit may be set:
During a power-on reset, both POF and BOF are set but the other ﬂag bits are cleared.
For any other reset, previously set ﬂag bits that have not been cleared will remain set.

8.16.1 Reset vector

Following reset, the P89LPC933/934/935/936 will fetch instructions from either address 0000H or the boot address. The boot address is formed by using the boot vector as the high byte of the address and the low byte of the address = 00H. The boot address will be used if a UART break reset occurs, or the non-volatile boot status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see P89LPC933/934/935/936 User manual). Otherwise, instructions will be fetched from address 0000H.

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8.17 Timers/counters 0 and 1

The P89LPC933/934/935/936 has two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. Both can be conﬁgured to operate either as timers or event counter. An option to automatically toggle the T0 and/or T1 pins upon timer overﬂow has been added. In the ‘timer’ function, the register is incremented every machine cycle. In the ‘counter’ function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled once during every machine cycle. Timer 0 and Timer 1 have ﬁve operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1, 2 and 6 are the same for both timers/counters. Mode 3 is different.

8.17.1 Mode 0

Putting either timer into Mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. In this mode, the timer register is conﬁgured as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.

8.17.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

8.17.3 Mode 2

Mode 2 conﬁgures the timer register as an 8-bit counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1.

8.17.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.

8.17.5 Mode 6

In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks.

8.17.6 Timer overﬂow toggle output

Timers 0 and 1 can be conﬁgured to automatically toggle a port output whenever a timer overﬂow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the ﬁrst timer overﬂow when this mode is turned on.

8.18 RTC/system timer

The P89LPC933/934/935/936 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered-down. The RTC can be a wake-up or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will be reloaded again and the RTCF ﬂag will be set. The clock source for this counter can be either the CPU clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is not

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8.19 CCU (P89LPC935/936)

This unit features:

A 16-bit timer with 16-bit reload on overﬂow.
Selectable clock, with prescaler to divide clock source by any integral number between 1 and 1024.
Four compare/PWM outputs with selectable polarity.
Symmetrical/asymmetrical PWM selection.
Two capture inputs with event counter and digital noise rejection ﬁlter.
Seven interrupts with common interrupt vector (one overﬂow, two capture, four compare).
Safe 16-bit read/write via shadow registers.

8.19.1 CCU clock

The CCU runs on the CCUCLK, which is either PCLK in basic timer mode, or the output of a Phase-Locked Loop (PLL). The PLL is designed to use a clock source between 0.5 MHz to 1 MHz that is multiplied by 32 to produce a CCUCLK between 16 MHz and 32 MHz in PWM mode (asymmetrical or symmetrical). The PLL contains a 4-bit divider to help divide PCLK into a frequency between 0.5 MHz and 1 MHz.

8.19.2 CCUCLK prescaling

This CCUCLK can further be divided down by a prescaler. The prescaler is implemented as a 10-bit free-running counter with programmable reload at overﬂow.

8.19.3 Basic timer operation

The timer is a free-running up/down counter with a direction control bit. If the timer counting direction is changed while the counter is running, the count sequence will be reversed. The timer can be written or read at any time. When a reload occurs, the CCU Timer Overﬂow Interrupt Flag will be set, and an interrupt generated if enabled. The 16-bit CCU timer may also be used as an 8-bit up/down timer.

8.19.4 Output compare

There are four output compare channels A, B, C and D. Each output compare channel needs to be enabled in order to operate and the user will have to set the associated I/O pin to the desired output mode to connect the pin. When the contents of the timer matches that of a capture compare control register, the Timer Output Compare Interrupt Flag (TOCFx) becomes set. An interrupt will occur if enabled.

8.19.5 Input capture

Input capture is always enabled. Each time a capture event occurs on one of the two input capture pins, the contents of the timer is transferred to the corresponding 16-bit input capture register. The capture event can be programmed to be either rising or falling edge triggered. A simple noise ﬁlter can be enabled on the input capture by enabling the Input

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8.19.6 PWM operation

PWM operation has two main modes, symmetrical and asymmetrical. In asymmetrical PWM operation the CCU timer operates in down-counting mode regardless of the direction control bit. In symmetrical mode, the timer counts up/down alternately. The main difference from basic timer operation is the operation of the compare module, which in PWM mode is used for PWM waveform generation. As with basic timer operation, when the PWM (compare) pins are connected to the compare logic, their logic state remains unchanged. However, since bit FCO is used to hold the halt value, only a compare event can change the state of the pin. Fig 10. Asymmetrical PWM, down-counting mode Fig 11. Symmetrical PWM TOR2 compare value timer value non-inverted inverted 0x0000 002aaa893 TOR2 compare value timer value non-inverted inverted 002aaa894

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8.19.7 Alternating output mode

In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating pairs for bridge drive control. In this mode the output of these PWM channels are alternately gated on every counter cycle.

8.19.8 PLL operation

The PWM module features a PLL that can be used to generate a CCUCLK frequency between 16 MHz and 32 MHz. At this frequency the PWM module provides ultrasonic PWM frequency with 10-bit resolution provided that the crystal frequency is 1 MHz or higher. The PLL is fed an input signal from 0.5 MHz to 1 MHz and generates an output signal of 32 times the input frequency. This signal is used to clock the timer. The user will have to set a divider that scales PCLK by a factor from 1 to 16. This divider is found in the SFR register TCR21. The PLL frequency can be expressed as shown in Equation1. (1) Where: N is the value of PLLDV.3 to PLLDV.0. Since N ranges from 0 to 15, the CCLK frequency can be in the range of PCLK to PCLK ⁄16. Fig 12. Alternate output mode TIMER VALUE 002aaa895 TOR2 COMPARE VALUE A (or C) COMPARE VALUE B (or D) PWM OUTPUT (OCA or OCC) PWM OUTPUT (OCB or OCD) PLL frequency PCLK

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8.19.9 CCU interrupts

There are seven interrupt sources on the CCU which share a common interrupt vector.

8.20 UART

The P89LPC933/934/935/936 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overﬂow cannot be used as a baud rate source. The P89LPC933/934/935/936 does include an independent baud rate generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overﬂow, or the independent baud rate generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options. The UART can be operated in four modes: shift register, 8-bit UART, 9-bit UART, and CPU clock⁄32 or CPUclock⁄16.

8.20.1 Mode 0

Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted or received, LSB ﬁrst. The baud rate is ﬁxed at 1⁄16 of the CPU clock frequency. Fig 13. Capture/compare unit interrupts 002aaa896 interrupt to CPU TOIE2 (TICR2.7) TOIF2 (TIFR2.7) TICIE2A (TICR2.0) TICF2A (TIFR2.0) TICIE2B (TICR2.1) TICF2B (TIFR2.1) TOCIE2A (TICR2.3) TOCF2A (TIFR2.3) TOCIE2B (TICR2.4) TOCF2B (TIFR2.4) TOCIE2C (TICR2.5) TOCF2C (TIFR2.5) TOCIE2D (TICR2.6) TOCF2D (TIFR2.6) EA (IEN0.7) ECCU (IEN1.4) PRIORITY ENCODER other interrupt sources ENCINT.0 ENCINT.1 ENCINT.2

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8.20.2 Mode 1

10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB ﬁrst), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8 in special function register SCON. The baud rate is variable and is determined by the Timer 1 overﬂow rate or the baud rate generator (described in Section 8.20.5 “Baud rate generator and selection”).

8.20.3 Mode 2

11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logic 1). When data is transmitted, the 9thdata bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1. Or, for example, the parity bit (P , in the PSW) could be moved into TB8. When data is received, the 9 th data bit goes into RB8 in special function register SCON, while the stop bit is not saved. The baud rate is programmable to either1⁄16 or1⁄32 of the CPU clock frequency, as determined by the SMOD1 bit in PCON.

8.20.4 Mode 3

11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB ﬁrst), a programmable 9 thdata bit, and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overﬂow rate or the baud rate generator (described in Section 8.20.5 “Baud rate generator and selection”).

8.20.5 Baud rate generator and selection

The P89LPC933/934/935/936 enhanced UART has an independent baud rate generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be used for other timing functions. The UART can use either Timer 1 or the baud rate generator output (see Figure14). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The independent baud rate generator uses CCLK.

8.20.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up when SMOD0 is logic 0. Fig 14. Baud rate sources for UART (Modes 1, 3) baud rate modes 1 and 3 SBRGS = 1 SBRGS = 0 SMOD1 = 0 SMOD1 = 1timer 1 overflow (PCLK-based) baud rate generator (CCLK-based) 002aaa897

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8.20.7 Break detect

Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device and force the device into ISP mode.

8.20.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the ﬁrst character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 =0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SnBUF while the previous data is being shifted out. Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = 0).

8.20.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated when the double buffer is ready to receive new data.

8.20.10 The 9th bit (bit 8) in double buffering (modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the Tx interrupt. If double buffering is enabled, TB8must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data.

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8.21 I2C-bus serial interface

The I2C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features:

Bidirectional data transfer between masters and slaves
Multi master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer
The I2C-bus may be used for test and diagnostic purposes. A typical I2C-bus conﬁguration is shown inFigure15. The P89LPC933/934/935/936 device provides a byte-oriented I2C-bus interface that supports data transfers up to 400 kHz. Fig 15. I2C-bus conﬁguration OTHER DEVICE WITH I2C-BUS INTERFACE SDA SCL R PR P OTHER DEVICE WITH I2C-BUS INTERFACE P1.3/SDA P1.2/SCL P89LPC935 I2C-bus 002aab082

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8.22 SPI

The P89LPC933/934/935/936 provides another high-speed serial communication interface—the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in Master mode or up to 2 Mbit/s in Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection. The SPI interface has four pins: SPICLK, MOSI, MISO and SS:

SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data ﬂows from master to slave on MOSI (Master Out Slave In) pin and ﬂows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output in the master mode and is input in the slave mode. If the SPI system is disabled, i.e., SPEN (SPCTL.6) = 0 (reset value), these pins are conﬁgured for port functions.
SS is the optional slave select pin. In a typical conﬁguration, an SPI master asserts one of its port pins to select one SPI device as the current slave. An SPI slave device uses its SS pin to determine whether it is selected. Typical connections are shown inFigure18 throughFigure20. Fig 17. SPI block diagram 002aaa900 CPU clock DIVIDER BY 4, 16, 64, 128 SELECT CLOCK LOGIC SPI CONTROL REGISTER READ DATA BUFFER 8-BIT SHIFT REGISTER SPI CONTROL SPI STATUS REGISTER SPR1 SPIF WCOL SPR0 SPI clock (master) PIN CONTROL LOGIC S M S M M S MISO P2.3 MOSI P2.2 SPICLK P2.5 SS P2.4 SPI interrupt request internal data bus SSIG SPEN SPEN MSTR DORD MSTR CPHA CPOL SPR1 SPR0 MSTR SPEN clock

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8.22.1 Typical SPI conﬁgurations

Fig 18. SPI single master single slave conﬁguration Fig 19. SPI dual device conﬁguration, where either can be a master or a slave 002aaa901 master slave 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR 8-BIT SHIFT REGISTER MISO MOSI SPICLK PORT MISO MOSI SPICLK SS 002aaa902 master slave 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR SPI CLOCK GENERATOR 8-BIT SHIFT REGISTER MISO MOSI SPICLK MISO MOSI SPICLK SSSS

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8.23 Analog comparators

Two analog comparators are provided on the P89LPC933/934/935/936. Input and output options allow use of the comparators in a number of different conﬁgurations. Comparator operation is such that the output is a logic 1 (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be conﬁgured to cause an interrupt when the output value changes. The overall connections to both comparators are shown in Figure21. The comparators function to VDD = 2.4 V. When each comparator is ﬁrst enabled, the comparator output and interrupt ﬂag are not guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt ﬂag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. When a comparator is disabled the comparator’s output, COn, goes HIGH. If the comparator output was LOW and then is disabled, the resulting transition of the comparator output from a LOW to HIGH state will set the comparator ﬂag, CMFn. This will cause an interrupt if the comparator interrupt is enabled. The user should therefore disable the comparator interrupt prior to disabling the comparator. Additionally, the user should clear the comparator ﬂag, CMFn, after disabling the comparator.

8.23.1 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as V ref(bg), is 1.23 V± 10 %. Fig 21. Comparator input and output connections comparator 1 CP1 CN1 (P0.4) CIN1A (P0.3) CIN1B (P0.5) CMPREF Vref(bg) OE1 change detect CO1 CMF1 interrupt 002aaa904 CMP1 (P0.6) ECchange detect CMF2 comparator 2 OE2 CO2 CMP2 (P0.0) CP2 CN2 (P0.2) CIN2A (P0.1) CIN2B

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8.23.2 Comparator interrupt

Each comparator has an interrupt ﬂag contained in its conﬁguration register. This ﬂag is set whenever the comparator output changes state. The ﬂag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. If both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the ﬂags to determine which comparator caused the interrupt.

8.23.3 Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode. If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake-up the processor. If the comparator output to a pin is enabled, the pin should be conﬁgured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with theoscillatorstopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. Comparators consume power in Power-down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparators via PCONA.5, or put the device in Total Power-down mode.

8.24 Keypad interrupt

The Keypad Interrupt (KBI) function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can conﬁgure the port via SFRs for different tasks. The Keypad Interrupt Mask register (KBMASK) is used to deﬁne which input pins connected to Port 0 can trigger the interrupt. The Keypad Pattern register (KBPATN) is used to deﬁne a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt Control register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control register (KBCON) is used to deﬁne equal or not-equal for the comparison. In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake-up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. In order to set the ﬂag and cause an interrupt, the pattern on Port 0 must be held longer than six CCLKs.

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8.25 Watchdog timer

The watchdog timer causes a system reset when it underﬂows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler. The clock source for the prescaler is either the PCLK or the nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a power-on reset. When the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure22 shows the watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered-down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a fewµs to a few seconds. Please refer to the P89LPC933/934/935/936 User manual for more details.

8.26 Additional features

8.26.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets.

8.26.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register. (1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence. Fig 22. Watchdog timer in Watchdog mode (WDTE = 1) PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLKWDCON (A7H) SHADOW REGISTER PRESCALER 002aaa905 8-BIT DOWN COUNTER WDL (C1H) watchdog oscillator PCLK ÷32 MOV WFEED1, #0A5H MOV WFEED2, #05AH reset(1)

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8.27 Data EEPROM (P89LPC935/936)

The P89LPC935/936 has 512 bytes of on-chip Data EEPROM. The Data EEPROM is SFR based, byte readable, byte writable, and erasable (via row ﬁll and sector ﬁll). The user can read, write and ﬁll the memory via SFRs and one interrupt. This Data EEPROM provides 100,000 minimum erase/program cycles for each byte.

Byte mode: In this mode, data can be read and written one byte at a time.
Row ﬁll: In this mode, the addressed row (64 bytes) is ﬁlled with a single value. The entire row can be erased by writing 00H.
Sector ﬁll: In this mode, all 512 bytes are ﬁlled with a single value. The entire sector can be erased by writing 00H. After the operation ﬁnishes, the hardware will set the EEIF bit, which if enabled will generate an interrupt. The ﬂag is cleared by software.

8.28 Flash program memory

8.28.1 General description

The P89LPC933/934/935/936 ﬂash memory provides in-circuit electrical erasure and programming. The ﬂash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any ﬂash sector (1 kB or 2 kB depending on the device) or page (64 bytes). The Chip Erase operation will erase the entire program memory. ICP using standard commercial programmers is available. In addition, IAP and byte-erase allows code memory to be used for non-volatile data storage. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC933/934/935/936 ﬂash reliably stores memory contents even after 100,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. The P89LPC933/934/935/936 uses V DD as the supply voltage to perform the Program/Erase algorithms.

8.28.2 Features

Programming and erase over the full operating voltage range.
Byte erase allows code memory to be used for data storage.
Read/Programming/Erase using ISP/IAP/ICP .
Internal ﬁxed boot ROM, containing low-level IAP routines available to user code.
Default loader providing ISP via the serial port, located in upper end of user program memory.
Boot vector allows user-provided ﬂash loader code to reside anywhere in the ﬂash memory space, providing ﬂexibility to the user.
Any ﬂash program/erase operation in 2 ms.
Programming with industry-standard commercial programmers.
Programmable security for the code in the ﬂash for each sector.
100,000 typical erase/program cycles for each byte.
10 year minimum data retention.

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8.28.3 Flash organization

The program memory consists of eight 2 kB sectors on the P89LPC936 device, eight 1 kB sectors on the P89LPC934/935 devices, and four 1 kB sectors on the P89LPC933 device. Each sector can be further divided into 64-byte pages. In addition to sector erase, page erase, and byte erase, a 64-byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time.

8.28.4 Using ﬂash as data storage

The ﬂash code memory array of this device supports individual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the sector containing the byte has not been secured (a MOVC instruction is not allowed to read code memory contents of a secured sector). Thus any byte in a non-secured sector may be used for non-volatile data storage.

8.28.5 Flash programming and erasing

Four different methods of erasing or programming of the ﬂash are available. The ﬂash may be programmed or erased in the end-user application (IAP) under control of the application’s ﬁrmware. Another option is to use the ICP mechanism. This ICP system provides for programming through a serial clock - serial data interface. As shipped from the factory, the upper 512 bytes of user code space contains a serial ISP routine allowing the device to be programmed in circuit through the serial port. The ﬂash may also be programmed or erased using a commercially available EPROM programmer which supports this device. This device does not provide for direct veriﬁcation of code memory contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire user code space.

8.28.6 In-circuit programming

ICP is performed without removing the microcontroller from the system. The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC933/934/935/936 through a two-wire serial interface. The Philips ICP facility has made ICP in an embedded application—using commercially available programmers—possible with a minimum of additional expense in components and circuit board area. The ICP function uses ﬁve pins. Only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature. Additional details may be found in the P89LPC933/934/935/936 User manual.

8.28.7 In-application programming

IAP is performed in the application under the control of the microcontroller’s ﬁrmware. The IAP facility consists of internal hardware resources to facilitate programming and erasing. The Philips IAP has made IAP in an embedded application possible without additional components. Two methods are available to accomplish IAP . A set of predeﬁned IAP functions are provided in a boot ROM and can be called through a common interface, PGM_MTP . Several IAP calls are available for use by an application program to permit selective erasing and programming of ﬂash sectors, pages, security bits, conﬁguration bytes, and device ID. These functions are selected by setting up the microcontroller’s registers before making a call to PGM_MTP at FF03H. The boot ROM occupies the program memory space at the top of the address space from FF00H to FFEFH, thereby not conﬂicting with the user program memory space.

8.28.8 ISP

facilitate remote programming of the P89LPC933/934/935/936 through the serial port. available to interface your application to an external circuit in order to use this feature.

8.28.9 Power-on reset code execution

used as the high byte of the execution address and the low byte is set to 00H. Table9 shows the factory default boot vector settings for these devices. Flash Magic version 1.98, or later. erase the pages located in this sector which are not used by the boot loader. Table 9. Default boot vector values and ISP entry points

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8.28.10 Hardware activation of the boot loader

The boot loader can also be executed by forcing the device into ISP mode during a power-on sequence (see the P89LPC933/934/935/936 User manual for speciﬁc information). This has the same effect as having a non-zero status byte. This allows an application to be built that will normally execute user code but can be manually forced into ISP operation. If the factory default setting for the boot vector is changed, it will no longer point to the factory preprogrammed ISP boot loader code. After programming the ﬂash, the status byte should be programmed to zero in order to allow execution of the user’s application code beginning at address 0000H.

8.29 User conﬁguration bytes

Some user-conﬁgurable features of the P89LPC933/934/935/936 must be deﬁned at power-up and therefore cannot be set by the program after start of execution. These features are conﬁgured through the use of the ﬂash byte UCFG1. Please see the P89LPC933/934/935/936 User manual for additional details.

8.30 User sector security bytes

There are eight User Sector Security Bytes on the P89LPC933/934/935/936 device. Each byte corresponds to one sector. Please see the P89LPC933/934/935/936 User manualfor additional details. 9. A/D converter

9.1 General description

The P89LPC935/936 have two 8-bit, 4-channel multiplexed successive approximation analog-to-digital converter modules sharing common control logic. The P89LPC933/934 have a single 8-bit, 4-channel multiplexed analog-to-digital converter and an additional DAC module. A block diagram of the A/D converter is shown in Figure23. Each A/D consists of a 4-input multiplexer which feeds a sample-and-hold circuit providing an input signal to one of two comparator inputs. The control logic in combination with the SAR drives a digital-to-analog converter which provides the other input to the comparator. The output of the comparator is fed to the SAR.

9.2 Features

n Two (P89LPC935/936) 8-bit, 4-channel multiplexed input, successive approximation A/D converters with common control logic (one A/D on the P89LPC933/934). n Four result registers for each A/D. n Six operating modes: u Fixed channel, single conversion mode. u Fixed channel, continuous conversion mode. u Auto scan, single conversion mode. u Auto scan, continuous conversion mode. u Dual channel, continuous conversion mode. u Single step mode. n Four conversion start modes: u Timer triggered start.

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9.3 Block diagram

9.4 A/D operating modes

9.4.1 Fixed channel, single conversion mode

A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after the conversion completes. Fig 23. ADC block diagram comp DAC1 SAR INPUT MUX CONTROL LOGIC comp DAC0 SAR INPUT MUX CCLK 002aab080

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9.4.2 Fixed channel, continuous conversion mode

A single input channel can be selected for continuous conversion. The results of the conversions will be sequentially placed in the four result registers. An interrupt, if enabled, will be generated after every four conversions. Additional conversion results will again cycle through the four result registers, overwriting the previous results. Continuous conversions continue until terminated by the user.

9.4.3 Auto scan, single conversion mode

Any combination of the four input channels can be selected for conversion. A single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after all selected channels have been converted. If only a single channel is selected this is equivalent to single channel, single conversion mode.

9.4.4 Auto scan, continuous conversion mode

Any combination of the four input channels can be selected for conversion. A conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after all selected channels have been converted. The process will repeat starting with the ﬁrst selected channel. Additional conversion results will again cycle through the four result registers, overwriting the previous results.Continous conversions continue until terminated by the user.

9.4.5 Dual channel, continuous conversion mode

This is a variation of the auto scan continuous conversion mode where conversion occurs on two user-selectable inputs. The result of the conversion of the ﬁrst channel is placed in result register, ADxDAT0. The result of the conversion of the second channel is placed in result register, ADxDAT1. The ﬁrst channel is again converted and its result stored in ADxDAT2. The second channel is again converted and its result placed in ADxDAT3. An interrupt is generated, if enabled, after every set of four conversions (two conversions per channel).

9.4.6 Single step mode

This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any combination of the four input channels can be selected for conversion. After each channel is converted, an interrupt is generated, if enabled, and the A/D waits for the next start condition. May be used with any of the start modes.

9.5 Conversion start modes

9.5.1 Timer triggered start

An A/D conversion is started by the overﬂow of Timer 0. Once a conversion has started, additional Timer 0 triggers are ignored until the conversion has completed. The Timer triggered start mode is available in all A/D operating modes.

9.5.2 Start immediately

Programming this mode immediately starts a conversion.This start mode is available in all A/D operating modes.

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9.5.3 Edge triggered

An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has started, additional edge triggers are ignored until the conversion has completed. The edge triggered start mode is available in all A/D operating modes.

9.5.4 Dual start immediately (P89LPC935/936)

Programming this mode starts a synchronized conversion of both A/D converters.This start mode is available in all A/D operating modes. Both A/D converters must be in the same operating mode. In the continuous conversion modes, both A/D converters must select an identical number of channels. Any trigger of either A/D will start a simultaneous conversion of both A/Ds.

9.6 Boundary limits interrupt

Each of the A/D converters has both a high and low boundary limit register. After the four MSBs have been converted, these four bits are compared with the four MSBs of the boundary high and low registers. If the four MSBs of the conversion are outside the limit an interrupt will be generated, if enabled. If the conversion result is within the limits, the boundary limits will again be compared after all 8 bits have been converted. An interrupt will be generated, if enabled, if the result is outside the boundary limits. The boundary limit may be disabled by clearing the boundary limit interrupt enable.

9.7 DAC output to a port pin with high output impedance

Each A/D converter’s DAC block can be output to a port pin. In this mode, the ADxDAT3 register is used to hold the value fed to the DAC. After a value has been written to the DAC (written to ADxDAT3), the DAC output will appear on the channel 3 pin.

9.8 Clock divider

The A/D converter requires that its internal clock source be in the range of 500 kHz to 3.3 MHz to maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose.

9.9 Power-down and Idle mode

In Idle mode the A/C converter, if enabled, will continue to function and can cause the device to exit Idle mode when the conversion is completed if the A/D interrupt is enabled. In Power-down mode or Total Power-down mode, the A/D does not function. If the A/D is enabled, it will consume power. Power can be reduced by disabling the A/D.

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. Table 10. Limiting values

Table 11. Static characteristics VDD = 2.4 V to 3.6 V unless otherwise speciﬁed. Tamb = −40 °C to +85°C for industrial,−40 °C to +125°C for extended, unless otherwise speciﬁed.

[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V. real-time clock, and watchdog timer. brownout detect, and watchdog timer. exceed the related speciﬁcation. [6] Pin capacitance is characterized but not tested. [7] Measured with port in quasi-bidirectional mode. [8] Measured with port in high-impedance mode.

11.1 IOH as a function of VOH

Table 11. Static characteristics …continued VDD = 2.4 V to 3.6 V unless otherwise speciﬁed. Tamb = −40 °C to +85°C for industrial,−40 °C to +125°C for extended, unless otherwise speciﬁed.

Table 12. Dynamic characteristics (12 MHz) VDD = 2.4 V to 3.6 V unless otherwise speciﬁed.

[1] Parameters are valid over ambient temperature range unless otherwise speciﬁed. [2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. Table 12. Dynamic characteristics (12 MHz) …continued VDD = 2.4 V to 3.6 V unless otherwise speciﬁed.

Table 13. Dynamic characteristics (18 MHz) VDD = 3.0 V to 3.6 V unless otherwise speciﬁed.

[1] Parameters are valid over ambient temperature range unless otherwise speciﬁed. [2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. Table 13. Dynamic characteristics (18 MHz) …continued VDD = 3.0 V to 3.6 V unless otherwise speciﬁed.

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12.1 Waveforms

Fig 25. Shift register mode timing 01 2 3 4 5 6 7 valid valid valid valid valid valid valid valid TXLXL 002aaa906 set TI set RI tXHQXtQVXH tXHDV tXHDX clock output data write to SBUF input data clear RI Fig 26. SPI master timing (CPHA = 0) TSPICYC tSPICLKH tSPICLKH tSPICLKL tSPICLKL master LSB/MSB outmaster MSB/LSB out tSPIDHtSPIDSU tSPIF tSPIOH tSPIDV tSPIRtSPIDV tSPIF tSPIR tSPIF tSPIR SS SPICLK (CPOL = 0) (output) 002aaa908 SPICLK (CPOL = 1) (output) MISO (input) MOSI (output) LSB/MSB inMSB/LSB in Fig 27. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) tCHCL tCLCX tCHCX Tcy(clk) tCLCH 002aaa907

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12.2 ISP entry mode

Table 14. Dynamic characteristics, ISP entry mode VDD = 2.4 V to 3.6 V, unless otherwise speciﬁed. Tamb = −40 °C to +85°C for industrial,−40 °C to +125°C for extended, unless otherwise speciﬁed.

13.1 Comparator electrical characteristics

[1] This parameter is characterized, but not tested in production. Table 15. Comparator electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise speciﬁed. Tamb = −40 °C to +85°C for industrial,−40 °C to +125°C for extended, unless otherwise speciﬁed.

13.2 ADC electrical characteristics

Table 16. ADC electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise speciﬁed. Tamb = −40 °C to +85°C for industrial,−40 °C to +125°C for extended, unless otherwise speciﬁed. All limits valid for an external source impedance of less than 10 kΩ .

P89LPC933_934_935_936_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 26 November 2008 68 of 75 NXP Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core 14. Package outline Fig 32. Package outline SOT261-2 (PLCC28) REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. SOT261-2 112E08 MS-018 EDR-7319 1925 51 1 detail X (A )3 bp w M A 1 A A 4 Lp b k Xy e E B DH EH v M B D Z D A Z E e v M A 0 5 10 mm scale 99-12-27 01-11-15 pin 1 index PLCC28: plastic leaded chip carrier; 28 leads SOT261-2 UNIT b mm 4.57 4.19 0.51 3.05 0.53 0.33 0.021 0.013 1.27 2.16 45o 0.18 0.10.18 DIMENSIONS (mm dimensions are derived from the original inch dimensions) 11.58 11.43 12.57 12.32 2.160.81 0.66 1.22 1.07 0.180 0.165 0.02 0.12 0.25 1.44 1.02 0.057 0.040 0.456 0.450 11.58 11.43 0.456 0.450 0.495 0.485 12.57 12.32 0.495 0.485 10.92 9.91 0.43 0.39 10.92 9.91 0.43 0.39 0.0850.032 0.026 0.048 0.042 Ee inches De A A 1 min. A 4 max. bp ey wvD (1) E(1) H D H E ZD (1) max. ZE(1) max. b1 kA 3 LpeD eE

P89LPC933_934_935_936_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 26 November 2008 69 of 75 NXP Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core Fig 33. Package outline SOT361-1 (TSSOP28) UNIT A 1 A 2 A 3 bp cD (1) E (2) (1)eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 9.8 9.6 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.8 0.5 o o0.13 0.10.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT361-1 MO-153 99-12-27 03-02-19 0.25 w M bp Z e 11 4 28 15 pin 1 index q AA 1 A 2 Lp Q detail X L (A )3 H E E c v M A XAD y 0 2.5 5 mm scale TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1 A max. 1.1

P89LPC933_934_935_936_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 26 November 2008 70 of 75 NXP Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core Fig 34. Package outline SOT788-1 (HVQFN28) 0.651 A 1 EhbcUNIT ye REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 6.1 5.9 6.1 5.9 D h 4.25 3.95 4.25 3.95 3.9 3.90.35 0.25 0.05 0.00 0.2 0.05 0.1 DIMENSIONS (mm are the original dimensions) 0.75 0.50 L 0.1 v 0.05 w 0 2.5 5 mm scale SOT788-1 HVQFN28: plastic thermal enhanced very thin quad flat package; no leads; 28 terminals; body 6 x 6 x 0.85 mm A (1) max. A A1 c detail X yy1 Ce L Eh D h e b 81 4 28 22 157 X D E C B A 02-10-22 terminal 1 index area terminal 1 index area AC C Bv M w M Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. D (1) E (1)

Table 17. Acronym list

Table 18. Revision history

20081126 Product data sheet - P89LPC933_934_

the new identity guidelines of NXP Semiconductors.

Legal texts have been adapted to the new company name where appropriate.
Added extended temperature device P89LPC933HDH. P89LPC933_934_ 935_936_6

20050620 Product data sheet - P89LPC933_934_

20041103 Product data sheet - P89LPC933_934_

20040209 Objective data - P89LPC933_934_

P89LPC933_934_935_936_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 26 November 2008 73 of 75 NXP Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core 17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

17.2 Deﬁnitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I 2C-bus — logo is a trademark of NXP B.V. 18. Contact information For more information, please visit:http://www.nxp.com For sales ofﬁce addresses, please send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

P89LPC933_934_935_936_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 26 November 2008 74 of 75 continued >> NXP Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core 19. Contents

8.20.9 Transmit interrupts with double buffering

8.20.10 The 9

th bit (bit 8) in double buffering

NXP Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 26 November 2008 Document identifier: P89LPC933_934_935_936_7 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 9.4.2 Fixed channel, continuous conversion mode . 54 9.4.5 Dual channel, continuous conversion mode . . 54

9.7 DAC output to a port pin with high output

11.1 I

Product Information

P89LPC933 specifications and overview.

Summary

8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs Rev. 07-26 November 2008

Description

8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs Rev. 07-26 November 2008

Source title P89LPC933 Datasheet(PDF) - NXP Semiconductors

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