Microcontroller

P89LPC9321FA

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM Rev. 01-9 December 2008

Manufacturer: NXP Semiconductors

Document: 70 Pages / 342Kb

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Technical content

General description The P89LPC9321 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC9321 in order to reduce component count, board space, and system cost. 2. Features

2.1 Principal features

n 8 kB byte-erasable ﬂash code memory organized into 1 kB sectors and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. n 256-byte RAM data memory and a 512-byte auxiliary on-chip RAM. n 512-byte customer data EEPROM on-chip allows serialization of devices, storage of setup parameters, etc. n Two analog comparators with selectable inputs and reference source. n Single Programmable Gain Ampliﬁer (PGA) with selectable gains of 2x, 4x, 8x, or 16x can be applied to analog comparator inputs. n Two 16-bit counter/timers (each may be conﬁgured to toggle a port output upon timer overﬂow or to become a PWM output). n A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit prescaler and a programmable and readable 16-bit timer. n Enhanced UART with a fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 kHz byte-wide I2C-bus communication port and SPI communication port. n Capture/Compare Unit (CCU) provides PWM, input capture, and output compare functions. n 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V). n 4-level low voltage (brownout) detect allows a graceful system shutdown when power fails. May optionally be conﬁgured as an interrupt. n 28-pin TSSOP , PLCC and DIP packages with 23 I/O pins minimum and up to 26 I/O pins while using on-chip oscillator and reset options. P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable ﬂash with 512-byte data EEPROM Rev. 01 — 9 December 2008 Product data sheet

2.2 Additional features

n A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI. n Serial ﬂash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. n Serial ﬂash In-System Programming (ISP) allows coding while the device is mounted in the end application. n In-Application Programming (IAP) of the ﬂash code memory. This allows changing the code in a running application. n Watchdog timer with separate on-chip oscillator, nominal 400 kHz, calibrated to±5% , requiring no external components. The watchdog prescaler is selectable from eight values. n High-accuracy internal RC oscillator option, with clock doubler option, allows operation without external oscillator components. The RC oscillator option is selectable and ﬁne tunable. n Switching on the ﬂy among internal RC oscillator, watchdog oscillator, external clock source provides optimal support of minimal power active mode with fast switching to maximum performance. n Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical power-down current is 1µA (total power-down with voltage comparators disabled). n Active-LOW reset. On-chip power-on reset allows operation without external reset components. A software reset function is also available. n Conﬁgurable on-chip oscillator with frequency range options selected by user programmed ﬂash conﬁguration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz. n Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function. n Programmable port output conﬁguration options: quasi-bidirectional, open drain, push-pull, input-only. n High current sourcing/sinking (20 mA) on eight I/O pins (P0.3 to P0.7, P1.4, P1.6, P1.7). All other port pins have high sinking capability (20 mA). A maximum limit is speciﬁed for the entire chip. n Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. n Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. n Only power and ground connections are required to operate the P89LPC9321 when internal reset option is selected. n Four interrupt priority levels. n Eight keypad interrupt inputs, plus two additional external interrupt inputs. n Schmitt trigger port inputs. n Second data pointer. n Emulation support.

3.1 Ordering options

Table 1. Ordering information Table 2. Ordering options

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 4 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core 4. Block diagram Fig 1. Block diagram ACCELERATED 2-CLOCK 80C51 CPU 8 kB CODE FLASH 256-BYTE DATA RAM PORT 2 CONFIGURABLE I/Os PORT 1 CONFIGURABLE I/Os PORT 0 CONFIGURABLE I/Os KEYPAD INTERRUPT PROGRAMMABLE OSCILLATOR DIVIDER CPU clock CONFIGURABLE OSCILLATOR ON-CHIP RC OSCILLATOR WITH CLOCK DOUBLER internal bus POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) 002aae102 UART ANALOG COMPARATORS (PGA1) 512-BYTE AUXILIARY RAM I2C-BUS 512-BYTE DATA EEPROM PORT 3 CONFIGURABLE I/Os CCU (CAPTURE/ COMPARE UNIT) P89LPC9321 WATCHDOG TIMER AND OSCILLATOR TIMER 0 TIMER 1 REAL-TIME CLOCK/ SYSTEM TIMER SPI P3[1:0] P2[7:0] P1[7:0] P0[7:0] TXD RXD SCL SDA CMP2 CIN2B CIN2A CMP1 CIN1A CIN1B OCA OCB OCC OCD ICA ICB SPICLK MOSI MISO SS CRYSTAL OR RESONATOR XTAL2 XTAL1

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 5 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core 5. Functional diagram Fig 2. Functional diagram VDD VSS PORT 0 PORT 3 TXD RXD INT0 INT1 RST SCL SDA 002aae103 CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF CMP1 XTAL2 XTAL1 KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI6 KBI7 MOSI MISO SS SPICLK PORT 1 PORT 2 P89LPC9321 OCB OCC ICB OCD OCA ICA CLKOUT

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 6 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core 6. Pinning information

6.1 Pinning

Fig 3. P89LPC9321 TSSOP28 pin conﬁguration Fig 4. P89LPC9321 PLCC28 pin conﬁguration P89LPC9321FDH 002aae104 P2.0/ICB P2.1/OCD P0.0/CMP2/KBI0 P1.7/OCC P1.6/OCB P1.5/RST VSS P3.1/XTAL1 P3.0/XTAL2/CLKOUT P1.4/INT1 P1.3/INT0/SDA P1.2/T0/SCL P2.2/MOSI P2.3/MISO P2.7/ICA P2.6/OCA P0.1/CIN2B/KBI1 P0.2/CIN2A/KBI2 P0.3/CIN1B/KBI3 P0.4/CIN1A/KBI4 P0.5/CMPREF/KBI5 V DD P0.6/CMP1/KBI6 P0.7/T1/KBI7 P1.0/TXD P1.1/RXD P2.5/SPICLK P2.4/SS P89LPC9321FA 002aae105 P1.6/OCB P1.5/RST VSS P3.1/XTAL1 P3.0/XTAL2/CLKOUT P1.4/INT1 P1.3/INT0/SDA P1.7/OCC P0.0/CMP2/KBI0 P2.1/OCD P2.0/ICB P2.7/ICA P2.6/OCA P0.1/CIN2B/KBI1 P0.2/CIN2A/KBI2 P0.3/CIN1B/KBI3 P0.4/CIN1A/KBI4 P0.5/CMPREF/KBI5 V DD P0.6/CMP1/KBI6 P0.7/T1/KBI7 P1.2/T0/SCL P2.2/MOSI P2.3/MISO P2.4/SS P2.5/SPICLK P1.1/RXD P1.0/TXD

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 7 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core Fig 5. P89LPC9321 DIP28 pin conﬁguration P89LPC9321FN 002aae106 P2.0/ICB P2.1/OCD P0.0/CMP2/KBI0 P1.7/OCC P1.6/OCB P1.5/RST VSS P3.1/XTAL1 P3.0/XTAL2/CLKOUT P1.4/INT1 P1.3/INT0/SDA P1.2/T0/SCL P2.2/MOSI P2.3/MISO P2.7/ICA P2.6/OCA P0.1/CIN2B/KBI1 P0.2/CIN2A/KBI2 P0.3/CIN1B/KBI3 P0.4/CIN1A/KBI4 P0.5/CMPREF/KBI5 V DD P0.6/CMP1/KBI6 P0.7/T1/KBI7 P1.0/TXD P1.1/RXD P2.5/SPICLK P2.4/SS

6.2 Pin description

Table 3. Pin description The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt trigger inputs. I CIN2B — Comparator 2 positive input B. I CIN2A — Comparator 2 positive input A. 24 I/O P0.3 — Port 0 bit 3. High current source. I CIN1B — Comparator 1 positive input B. 23 I/O P0.4 — Port 0 bit 4. High current source. I CIN1A — Comparator 1 positive input A. 22 I/O P0.5 — Port 0 bit 5. High current source. I CMPREF — Comparator reference (negative) input.

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. P0.6/CMP1/KBI6 20 I/O P0.6 — Port 0 bit 6. High current source. O CMP1 — Comparator 1 output. P0.7/T1/KBI7 19 I/O P0.7 — Port 0 bit 7. High current source. I/O T1 — Timer/counter 1 external count input or overﬂow output. Port 1 pins as inputs and outputs depends upon the port conﬁguration selected. All pins have Schmitt trigger inputs. O TXD — Transmitter output for serial port. I RXD — Receiver input for serial port. P1.2/T0/SCL 12 I/O P1.2 — Port 1 bit 2 (open-drain when used as output). 2C-bus serial clock input/output. P1.3/INT0/SDA 11 I/O P1.3 — Port 1 bit 3 (open-drain when used as output). I INT0 — External interrupt 0 input. I/O SDA — I2C-bus serial data input/output. P1.4/INT1 10 I/O P1.4 — Port 1 bit 4. High current source. I INT1 — External interrupt 1 input. P1.5/RST 6 I P1.5 — Port 1 bit 5 (input only). execution at address 0. Also used during a power-on sequence to force ISP mode. P1.6/OCB 5 I/O P1.6 — Port 1 bit 6. High current source. P1.7/OCC 4 I/O P1.7 — Port 1 bit 7. High current source. All pins have Schmitt trigger inputs.

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. when conﬁgured as slave, this pin is input. conﬁgured as slave, this pin is input. All pins have Schmitt trigger inputs. selected via the ﬂash conﬁguration. O CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6). used to generate the clock for the RTC/system timer. SS 7I Ground: 0 V reference. Table 3. Pin description …continued

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 11 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core 7. Functional description Remark: Please refer to the P89LPC9321 User manual for a more detailed functional description.

7.1 Special function registers

Remark: SFR accesses are restricted in the following ways:

User mustnot attempt to access any SFR locations not deﬁned.
Accesses to any deﬁned SFR locations must be strictly for the functions for the SFRs.
SFR bits labeled ‘-’, ‘0’ or ‘1’ canonly be written and read as follows: – ‘-’ Unless otherwise speciﬁed,must be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives. – ‘0’must be written with ‘0’, and will return a ‘0’ when read. – ‘1’must be written with ‘1’, and will return a ‘1’ when read.

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. [1] All ports are in input only (high-impedance) state after power-up. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. [4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF . [5] On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [6] The only reset sources that affect these SFRs are power-on reset and watchdog reset.

indicates SFRs that are bit addressable.

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. used to access these extended SFRs. [2] The BOICFG1/0 will be copied from UCFG1.5 and UCFG1.3 when power-on reset. Table 5. Extended special function registers[1]

7.2 Enhanced CPU

The P89LPC9321 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

7.3 Clocks

7.3.1 Clock deﬁnitions

The P89LPC9321 device has several internal clocks as deﬁned below: OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources (seeFigure6) and can also be optionally divided to a slower frequency (see Section 7.11 “CCLK modiﬁcation: DIVM register”). Remark: fosc is deﬁned as the OSCCLK frequency. CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles). RCCLK — The internal 7.373 MHz RC oscillator output. The clock doubler option, when enabled, provides an output frequency of 14.746 MHz. PCLK — Clock for the various peripheral devices and is CCLK ⁄2.

7.3.2 CPU clock (OSCCLK)

The P89LPC9321 provides several user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are conﬁgured when the ﬂash is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source.

7.4 External crystal oscillator option

The external crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 18 MHz. It can be the clock source of OSCCLK, RTC and WDT.

7.4.1 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this conﬁguration.

7.4.2 Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this conﬁguration.

7.4.3 High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this conﬁguration.

7.5 Clock output

The P89LPC9321 supports a user-selectable clock output function on the XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on XTAL1) and if the RTC and WDT are not using the crystal oscillator as their clock source. This allows external devices to synchronize to the P89LPC9321. This output is enabled by the ENCLK bit in the TRIM register. The frequency of this clock output is 1⁄2 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power.

7.6 On-chip RC oscillator option

The P89LPC9321 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7.373 MHz± 1 % at room temperature. End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. When the clock doubler option is enabled (UCFG2.7 = 1), the output frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower. When clock doubler option is enabled, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in reset at power-up until V DD has reached its speciﬁed level.

7.7 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz, calibrated to ± 5 % at room temperature. This oscillator can be used to save power when a high clock frequency is not needed.

7.8 External clock input option

In this conﬁguration, the processor clock is derived from an external source driving the P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2 pin may be used as a standard port pin or a clock output. When using an oscillator frequency above 12 MHz, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in reset at power-up until V DD has reached its speciﬁed level.

7.9 Clock sources switch on the ﬂy

P89LPC9321 can implement clock source switch in any sources of watchdog oscillator,

7 MHz/14 MHz IRC oscillator, external clock source (external crystal or external clock

input) during code is running. CLKOK bit in CLKCON register is used to indicate the clock switch status. CLKOK is cleared when starting clock source switch and set when completed. Notice that when CLKOK is ‘0’, writing to CLKCON register is not allowed.

7.10 CCLK wake-up delay

The P89LPC9321 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles plus 60 µst o1 0 0µs. If the clock source is the internal RC oscillator, the delay is 200µs to 300 µs. If the clock source is watchdog oscillator or external clock, the delay is 32 OSCCLK cycles.

7.11 CCLK modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.

7.12 Low power select

The P89LPC9321 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower. Fig 6. Block diagram of oscillator control 002aae108 RTC CPU WDT DIVM CCLK UART OSCCLK I2C-BUS PCLK TIMER 0 AND TIMER 1 HIGH FREQUENCY MEDIUM FREQUENCY LOW FREQUENCY XTAL1 XTAL2 RC OSCILLATOR WITH CLOCK DOUBLER WATCHDOG OSCILLATOR (7.3728 MHz/14.7456 MHz ± 1 %) PCLK RCCLK SPI CCU 32 × PLL(400 kHz ± 5 %)

7.13 Memory organization

DATA 128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area.
IDATA Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.
SFR Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.
XDATA ‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the DPTR, R0, or R1. All or part of this space could be implemented on-chip. The P89LPC9321 has 512 bytes of on-chip XDATA memory, plus extended SFRs located in XDATA.
CODE 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC9321 has 8 kB of on-chip Code memory. The P89LPC9321 also has 512 bytes of on-chip data EEPROM that is accessed via SFRs (seeSection7.14).

7.14 Data RAM arrangement

The 768 bytes of on-chip RAM are organized as shown inTable6.

7.15 Interrupts

comparators 1 and 2, SPI, CCU, data EEPROM write completion. disable bit, EA, which disables all interrupts. Table 6. On-chip data memory usages

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 25 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1 and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced. If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level.

7.15.1 External interrupt inputs

The P89LPC9321 has two external interrupt inputs as well as the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers. These external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit IT1 or IT0 in Register TCON. In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle and a LOW in the next cycle, the interrupt request ﬂag IEn in TCON is set, causing an interrupt request. If an external interrupt is enabled when the P89LPC9321 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section 7.18 “Pow er reduction modes” for details.

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 26 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core Fig 7. Interrupt sources, interrupt enables, and power-down wake-up sources 002aae160 IE0 EX0 IE1 EX1 BOIF EBO KBIF EKBI interrupt to CPU wake-up (if in power-down) EWDRT CMF2 CMF1 EC EA (IE0.7) TF1 ET1 TI and RI/RI ES/ESR TI EST SI EI2C SPIF ESPI RTCF ERTC (RTCCON.1) WDOVF TF0 ET0 any CCU interrupt ECCU EEIF EIEE

7.16 I/O ports

7.16.1 Port conﬁgurations

select the output type for each port pin. RST) can only be an input and cannot be conﬁgured.

P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be conﬁgured to be either input-only or

7.16.1.1 Quasi-bidirectional output conﬁguration

the quasi-bidirectional output that serve different purposes.

7.16.1.2 Open-drain output conﬁguration

Table 7. Number of I/O pins available

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 28 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core An open-drain port pin has a Schmitt trigger input that also has a glitch suppression circuit.

7.16.1.3 Input-only conﬁguration

The input-only port conﬁguration has no output drivers. It is a Schmitt trigger input that also has a glitch suppression circuit.

7.16.1.4 Push-pull output conﬁguration

The push-pull output conﬁguration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output. A push-pull port pin has a Schmitt triggered input that also has a glitch suppression circuit. The P89LPC9321 device has high current source on eight pins in push-pull mode. See Table 9 “Limiting values”.

7.16.2 Port 0 analog functions

The P89LPC9321 incorporates two Analog Comparators. In order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port output into the Input-Only (high-impedance) mode. Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5. On any reset, PT0AD[1:5] defaults to logic 0s to enable digital functions.

7.16.3 Additional port features

After power-up, all pins are in Input-Only mode.Please note that this is different from the LPC76x series of devices.

After power-up, all I/O pins except P1.5, may be conﬁgured by software.
Pin P1.5 is input only. Pins P1.2 and P1.3 are conﬁgurable for either input-only or open-drain. Every output on the P89LPC9321 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to Table 10 “Static characteristics” for detailed speciﬁcations. All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.

7.17 Power monitoring functions

The P89LPC9321 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on detect and brownout detect.

7.17.1 Brownout detection

The brownout detect function determines if the power supply voltage drops below a certain level. Enhanced brownout detection has 3 independent functions: BOD reset, BOD interrupt and BOD EEPROM/FLASH. BOD reset is always on except in total power-down mode. It could not be disabled in software. BOD interrupt may be enabled or disabled in software. BOD EEPROM/FLASH is always on, except in power-down modes and could not be disabled in software. BOD reset and BOD interrupt, each has four trip voltage levels. BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are used as trip point conﬁguration bits of BOD reset. BOICFG1 bit and BOICFG0 bit in register BODCFG are used as trip point conﬁguration bits of BOD interrupt. BOD reset voltage should be lower than BOD interrupt trip point. BOD EEPROM/FLASH is used for ﬂash/Data EEPROM programming/erase protection and has only 1 trip voltage of 2.4 V. Please refer to P89LPC9321 User manual for detail conﬁgurations. If brownout detection is enabled the brownout condition occurs when VDD falls below the brownout trip voltage and is negated when VDD rises above the brownout trip voltage. For correct activation of brownout detect, the VDD rise and fall times must be observed. Please seeTable 10 “Static characteristics” for speciﬁcations.

7.17.2 Power-on detection

The Power-on detect has a function similar to the brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. The POF ﬂag in the RSTSRC register is set to indicate an initial power-up condition. The POF ﬂag will remain set until cleared by software.

7.18 Power reduction modes

The P89LPC9321 supports three different power reduction modes. These modes are Idle mode, Power-down mode, and total Power-down mode.

7.18.1 Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode.

7.18.2 Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC9321 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the data retention supply voltage V DDR . This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after VDD has been lowered to VDDR , therefore it is highly recommended to wake-up the processor via reset in this case. VDD must be raised to within the operating range before the Power-down mode is exited.

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 30 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during power-down. These include: Brownout detect, watchdog timer, comparators (note that comparators can be powered down separately), and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled.

7.18.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during power-down, there will be high power consumption. Please use an external low frequency clock to achieve low power with the RTC running during power-down.

7.19 Reset

The P1.5/RST pin can function as either a LOW-active reset input or as a digital input, P1.5. The Reset Pin Enable (RPE) bit in UCFG1, when set to logic 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin. Remark: During a power-up sequence, the RPE selection is overridden and this pin always functions as a reset input.An external circuit connected to this pin should not hold this pin LOW during a power-on sequence as this will keep the device in reset. After power-up this pin will function as deﬁned by the RPE bit. Only a power-up reset will temporarily override the selection deﬁned by RPE bit. Other sources of reset will not override the RPE bit. Note:During a power cycle, V DD must fall below VPOR before power is reapplied, in order to ensure a power-on reset (seeTable 10 “Static characteristics”). Reset can be triggered from the following sources:

External reset pin (during power-up or if user conﬁgured via UCFG1)
Power-on detect
Brownout detect
Watchdog timer
Software reset
UART break character detect reset For every reset source, there is a ﬂag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These ﬂag bits can be cleared in software by writing a logic 0 to the corresponding bit. More than one ﬂag bit may be set:
During a power-on reset, both POF and BOF are set but the other ﬂag bits are cleared.
A Watchdog reset is similar to a power-on reset, both POF and BOF are set but the other ﬂag bits are cleared.
For any other reset, previously set ﬂag bits that have not been cleared will remain set.

7.19.1 Reset vector

Following reset, the P89LPC9321 will fetch instructions from either address 0000H or the Boot address. The Boot address is formed by using the boot vector as the high byte of the address and the low byte of the address = 00H. The boot address will be used if a UART break reset occurs, or the non-volatile boot status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see P89LPC9321 User manual). Otherwise, instructions will be fetched from address 0000H.

7.20 Timers/counters 0 and 1

The P89LPC9321 has two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. Both can be conﬁgured to operate either as timers or event counters. An option to automatically toggle the T0 and/or T1 pins upon timer overﬂow has been added. In the ‘Timer’ function, the register is incremented every machine cycle. In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled once during every machine cycle. Timer 0 and Timer 1 have ﬁve operating modes (Modes 0, 1, 2, 3 and 6). Modes 0, 1, 2 and 6 are the same for both Timers/Counters. Mode 3 is different.

7.20.1 Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. In this mode, the Timer register is conﬁgured as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.

7.20.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

7.20.3 Mode 2

Mode 2 conﬁgures the Timer register as an 8-bit Counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1.

7.20.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.

7.20.5 Mode 6

In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks.

7.20.6 Timer overﬂow toggle output

Timers 0 and 1 can be conﬁgured to automatically toggle a port output whenever a timer overﬂow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the ﬁrst timer overﬂow when this mode is turned on.

7.21 RTC/system timer

The P89LPC9321 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered down. The RTC can be a wake-up or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will be reloaded again and the RTCF ﬂag will be set. The clock source for this counter can be either the CPU clock (CCLK) or the XTAL oscillator. Only power-on reset and watchdog reset will reset the RTC and its associated SFRs to the default state. The 16-bit loadable counter portion of the RTC is readable by reading the RTCDATL and RTCDATH registers.

7.22 CCU

This unit features:

A 16-bit timer with 16-bit reload on overﬂow.
Selectable clock, with prescaler to divide clock source by any integral number between 1 and 1024.
Four compare/PWM outputs with selectable polarity
Symmetrical/asymmetrical PWM selection
Two capture inputs with event counter and digital noise rejection ﬁlter
Seven interrupts with common interrupt vector (one overﬂow, two capture, four compare)
Safe 16-bit read/write via shadow registers.

7.22.1 CCU clock

The CCU runs on the CCUCLK, which is either PCLK in basic timer mode, or the output of a PLL. The PLL is designed to use a clock source between 0.5 MHz to 1 MHz that is multiplied by 32 to produce a CCUCLK between 16 MHz and 32 MHz in PWM mode (asymmetrical or symmetrical). The PLL contains a 4-bit divider to help divide PCLK into a frequency between 0.5 MHz and 1 MHz.

7.22.2 CCUCLK prescaling

This CCUCLK can further be divided down by a prescaler. The prescaler is implemented as a 10-bit free-running counter with programmable reload at overﬂow.

7.22.3 Basic timer operation

The timer is a free-running up/down counter with a direction control bit. If the timer counting direction is changed while the counter is running, the count sequence will be reversed. The timer can be written or read at any time.

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 33 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core When a reload occurs, the CCU Timer Overﬂow Interrupt Flag will be set, and an interrupt generated if enabled. The 16-bit CCU timer may also be used as an 8-bit up/down timer.

7.22.4 Output compare

There are four output compare channels: A, B, C and D. Each output compare channel needs to be enabled in order to operate and the user will have to set the associated I/O pin to the desired output mode to connect the pin. When the contents of the timer matches that of a capture compare control register, the Timer Output Compare Interrupt Flag (TOCFx) becomes set. An interrupt will occur if enabled.

7.22.5 Input capture

Input capture is always enabled. Each time a capture event occurs on one of the two input capture pins, the contents of the timer is transferred to the corresponding 16-bit input capture register. The capture event can be programmed to be either rising or falling edge triggered. A simple noise ﬁlter can be enabled on the input capture by enabling the Input Capture Noise Filter bit. If set, the capture logic needs to see four consecutive samples of the same value in order to recognize an edge as a capture event. An event counter can be set to delay a capture by a number of capture events.

7.22.6 PWM operation

PWM operation has two main modes, symmetrical and asymmetrical. In asymmetrical PWM operation the CCU timer operates in down-counting mode regardless of the direction control bit. In symmetrical mode, the timer counts up/down alternately. The main difference from basic timer operation is the operation of the compare module, which in PWM mode is used for PWM waveform generation. As with basic timer operation, when the PWM (compare) pins are connected to the compare logic, their logic state remains unchanged. However, since bit FCO is used to hold the halt value, only a compare event can change the state of the pin. Fig 8. Asymmetrical PWM, down-counting TOR2 compare value timer value non-inverted inverted 0x0000 002aaa893

7.22.7 Alternating output mode

In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating pairs for bridge drive control. In this mode the output of these PWM channels are alternately gated on every counter cycle.

7.22.8 PLL operation

The PWM module features a Phase Locked Loop that can be used to generate a CCUCLK frequency between 16 MHz and 32 MHz. At this frequency the PWM module provides ultrasonic PWM frequency with 10-bit resolution provided that the crystal frequency is 1 MHz or higher. The PLL is fed an input signal from 0.5 MHz to 1 MHz and generates an output signal of 32 times the input frequency. This signal is used to clock the timer. The user will have to set a divider that scales PCLK by a factor from 1 to 16. This divider is found in the SFR register TCR21. The PLL frequency can be expressed as shown in Equation1: (1) Where: N is the value of PLLDV3:0. Fig 9. Symmetrical PWM TOR2 compare value timer value non-inverted inverted 002aaa894 Fig 10. Alternate output mode TIMER VALUE 002aaa895 TOR2 COMPARE VALUE A (or C) COMPARE VALUE B (or D) PWM OUTPUT (OCA or OCC) PWM OUTPUT (OCB or OCD) PLL frequency PCLK

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 35 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core Since N ranges from 0 to 15, the CCLK frequency can be in the range of PCLK to PCLK16.

7.22.9 CCU interrupts

There are seven interrupt sources on the CCU which share a common interrupt vector.

7.23 UART

The P89LPC9321 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overﬂow cannot be used as a baud rate source. The P89LPC9321 does include an independent baud rate generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overﬂow, or the independent baud rate generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options. The UART can be operated in four modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16.

7.23.1 Mode 0

Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted or received, LSB ﬁrst. The baud rate is ﬁxed at 1⁄16 of the CPU clock frequency. Fig 11. Capture/compare unit interrupts 002aaa896 interrupt to CPU TOIE2 (TICR2.7) TOIF2 (TIFR2.7) TICIE2A (TICR2.0) TICF2A (TIFR2.0) TICIE2B (TICR2.1) TICF2B (TIFR2.1) TOCIE2A (TICR2.3) TOCF2A (TIFR2.3) TOCIE2B (TICR2.4) TOCF2B (TIFR2.4) TOCIE2C (TICR2.5) TOCF2C (TIFR2.5) TOCIE2D (TICR2.6) TOCF2D (TIFR2.6) EA (IEN0.7) ECCU (IEN1.4) PRIORITY ENCODER other interrupt sources ENCINT.0 ENCINT.1 ENCINT.2

7.23.2 Mode 1

10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB ﬁrst), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8 in special function register SCON. The baud rate is variable and is determined by the Timer 1 overﬂow rate or the baud rate generator (described in Section 7.23.5 “Baud rate generator and selection”).

7.23.3 Mode 2

11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logic 1). When data is transmitted, the 9thdata bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1. Or, for example, the parity bit (P , in the PSW) could be moved into TB8. When data is received, the 9 th data bit goes into RB8 in special function register SCON, while the stop bit is not saved. The baud rate is programmable to either1⁄16 or1⁄32 of the CPU clock frequency, as determined by the SMOD1 bit in PCON.

7.23.4 Mode 3

11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB ﬁrst), a programmable 9 thdata bit, and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overﬂow rate or the baud rate generator (described in Section 7.23.5 “Baud rate generator and selection”).

7.23.5 Baud rate generator and selection

The P89LPC9321 enhanced UART has an independent baud rate generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be used for other timing functions. The UART can use either Timer 1 or the baud rate generator output (see Figure12). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The independent baud rate generators use OSCCLK.

7.23.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up when SMOD0 is logic 0. Fig 12. Baud rate sources for UART (Modes 1, 3) baud rate modes 1 and 3 SBRGS = 1 SBRGS = 0 SMOD1 = 0 SMOD1 = 1timer 1 overflow (PCLK-based) baud rate generator (CCLK-based) 002aaa897

7.23.7 Break detect

Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device and force the device into ISP mode.

7.23.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to be written to SnBUF while the ﬁrst character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 =0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SBUF while the previous data is being shifted out. Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = 0).

7.23.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the TI interrupt is generated when the double buffer is ready to receive new data.

7.23.10 The 9th bit (bit 8) in double buffering (modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the TI interrupt. If double buffering is enabled, TBmust be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data.

7.24 I2C-bus serial interface

The I2C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features:

Bidirectional data transfer between masters and slaves
Multi master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer
The I2C-bus may be used for test and diagnostic purposes. A typical I2C-bus conﬁguration is shown inFigure13. The P89LPC9321 device provides a byte-oriented I2C-bus interface that supports data transfers up to 400 kHz.

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 38 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core Fig 13. I2C-bus conﬁguration OTHER DEVICE WITH I2C-BUS INTERFACE SDA SCL R PR P OTHER DEVICE WITH I2C-BUS INTERFACE P1.3/SDA P1.2/SCL P89LPC9321 I2C-bus 002aae109

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 39 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core Fig 14. I2C-bus serial interface block diagram INTERNAL BUS 002aaa899 ADDRESS REGISTER COMPARATOR SHIFT REGISTER I2ADR ACK BIT COUNTER / ARBITRATION AND SYNC LOGIC I2DAT TIMING AND CONTROL LOGIC SERIAL CLOCK GENERATOR CCLK interrupt INPUT FILTER OUTPUT STAGE INPUT FILTER OUTPUT STAGE P1.3 P1.3/SDA P1.2/SCL P1.2 timer 1 overflow CONTROL REGISTERS AND SCL DUTY CYCLE REGISTERS I2CON I2SCLH I2SCLL STATUS DECODERstatus bus STATUS REGISTER I2STAT

7.25 SPI

The P89LPC9321 provides another high-speed serial communication interface: the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in either Master mode or Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection. The SPI interface has four pins: SPICLK, MOSI, MISO and SS:

SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data ﬂows from master to slave on MOSI (Master Out Slave In) pin and ﬂows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output in the Master mode and is input in the Slave mode. If the SPI system is disabled, i.e., SPEN (SPCTL.6) = 0 (reset value), these pins are conﬁgured for port functions.
SS is the optional slave select pin. In a typical conﬁguration, an SPI master asserts one of its port pins to select one SPI device as the current slave. An SPI slave device uses its SS pin to determine whether it is selected. Typical connections are shown inFigure16 throughFigure18. Fig 15. SPI block diagram 002aaa900 CPU clock DIVIDER BY 4, 16, 64, 128 SELECT CLOCK LOGIC SPI CONTROL REGISTER READ DATA BUFFER 8-BIT SHIFT REGISTER SPI CONTROL SPI STATUS REGISTER SPR1 SPIF WCOL SPR0 SPI clock (master) PIN CONTROL LOGIC S M S M M S MISO P2.3 MOSI P2.2 SPICLK P2.5 SS P2.4 SPI interrupt request internal data bus SSIG SPEN SPEN MSTR DORD MSTR CPHA CPOL SPR1 SPR0 MSTR SPEN clock

7.25.1 Typical SPI conﬁgurations

Fig 16. SPI single master single slave conﬁguration Fig 17. SPI dual device conﬁguration, where either can be a master or a slave 002aaa901 master slave 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR 8-BIT SHIFT REGISTER MISO MOSI SPICLK PORT MISO MOSI SPICLK SS 002aaa902 master slave 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR SPI CLOCK GENERATOR 8-BIT SHIFT REGISTER MISO MOSI SPICLK MISO MOSI SPICLK SSSS

7.26 Analog comparators

Two analog comparators are provided on the P89LPC9321. Input and output options allow use of the comparators in a number of different conﬁgurations. Comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable inputs) is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be conﬁgured to cause an interrupt when the output value changes. The positive inputs of comparators could be ampliﬁed by Programmable Gain Ampliﬁer 1 (PGA1) module. The PGA1 can supply gain factors of 2x, 4x, 8x, or 16x, eliminating the need for external op-amps in the end application. The overall connections to both comparators are shown in Figure19. The comparators function to VDD = 2.4 V. When each comparator is ﬁrst enabled, the comparator output and interrupt ﬂag are not guaranteed to be stable for 10µs. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt ﬂag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. When a comparator is disabled the comparator’s output, COn, goes HIGH. If the comparator output was LOW and then is disabled, the resulting transition of the comparator output from a LOW to HIGH state will set the comparator ﬂag, CMFn. This will cause an interrupt if the comparator interrupt is enabled. The user should therefore disable the comparator interrupt prior to disabling the comparator. Additionally, the user should clear the comparator ﬂag, CMFn, after disabling the comparator. Fig 18. SPI single master multiple slaves conﬁguration 002aaa903 master slave 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR 8-BIT SHIFT REGISTER MISO MOSI SPICLK port port MISO MOSI SPICLK SS slave 8-BIT SHIFT REGISTER MISO MOSI SPICLK SS

7.26.1 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as V ref(bg), is 1.23 V± 10 %.

7.26.2 Comparator interrupt

Each comparator has an interrupt ﬂag contained in its conﬁguration register. This ﬂag is set whenever the comparator output changes state. The ﬂag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. If both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the ﬂags to determine which comparator caused the interrupt.

7.26.3 Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode. If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake-up the processor. If the comparator output to a pin is enabled, the pin should be conﬁgured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with theoscillatorstopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. Comparators consume power in Power-down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparators via PCONA.5, or put the device in Total Power-down mode. Fig 19. Comparator input and output connections comparator 1 CP1 CN1 (P0.4) CIN1A (P0.3) CIN1B (P0.5) CMPREF Vref(bg) OE1 CO1 CMF1 interrupt 002aad561 CMP1 (P0.6) EC CMF2 comparator 2 OE2 CO2 CMP2 (P0.0) CP2 CN2 (P0.2) CIN2A (P0.1) CIN2B PGA1 change detect change detect

7.27 KBI

The Keypad Interrupt function (KBI) is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can conﬁgure the port via SFRs for different tasks. The Keypad Interrupt Mask Register (KBMASK) is used to deﬁne which input pins connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to deﬁne a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to deﬁne equal or not-equal for the comparison. In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake-up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. In order to set the ﬂag and cause an interrupt, the pattern on Port 0 must be held longer than six CCLKs.

7.28 Watchdog timer

The watchdog timer causes a system reset when it underﬂows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler. The clock source for the prescaler can be the PCLK, the nominal 400 kHz watchdog oscillator or external crystal oscillator. The watchdog timer can only be reset by a power-on reset. When the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure20 shows the watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a fewµs to a few seconds. Please refer to the P89LPC9321 User manual for more details.

7.29 Additional features

7.29.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets.

7.29.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register.

7.29.3 Data EEPROM

The P89LPC9321 has 512 bytes of on-chip Data EEPROM. The Data EEPROM is SFR based, byte readable, byte writable, and erasable (via row ﬁll and sector ﬁll). The user can read, write and ﬁll the memory via SFRs and one interrupt. This Data EEPROM provides 100,000 minimum erase/program cycles for each byte.

Byte mode: In this mode, data can be read and written one byte at a time.
Row ﬁll: In this mode, the addressed row (64 bytes) is ﬁlled with a single value. The entire row can be erased by writing 00H.
Sector ﬁll: In this mode, all 512 bytes are ﬁlled with a single value. The entire sector can be erased by writing 00H. (1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence. Fig 20. Watchdog timer in Watchdog mode (WDTE = 1) PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLKWDCON (A7H) SHADOW REGISTER PRESCALER 002aae015 8-BIT DOWN COUNTER WDL (C1H) watchdog oscillator external crystal oscillator PCLK XTALWD ÷32 MOV WFEED1, #0A5H MOV WFEED2, #05AH reset(1)

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 46 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core After the operation ﬁnishes, the hardware will set the EEIF bit, which if enabled will generate an interrupt. The ﬂag is cleared by software. Remark: When voltage supply is lower than 2.4 V, the BOD FLASH is tripped and Data EEPROM program or erase is blocked. EWERR1 and EWERR0 bits are used to indicate the write error for BOD EEPROM. Both can be cleared by power on reset, watchdog reset or software write.

7.30 Flash program memory

7.30.1 General description

The P89LPC9321 ﬂash memory provides in-circuit electrical erasure and programming. The ﬂash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any ﬂash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase the entire program memory. ICP using standard commercial programmers is available. In addition, IAP and byte-erase allows code memory to be used for non-volatile data storage. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC9321 ﬂash reliably stores memory contents even after 100,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. The P89LPC9321 uses V DD as the supply voltage to perform the Program/Erase algorithms. When voltage supply is lower than 2.4 V, the BOD FLASH is tripped and ﬂash erase/program is blocked.

7.30.2 Features

Programming and erase over the full operating voltage range.
Byte erase allows code memory to be used for data storage.
Read/Programming/Erase using ISP/IAP/ICP .
Internal ﬁxed boot ROM, containing low-level IAP routines available to user code.
Default loader providing ISP via the serial port, located in upper end of user program memory.
Boot vector allows user-provided ﬂash loader code to reside anywhere in the ﬂash memory space, providing ﬂexibility to the user.
Any ﬂash program/erase operation in 2 ms.
Programming with industry-standard commercial programmers.
Programmable security for the code in the ﬂash for each sector.
100,000 typical erase/program cycles for each byte.
10 year minimum data retention.

7.30.3 Flash organization

The program memory consists of eight 1 kB sectors on the P89LPC9321 devices. Each sector can be further divided into 64-byte pages. In addition to sector erase, page erase, and byte erase, a 64-byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time.

7.30.4 Using ﬂash as data storage

The ﬂash code memory array of this device supports individual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the sector containing the byte has not been secured (a MOVC instruction is not allowed to read code memory contents of a secured sector). Thus any byte in a non-secured sector may be used for non-volatile data storage.

7.30.5 Flash programming and erasing

Four different methods of erasing or programming of the ﬂash are available. The ﬂash may be programmed or erased in the end-user application (IAP) under control of the application’s ﬁrmware. Another option is to use the ICP mechanism. This ICP system provides for programming through a serial clock/serial data interface. As shipped from the factory, the upper 512 bytes of user code space contains a serial ISP routine allowing for the device to be programmed in circuit through the serial port. The ﬂash may also be programmed or erased using a commercially available EPROM programmer which supports this device. This device does not provide for direct veriﬁcation of code memory contents. Instead, this device provides a 32-bit Cyclic Redundancy Check (CRC) result on either a sector or the entire user code space. Remark: When voltage supply is lower than 2.4 V, the BOD FLASH is tripped and ﬂash erase/program is blocked.

7.30.6 ICP

ICP is performed without removing the microcontroller from the system. The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC9321 through a two-wire serial interface. The NXP ICP facility has made in-circuit programming in an embedded application - using commercially available programmers - possible with a minimum of additional expense in components and circuit board area. The ICP function uses ﬁve pins. Only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature. Additional details may be found in the P89LPC9321 User manual.

7.30.7 IAP

IAP is performed in the application under the control of the microcontroller’s ﬁrmware. The IAP facility consists of internal hardware resources to facilitate programming and erasing. The NXP IAP has made in-application programming in an embedded application possible without additional components. Two methods are available to accomplish IAP . A set of predeﬁned IAP functions are provided in a Boot ROM and can be called through a common interface, PGM_MTP . Several IAP calls are available for use by an application program to permit selective erasing and programming of ﬂash sectors, pages, security bits, conﬁguration bytes, and device ID. These functions are selected by setting up the microcontroller’s registers before making a call to PGM_MTP at FF03H. The Boot ROM occupies the program memory space at the top of the address space from FF00H to FEFFH, thereby not conﬂicting with the user program memory space. In addition, IAP operations can be accomplished through the use of four SFRs consisting of a control/status register, a data register, and two address registers. Additional details may be found in the P89LPC9321 User manual.

7.30.8 ISP

interface your application to an external circuit in order to use this feature.

7.30.9 Power-on reset code execution

Status bit. Following reset, the P89LPC9321 examines the contents of the Boot Status bit. execution address and the low byte is set to 00H. boot loader entry point to perform ISP functions. This code can be erased by the user. erase the ﬁrst eight 64-byte pages located in this sector.

7.30.10 Hardware activation of the boot loader

code beginning at address 0000H.

7.31 User conﬁguration bytes

User’s Manual for additional details. Table 8. Default boot vector values and ISP entry points

7.32 User sector security bytes

There are eight User Sector Security Bytes on the P89LPC9321. Each byte corresponds to one sector. Please see the P89LPC9321 User manual for additional details.

7.33 PGA

Additional PGA module is integrated. The gain of PGA can be programmable to 2, 4, 8 and 16. Please refer to Table 10 “Static characteristics” for detailed speciﬁcations. Register PGACON1 and PGACON1B are used to for PGA1 conﬁguration. Register PGA1TRIM2X4X and PGA1TRIM8X16X provide trim value of PGA1 gain level. As power-on, default trim value for each gain setting is loaded into the PGA1 trim registers. For accurate measurements, offset calibration is required. Please see the P89LPC9321 User manual for detail conﬁguration, calibration, and usage information. In Power-down mode or Total Power-down mode, the PGA1 does not function. If the PGAs, is enabled, it will consume power. Power can be reduced by disabling the PGA1.

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. Table 9. Limiting values

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Table 10. Static characteristics VDD = 2.4 V to 3.6 V unless otherwise speciﬁed. Tamb = −40 °C to +85°C for industrial applications, unless otherwise speciﬁed.

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. [1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V. real-time clock, and watchdog timer. brownout detect, and watchdog timer. exceed the related speciﬁcation. Table 10. Static characteristics …continued VDD = 2.4 V to 3.6 V unless otherwise speciﬁed. Tamb = −40 °C to +85°C for industrial applications, unless otherwise speciﬁed.

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 53 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core [5] This speciﬁcation can be applied to pins which have A/D input or analog comparator input functions when the pin is not being used for those analog functions. When the pin is being used as an analog input pin, the maximum voltage on the pin must be limited to 4.0 V with respect to V SS . [6] Pin capacitance is characterized but not tested. [7] Measured with port in quasi-bidirectional mode. [8] Measured with port in high-impedance mode. [9] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is highest when V I is approximately 2 V.

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. [1] Parameters are valid over operating temperature range unless otherwise speciﬁed. [2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. Table 11. Dynamic characteristics (12 MHz) …continued VDD = 2.4 V to 3.6 V unless otherwise speciﬁed.

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. [1] Parameters are valid over operating temperature range unless otherwise speciﬁed. [2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. Table 12. Dynamic characteristics (18 MHz) …continued VDD = 3.0 V to 3.6 V unless otherwise speciﬁed.

10.1 Waveforms

Fig 21. Shift register mode timing 01 2 3 4 5 6 7 valid valid valid valid valid valid valid valid TXLXL 002aaa906 set TI set RI tXHQXtQVXH tXHDV tXHDX clock output data write to SBUF input data clear RI Fig 22. External clock timing tCHCL tCLCX tCHCX Tcy(clk) tCLCH 002aaa907 Fig 23. SPI master timing (CPHA = 0) TSPICYC tSPICLKH tSPICLKH tSPICLKL tSPICLKL master LSB/MSB outmaster MSB/LSB out tSPIDHtSPIDSU tSPIF tSPIOH tSPIDV tSPIRtSPIDV tSPIF tSPIR tSPIF tSPIR SS SPICLK (CPOL = 0) (output) 002aaa908 SPICLK (CPOL = 1) (output) MISO (input) MOSI (output) LSB/MSB inMSB/LSB in

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 59 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core Fig 24. SPI master timing (CPHA = 1) TSPICYC tSPICLKL tSPICLKL tSPICLKH tSPICLKH master LSB/MSB outmaster MSB/LSB out tSPIDHtSPIDSU tSPIF tSPIOH tSPIDV tSPIDV tSPIR tSPIDV tSPIF tSPIF tSPIR tSPIR SS SPICLK (CPOL = 0) (output) 002aaa909 SPICLK (CPOL = 1) (output) MISO (input) MOSI (output) LSB/MSB inMSB/LSB in Fig 25. SPI slave timing (CPHA = 0) TSPICYC tSPICLKH tSPICLKH tSPICLKL tSPICLKL tSPILEAD tSPILAG tSPIDSU tSPIDH tSPIDHtSPIDSU tSPIDSU tSPIR tSPIA tSPIOH tSPIDIS tSPIR slave MSB/LSB out MSB/LSB in LSB/MSB in slave LSB/MSB out tSPIDV tSPIOH tSPIOH tSPIDV tSPIR tSPIR tSPIF tSPIF SS SPICLK (CPOL = 0) (input) 002aaa910 SPICLK (CPOL = 1) (input) MISO (output) MOSI (input) not defined

10.2 ISP entry mode

Table 13. Dynamic characteristics, ISP entry mode VDD = 2.4 V to 3.6 V, unless otherwise speciﬁed. Tamb = −40 °C to +85°C for industrial applications, unless otherwise speciﬁed.

11.1 Comparator electrical characteristics

[1] This parameter is characterized, but not tested in production. Table 14. Comparator electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise speciﬁed. Tamb = −40 °C to +85°C for industrial applications, unless otherwise speciﬁed.

11.2 PGA electrical characteristics

Table 15. PGA electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise speciﬁed. Tamb = −40 °C to +85°C for industrial applications, unless otherwise speciﬁed. All limits valid for an external source impedance of less than 10 kΩ .

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 63 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core 12. Package outline Fig 28. PLCC28 package outline (SOT261-2) REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. SOT261-2 112E08 MS-018 EDR-7319 1925 51 1 detail X (A )3 bp w M A 1 A A 4 Lp b k Xy e E B DH EH v M B D Z D A Z E e v M A 0 5 10 mm scale 99-12-27 01-11-15 pin 1 index PLCC28: plastic leaded chip carrier; 28 leads SOT261-2 UNIT b mm 4.57 4.19 0.51 3.05 0.53 0.33 0.021 0.013 1.27 2.16 45o 0.18 0.10.18 DIMENSIONS (mm dimensions are derived from the original inch dimensions) 11.58 11.43 12.57 12.32 2.160.81 0.66 1.22 1.07 0.180 0.165 0.02 0.12 0.25 1.44 1.02 0.057 0.040 0.456 0.450 11.58 11.43 0.456 0.450 0.495 0.485 12.57 12.32 0.495 0.485 10.92 9.91 0.43 0.39 10.92 9.91 0.43 0.39 0.0850.032 0.026 0.048 0.042 Ee inches De A A 1 min. A 4 max. bp ey wvD (1) E(1) H D H E ZD (1) max. ZE(1) max. b1 kA 3 LpeD eE

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 64 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core Fig 29. TSSOP28 package outline (SOT361-1) UNIT A 1 A 2 A 3 bp cD (1) E (2) (1)eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 9.8 9.6 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.8 0.5 o o0.13 0.10.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT361-1 MO-153 99-12-27 03-02-19 0.25 w M bp Z e 11 4 28 15 pin 1 index q AA 1 A 2 Lp Q detail X L (A )3 H E E c v M A XAD y 0 2.5 5 mm scale TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1 A max. 1.1

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 65 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core Fig 30. DIP28 package outline (SOT117-1) UNIT A max. 1 2 b1 (1)(1) (1)cD E w eM HL REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches DIMENSIONS (mm dimensions are derived from the original inch dimensions) SOT117-1 99-12-27 03-02-13 A min. A max. b Z max.M Ee1 1.7 1.3 0.53 0.38 0.32 0.23 14.1 13.7 3.9 15.24 17.15 15.90 1.75.1 0.51 4 0.066 0.051 0.020 0.014 0.013 0.009 1.41 1.34 0.56 0.54 0.15 0.60 0.68 051G05 MO-015 SC-510-28 M H c (e )1 M E A L seating plane w M e D A 2 Z b E pin 1 index 0 5 10 mm scale Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. DIP28: plastic dual in-line package; 28 leads (600 mil) SOT117-1

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 68 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core 15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

15.2 Deﬁnitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I 2C-bus — logo is a trademark of NXP B.V. 16. Contact information For more information, please visit:http://www.nxp.com For sales ofﬁce addresses, please send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 69 of 70 continued >> NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core 17. Contents

7.23.9 Transmit interrupts with double buffering

7.23.10 The 9

th bit (bit 8) in double buffering

NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 December 2008 Document identifier: P89LPC9321_1 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

Product Information

P89LPC9321FA specifications and overview.

Summary

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM Rev. 01-9 December 2008

Description

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM Rev. 01-9 December 2008

Source title P89LPC9321FA Datasheet(PDF) - NXP Semiconductors

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