Microcontroller

P89LPC9171FDH

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core, 2 kB 3 V byte-erasable flash with 8-bit ADC Rev. 02-9 February 2010

Manufacturer: NXP Semiconductors

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Technical content

General description The P89LPC9151/9161/9171 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the device in order to reduce component count, board space, and system cost. 2. Features

2.1 Principal features

2 kB byte-erasable flash code memory organized into 256-byte sectors and 16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. 256-byte RAM data memory. 4-input multiplexed 8-bit ADC/single DAC output. Two analog comparators with selectable inputs and reference source. Two 16-bit counter/timers. Timer 0 (and Timer 1 - P89LPC9171) may be configured to toggle a port output upon timer overflow or to become a PWM output. A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit prescaler and a programmable and readable 16-bit timer. Enhanced UART with a fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 kHz byte-wide I2C-bus communication port. SPI communication port (P89LPC9161). 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V). Enhanced low voltage (brownout) detect allows a graceful system shutdown when power fails. 16-pin TSSOP with 12 I/O pins minimum and up to 14 I/O pins while using on-chip oscillator and reset options (P89LPC9161/9171), and 14-pin TSSOP packages with 10 I/O pins minimum and up to 12 I/O pins while using on-chip oscillator and reset options (P89LPC9151). P89LPC9151/9161/9171 8-bit microcontroller with accelerated two-clock 80C51 core, 2 kB 3 V byte-erasable flash with 8-bit ADC Rev. 02 — 9 February 2010 Product data sheet

2.2 Additional features

A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI. In-Application Programming (IAP-Lite) and byte erase allows code memory to be used for non-volatile data storage. Serial flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. Watchdog timer with separate on-chip oscillator, nominal 400 kHz, calibrated to ±5 %, requiring no external components. The watchdog prescaler is selectable from eight values. High-accuracy internal RC oscillator option, with clock doubler option, allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable. Clock switching on the fly among internal RC oscillator, watchdog oscillator, external clock input provides optimal support of minimal power active mode with fast switching to maximum performance. Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical power-down current is 1 μA (total power-down with voltage comparators disabled). Active-LOW reset. On-chip power-on reset allows operation without external reset components. A software reset function is also available. Configurable on-chip oscillator with frequency range options selected by user programmed flash configuration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz. Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function. Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only. High current sourcing/sinking (20 mA) at 4 I/O pins on the P89LPC9151, 3 I/O pins on the P89LPC9161 and 5 I/O pins on the P89LPC9171. All other port pins have high sinking capability (20 mA). A maximum limit is specified for the entire chip. Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. Only power and ground connections are required to operate the P89LPC9151/9161/9171 when internal reset option is selected. Four interrupt priority levels. Five/six keypad interrupt inputs, plus two additional external interrupt inputs. Schmitt trigger port inputs. Second data pointer. Emulation support.

3.1 Ordering options

Table 1. Ordering information Table 2. Ordering options

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 4 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC 4. Block diagram Fig 1. Block diagram (P89LPC9151) 2 kB CODE FLASH I2C CMP2 CIN2B CIN2A CIN1A CIN1B CMPREF P1[5:0] P0[5:0] TXD RXD SCL AD10 AD11 AD12 AD13 P89LPC9151 002aae564

256 BYTE DATA RAM

ACCELERATED 2-CLOCK 80C51 CPU UART ADC1/DAC1 REAL TIME CLOCK/ SYSTEM TIMER TIMER 0 TIMER 1 ANALOG COMPARATORS POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) ON-CHIP RC OSCILLATOR WITH CLOCK DOUBLER SDA DAC1

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 5 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Fig 2. Block diagram (P89LPC9161) 2 kB CODE FLASH I2C CIN2B CIN2A CIN1A CIN1B CMPREF P2[5:2] P1.5, P1[3:0] P0[5:1] TXD RXD SCL AD10 AD11 AD12 AD13 SPI MOSI MISO SPICLK P89LPC9161 002aae565 SS ACCELERATED 2-CLOCK 80C51 CPU UART ADC1/DAC1 REAL TIME CLOCK/ SYSTEM TIMER TIMER 0 TIMER 1 ANALOG COMPARATORS POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) SDA DAC1 ON-CHIP RC OSCILLATOR WITH CLOCK DOUBLER

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 6 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Fig 3. Block diagram (P89LPC9171) 2 kB CODE FLASH I2C CMP2 CIN2B CIN2A CIN1A CIN1B CMPREF P2.2 P1[5:0] P0.7, P[5:0] TXD RXD SCL AD10 AD11 AD12 AD13 P89LPC9171 002aae566 ACCELERATED 2-CLOCK 80C51 CPU UART ADC1/DAC1 REAL TIME CLOCK/ SYSTEM TIMER TIMER 0 TIMER 1 ANALOG COMPARATORS POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) SDA DAC1 ON-CHIP RC OSCILLATOR WITH CLOCK DOUBLER

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 7 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC 5. Functional diagram Fig 4. Functional diagram (P89LPC9151) KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 AD10 AD11 AD12 AD13 CLKIN CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF TXD RXD INT0 INT1 RST SCL P89LPC9151 002aae567 VDD VSS DAC1 PORT 0 PORT 1 SDA Fig 5. Functional diagram (P89LPC9161) KBI1 KBI2 KBI3 KBI4 KBI5 AD10 AD11 AD12 AD13 CLKIN CIN2B CIN2A CIN1B CIN1A CMPREF TXD RXD INT0 MOSI MIS0 SPICLK RST SCL P89LPC9161 002aae568 VDD VSS SS DAC1 PORT 0 PORT 1 PORT 2 SDA

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 8 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Fig 6. Functional diagram (P89LPC9171) KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 AD10 AD11 AD12 AD13 CLKIN KBI7 CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF TXD RXD INT0 INT1 RST SCL P89LPC9171 002aae569 VDD VSS DAC1 CLKOUT PORT 0 PORT 1 PORT 2 SDA

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 9 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC 6. Pinning information

6.1 Pinning

Fig 7. P89LPC9151 TSSOP14 pin configuration Fig 8. P89LPC9161 TSSOP16 pin configuration Fig 9. P89LPC9171 TSSOP16 pin configuration P89LPC9151 P0.1/CIN2B/KBI1/AD10 P0.2/CIN2A/KBI2/AD11 P0.0/CMP2/KBI0 P0.3/CIN1B/KBI3/AD12 P1.5/RST P0.4/CIN1A/KBI4/AD13/DAC1 VSS P0.5/CMPREF/KBI5/CLKIN P1.4/INT1 VDD P1.3/INT0/SDA P1.0/TXD P1.2/T0/SCL P1.1/RXD 002aae570 7 8 P89LPC9161 P0.1/CIN2B/KBI1/AD10 P0.2/CIN2A/KBI2/AD11 P2.4/SS P0.3/CIN1B/KBI3/AD12 P1.5/RST P0.4/CIN1A/KBI4/AD13/DAC1 VSS P0.5/CMPREF/KBI5/CLKIN P2.3/MISO V DD P2.2/MOSI P2.5/SPICLK P1.3/INT0/SDA P1.0/TXD P1.2/T0/SCL P1.1/RXD 002aae571 P89LPC9171 P0.1/CIN2B/KBI1/AD10 P0.2/CIN2A/KBI2/AD11 P0.0/CMP2/KBI0 P0.3/CIN1B/KBI3/AD12 P1.5/RST P0.4/CIN1A/KBI4/AD13/DAC1 VSS P0.5/CMPREF/KBI5/CLKIN P2.2 V DD P1.4/INT1 P0.7/T1/KBI7/CLKOUT P1.3/INT0/SDA P1.0/TXD P1.2/T0/SCL P1.1/RXD 002aae572

6.2 Pin description

Table 3. P89LPC9151 Pin description The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt trigger inputs. I CIN2B — Comparator 2 positive input B. I AD10 — ADC1 channel 0 analog input. I CIN2A — Comparator 2 positive input A. I AD11 — ADC1 channel 1 analog input. 13 I/O P0.3 — Port 0 bit 3. High current source. I CIN1B — Comparator 1 positive input B. I AD12 — ADC1 channel 2 analog input. 12 I/O P0.4 — Port 0 bit 4. High current source. I CIN1A — Comparator 1 positive input A. O DAC1 — Digital-to-analog converter output 1. I AD13 — ADC1 channel 3 analog input. 11 I/O P0.5 — Port 0 bit 5. High current source. I CMPREF — Comparator reference (negative) input. I CLKIN — External clock input. Port 1 pins as inputs and outputs depends upon the port configuration selected. All pins have Schmitt trigger inputs.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. O TXD — Transmitter output for serial port. I RXD — Receiver input for serial port. P1.2/T0/SCL 7 I/O P1.2 — Port 1 bit 2 (open-drain when used as output). I/O SCL — I2C-bus serial clock input/output. P1.3/INT0/SDA 6 I/O P1.3 — Port 1 bit 3 (open-drain when used as output). I INT0 — External interrupt 0 input. I/O SDA — I2C-bus serial data input/output. P1.4/INT1 5 I/O P1.4 — Port 1 bit 4. High current source. I INT1 — External interrupt 1 input. P1.5/RST 3 I P1.5 — Port 1 bit 5 (input only).

Also used during a power-on sequence to force ISP

VSS 4 I Ground: 0 V reference.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Table 4. P89LPC9161 Pin description The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt trigger inputs. I CIN2B — Comparator 2 positive input B. I AD10 — ADC1 channel 0 analog input. I CIN2A — Comparator 2 positive input A. I AD11 — ADC1 channel 1 analog input. 15 I/O P0.3 — Port 0 bit 3. High current source. I CIN1B — Comparator 1 positive input B. I AD12 — ADC1 channel 2 analog input. 14 I/O P0.4 — Port 0 bit 4. High current source. I CIN1A — Comparator 1 positive input A. O DAC1 — Digital-to-analog converter output 1. I AD13 — ADC1 channel 3 analog input. 13 I/O P0.5 — Port 0 bit 5. High current source. I CMPREF — Comparator reference (negative) input. I CLKIN — External clock input. Port 1 pins as inputs and outputs depends upon the port configuration selected. All pins have Schmitt trigger inputs. O TXD — Transmitter output for serial port. I RXD — Receiver input for serial port.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. P1.2/T0/SCL 8 I/O P1.2 — Port 1 bit 2 (open-drain when used as output). I/O SCL — I2C-bus serial clock input/output. P1.3/INT0/SDA 7 I/O P1.3 — Port 1 bit 3 (open-drain when used as output). I INT0 — External interrupt 0 input. I/O SDA — I2C-bus serial data input/output. P1.5/RST 3 I P1.5 — Port 1 bit 5 (input only).

Also used during a power-on sequence to force ISP

Section 7.15 “I/O ports” for details. All pins have Schmitt trigger inputs. when configured as slave, this pin is input. configured as slave, this pin is input. VSS 4 I Ground: 0 V reference.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Table 5. P89LPC9171 Pin description The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt trigger inputs. I CIN2B — Comparator 2 positive input B. I AD10 — ADC1 channel 0 analog input. I CIN2A — Comparator 2 positive input A. I AD11 — ADC1 channel 1 analog input. 15 I/O P0.3 — Port 0 bit 3. High current source. I CIN1B — Comparator 1 positive input B. I AD12 — ADC1 channel 2 analog input. 14 I/O P0.4 — Port 0 bit 4. High current source. I CIN1A — Comparator 1 positive input A. O DAC1 — Digital-to-analog converter output 1. I AD13 — ADC1 channel 3 analog input. 13 I/O P0.5 — Port 0 bit 5. High current source. I CMPREF — Comparator reference (negative) input. I CLKIN — External clock input. 11 I/O P0.7 — Port 0 bit 7. High current source. I/O T1 — Timer/counter 1 external count input or overflow output.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Port 1 pins as inputs and outputs depends upon the port configuration selected. All pins have Schmitt trigger inputs. O TXD — Transmitter output for serial port. I RXD — Receiver input for serial port. P1.2/T0/SCL 8 I/O P1.2 — Port 1 bit 2 (open-drain when used as output). I/O SCL — I2C-bus serial clock input/output. P1.3/INT0/SDA 7 I/O P1.3 — Port 1 bit 3 (open-drain when used as output). I INT0 — External interrupt 0 input. I/O SDA — I2C-bus serial data input/output. P1.4/INT1 6 I/O P1.4 — Port 1 bit 4. High current source. I INT1 — External interrupt 1 input. P1.5/RST 3 I P1.5 — Port 1 bit 5 (input only).

Also used during a power-on sequence to force ISP

selected. Refer to Section 7.15 “I/O ports” for details. This pin has Schmitt trigger inputs. VSS 4 I Ground: 0 V reference.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 16 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC 7. Functional description Remark: Please refer to the P89LPC9151/9161/9171 User manual for a more detailed functional description.

7.1 Special function registers

Remark: SFR accesses are restricted in the following ways:

User must not attempt to access any SFR locations not defined.
Accesses to any defined SFR locations must be strictly for the functions for the SFRs.
SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows: – ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives. – ‘0’ must be written with ‘0’, and will return a ‘0’ when read. – ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. [1] All ports are in input only (high-impedance) state after power-up. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. [4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF. [5] On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [6] The only reset sources that affect these SFRs are power-on reset and watchdog reset.

indicates SFRs that are bit addressable.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. used to access these extended SFRs. [2] The BOICFG1/0 will be copied from UCFG1.5 and UCFG1.3 when power-on reset. Table 7. Extended special function registers - P89LPC9151 [1]

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. 8-bit microcontroller with 8-bit ADC[1] All ports are in input only (high-impedance) state after power-up. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. [4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF. [5] On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [6] The only reset sources that affect these SFRs are power-on reset and watchdog reset.

indicates SFRs that are bit addressable.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. used to access these extended SFRs. [2] The BOICFG1/0 will be copied from UCFG1.5 and UCFG1.3 when power-on reset. Table 9. Extended special function registers - P89LPC9161 [1]

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

indicates SFRs that are bit addressable.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. used to access these extended SFRs. [2] The BOICFG1/0 will be copied from UCFG1.5 and UCFG1.3 when power-on reset. Table 11. Extended special func tion registers - P89LPC9171[1]

7.2 Enhanced CPU

The P89LPC9151/9161/9171 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

7.3 Clocks

7.3.1 Clock definitions

The P89LPC9151/9161/9171 device has several internal clocks as defined below: OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources (see Figure 10) and can also be optionally divided to a slower frequency (see Section 7.10 “CCLK modification: DIVM register”). Remark: fosc is defined as the OSCCLK frequency. CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles). RCCLK — The internal 7.373 MHz RC oscillator output. The clock doubler option, when enabled, provides an output frequency of 14.746 MHz. PCLK — Clock for the various peripheral devices and is CCLK⁄2.

7.3.2 CPU clock (OSCCLK)

The P89LPC9151/9161/9171 provides several user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the flash is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, or an external clock source.

7.4 Clock output (P89LPC9171)

The P89LPC9171 supports a user-selectable clock output function on the P0.7/CLKOUT pin. This allows external devices to synchronize to the P89LPC9171. This output is enabled by the ENCLK bit in the TRIM register. The frequency of this clock output is 1⁄2 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power.

7.5 On-chip RC oscillator option

The P89LPC9151/9161/9171 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7.373 MHz ± 1 % at room temperature. End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. When the clock doubler option is enabled (UCFG2.7 = 1), the output frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 39 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC running at 8 MHz or slower. When clock doubler option is enabled, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in reset at power-up until VDD has reached its specified level.

7.6 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz, calibrated to ±5 % at room temperature. This oscillator can be used to save power when a high clock frequency is not needed.

7.7 External clock input option

In this configuration, the processor clock is derived from an external source driving the P0.5/CLKIN pin. The rate may be from 0 Hz up to 18 MHz. When the frequency above 12 MHz, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in reset at power-up until VDD has reached its specified level. Remark: When using P0.5 as a clock input option, please make sure that P0.5 is configured as input only mode.

7.8 Clock sources switch on the fly

P89LPC9151/9161/9171 can implement clock source switch in any sources of watchdog oscillator, 7 MHz/14 MHz IRC oscillator, or external clock input during code is running. CLKOK bit in CLKCON register is used to indicate the clock switch status. CLKOK is cleared when starting clock source switch and set when completed. Notice that when CLKOK is ‘0’, writing to CLKCON register is not allowed. Fig 10. Block diagram of oscillator control 002aae574 RTC CPU WDT DIVM CCLK OSCCLK XCLK RCCLK I2C-BUS UART PCLK TIMER 0 AND TIMER 1 CLKIN RC OSCILLATOR WATCHDOG OSCILLATOR PCLK RCCLK SPI (P89LPC9161) RTCS1:0 ADC1/DAC1 CLKOUT (7.3728 MHz/14.7456 MHz ± 1 %) (400 kHz ± 5 %)

7.9 CCLK wake-up delay

The P89LPC9151/9161/9171 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles plus 60 μs to 100 μs. If the clock source is the internal RC oscillator, the delay is 200 μs to 300 μs. If the clock source is watchdog oscillator or external clock, the delay is 32 OSCCLK cycles.

7.10 CCLK modificati on: DIVM register

The OSCCLK frequency can be divided down up to 510 times by configuring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.

7.11 Low power select

The P89LPC9151/9161/9171 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

7.12 Memory organization

DATA 128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area.
IDATA Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.
SFR Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.
XDATA ‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the DPTR, R0, or R1. All or part of this space could be implemented on-chip. Extended SFRs located in XDATA.
CODE 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC9151/9161/9171 has 2 kB on-chip Code memory.

7.13 Data RAM arrangement

The 256 bytes of on-chip RAM are organized as shown in Table 12.

7.14 Interrupts

great flexibility in controlling the handling of the many interrupt sources. watchdog/RTC, I2C-bus, keyboard, comparators 1 and 2, A/D completion. watchdog/RTC, I2C-bus, keyboard, comparators 1 and 2, SPI, ADC completion. disable bit, EA, which disables all interrupts. Table 12. On-chip data memory usages

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 42 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1 and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced. If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level.

7.14.1 External interrupt inputs

The P89LPC9151 and P89LPC9171 have two external interrupt inputs as well as the Keypad Interrupt function. The P89LPC9161 has one external interrupt input as well as the Keypad Interrupt function These external interrupt inputs are identical to those present on the standard 80C51 microcontrollers. These external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit IT1 or IT0 in Register TCON. In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an interrupt request. If an external interrupt is enabled when the P89LPC9151/9161/9171 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section 7.17 “Power reduction modes” for details.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 43 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Fig 11. Interrupt sources, interrupt enables, and power-down wake-up sources IE0 EX0 IE1 EX1 EC EA (IE0.7) CMF1 KBIF EKBI BOIF EBO CMF2 TF0 ET0 TF1 ET1 ES/ESR TI and RI/RI TI EST SI EI2C SPIF ESPI EAD ENADCI1 ADCI1 ENBI1 BNDI1 002aae575 RTCF ERTC (RTCCON.1) WDOVF (P89LPC9161) EWDRT wake-up (if in power-down) interrupt to CPU

7.15 I/O ports

The P89LPC9151 has two I/O ports: Port 0 and Port 1. Ports 0 and 1 are both 6-bit ports. [1] Required for operation above 12 MHz. [1] Required for operation above 12 MHz.

7.15.1 Port configurations

port select the output type for each port pin.

P1.5 ( RST) can only be an input and cannot be configured.
P1.2 (SCL/T0) and P1.3 (SDA/ INT0) may only be configured to be either input-only or

7.15.1.1 Quasi-bidirectional output configuration

Table 13. Number of I/O pins available (P89LPC9151) Table 14. Number of I/O pins available (P89LPC9161 and P89LPC9171)

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 45 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC LOW, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. The P89LPC9151/9161/9171 is a 3 V device, but the pins are 5 V tolerant. In quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current flowing from the pin to VDD, causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is discouraged. A quasi-bidirectional port pin has a Schmitt trigger input that also has a glitch suppression circuit.

7.15.1.2 Open-drain output configuration

The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to V DD. An open-drain port pin has a Schmitt trigger input that also has a glitch suppression circuit.

7.15.1.3 Input-only configuration

The input-only port configuration has no output drivers. It is a Schmitt trigger input that also has a glitch suppression circuit.

7.15.1.4 Push-pull output configuration

The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output. A push-pull port pin has a Schmitt triggered input that also has a glitch suppression circuit. The P89LPC9151/9161/9171 device has high current source on eight pins in push-pull mode. See Table 15 “Limiting values”.

7.15.2 Port 0 analog functions

The P89LPC9151/9161/9171 incorporates two Analog Comparators. In order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port output into the Input-Only (high-impedance) mode. Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5. On any reset, PT0AD[1:5] defaults to logic 0s to enable digital functions.

7.15.3 Additional port features

After power-up, all pins are in Input-Only mode. Please note that this is different from the LPC76x series of devices.

After power-up, all I/O pins except P1.5, may be configured by software.
Pin P1.5 is input only. Pins P1.2 and P1.3 are configurable for either input-only or open-drain.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 46 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Every output on the P89LPC9151/9161/9171 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to Table 16 “Static characteristics” for detailed specifications. All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.

7.16 Power monitoring functions

The P89LPC9151/9161/9171 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on detect and brownout detect.

7.16.1 Brownout detection

The brownout detect function determines if the power supply voltage drops below a certain level. Enhanced brownout detection has 3 independent functions: BOD reset, BOD interrupt and BOD FLASH. BOD reset is always on except in total Power-down mode. It could not be disabled in software. BOD interrupt may be enabled or disabled in software. BOD FLASH is always on, except in Power-down modes and could not be disabled in software. BOD reset and BOD interrupt, each has four trip voltage levels. BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are used as trip point configuration bits of BOD reset. BOICFG1 bit and BOICFG0 bit in register BODCFG are used as trip point configuration bits of BOD interrupt. BOD reset voltage should be lower than BOD interrupt trip point. BOD FLASH is used for flash programming/erase protection and has only 1 trip voltage of 2.4 V. Please refer to P89LPC9151/9161/9171 User manual for detail configurations. If brownout detection is enabled the brownout condition occurs when VDD falls below the brownout trip voltage and is negated when VDD rises above the brownout trip voltage. For correct activation of brownout detect, the VDD rise and fall times must be observed. Please see Table 16 “Static characteristics” for specifications.

7.16.2 Power-on detection

The Power-on detect has a function similar to the brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. The POF flag in the RSTSRC register is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software.

7.17 Power reduction modes

The P89LPC9151/9161/9171 supports three different power reduction modes. These modes are Idle mode, Power-down mode, and total Power-down mode.

7.17.1 Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode.

7.17.2 Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC9151/9161/9171 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the data retention supply voltage V DDR. This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after VDD has been lowered to VDDR, therefore it is highly recommended to wake-up the processor via reset in this case. VDD must be raised to within the operating range before the Power-down mode is exited. Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during power-down. These include: Brownout detect, watchdog timer, comparators (note that comparators can be powered down separately), and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled.

7.17.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during power-down, there will be high power consumption. Please use an external low frequency clock to achieve low power with the RTC running during power-down.

7.18 Reset

The P1.5/RST pin can function as either a LOW-active reset input or as a digital input, P1.5. The Reset Pin Enable (RPE) bit in UCFG1, when set to logic 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin. Remark: During a power-up sequence, the RPE selection is overridden and this pin always functions as a reset input. An external circuit connected to this pin should not hold this pin LOW during a power-on sequence as this will keep the device in reset. After power-up this pin will function as defined by the RPE bit. Only a power-up reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the RPE bit. Note: During a power cycle, VDD must fall below VPOR before power is reapplied, in order to ensure a power-on reset (see Table 16 “Static characteristics”). Reset can be triggered from the following sources:

External reset pin (during power-up or if user configured via UCFG1)
Power-on detect
Brownout detect
Watchdog timer
Software reset
UART break character detect reset For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a logic 0 to the corresponding bit. More than one flag bit may be set:

During a power-on reset, both POF and BOF are set but the other flag bits are cleared.
A Watchdog reset is similar to a power-on reset, both POF and BOF are set but the other flag bits are cleared.
For any other reset, previously set flag bits that have not been cleared will remain set.

7.18.1 Reset vector

Following reset, the P89LPC9151/9161/9171 will fetch instructions from either address 0000H or the Boot address. The Boot address is formed by using the boot vector as the high byte of the address and the low byte of the address = 00H. The boot address will be used if a UART break reset occurs, or the non-volatile boot status bit (BOOTSTAT.0) = 1.

7.19 Timers/counters 0 and 1

The P89LPC9151/9161/9171 devices have two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. An option to automatically toggle the T0 pin upon timer overflow has been added. In addition an option to toggle the T1 pin upon overflow has been added on the P89LPC9171. In the ‘Timer’ function, the register is incremented every machine cycle. In the ‘Counter’ function, the register of Timer 0 is incremented in response to a 1-to-0 transition at its external input pin. This external input is sampled once every machine cycle. Timer 0 has five operating modes (Modes 0, 1, 2, 3 and 6). Timer 1 has four operating modes (Modes 0, 1, 2, and 3), except on the P89LPC9171 where Timer 1 also has Mode 6. Modes 0, 1, 2 and 6 are the same for both Timers/Counters. Mode 3 is different.

7.19.1 Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.

7.19.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

7.19.3 Mode 2

Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1.

7.19.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.

7.19.5 Mode 6

In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks.

7.19.6 Timer overflow toggle output

Timer 0 (and Timer 1 on the P89LPC9171) can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on.

7.20 RTC/system timer

The P89LPC9151/9161/9171 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered down. The RTC can be a wake-up or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will be reloaded again and the RTCF flag will be set. The clock source for this counter can be either the CPU clock (CCLK) or the external clock input, provided that the external clock input is not being used as the CPU clock. If the external clock input is used as the CPU clock, then the RTC will use CCLK as its clock source. Only power-on reset will reset the RTC and its associated SFRs to the default state. The 16-bit loadable counter portion of the RTC is readable by reading the RTCDATL and RTCDATH registers.

7.21 UART

The P89LPC9151/9161/9171 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC9151/9161/9171 does include an independent baud rate generator. The baud rate can be selected from the oscillator (divided by a constant), Timer overflow, or the independent baud rate generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options. The UART can be operated in four modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16.

7.21.1 Mode 0

Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at 1⁄16 of the CPU clock frequency.

7.21.2 Mode 1

10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8 in special function register SCON. The baud rate is variable and is determined by the Timer 1 overflow rate or the baud rate generator (described in Section 7.21.5 “Baud rate generator and selection”).

7.21.3 Mode 2

11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 50 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9th data bit goes into RB8 in special function register SCON, while the stop bit is not saved. The baud rate is programmable to either 1⁄16 or 1⁄32 of the CPU clock frequency, as determined by the SMOD1 bit in PCON.

7.21.4 Mode 3

11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the baud rate generator (described in Section 7.21.5 “Baud rate generator and selection”).

7.21.5 Baud rate generator and selection

The P89LPC9151/9161/9171 enhanced UART has an independent baud rate generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be used for other timing functions. The UART can use either Timer 1 or the baud rate generator output (see Figure 12). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The independent baud rate generators use OSCCLK.

7.21.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up when SMOD0 is logic 0.

7.21.7 Break detect

Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device and force the device into ISP mode.

7.21.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. Fig 12. Baud rate so urces for UART (Modes 1, 3) baud rate modes 1 and 3 SBRGS = 1 SBRGS = 0 SMOD1 = 0 SMOD1 = 1timer 1 overflow (PCLK-based) baud rate generator (CCLK-based) 002aaa897

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 51 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SBUF while the previous data is being shifted out. Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = 0).

7.21.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the TI interrupt is generated when the double buffer is ready to receive new data.

7.21.10 The 9 th bit (bit 8) in double buffering (modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the TI interrupt. If double buffering is enabled, TB must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data.

7.22 I 2C-bus serial interface

The I2C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features:

Bidirectional data transfer between masters and slaves
Multi master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer
The I2C-bus may be used for test and diagnostic purposes. A typical I2C-bus configuration is shown in Figure 13. The P89LPC9151/9161/9171 device provides a byte-oriented I2C-bus interface that supports data transfers up to 400 kHz. Fig 13. I 2C-bus configuration OTHER DEVICE WITH I2C-BUS INTERFACE SDA SCL RPRP OTHER DEVICE WITH I2C-BUS INTERFACE P1.3/SDA P1.2/SCL P89LPC9151/9161/ 9171 I2C-bus 002aae576

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 52 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Fig 14. I 2C-bus serial interface block diagram INTERNAL BUS 002aaa899 ADDRESS REGISTER COMPARATOR SHIFT REGISTER I2ADR ACK BIT COUNTER / ARBITRATION AND SYNC LOGIC I2DAT TIMING AND CONTROL LOGIC SERIAL CLOCK GENERATOR CCLK interrupt INPUT FILTER OUTPUT STAGE INPUT FILTER OUTPUT STAGE P1.3 P1.3/SDA P1.2/SCL P1.2 timer 1 overflow CONTROL REGISTERS AND SCL DUTY CYCLE REGISTERS I2CON I2SCLH I2SCLL STATUS DECODERstatus bus STATUS REGISTER I2STAT

7.23 SPI (P89LPC9161)

The P89LPC9161 provides another high-speed serial communication interface: the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in either Master mode or Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection. The SPI interface has four pins: SPICLK, MOSI, MISO and SS:

SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output in the Master mode and is input in the Slave mode. If the SPI system is disabled, i.e., SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
SS is the optional slave select pin. In a typical configuration, an SPI master asserts one of its port pins to select one SPI device as the current slave. An SPI slave device uses its SS pin to determine whether it is selected. Typical connections are shown in Figure 16 through Figure 18. Fig 15. SPI block diagram 002aaa900 CPU clock DIVIDER BY 4, 16, 64, 128 SELECT CLOCK LOGIC SPI CONTROL REGISTER READ DATA BUFFER 8-BIT SHIFT REGISTER SPI CONTROL SPI STATUS REGISTER SPR1 SPIF WCOL SPR0 SPI clock (master) PIN CONTROL LOGIC S M S M M S MISO P2.3 MOSI P2.2 SPICLK P2.5 SS P2.4 SPI interrupt request internal data bus SSIG SPEN SPEN MSTR DORD MSTR CPHA CPOL SPR1 SPR0 MSTR SPEN clock

7.23.1 Typical SPI configurations

Fig 16. SPI single master single slave configuration Fig 17. SPI dual device configuration, where either can be a master or a slave 002aaa901 master slave 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR 8-BIT SHIFT REGISTER MISO MOSI SPICLK PORT MISO MOSI SPICLK SS 002aaa902 master slave 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR SPI CLOCK GENERATOR 8-BIT SHIFT REGISTER MISO MOSI SPICLK MISO MOSI SPICLK SSSS

7.24 Analog comparators

Two analog comparators are provided on the P89LPC9151/9161/9171. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable inputs) is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be configured to cause an interrupt when the output value changes. Comparator 1 may be output to a port pin. The overall connections to both comparators are shown in Figure 19. The comparators function to VDD = 2.4 V. When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 μs. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. When a comparator is disabled the comparator’s output, COn, goes HIGH. If the comparator output was LOW and then is disabled, the resulting transition of the comparator output from a LOW to HIGH state will set the comparator flag, CMFn. This will cause an interrupt if the comparator interrupt is enabled. The user should therefore disable the comparator interrupt prior to disabling the comparator. Additionally, the user should clear the comparator flag, CMFn, after disabling the comparator. Fig 18. SPI single master multiple slaves configuration 002aaa903 master slave 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR 8-BIT SHIFT REGISTER MISO MOSI SPICLK port port MISO MOSI SPICLK SS slave 8-BIT SHIFT REGISTER MISO MOSI SPICLK SS

7.24.1 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as V ref(bg), is 1.23 V ± 10 %.

7.24.2 Comparator interrupt

Each comparator has an interrupt flag contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. If both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the flags to determine which comparator caused the interrupt.

7.24.3 Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode. If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake-up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. Comparators consume power in Power-down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparators via PCONA.5, or put the device in Total Power-down mode. Fig 19. Comparator input and output connections comparator 1 CP1 CN1 (P0.4) CIN1A (P0.3) CIN1B (P0.5) CMPREF Vref(bg) OE1 CO1 CMF1 interrupt 002aae433 CMP1 (P0.6) EC CMF2 comparator 2 OE2 CO2 CMP2 (P0.0) CP2 CN2 (P0.2) CIN2A (P0.1) CIN2B change detect change detect

7.25 KBI

The Keypad Interrupt function (KBI) is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can configure the port via SFRs for different tasks. The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to define equal or not-equal for the comparison. In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake-up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than six CCLKs.

7.26 Watchdog timer

The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler. The clock source for the prescaler can be the PCLK, or the nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a power-on reset. When the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure 20 shows the watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few μs to a few seconds. Please refer to the P89LPC9151/9161/9171 User manual for more details.

7.27 Additional features

7.27.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets.

7.27.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register.

7.28 Flash program memory

7.28.1 General description

The P89LPC9151/9161/9171 flash memory provides in-circuit electrical erasure and programming. The flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any flash sector (256 bytes) or page (16 bytes). The Chip Erase operation will erase the entire program memory. ICP using standard commercial programmers is available. In addition, IAP (IAP-Lite) and byte-erase allows code memory to be used for non-volatile data storage. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC9151/9161/9171 flash reliably stores memory contents even after 100,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. The (1) Watchdog reset can also be caused by an in valid feed sequence, or by writing to WDCON not immediately followed by a feed sequence. Fig 20. Watchdog timer in Watchdog mode (WDTE = 1) PRE2 PRE1 PRE0 – – WDRUN WDTOF WDCLKWDCON (A7H) CONTROL REGISTER PRESCALER 002aae577 SHADOW REGISTER FOR WDCON 8-BIT DOWN COUNTER WDL (C1H) Watchdog oscillator PCLK ÷32 MOV WFEED1, #0A5H MOV WFEED2, #05AH reset(1)

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 59 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC P89LPC9151/9161/9171 uses VDD as the supply voltage to perform the Program/Erase algorithms. When voltage supply is lower than 2.4 V, the BOD FLASH is tripped and flash erase/program is blocked.

7.28.2 Features

Programming and erase over the full operating voltage range.
Byte erase allows code memory to be used for data storage.
Read/Programming/Erase using ICP.
Any flash program/erase operation in 2 ms.
Programming with industry-standard commercial programmers.
Programmable security for the code in the flash for each sector.
100,000 typical erase/program cycles for each byte.
10 year minimum data retention.

7.28.3 Flash organization

The program memory consists of eight 256-byte sectors on the P89LPC9151/9161/9171 devices. Each sector can be further divided into 16-byte pages. In addition to sector erase, page erase, and byte erase, a 16-byte page register is included which allows from 1 byte to 16 bytes of a given page to be programmed at the same time, substantially reducing overall programming time. In addition, erasing and reprogramming of user-programmable configuration bytes including UCFG1, the Boot Status Bit, and the Boot Vector is supported.

7.28.4 Using flash as data storage

The flash code memory array of this device supports individual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the sector containing the byte has not been secured (a MOVC instruction is not allowed to read code memory contents of a secured sector). Thus any byte in a non-secured sector may be used for non-volatile data storage.

7.28.5 Flash programming and erasing

Two different methods of erasing or programming of the flash are available. The flash may be programmed or erased in the end-user application (IA-Lite) under control of the application’s firmware. Another option is to use the ICP mechanism. This ICP system provides for programming through a serial clock/serial data interface. This device does not provide for direct verification of code memory contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire user code space. Remark: When voltage supply is lower than 2.4 V, the BOD FLASH is tripped and flash erase/program is blocked.

7.28.6 ICP

ICP is performed without removing the microcontroller from the system. The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC9151/9161/9171 through a two-wire serial interface. The NXP ICP facility has made in-circuit programming in an embedded application - using commercially available programmers - possible with a minimum of additional expense in components and circuit

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 60 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC board area. The ICP function uses five pins. Only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature. Additional details may be found in the P89LPC9151/9161/9171 User manual.

7.28.7 IAP-Lite

IAP-Lite is performed in the application under the control of the microcontroller’s firmware. The IAP facility consists of internal hardware resources to facilitate programming and erasing. The IAP-Lite operations are accomplished through the use of four SFRs consisting of a control/status register, a data register, and two address registers. Additional details may be found in the P89LPC9151/9161/9171 User’s Manual.

7.29 User configuration bytes

Some user-configurable features of the P89LPC9151/9161/9171 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of the flash byte UCFG1 and UCFG2. Please see the P89LPC9151/9161/9171 User’s Manual for additional details.

7.30 User sector security bytes

There are 8 User Sector Security Bytes on the P89LPC9151/9161/9171. Each byte corresponds to one sector. Please see the P89LPC9151/9161/9171 User manual for additional details. 8. ADC

8.1 General description

The P89LPC9151/9161/9171 devices have a single 8-bit, 4-channel multiplexed analog-to-digital converter. A block diagram of the A/D converter is shown in Figure 21. The A/D consists of a 4-input multiplexer which feeds a sample-and-hold circuit providing an input signal to one of two comparator inputs. The control logic in combination with the SAR drives a digital-to-analog converter which provides the other input to the comparator. The output of the comparator is fed to the SAR.

8.2 Features

8-bit, 4-channel multiplexed input, successive approximation ADC. Four A/D result registers. Six operating modes: Fixed channel, single conversion mode. Fixed channel, continuous conversion mode. Auto scan, single conversion mode. Auto scan, continuous conversion mode. Dual channel, continuous conversion mode. Single step mode. Three conversion start modes: Timer triggered start. Start immediately.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 61 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Edge triggered. 8-bit conversion time of ≥ 1.61 μs at an A/D clock of 8.0 MHz. Interrupt or polled operation. Boundary limits interrupt. DAC output to a port pin with high output impedance. Clock divider. Power-down mode.

8.3 Block diagram

8.4 ADC operating modes

8.4.1 Fixed channel, single conversion mode

A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after the conversion completes.

8.4.2 Fixed channel, continuous conversion mode

A single input channel can be selected for continuous conversion. The results of the conversions will be sequentially placed in the four result register. The user may select whether an interrupt can be generated after every four conversions. Additional conversion results will again cycle through the four result register, overwriting the previous results. Continuous conversions continue until terminated by the user.

8.4.3 Auto scan, single conversion mode

Any combination of the four input channels can be selected for conversion. A single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after all selected channels have been converted. If only a single channel is selected this is equivalent to single channel, single conversion mode.

8.4.4 Auto scan, continuous conversion mode

Any combination of the four input channels can be selected for conversion. A conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after Fig 21. ADC block diagram SAR 002aaa783 cclk comp DAC1 CONTROL LOGIC INPUT MUX

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 62 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC all selected channels have been converted. The process will repeat starting with the first selected channel. Additional conversion results will again cycle through the four result register pairs, overwriting the previous results. Continuous conversions continue until terminated by the user.

8.4.5 Dual channel, continuous conversion mode

This is a variation of the auto scan continuous conversion mode where conversion occurs on two user-selectable inputs. The result of the conversion of the first channel is placed in the result register, AD1DAT0. The result of the conversion of the second channel is placed in result register, AD1DAT1. The first channel is again converted and its result stored in AD1DAT2. The second channel is again converted and its result placed in AD1DAT3. An interrupt is generated, if enabled, after every set of four conversions (two conversions per channel).

8.4.6 Single step mode

This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any combination of the four input channels can be selected for conversion. After each channel is converted, an interrupt is generated, if enabled, and the A/D waits for the next start condition. May be used with any of the start modes.

8.5 Conversion start modes

8.5.1 Timer triggered start

An A/D conversion is started by the overflow of Timer 0. Once a conversion has started, additional Timer 0 triggers are ignored until the conversion has completed. The Timer triggered start mode is available in all ADC operating modes.

8.5.2 Start immediately

Programming this mode immediately starts a conversion. This start mode is available in all ADC operating modes.

8.5.3 Edge triggered

An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has started, additional edge triggers are ignored until the conversion has completed. The edge triggered start mode is available in all ADC operating modes.

8.6 Boundary limits interrupt

Each of the A/D converters has both a high and low boundary limit register. The user may select whether an interrupt is generated when the conversion result is within (or equal to) the high and low boundary limits or when the conversion result is outside the boundary limits. An interrupt will be generated, if enabled, if the result meets the selected interrupt criteria. The boundary limit may be disabled by clearing the boundary limit interrupt enable. An early detection mechanism exists when the interrupt criteria has been selected to be outside the boundary limits. In this case, after the four MSBs have been converted, these four bits are compared with the four MSBs of the boundary high and low registers. If the four MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits) an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 63 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC criteria, the boundary limits will again be compared after all 8 bits have been converted. The boundary status register (BNDSTA0) flags the channels which caused a boundary interrupt.

8.7 DAC output to a port pin with high output impedance

The DAC block of ADC1 can be output to a port pin. In this mode, the AD1DAT3 register is used to hold the value fed to the DAC. After a value has been written to the DAC (written to AD1DAT3), the DAC output will appear on the channel 3 pin.

8.8 Clock divider

The ADC requires that its internal clock source be in the range of 320 kHz to 8 MHz to maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose.

8.9 Power-down and Idle mode

In Idle mode the A/C converter, if enabled, will continue to function and can cause the device to exit Idle mode when the conversion is completed if the A/D interrupt is enabled. In Power-down mode or Total Power-down mode, the A/D does not function. If the A/D is enabled, it will consume power. Power can be reduced by disabling the A/D.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Table 16. Static characteristics VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.

3.6 V all ports, all modes

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. [1] Typical ratings are not guaranteed. The va lues listed are at room temperature, 3 V. [2] The I DD(oper) specification is measured using an external clock with code while(1) {} executed from on-chip flash. brownout detect, and watchdog timer. exceed the related specification. [8] Pin capacitance is characterized but not tested. [9] Measured with port in quasi-bidirectional mode. [10] Measured with port in high-impedance mode. highest when VI is approximately 2 V. Table 16. Static characteristics …continued VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.

10.1 Current characteristics

Note: The graphs provided are a statistical summary based on a limited number of samples and only for information purposes. The performance characteristics listed are not tested or guaranteed. Test conditions: normal mode, code while(1) {} executed from on-chip flash; using an external clock. Fig 23. I DD(oper) versus frequency at +25 °C Test conditions: normal mode, code while(1) {} executed from on-chip flash; using an external clock. Fig 24. I DD(oper) versus frequency at −40 °C VDD (V) 2.4 3.63.22.8 002aae363 IDD (mA)

18 MHz

12 MHz

8 MHz

6 MHz

4 MHz

2 MHz

1 MHz

VDD (V) 2.4 3.63.22.8 002aae364 IDD (mA)

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 68 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Test conditions: normal mode, code while(1) {} executed from on-chip flash; using an external clock. Fig 25. I DD(oper) versus frequency at +85 °C Test conditions: idle mode entered executing code from on-chip flash; using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer. Fig 26. I DD(idle) versus frequency at +25 °C VDD (V) 2.4 3.63.22.8 002aae365 IDD (mA) VDD (V) 2.4 3.63.22.8 002aae366 2.0 3.0 1.0 4.0 5.0 IDD (mA) 0.0

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 69 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Test conditions: idle mode entered executing code from on-chip flash; using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer. Fig 27. I DD(idle) versus frequency at −40 °C Test conditions: idle mode entered executing code from on-chip flash; using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer. Fig 28. I DD(idle) versus frequency at +85 °C VDD (V) 2.4 3.63.22.8 002aae367 2.0 3.0 1.0 4.0 5.0 IDD (mA) 0.0 VDD (V) 2.4 3.63.22.8 002aae368 2.0 3.0 1.0 4.0 5.0 IDD (mA) 0.0

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 70 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Test conditions: power-down mode, using internal RC oscillator with the following functions disabled: comparators, real-time clock, and watchdog timer. (1) +85 °C (2) +25 °C (3) −40 °C Fig 29. I DD(pd) versus VDD Test conditions: Total power-down mode, using internal RC oscillator with the following functions disabled: comparators, brownout detect, real-time clock, and watchdog timer. (1) +85 °C (2) −40 °C (3) +25 °C Fig 30. I DD(tpd) versus VDD VDD (V) 2.4 3.63.22.8 002aae369 14.0 16.0 12.0 18.0 20.0 IDD (μA) 10.0 (2) (3) (1) VDD (V) 2.4 3.63.22.8 002aae370 0.4 0.8 1.2 IDD (μA) 0.0 (1) (2) (3)

10.2 Internal RC/watchdog os cillator characteristics

Note: The graphs provided are a statistical summary based on a limited number of samples and only for information purposes. The performance characteristics listed are not tested or guaranteed. Central frequency of internal RC oscillator = 7.3728 MHz Fig 31. Average internal RC oscillator frequency versus V DD at +25 °C Note: Central frequency of internal RC oscillator = 7.3728 MHz Fig 32. Average internal RC oscillator frequency versus V DD at −40 °C VDD (V) 2.4 3.63.22.8 002aae344 −0.1 0.1 0.2 frequency deviation (%) −0.2 VDD (V) 2.4 3.63.22.8 002aae346 −0.1 0.1 0.2 frequency deviation (%) −0.2

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 72 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Central frequency of internal RC oscillator = 7.3728 MHz Fig 33. Average internal RC oscillator frequency versus V DD at +85 °C Central frequency of watchdog oscillator = 400 kHz Fig 34. Average watchdog oscillator frequency versus V DD at +25 °C VDD (V) 2.4 3.63.22.8 002aae347 −0.2 −0.4 0.2 frequency deviation (%) −0.6 VDD (V) 2.4 3.63.22.8 002aae348 0.5 −0.5 1.5 2.5 frequency deviation (%) −1.5

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 73 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Central frequency of watchdog oscillator = 400 kHz Fig 35. Average watchdog oscillator frequency versus V DD at −40 °C Central frequency of watchdog oscillator = 400 kHz Fig 36. Average watchdog oscillator frequency versus V DD at +85 °C VDD (V) 2.4 3.63.22.8 002aae349 −1.5 −2.5 −0.5 0.5 frequency deviation (%) −3.5 VDD (V) 2.4 3.63.22.8 002aae350 −0.5 −1.5 0.5 1.5 frequency deviation (%) −2.5

10.3 BOD characteristics

[1] Typical ratings are not guaranteed. The va lues listed are at room temperature, 3 V. Table 17. BOD static characteristics VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. [1] Parameters are valid over operating tem perature range unless otherwise specified. [2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. Table 18. Dynamic characteristics (12 MHz) …continued VDD = 2.4 V to 3.6 V unless otherwise specified.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. [1] Parameters are valid over operating tem perature range unless otherwise specified. [2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. Table 19. Dynamic characteristics (18 MHz) …continued VDD = 3.0 V to 3.6 V unless otherwise specified.

11.1 Waveforms

Fig 38. External clock timing (wit h an amplitude of at least Vi(RMS) = 200 mV) tCHCL tCLCX tCHCX Tcy(clk) tCLCH 002aaa907 Fig 39. Shift register mode timing 0 1 23 456 7 valid valid valid valid valid valid valid valid TXLXL 002aaa906 set TI set RI tXHQXtQVXH tXHDV tXHDX clock output data write to SBUF input data clear RI Fig 40. SPI master timing (CPHA = 0) TSPICYC tSPICLKH tSPICLKH tSPICLKL tSPICLKL master LSB/MSB outmaster MSB/LSB out tSPIDHtSPIDSU tSPIF tSPIOH tSPIDV tSPIR tSPIDV tSPIF tSPIR tSPIF tSPIR SS SPICLK (CPOL = 0) (output) 002aaa908 SPICLK (CPOL = 1) (output) MISO (input) MOSI (output) LSB/MSB inMSB/LSB in

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 80 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Fig 41. SPI master timing (CPHA = 1) TSPICYC tSPICLKL tSPICLKL tSPICLKH tSPICLKH master LSB/MSB outmaster MSB/LSB out tSPIDHtSPIDSU tSPIF tSPIOH tSPIDV tSPIR tSPIDV tSPIF tSPIF tSPIR tSPIR SS SPICLK (CPOL = 0) (output) 002aaa909 SPICLK (CPOL = 1) (output) MISO (input) MOSI (output) LSB/MSB inMSB/LSB in Fig 42. SPI slave timing (CPHA = 0) TSPICYC tSPICLKH tSPICLKH tSPICLKL tSPICLKL tSPILEAD tSPILAG tSPIDSU tSPIDH tSPIDHtSPIDSU tSPIDSU tSPIF tSPIA tSPIOH tSPIDIS tSPIR slave MSB/LSB out MSB/LSB in LSB/MSB in slave LSB/MSB out tSPIDV tSPIOH tSPIOH tSPIDV tSPIR tSPIR tSPIF tSPIF SS SPICLK (CPOL = 0) (input) 002aaa910 SPICLK (CPOL = 1) (input) MISO (output) MOSI (input) not defined

12.1 Comparator electr ical characteristics

[1] This parameter is characterized, but not tested in production. Table 20. Comparator electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.

12.2 ADC electrical characteristics

Table 21. ADC/temperature senso r electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified. All limits valid for an external source impedance of less than 10 kΩ.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 83 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC (1) Example of an actual transfer curve. (2) The ideal transfer curve. Fig 45. ADC characteristics 002aae372 255 254 253 252 (2) (1) 256253 254 2557123456

1 LSB

(ideal) code out VDDA − VSSA 256 offset error EO gain error EG offset error EO VIA (LSBideal)

1 LSB =

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 84 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC 13. Package outline Fig 46. TSSOP14 package outline (SOT402-1) UNIT A 1 A2 A3 bp cD (1) E (2) (1)eH E LL p QZ ywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 o o0.13 0.10.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT402-1 MO-153 99-12-27 03-02-18 w M bp D Z e 0.25 14 8 θ AA1 Lp Q detail X L (A )3 HE E c v M A XA y 0 2.5 5 mm scale TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 A max. 1.1 pin 1 index

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 85 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Fig 47. TSSOP16 package outline (SOT403-1) UNIT A 1 A2 A3 bp cD (1) E (2) (1)eH E LL p QZ ywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 o o0.13 0.10.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT403-1 MO-153 99-12-27 03-02-18 w M bp D Z e 0.25 16 9 θ AA1 Lp Q detail X L (A )3 HE E c v M A XA y 0 2.5 5 mm scale TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 A max. 1.1 pin 1 index

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 88 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC 16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products — Unless the data sheet of an NXP Semiconductors product expressly states that the product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 89 of 91 continued >> NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 90 of 91 continued >> NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC 18. Contents

7.21.9 Transmit interrupts with double buffering enabled

7.21.10 The 9 th bit (bit 8) in double buffering (modes 1, 2

NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 February 2010 Document identifier: P89LPC9151_61_71_2 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 8.4.2 Fixed channel, contin uous conversion mode . 61 8.4.5 Dual channel, continuous conversion mode. . 62

8.7 DAC output to a port pin with high output

10.2 Internal RC/watchdog oscillator characteristics 71

Product Information

P89LPC9171FDH specifications and overview.

Summary

8-bit microcontroller with accelerated two-clock 80C51 core, 2 kB 3 V byte-erasable flash with 8-bit ADC Rev. 02-9 February 2010

Description

8-bit microcontroller with accelerated two-clock 80C51 core, 2 kB 3 V byte-erasable flash with 8-bit ADC Rev. 02-9 February 2010

Source title P89LPC9171FDH Datasheet(PDF) - NXP Semiconductors

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