Microcontroller

P89LPC914FDH

NXP Semiconductors

8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM Rev. 03-17 December 2004

Manufacturer: NXP Semiconductors

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P89LPC912 PHILIPS | Alldatasheet

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8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM Rev. 03 — 17 December 2004 Product data 1. General description The P89LPC912/913/914 are single-chip microcontrollers in low-cost 14-pin packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system level functions have been incorporated into the P89LPC912/913/914 in order to reduce component count, board space, and system cost. 2. Features ■ 1 kB byte-erasable Flash code memory organized into 256-byte sectors and 16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. ■ 128-byte RAM data memory. ■ Two 16-bit counter/timers. Each timer may be conﬁgured to toggle a port output upon timer overﬂow or to become a PWM output. ■ 23-bit system timer that can also be used as a Real-Time clock. ■ Two analog comparators with selectable inputs and reference source. ■ Enhanced UART with fractional baudrate generator, break detect, framing error detection, automatic address detection and versatile interrupt capabilities (P89LPC913, P89LPC914). ■ SPI communication port. ■ Internal RC oscillator (factory calibrated to±1 %) option allows operation without external oscillator components. The RC oscillator option is selectable and ﬁne tunable. ■ 2.4 V to 3.6 V V DD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V). ■ Up to 12 I/O pins when using internal oscillator and reset options. 3. Additional features

14-pin TSSOP packages.
A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz (167 ns to 333 ns at 12 MHz). This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI.
In-Application Programming (IAP-Lite) and byte erase allows code memory to be used for non-volatile data storage.

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 2 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Serial Flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs.
Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from 8 values.
Low voltage reset (Brownout detect) allows a graceful system shutdown when power fails. May optionally be conﬁgured as an interrupt.
Idle and two different Power-down reduced power modes. Improved wake-up from Power-down mode (a low interrupt input starts execution). Typical Power-down current is 1µA (total Power-down with voltage comparators disabled).
Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available.
Conﬁgurable on-chip oscillator with frequency range options selected by user programmed Flash conﬁguration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz (P89LPC912, P89LPC913).
Oscillator Fail Detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function.
Programmable port output conﬁguration options: quasi-bidirectional, open drain, push-pull, input-only.
Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern.
LED drive capability (20 mA) on all port pins. A maximum limit is speciﬁed for the entire chip.
Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times.
Only power and ground connections are required to operate the P89LPC912/913/914 when internal reset option is selected.
Four interrupt priority levels.
Four keypad interrupt inputs.
Second data pointer.
Schmitt trigger port inputs.
Emulation support.

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 3 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 4. Ordering information

4.1 Ordering options

Table 1: Ordering information Type number Package Name Description Version P89LPC912FDH TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 P89LPC913FDH P89LPC914FDH Table 2: Type number Temperature range Frequency P89LPC912FDH −40 °Ct o+ 8 5°C 0 MHz to 18 MHz P89LPC913FDH P89LPC914FDH 0 MHz to 12 MHz

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 4 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 5. Block diagram Fig 1. P89LPC912 block diagram. HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU 1 kB CODE FLASH 128-BYTE DATA RAM PORT 3 CONFIGURABLE I/Os PORT 0 CONFIGURABLE I/Os KEYPAD INTERRUPT PROGRAMMABLE OSCILLATOR DIVIDER CPU CLOCK CONFIGURABLE OSCILLATOR ON-CHIP RC OSCILLATOR INTERNAL BUS CRYSTAL OR RESONATOR POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) 002aaa472 SPI REAL-TIME CLOCK/ SYSTEM TIMER TIMER 0 TIMER 1 WATCHDOG TIMER AND OSCILLATOR ANALOG COMPARATORS PORT 2 CONFIGURABLE I/Os PORT 1 CONFIGURABLE I/Os P89LPC912

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 5 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Fig 2. P89LPC913 block diagram. HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU 1 kB CODE FLASH 128-BYTE DATA RAM PORT 3 CONFIGURABLE I/Os PORT 0 CONFIGURABLE I/Os KEYPAD INTERRUPT PROGRAMMABLE OSCILLATOR DIVIDER CPU CLOCK CONFIGURABLE OSCILLATOR ON-CHIP RC OSCILLATOR INTERNAL BUS CRYSTAL OR RESONATOR POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) 002aaa473 SPI REAL-TIME CLOCK/ SYSTEM TIMER UART TIMER 0 TIMER 1 WATCHDOG TIMER AND OSCILLATOR ANALOG COMPARATORS PORT 2 CONFIGURABLE I/Os PORT 1 CONFIGURABLE I/Os P89LPC913

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 6 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Fig 3. P89LPC914 block diagram. HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU 1 kB CODE FLASH 128-BYTE DATA RAM PORT 0 CONFIGURABLE I/Os KEYPAD INTERRUPT PROGRAMMABLE OSCILLATOR DIVIDER CPU CLOCK ON-CHIP RC OSCILLATOR INTERNAL BUS POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) 002aaa474 SPI REAL-TIME CLOCK/ SYSTEM TIMER UART TIMER 0 TIMER 1 WATCHDOG TIMER AND OSCILLATOR ANALOG COMPARATORS PORT 2 CONFIGURABLE I/Os PORT 1 CONFIGURABLE I/Os P89LPC914

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 7 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 6. Pinning information

6.1 Pinning

Fig 4. P89LPC912 TSSOP14 pin conﬁguration. Fig 5. P89LPC913 TSSOP14 pin conﬁguration. Fig 6. P89LPC914 TSSOP14 pin conﬁguration. handbook, halfpage P89LPC912FDH 002aaa478 P2.2/MOSI SPICLK/P2.5 RST/P1.5 VSS P0.6/CMP1/KBI6 P1.2/T0 XTAL1/P3.1 P2.3/MISO P0.2/CIN2A/KBI2 P0.4/CIN1A/KBI4 P0.5/CMPREF/KBI5 VDD P2.4/SS CLKOUT/XTAL2/P3.0 handbook, halfpage P89LPC913FDH 002aaa479 P2.2/MOSI SPICLK/P2.5 RST/P1.5 VSS P0.6/CMP1/KBI6 P1.1/RXD XTAL1/P3.1 P2.3/MISO P0.2/CIN2A/KBI2 P0.4/CIN1A/KBI4 P0.5/CMPREF/KBI5 VDD P1.0/TXD CLKOUT/XTAL2/P3.0 handbook, halfpage P89LPC914FDH 002aaa480 P2.2/MOSI SPICLK/P2.5 RST/P1.5 VSS P0.6/CMP1/KBI6 P1.1/RXD P1.2/T0 P2.3/MISO P0.2/CIN2A/KBI2 P0.4/CIN1A/KBI4 P0.5/CMPREF/KBI5 VDD P1.0/TXD P2.4/SS

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 8 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

6.2 Pin description

Table 3: P89LPC912 pin description Symbol Pin Type Description P0.2, P0.4 to P0.6 I/O Port 0:Port 0 is a 4-bit I/O port with a user-conﬁgurable output type. During reset Port 0 latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer toSection 9.11.1 “Port conﬁgurations” andTable 13 “DC electrical characteristics” for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below: 13 I/O P0.2 — Port 0 bit 2. I CIN2A — Comparator 2 positive input A. I KBI2 — Keyboard input 2. 12 I/O P0.4 — Port 0 bit 4. I CIN1A — Comparator 1 positive input A. I KBI4 — Keyboard input 4. 11 I/O P0.5 — Port 0 bit 5. I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5. 5 I/O P0.6 — Port 0 bit 6. O CMP1 — Comparator 1 output. I KBI6 — Keyboard input 6. P1.2, P1.5 I/O (P1.2); I (P1.5) Port 1:Port 1 is a 2-bit I/O port with P1.2 having a user-conﬁgurable output type as noted below. During reset Port 1 latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of the P1.2 input and outputs depends upon the port conﬁguration selected. Refer toSection 9.11.1 “Port conﬁgurations”and Table 13 “DC electrical characteristics”for details. P1.2 is an open drain when used as an output. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below: 6 I/O P1.2 — Port 1 bit 2. (Open drain when used as an output.) I/O T0 — Timer/counter 0 external count input or overﬂow output. (Open drain when used as outputs.). 3I P1.5 — Port 1 bit 5. (Input only.) I RST — External Reset input during power-on or if selected via UCFG1. When functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until V DD has reached its speciﬁed level. When system power is removed VDD will fall below the minimum speciﬁed operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V DD falls below the minimum speciﬁed operating voltage.

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 9 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. P2.2 to P2.5 I/O Port 2:Port 2 is a 4-bit I/O port with a user-conﬁgurable output type. During reset Port 2 latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer toSection 9.11.1 “Port conﬁgurations” andTable 13 “DC electrical characteristics” for details. All pins have Schmitt triggered inputs. Port 2 also provides various special functions as described below: 1 I/O P2.2 — Port 2 bit 2. I/O MOSI — SPI master out slave in. When conﬁgured as master, this pin is output, when conﬁgured as slave, this pin is input. 14 I/O P2.3 — Port 2 bit 3. I/O MISO — SPI master in slave out. When conﬁgured as master, this pin is input, when conﬁgured as slave, this pin is output. 9 I/O P2.4 — Port 2 bit 4. I SS — SPI Slave select. 2 I/O P2.5 — Port 2 bit 5. I/O SPICLK — SPI clock. When conﬁgured as master, this pin is output, when conﬁgured as slave, this pin is input. P3.0 to P3.1 I/O Port 3:Port 3 is a 2-bit I/O port with a user-conﬁgurable output type. During reset Port 3 latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer toSection 9.11.1 “Port conﬁgurations” andTable 13 “DC electrical characteristics” for details. All pins have Schmitt triggered inputs. Port 3 also provides various special functions as described below: 8 I/O P3.0 — Port 3 bit 0. O XTAL2 — Output from the oscillator ampliﬁer (when a crystal oscillator option is selected via the FLASH conﬁguration). O CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It can be used if the CPU clock is the internal RC oscillator, Watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the Real-Time clock/system timer. 7 I/O P3.1 — Port 3 bit 1. I XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when selected via the FLASH conﬁguration). It can be a port pin if internal RC oscillator or Watchdog oscillator is used as the CPU clock source,and if XTAL1/XTAL2 are not used to generate the clock for the Real-Time clock/system timer. V SS 4I Ground: 0 V reference. VDD 10 I Power Supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes. Table 3: P89LPC912 pin description…continued Symbol Pin Type Description

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 10 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Table 4: P89LPC913 pin description Symbol Pin Type Description P0.2, P0.4 to P0.6 I/O Port 0:Port 0 is a 4-bit I/O port with a user-conﬁgurable output type. During reset Port 0 latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer toSection 9.11.1 “Port conﬁgurations” andTable 13 “DC electrical characteristics” for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below: 13 I/O P0.2 — Port 0 bit 2. I CIN2A — Comparator 2 positive input A. I KBI2 — Keyboard input 2. 12 I/O P0.4 — Port 0 bit 4. I CIN1A — Comparator 1 positive input A. I KBI4 — Keyboard input 4. 11 I/O P0.5 — Port 0 bit 5. I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5. 5 I/O P0.6 — Port 0 bit 6. O CMP1 — Comparator 1 output. I KBI6 — Keyboard input 6. P1.0, P1.1, P1.5 I/O (P1.0, P1.1); I (P1.5) Port 1:Port 1 is a 3-bit I/O port with a user-conﬁgurable output type, except for P1.5 noted below. During reset Port 1 latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of the conﬁgurable Port 1 pins as inputs and outputs depends upon the port conﬁguration selected. Each of the conﬁgurable port pins are programmed independently. Refer toSection 9.11.1 “Port conﬁgurations” andTable 13 “DC electrical characteristics” for details. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below: 9 I/O P1.0 — Port 1 bit 0. O TxD — Transmitter output for the serial port. 6 I/O P1.1 — Port 1 bit 1. I RxD — Receiver input for the serial port. 3I P1.5 — Port 1 bit 5 (input only). I RST — External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until V DD has reached its speciﬁed level. When system power is removed VDD will fall below the minimum speciﬁed operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V DD falls below the minimum speciﬁed operating voltage.

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 11 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. P2.2, P2.3, P2.5 I/O Port 2: Port 2 is a 3-bit I/O port with a user-conﬁgurable output type. During reset Port 2 latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer toSection 9.11.1 “Port conﬁgurations” andTable 13 “DC electrical characteristics” for details. All pins have Schmitt triggered inputs. Port 2 also provides various special functions as described below: 13 I/O P2.2 — Port 2 bit 2. I/O MOSI — SPI master out slave in. When conﬁgured as master, this pin is output, when conﬁgured as slave, this pin is input. 14 I/O P2.3 — Port 2 bit 3. I/O MISO — SPI master in slave out. When conﬁgured as master, this pin is input, when conﬁgured as slave, this pin is output. 16 I/O P2.5 — Port 2 bit 5. I/O SPICLK — SPI clock. When conﬁgured as master, this pin is output, when conﬁgured as slave, this pin is input. P3.0 to P3.1 I/O Port 3:Port 3 is a 2-bit I/O port with a user-conﬁgurable output type. During reset Port 3 latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer toSection 9.11.1 “Port conﬁgurations” andTable 13 “DC electrical characteristics” for details. All pins have Schmitt triggered inputs. Port 3 also provides various special functions as described below: 8 I/O P3.0 — Port 3 bit 0. O XTAL2 — Output from the oscillator ampliﬁer (when a crystal oscillator option is selected via the FLASH conﬁguration). O CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It can be used if the CPU clock is the internal RC oscillator, Watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the Real-Time clock/system timer. 7 I/O P3.1 — Port 3 bit 1. I XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when selected via the FLASH conﬁguration). It can be a port pin if internal RC oscillator or Watchdog oscillator is used as the CPU clock source,and if XTAL1/XTAL2 are not used to generate the clock for the Real-Time clock/system timer. V SS 4I Ground: 0 V reference. VDD 10 I Power Supply:This is the power supply voltage for normal operation as well as Idle and Power-down modes. Table 4: P89LPC913 pin description…continued Symbol Pin Type Description

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 12 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Table 5: P89LPC914 pin description Symbol Pin Type Description P0.2, P0.4 to P0.6 I/O Port 0:Port 0 is a 4-bit I/O port with a user-conﬁgurable output type. During reset Port 0 latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer toSection 9.11.1 “Port conﬁgurations” andTable 13 “DC electrical characteristics” for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below: 13 I/O P0.2 — Port 0 bit 2. I CIN2A — Comparator 2 positive input A. I KBI2 — Keyboard input 2. 12 I/O P0.4 — Port 0 bit 4. I CIN1A — Comparator 1 positive input A. I KBI4 — Keyboard input 4. 11 I/O P0.5 — Port 0 bit 5. I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5. 5 I/O P0.6 — Port 0 bit 6. O CMP1 — Comparator 1 output. I KBI6 — Keyboard input 6. P1.0 to P1.2, P1.5 I/O (P1.0 to P1.2); I (P1.5) Port 1: Port 1 is a 4-bit I/O port with a user-conﬁgurable output type, except for three pins noted below. During reset Port 1 latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of the conﬁgurable Port 1 pins as inputs and outputs depends upon the port conﬁguration selected. Each of the conﬁgurable port pins are programmed independently. Refer toSection 9.11.1 “Port conﬁgurations”and Table 13 “DC electrical characteristics”for details. P1.2 is an open drain when used as an output. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below: 9 I/O P1.0 — Port 1 bit 0. O TxD — Transmitter output for the serial port. 6 I/O P1.1 — Port 1 bit 1. I RxD — Receiver input for the serial port. 7 I/O P1.2 — Port 1 bit 2. (Open drain when used as an output.) I/O T0 — Timer/counter 0 external count input or overﬂow output. (Open drain when used as outputs.) 3I P1.5 — Port 1 bit 5 (input only). I RST — External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 13 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. P2.2 to P2.5 I/O Port 2: Port 2 is a 4-bit I/O port with a user-conﬁgurable output type. During reset Port 2 latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer toSection 9.11.1 “Port conﬁgurations” andTable 13 “DC electrical characteristics” for details. All pins have Schmitt triggered inputs. Port 2 also provides various special functions as described below: 1 I/O P2.2 — Port 2 bit 2. I/O MOSI — SPI master out slave in. When conﬁgured as master, this pin is output, when conﬁgured as slave, this pin is input. 14 I/O P2.3 — Port 2 bit 3. I/O MISO — SPI master in slave out. When conﬁgured as master, this pin is input, when conﬁgured as slave, this pin is output. 8 I/O P2.4 — Port 2 bit 4. I SS — SPI Slave select. 2 I/O P2.5 — Port 2 bit 5. I/O SPICLK — SPI clock. When conﬁgured as master, this pin is output, when conﬁgured as slave, this pin is input. VSS 4I Ground: 0 V reference. VDD 10 I Power Supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes. Table 5: P89LPC914 pin description…continued Symbol Pin Type Description

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 14 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 7. Logic symbols Fig 7. P89LPC912 logic symbol. Fig 8. P89LPC913 logic symbol. Fig 9. P89LPC914 logic symbol. VDD VSS P89LPC912 PORT 0PORT 3 PORT 1 RST 002aaa475 CIN2A CIN1A CMPREF CMP1 XTAL2 XTAL1 KBI2 KBI4 KBI5 KBI6 CLKOUT PORT 2 MOSI MISO SS SPICLK VDD VSS P89LPC913 PORT 0PORT 3 PORT 1 RxD TxD 002aaa476 CIN2A CIN1A CMPREF CMP1 XTAL2 XTAL1 KBI2 KBI4 KBI5 KBI6 CLKOUT PORT 2 MOSI MISO SPICLK RST VDD VSS P89LPC914 PORT 0 PORT 1 RxD TxD 002aaa477 CIN2A CIN1A CMPREF CMP1 KBI2 KBI4 KBI5 KBI6 PORT 2 MOSI MISO SS RST SPICLK

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 15 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

7.1 Product comparison

Table 6highlights the differences between these three devices. For a complete list of device features, please seeSection 2 “Features” on page 1. 8. Special function registers Remark: Special Function Registers (SFRs) accesses are restricted in the following ways:

User mustnot attempt to access any SFR locations not deﬁned.
Accesses to any deﬁned SFR locations must be strictly for the functions for the SFRs.
SFR bits labeled ‘-’, ‘0’ or ‘1’ canonly be written and read as follows: – ‘-’ Unless otherwise speciﬁed,must be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives. – ‘0’must be written with ‘0’, and will return a ‘0’ when read. – ‘1’must be written with ‘1’, and will return a ‘1’ when read. Table 6: Product comparison Type number External crystal pins X2 CLKOUT T0 PWM output SPI with SS pin SPI without SS pin UART Max fosc (MHz)TxD RxD P89LPC912 X X X X - - - 18 P89LPC913 X X - - X X X 18 P89LPC914 - - X X - X X 12

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 — 17 December 2004 16 of 63 Table 7: P89LPC912 Special function registers* indicates SFRs that are bit addressable. Name Description SFR addr. Bit functions and addresses Reset value MSB LSB Hex Binary Bit address E7 E6 E5 E4 E3 E2 E1 E0 ACC* Accumulator E0H 00 00000000 AUXR1 Auxiliary function register A2H CLKLP - - ENT0 SRST 0 - DPS 00 [1] 000000x0 Bit address F7 F6 F5 F4 F3 F2 F1 F0 B* B register F0H 00 00000000 CMP1 Comparator 1 control register ACH - - CE1 - CN1 OE1 CO1 CMF1 00 [1] xx000000 CMP2 Comparator 2 control register ADH - - CE2 - CN2 - CO2 CMF2 00 [1] xx000000 DIVM CPU clock divide-by-M control 95H 00 00000000 DPTR Data pointer (2 bytes) DPH Data pointer high 83H 00 00000000 DPL Data pointer low 82H 00 00000000 FMADRH Program Flash address high E7H - - - - - - 00 00000000 FMADRL Program Flash address low E6H 00 00000000 FMCON Program Flash Control (Read) E4H BUSY - - - HVA HVE SV OI 70 01110000 Program Flash Control (Write) FMCMD. FMCMD. FMCMD.5 FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMDATA Program Flash data E5H 00 00000000 Bit address AF AE AD AC AB AA A9 A8 IEN0* Interrupt enable 0 A8H EA EWDRT EBO - ET1 - ET0 - 00 00000000 Bit address EF EE ED EC EB EA E9 E8 IEN1* Interrupt enable 1 E8H - - - - ESPI EC EKBI - 00 [1] 00x00000 Bit address BF BE BD BC BB BA B9 B8 IP0* Interrupt priority 0 B8H - PWDRT PBO - PT1 - PT0 - 00 [1] x0000000 IP0H Interrupt priority 0 high B7H - PWDRTH PBOH - PT1H - PT0H - 00 [1] x0000000 Bit address FF FE FD FC FB FA F9 F8 IP1* Interrupt priority 1 F8H - - - - PSPI PC PKBI - 00 [1] 00x00000 IP1H Interrupt priority 1 high F7H - - - - PSPIH PCH PKBIH - 00 [1] 00x00000 KBCON Keypad control register 94H - - - - - - PATN _SEL KBIF 00 [1] xxxxxx00

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 — 17 December 2004 17 of 63 KBMASK Keypad interrupt mask register 86H 00 00000000 KBPATN Keypad pattern register 93H FF 11111111 Bit address 87 86 85 84 83 82 81 80 P0* Port 0 80H CMP1/ KB6 CMPREF/ KB5 CIN1A/ KB4 CIN2A/ KB2 [1] Bit address 97 96 95 94 93 92 91 90 P1* Port 1 90H RST T0 [1] Bit address A7 A6 A5 A4 A3 A2 A1 A0 P2* Port 2 A0H SPICLK SS MISO MOSI [1] Bit address B7 B6 B5 B4 B3 B2 B1 B0 P3* Port 3 B0H XTAL1 XTAL2 [1] P0M1 Port 0 output mode 1 84H (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.2) FF 11111111 P0M2 Port 0 output mode 2 85H (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.2) 00 00000000 P1M1 Port 1 output mode 1 91H (P1M1.2) D3 [1] 11x1xx11 P1M2 Port 1 output mode 2 92H (P1M2.2) - 00 [1] 00x0xx00 P2M1 Port 2 output mode 1 A4H (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) FF 11111111 P2M2 Port 2 output mode 2 A5H (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) 00 00000000 P3M1 Port 3 output mode 1 B1H (P3M1.1) (P3M1.0) 03 [1] xxxxxx11 P3M2 Port 3 output mode 2 B2H (P3M2.1) (P3M2.0) 00 [1] xxxxxx00 PCON Power control register 87H - - BOPD BOI GF1 GF0 PMOD1 PMOD0 00 00000000 PCONA Power control register A B5H RTCPD - VCPD - - SPPD - - 00 [1] 00000000 Bit address D7 D6 D5 D4 D3 D2 D1 D0 PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 00000000 PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 - PT0AD.2 - - 00 xx00000x RSTSRC Reset source register DFH - - BOF POF - R_WD R_SF R_EX [2] RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60 [1][5]011xxx00 RTCH Real-time clock register high D2H 00[5] 00000000 RTCL Real-time clock register low D3H 00[5] 00000000 SP Stack pointer 81H 07 00000111 Table 7: P89LPC912 Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. Bit functions and addresses Reset value MSB LSB Hex Binary

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 — 17 December 2004 18 of 63 [1] All ports are in input only (high impedance) state after power-up. [2] The RSTSRC register reﬂects the cause of the P89LPC912 reset. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the power-on reset value is xx110000. [3] After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOF bit is ‘1’ after Watchdog reset and is ‘0’ after power-onreset. Other resets will not affect WDTOF . [4] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [5] The only reset source that affects these SFRs is power-on reset. SPCTL SPI control register E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 04 00000100 SPSTAT SPI status register E1H SPIF WCOL - - - - - - 00 00xxxxxx SPDAT SPI data register E3H 00 00000000 TAMOD Timer 0 and 1 auxiliary mode 8FH - - - - - - - T0M2 00 xxx0xxx0 Bit address 8F 8E 8D 8C 8B 8A 89 88 TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 - - - - 00 00000000 TH0 Timer 0 high 8CH 00 00000000 TH1 Timer 1 high 8DH 00 00000000 TL0 Timer 0 low 8AH 00 00000000 TL1 Timer 1 low 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H - - T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 00000000 [4] [5] WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK [3] [5] WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H Table 7: P89LPC912 Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. Bit functions and addresses Reset value MSB LSB Hex Binary

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 — 17 December 2004 19 of 63 Table 8: P89LPC913 Special function registers* indicates SFRs that are bit addressable. Name Description SFR addr. Bit functions and addresses Reset value MSB LSB Hex Binary Bit address E7 E6 E5 E4 E3 E2 E1 E0 ACC* Accumulator E0H 00 00000000 AUXR1 Auxiliary function register A2H CLKLP EBRR - - SRST 0 - DPS 00 [1] 000000x0 Bit address F7 F6 F5 F4 F3 F2 F1 F0 B* B register F0H 00 00000000 BRGR0 [2] Baud rate generator rate low BEH 00 00000000 BRGR1 [2] Baud rate generator rate high BFH 00 00000000 BRGCON Baud rate generator control BDH - - - - - - SBRGS BRGEN 00 [6] xxxxxx00 CMP1 Comparator 1 control register ACH - - CE1 - CN1 OE1 CO1 CMF1 00 [1] xx000000 CMP2 Comparator 2 control register ADH - - CE2 - CN2 - - CMF2 00 [1] xx000000 DIVM CPU clock divide-by-M control 95H 00 00000000 DPTR Data pointer (2 bytes) DPH Data pointer high 83H 00 00000000 DPL Data pointer low 82H 00 00000000 FMADRH Program Flash address high E7H - - - - - - 00 00000000 FMADRL Program Flash address low E6H 00 00000000 FMCON Program Flash Control (Read) E4H BUSY - - - HVA HVE SV OI 70 01110000 Program Flash Control (Write) FMCMD. FMCMD. FMCMD.5 FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMDATA Program Flash data E5H 00 00000000 Bit address AF AE AD AC AB AA A9 A8 IEN0* Interrupt enable 0 A8H EA EWDRT EBO ES/ESR ET1 - ET0 - 00 00000000 Bit address EF EE ED EC EB EA E9 E8 IEN1* Interrupt enable 1 E8H - EST - - ESPI EC EKBI - 00 [1] 00x00000 Bit address BF BE BD BC BB BA B9 B8 IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 - PT0 - 00 [1] x0000000 IP0H Interrupt priority 0 high B7H - PWDRTH PBOH PSH/ PSRH PT1H - PT0H - 00 [1] x0000000

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 — 17 December 2004 20 of 63 Bit address FF FE FD FC FB FA F9 F8 IP1* Interrupt priority 1 F8H - PST - - PSPI PC PKBI - 00 [1] 00x00000 IP1H Interrupt priority 1 high F7H - PSTH - - PSPIH PCH PKBIH - 00 [1] 00x00000 KBCON Keypad control register 94H - - - - - - PATN _SEL KBIF 00 [1] xxxxxx00 KBMASK Keypad interrupt mask register 86H 00 00000000 KBPATN Keypad pattern register 93H FF 11111111 Bit address 87 86 85 84 83 82 81 80 P0* Port 0 80H CMP1/ KB6 CMPREF/ KB5 CIN1A/ KB4 CIN2A/ KB2 [1] Bit address 97 96 95 94 93 92 91 90 P1* Port 1 90H RST RxD TxD [1] Bit address A7 A6 A5 A4 A3 A2 A1 A0 P2* Port 2 A0H SPICLK MISO MOSI [1] Bit address B7 B6 B5 B4 B3 B2 B1 B0 P3* Port 3 B0H XTAL1 XTAL2 [1] P0M1 Port 0 output mode 1 84H (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.2) FF 11111111 P0M2 Port 0 output mode 2 85H (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.2) 00 00000000 P1M1 Port 1 output mode 1 91H (P1M1.1) (P1M1.0) D3 [1] 11x1xx11 P1M2 Port 1 output mode 2 92H (P1M2.1) (P1M2.0) 00 [1] 00x0xx00 P2M1 Port 2 output mode 1 A4H (P2M1.5) (P2M1.3) (P2M1.2) FF 11111111 P2M2 Port 2 output mode 2 A5H (P2M2.5) (P2M2.3) (P2M2.2) 00 00000000 P3M1 Port 3 output mode 1 B1H (P3M1.1) (P3M1.0) 03 [1] xxxxxx11 P3M2 Port 3 output mode 2 B2H (P3M2.1) (P3M2.0) 00 [1] xxxxxx00 PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 00000000 PCONA Power control register A B5H RTCPD - VCPD - - SPPD SPD - 00 [1] 00000000 Table 8: P89LPC913 Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. Bit functions and addresses Reset value MSB LSB Hex Binary

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 — 17 December 2004 21 of 63 Bit address D7 D6 D5 D4 D3 D2 D1 D0 PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 00000000 PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 - PT0AD.2 - - 00 xx00000x RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX [3] RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60 [1][6]011xxx00 RTCH Real-time clock register high D2H 00[6] 00000000 RTCL Real-time clock register low D3H 00[6] 00000000 SADDR Serial port address register A9H 00 00000000 SADEN Serial port address enable B9H 00 00000000 SBUF Serial port data buffer register 99H xx xxxxxxxx Bit address 9F 9E 9D 9C 9B 9A 99 98 SCON Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 00000000 SSTAT Serial port extended status register BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000 SP Stack pointer 81H 07 00000111 SPCTL SPI control register E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 04 00000100 SPSTAT SPI status register E1H SPIF WCOL - - - - - - 00 00xxxxxx SPDAT SPI data register E3H 00 00000000 Bit address 8F 8E 8D 8C 8B 8A 89 88 TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 - - - - 00 00000000 TH0 Timer 0 high 8CH 00 00000000 TH1 Timer 1 high 8DH 00 00000000 TL0 Timer 0 low 8AH 00 00000000 TL1 Timer 1 low 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H - - T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 00000000 [5] [6] WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK [4] [6] Table 8: P89LPC913 Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. Bit functions and addresses Reset value MSB LSB Hex Binary

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 — 17 December 2004 23 of 63 Table 9: P89LPC914 Special function registers* indicates SFRs that are bit addressable. Name Description SFR addr. Bit functions and addresses Reset value MSB LSB Hex Binary Bit address E7 E6 E5 E4 E3 E2 E1 E0 ACC* Accumulator E0H 00 00000000 AUXR1 Auxiliary function register A2H - EBRR - ENT0 SRST 0 - DPS 00 [1] 000000x0 Bit address F7 F6 F5 F4 F3 F2 F1 F0 B* B register F0H 00 00000000 BRGR0 [2] Baud rate generator rate low BEH 00 00000000 BRGR1 [2] Baud rate generator rate high BFH 00 00000000 BRGCON Baud rate generator control BDH - - - - - - SBRGS BRGEN 00 [6] xxxxxx00 CMP1 Comparator 1 control register ACH - - CE1 - CN1 OE1 CO1 CMF1 00 [1] xx000000 CMP2 Comparator 2 control register ADH - - CE2 - CN2 - CO2 CMF2 00 [1] xx000000 DIVM CPU clock divide-by-M control 95H 00 00000000 DPTR Data pointer (2 bytes) DPH Data pointer high 83H 00 00000000 DPL Data pointer low 82H 00 00000000 FMADRH Program Flash address high E7H - - - - - - 00 00000000 FMADRL Program Flash address low E6H 00 00000000 FMCON Program Flash Control (Read) E4H BUSY - - - HVA HVE SV OI 70 01110000 Program Flash Control (Write) FMCMD. FMCMD. FMCMD.5 FMCMD. FMCMD. FMCMD. FMCMD.1 FMCMD. FMDATA Program Flash data E5H 00 00000000 Bit address AF AE AD AC AB AA A9 A8 IEN0* Interrupt enable 0 A8H EA EWDRT EBO ES/ESR ET1 - ET0 - 00 00000000 Bit address EF EE ED EC EB EA E9 E8 IEN1* Interrupt enable 1 E8H - EST - - ESPI EC EKBI - 00 [1] 00x00000 Bit address BF BE BD BC BB BA B9 B8 IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 - PT0 - 00 [1] x0000000 IP0H Interrupt priority 0 high B7H - PWDRTH PBOH PSH/ PSRH PT1H - PT0H - 00 [1] x0000000

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 — 17 December 2004 24 of 63 Bit address FF FE FD FC FB FA F9 F8 IP1* Interrupt priority 1 F8H - PST - - PSPI PC PKBI - 00 [1] 00x00000 IP1H Interrupt priority 1 high F7H - PSTH - - PSPIH PCH PKBIH - 00 [1] 00x00000 KBCON Keypad control register 94H - - - - - - PATN_SEL KBIF 00 [1] xxxxxx00 KBMASK Keypad interrupt mask register 86H 00 00000000 KBPATN Keypad pattern register 93H FF 11111111 Bit address 87 86 85 84 83 82 81 80 P0* Port 0 80H CMP1/ KB6 CMPREF/ KB5 CIN1A/ KB4 CIN2A/ KB2 [1] Bit address 97 96 95 94 93 92 91 90 P1* Port 1 90H RST T0 RxD TxD [1] Bit address A7 A6 A5 A4 A3 A2 A1 A0 P2* Port 2 A0H SPICLK SS MISO MOSI [1] P0M1 Port 0 output mode 1 84H (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.2) FF 11111111 P0M2 Port 0 output mode 2 85H (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.2) 00 00000000 P1M1 Port 1 output mode 1 91H (P1M1.2) (P1M1.1) (P1M1.0) D3 [1] 11x1xx11 P1M2 Port 1 output mode 2 92H (P1M2.2) (P1M2.1) (P1M2.0) 00 [1] 00x0xx00 P2M1 Port 2 output mode 1 A4H (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) FF 11111111 P2M2 Port 2 output mode 2 A5H (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) 00 00000000 PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 00000000 PCONA Power control register A B5H RTCPD - VCPD - - SPPD SPD - 00 [1] 00000000 Bit address D7 D6 D5 D4 D3 D2 D1 D0 PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 00000000 PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 - PT0AD.2 - - 00 xx00000x RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX [3] RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60 [1][6]011xxx00 RTCH Real-time clock register high D2H 00[6] 00000000 RTCL Real-time clock register low D3H 00[6] 00000000 SADDR Serial port address register A9H 00 00000000 Table 9: P89LPC914 Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. Bit functions and addresses Reset value MSB LSB Hex Binary

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 — 17 December 2004 25 of 63 [1] All ports are in input only (high impedance) state after power-up. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any of them is written if BRGEN = 1, result is unpredictable. [3] The RSTSRC register reﬂects the cause of the P89LPC912 reset. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the power-on reset value is xx110000. [4] After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOF bit is ‘1’ after Watchdog reset and is ‘0’ after power-onreset. Other resets will not affect WDTOF . [5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [6] The only reset source that affects these SFRs is power-on reset. SADEN Serial port address enable B9H 00 00000000 SBUF Serial port data buffer register 99H xx xxxxxxxx Bit address 9F 9E 9D 9C 9B 9A 99 98 SCON Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 00000000 SSTAT Serial port extended status register BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000 SP Stack pointer 81H 07 00000111 SPCTL SPI control register E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 04 00000100 SPSTAT SPI status register E1H SPIF WCOL - - - - - - 00 00xxxxxx SPDAT SPI data register E3H 00 00000000 TAMOD Timer 0 and 1 auxiliary mode 8FH - - - - - - - T0M2 00 xxx0xxx0 Bit address 8F 8E 8D 8C 8B 8A 89 88 TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 - - - - 00 00000000 TH0 Timer 0 high 8CH 00 00000000 TH1 Timer 1 high 8DH 00 00000000 TL0 Timer 0 low 8AH 00 00000000 TL1 Timer 1 low 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H - - T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 00000000 [5] [6] WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK [4] [6] WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H Table 9: P89LPC914 Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. Bit functions and addresses Reset value MSB LSB Hex Binary

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 26 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9. Functional description Remark: Please refer to theP89LPC912/913/914 User’s Manual for a more detailed functional description.

9.1 Enhanced CPU

The P89LPC912/913/914 uses an enhanced 80C51 CPU which runs at 6 times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

9.2 Clocks

9.2.1 Clock deﬁnitions

The P89LPC912/913/914 device has several internal clocks as deﬁned below: OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources (seeFigure 10,11, and12) and can also be optionally divided to a slower frequency (seeSection 9.7 “CPU Clock (CCLK) modiﬁcation: DIVM register”). Note: fosc is deﬁned as the OSCCLK frequency. CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles). RCCLK — The internal 7.373 MHz RC oscillator output. PCLK — Clock for the various peripheral devices and is CCLK/2

9.2.2 CPU clock (OSCCLK)

The P89LPC912/913/914 provide user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are conﬁgured when the FLASH is programmed and include an on-chip Watchdog oscillator and an on-chip RC oscillator. In addition, both the P89LPC912 and P89LPC913 provide an oscillator using an external crystal or an external clock source. The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 12 MHz.

9.2.3 Low speed oscillator option (P89LPC912, P89LPC913)

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this conﬁguration.

9.2.4 Medium speed oscillator option (P89LPC912, P89LPC913)

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this conﬁguration.

9.2.5 High speed oscillator option (P89LPC912, P89LPC913)

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this conﬁguration.When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until V DD has

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 27 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. reached its speciﬁed level. When system power is removed VDD will fall below the minimum speciﬁed operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V DD falls below the minimum speciﬁed operating voltage.

9.2.6 Clock output (P89LPC912, P89LPC913)

The P89LPC912 supports a user selectable clock output function on the XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, Watchdog oscillator, external clock input on X1) and if the Real-Time clock is not using the crystal oscillator as its clock source. This allows external devices to synchronize to the P89LPC912. This output is enabled by the ENCLK bit in the TRIM register. The frequency of this clock output is 1⁄2 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power.

9.3 On-chip RC oscillator option

The P89LPC912/913/914 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz,±2.5 %. End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies.

9.4 Watchdog oscillator option

The Watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.

9.5 External clock input option (P89LPC912, P89LPC913)

In this conﬁguration, the processor clock is derived from an external source driving the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 12 MHz. The XTAL2/P3.0 pin may be used as a standard port pin or a clock output.When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until V DD has reached its speciﬁed level. When system power is removed VDD will fall below the minimum speciﬁed operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V DD falls below the minimum speciﬁed operating voltage.

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 28 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Fig 10. Block diagram of oscillator control (P89LPC912). Fig 11. Block diagram of oscillator control (P89LPC913). 002aaa481 RTC CPU WDT SPI DIVM CCLKOSCCLK PCLK TIMER 0 and TIMER 1 High freq. Med. freq. Low freq. XTAL1 XTAL2 RC OSCILLATOR WATCHDOG OSCILLATOR (7.3728 MHz) (400 kHz) Oscillator clock CPU clock Peripheral clock 002aaa482 RTC CPU WDT SPI DIVM CCLKOSCCLK PCLK TIMER 0 and TIMER 1 High freq. Med. freq. Low freq. XTAL1 XTAL2 RC OSCILLATOR WATCHDOG OSCILLATOR (7.3728 MHz) (400 kHz) Oscillator clock CPU clock Peripheral clock UART BAUD RATE GENERATOR CCLK /KB82

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 29 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

9.6 CPU Clock (CCLK) wake-up delay

The P89LPC912/913/914 has an internal wake-up timer that delays the clock until it stabilizes, depending to the clock source used. If the clock source is any of the three crystal selections (P89LPC912, P89LPC913) the delay is 992 OSCCLK cycles plus 60 to 100µs. If the clock source is either the internal RC oscillator, Watchdog oscillator, or external clock, the delay is 224 OSCCLK cycles plus 60 to 100µs.

9.7 CPU Clock (CCLK) modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.

9.8 Low power select

The P89LPC912 and P89LPC913 are designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the power consumption further. On any reset, CLKLP is ‘0’ allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

9.9 Memory organization

The various P89LPC912/913/914 memory spaces are as follows:

DATA 128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. Fig 12. Block diagram of oscillator control (P89LPC914). 002aaa483 RTC CPU WDT SPI DIVM CCLKOSCCLK PCLK TIMER 0 and TIMER 1 RC OSCILLATOR WATCHDOG OSCILLATOR (7.3728 MHz) (400 kHz) Oscillator clock CPU clock Peripheral clock UART BAUD RATE GENERATOR CCLK /KB82

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 30 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

SFR Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.
CODE 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC912/913/914 has 1 kB of on-chip Code memory.

9.10 Interrupts

The P89LPC912/913/914 uses a four priority level interrupt structure. This allows great ﬂexibility in controlling the handling of the many interrupt sources. The P89LPC912 supports 7 interrupt sources: timers 0 and 1, brownout detect, Watchdog/Real-Time clock, keyboard, comparators 1 and 2, and SPI. The P89LPC913 and P89LPC914 devices support 10 interrupt sources: timers 0 and 1, serial port Tx, serial port Rx, combined serial port Rx/Tx, brownout detect, Watchdog/Real-Time clock, keyboard, comparators 1 and 2, and SPI. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts. Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced. If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level.

9.10.1 External interrupt inputs

The P89LPC912/913/914 has a Keypad Interrupt function. This can be used as an external interrupt input. If enabled when the P89LPC912/913/914 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer toSection 9.13 “Power reduction modes” for details.

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 31 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

9.11 I/O ports

The P89LPC912 and P89LPC913 devices have 4 I/O ports: Port 0, Port 1, Port 2 and Port 3. The exact number of I/O pins available depends on the clock and reset options chosen, as shown inTable 10. Fig 13. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC912). 002aaa484 BOF EBO KBF EKB INTERRUPT TO CPU WAKE-UP (IF IN POWER-DOWN) EWDRT CMF2 CMF1 EC EA (IE0.7) TF0 ET0 TF1 ET1 SPIF ESPI RTCF ERTC (RTCCON.1) WDOVF Fig 14. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC913, P89LPC914). 002aaa485 BOF EBO KBF EKB INTERRUPT TO CPU WAKE-UP (IF IN POWER-DOWN) EWDRT CMF2 CMF1 EC EA (IE0.7) RTCF ERTC (RTCCON.1) WDOVF TF0 ET0 TF1 ET1 TI & RI/RI ES/ESR TI EST SPIF ESPI

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 32 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. [1] Required for operation above 12 MHz. The P89LPC914 has 3 I/O ports: Port 0, Port 1, and Port 2. The exact number of I/O pins available depends on the reset option chosen, as shown inTable 11. [1] Required for external clock frequency above 12 MHz.

9.11.1 Port conﬁgurations

Except as listed below, every I/O pin on the P89LPC912/913/914 may be conﬁgured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two conﬁguration registers for each port select the output type for each port pin. P1.5/ RST can only be an input and cannot be conﬁgured. P1.2/T0 may only be conﬁgured to be either input-only or open drain (P89LPC912, P89LPC914).

9.11.2 Quasi-bidirectional output conﬁguration

Quasi-bidirectional output type can be used as both an input and output without the need to reconﬁgure the port. This is possible because when the port outputs a logic HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the pin is driven LOW, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. The P89LPC912/913/914 is a 3 V device, but the pins are 5 V-tolerant. In quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current ﬂowing from the pin to V DD , causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is discouraged. Table 10: Number of I/O pins available (P89LPC912, P89LPC913) Clock source Reset option Number of I/O pins (14-pin package) On-chip oscillator or watchdog oscillator No external reset (except during power-up) External RST pin supported 11 External clock input No external reset (except during power-up) ExternalRST pin supported 10 Low/medium/high speed oscillator (external crystal or resonator) No external reset (except during power-up) ExternalRST pin supported[1] 9 Table 11: Number of I/O pins available (P89LPC914) Reset option Number of I/O pins (14-pin package) No external reset (except during power-up) 12 External RST pin supported[1] 11

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 33 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch suppression circuit.

9.11.3 Open-drain output conﬁguration

The open-drain output conﬁguration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic ‘0’. To be used as a logic output, a port conﬁgured in this manner must have an external pull-up, typically a resistor tied to V DD . An open-drain port pin has a Schmitt-triggered input that also has a glitch suppression circuit.

9.11.4 Input-only conﬁguration

The input-only port conﬁguration has no output drivers. It is a Schmitt-triggered input that also has a glitch suppression circuit.

9.11.5 Push-pull output conﬁguration

The push-pull output conﬁguration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic ‘1’. The push-pull mode may be used when more source current is needed from a port output. A push-pull port pin has a Schmitt-triggered input that also has a glitch suppression circuit.

9.11.6 Port 0 analog functions

The P89LPC912/913/914 incorporates two Analog Comparators. In order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port output into the Input-Only (high impedance) mode as described inSection 9.11.4 “Input-only conﬁguration”. Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On any reset, the PT0AD bits default to ‘0’s to enable digital functions.

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9.11.7 Additional port features

After power-up, all pins are in Input-Only mode. After power-up all I/O pins except P1.5, may be conﬁgured by software.

Pin P1.5 is input only.
P1.2/T0 is conﬁgurable for either input-only or open-drain (P89LPC912, P89LPC914). Every output on the P89LPC912/913/914 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer toTable 13 “DC electrical characteristics” for detailed speciﬁcations. All port pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.

9.12 Power monitoring functions

The P89LPC912/913/914 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on Detect and Brownout detect.

9.12.1 Brownout detection

The Brownout detect function determines if the power supply voltage drops below a certain level. The default operation is for a Brownout detection to cause a processor reset, however, it may alternatively be conﬁgured to generate an interrupt. Brownout detection may be enabled or disabled in software. If Brownout detection is enabled, the brownout condition occurs when V DD falls below the brownout trip voltage, VBO (seeTable 13 “DC electrical characteristics”), and is negated when VDD rises above VBO . If the P89LPC912/913/914 device is to operate with a power supply that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from operating. For correct activation of Brownout detect, the V DD rise and fall times must be observed. Please seeTable 13 “DC electrical characteristics” for speciﬁcations.

9.12.2 Power-on detection

The Power-on Detect has a function similar to the Brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where Brownout detect can work. The POF ﬂag in the RSTSRC register is set to indicate an initial power-up condition. The POF ﬂag will remain set until cleared by software.

9.13 Power reduction modes

The P89LPC912/913/914 supports three different power reduction modes. These modes are Idle mode, Power-down mode, and total Power-down mode.

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 35 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

9.13.1 Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode.

9.13.2 Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC912/913/914 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the RAM keep-alive voltage V RAM . This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after VDD has been lowered to VRAM , therefore it is highly recommended to wake up the processor via reset in this case. VDD must be raised to within the operating range before the Power-down mode is exited. Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during Power-down. These include: Brownout detect, Watchdog Timer, Comparators (note that Comparators can be powered-down separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clockand the RTC is enabled.

9.13.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clockand the RTC is enabled. If the internal RC oscillator is used to clock the RTC during Power-down, there will be high power consumption. Please use an external low frequency clock to achieve low power with the Real-Time Clock running during Power-down.

9.14 Reset

The P1.5/RST pin can function as either an active-LOW reset input or as a digital input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin. Remark: During a power-up sequence, the RPE selection is overridden and this pin will always function as a reset input.An external circuit connected to this pin should not hold this pin LOW during a power-on sequence as this will keep the device in reset. After power-up this input will function either as an external reset input or as a digital input as deﬁned by the RPE bit. Only a power-up reset will temporarily override the selection deﬁned by RPE bit. Other sources of reset will not override the RPE bit.

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 36 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Reset can be triggered from the following sources:

External reset pin (during power-up or if user conﬁgured via UCFG1. This option must be used for an oscillator frequency above 12 MHz.)
Power-on detect
Brownout detect
Watchdog Timer
Software reset
UART break character detect reset (P80LPC913, P89LPC914). For every reset source, there is a ﬂag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These ﬂag bits can be cleared in software by writing a ‘0’ to the corresponding bit. More than one ﬂag bit may be set:
During a power-on reset, both POF and BOF are set but the other ﬂag bits are cleared.
For any other reset, previously set ﬂag bits that have not been cleared will remain set.

9.15 Timers/counters 0 and 1

The P89LPC912/913/914 devices have two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. An option to automatically toggle the T0 pin upon timer overﬂow has been added (P89LPC912, P89LPC914). In the ‘Timer’ function, the register is incremented every machine cycle. In the ‘Counter’ function, the register of Timer 0 is incremented in response to a 1-to-0 transition at its external input pin, T0. This external input is sampled once very machine cycle. Timer 0 has four operating modes (modes 0, 1, 2, and 3) on the P89LPC913). Timer 0 has ﬁve operating modes (modes 0, 1, 2, 3, and 6 on the P89LPC912 and P89LPC914. Timer 1 has four operating modes (modes 0, 1, 2, and 3) on all devices. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 is different.

9.15.1 Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. In this mode, the Timer register is conﬁgured as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.

9.15.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

9.15.3 Mode 2

Mode 2 conﬁgures the Timer register as an 8-bit Counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1.

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9.15.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.

9.15.5 Mode 6 (P89LPC912, P89LPC914)

In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks.

9.15.6 Timer overﬂow toggle output (P89LPC912, P89LPC914)

Timers 0 can be conﬁgured to automatically toggle the T0 output whenever a timer overﬂow occurs. The same device pins that are used for the T0 count input is also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the ﬁrst timer overﬂow when this mode is turned on.

9.16 Real-Time clock/system timer

The P89LPC912/913/914 devices have a simple Real-Time clock that allows a user to continue running an accurate timer while the rest of the device is powered-down. The Real-Time clock can be a wake-up or an interrupt source. The Real-Time clock is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. When it reaches all ‘0’s, the counter will be reloaded again and the RTCF ﬂag will be set. On the P89LPC914 the clock source for this counter is the CPU clock (CCLK). On the P89LPC912 and P89LPC913 devices, the clock source for this counter can either be the CPU clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is not being used as the CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as its clock source. Only power-on reset will reset the Real-Time clock and its associated SFRs to the default state.

9.17 UART (P89LPC913, P89LPC914)

The P89LPC913 and P89LPC914 devices have an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overﬂow cannot be used as a baud rate source. The P89LPC913 does include an independent Baud Rate Generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overﬂow, or the independent Baud Rate Generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options. The UART can be operated in 4 modes: shift register, 8-bit UART, 9-bit UART, and CCLK/32 or CCLK/16.

9.17.1 Mode 0

Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted or received, LSB ﬁrst. The baud rate is ﬁxed at 1⁄16 of the CPU clock frequency.

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9.17.2 Mode 1

10 bits are transmitted (through TxD) or received (through RxD): a start bit (logical ‘0’), 8 data bits (LSB ﬁrst), and a stop bit (logical ‘1’). When data is received, the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is variable and is determined by the Timer 1 overﬂow rate or the Baud Rate Generator (described inSection 9.17.5 “Baud rate generator and selection”).

9.17.3 Mode 2

11 bits are transmitted (through TxD) or received (through RxD): start bit (logical ‘0’), 8 data bits (LSB ﬁrst), a programmable 9 th data bit, and a stop bit (logical ‘1’). When data is transmitted, the 9thdata bit (TB8 in SCON) can be assigned the value of ‘0’ or ‘1’. Or, for example, the parity bit (P , in the PSW) could be moved into TB8. When data is received, the 9 th data bit goes into RB8 in Special Function Register SCON, while the stop bit is not saved. The baud rate is programmable to either1⁄16 or1⁄32 of the CCLK frequency, as determined by the SMOD1 bit in PCON.

9.17.4 Mode 3

11 bits are transmitted (through TxD) or received (through RxD): a start bit (logical ‘0’), 8 data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logical ‘1’). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overﬂow rate or the Baud Rate Generator (described in sectionSection 9.17.5 “Baud rate generator and selection”).

9.17.5 Baud rate generator and selection

The P89LPC913 and P89LPC914 devices have an independent Baud Rate Generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1. If the baud rate generator is used, Timer 1 can be used for other timing functions. The UART can use either Timer 1 or the baud rate generator output (seeFigure 15). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The independent Baud Rate Generator uses CCLK.

9.17.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is ‘1’, framing errors can be made available in SCON.7, respectively. If SMOD0 is ‘0’, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up when SMOD0 is ‘0’. Fig 15. Baud rate sources for UART (Modes 1, 3). Baud Rate Modes 1 and 3 SBRGS = 1 SBRGS = 0 SMOD1 = 0 SMOD1 = 1 /KB82 Timer 1 Overflow (PCLK-based) Baud Rate Generator (CCLK-based) 002aaa419

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9.17.7 Break detect

Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device.

9.17.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the ﬁrst character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 =‘0’), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SnBUF while the previous data is being shifted out. Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = ‘0’).

9.17.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated when the double buffer is ready to receive new data.

9.17.10 The 9

th bit (bit 8) in double buffering (Modes 1, 2 and 3) If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the Tx interrupt. If double buffering is enabled, TB8must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data.

9.18 Serial Peripheral Interface (SPI)

P89LPC912/913/914 provides another high-speed serial communication interface—the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported in Master or 3 Mbit/s in Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection.

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 40 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. The SPI interface has four pins: SPICLK, MOSI, MISO, andSS:

SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data ﬂows from master to slave on MOSI (Master Out Slave In) pin and ﬂows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal Fig 16. SPI block diagram (P89LPC912, P89LPC914). 002aaa497 CPU clock DIVIDER BY 4, 16, 64, 128 SELECT CLOCK LOGIC SPI CONTROL REGISTER READ DATA BUFFER 8-BIT SHIFT REGISTER SPI CONTROL SPI STATUS REGISTER SPR1 SPIF WCOL SPR0 SPI clock (master) PIN CONTROL LOGIC S M S M M S MISO P2.3 MOSI P2.2 SPICLK P2.5 SS P2.4 SPI interrupt request internal data bus SSIG SPEN SPEN MSTR DORD MSTR CPHA CPOL SPR1 SPR0 MSTR SPEN clock Fig 17. SPI block diagram (P89LPC913). 002aaa498 CPU clock DIVIDER BY 4, 16, 64, 128 SELECT CLOCK LOGIC clock SPI CONTROL REGISTER READ DATA BUFFER 8-BIT SHIFT REGISTER SPI CONTROL SPI STATUS REGISTER SPR1 SPIF WCOL SPR0 SPI clock (master) PIN CONTROL LOGIC S M S M M S MISO P2.3 MOSI P2.2 SPICLK P2.5 SPI interrupt request internal data bus SSIG SPEN SPEN MSTR DORD MSTR CPHA CPOL SPR1 SPR0 MSTR SPEN

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 41 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. is output in the master mode and is input in the slave mode. If the SPI system is disabled, i.e. SPEN (SPCTL.6) = 0 (reset value), these pins are conﬁgured for port functions.

SS is the optional slave select pin. In a typical conﬁguration, an SPI master asserts one of its port pins to select one SPI device as the current slave. An SPI slave device uses its SS pin to determine whether it is selected. Typical connections are shown inFigure 18,19, and20.
The 89LPC913 does not have the slave select pin,SS. The SPI interface is set to Master mode and an I/O pin may be used to implement theSS function. Typical connections are shown inFigure 18 and19.

9.18.1 Typical SPI conﬁgurations

Fig 18. SPI single master single slave conﬁguration. 002aaa435 Master Slave 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR 8-BIT SHIFT REGISTER MISO MOSI SPICLK PORT MISO MOSI SPICLK SS

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 42 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Fig 19. SPI single master multiple slaves conﬁguration. Fig 20. SPI dual device conﬁguration, where either can be a master or a slave. 002aaa437 Master Slave 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR 8-BIT SHIFT REGISTER MISO MOSI SPICLK port port MISO MOSI SPICLK SS Slave 8-BIT SHIFT REGISTER MISO MOSI SPICLK SS 002aaa499 Master Slave 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR SPI CLOCK GENERATOR 8-BIT SHIFT REGISTER MISO MOSI SPICLK MISO MOSI SPICLK SSSS

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 43 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

9.19 Analog comparators

Two analog comparators are provided on the P89LPC912/913/914. Input and output options allow use of the comparators in a number of different conﬁgurations. Comparator operation is such that the output is a logical ‘1’ when the positive input is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be conﬁgured to cause an interrupt when the output value changes. Comparator 1 may be output to a port pin. The overall connections to both comparators are shown inFigure 21. The comparators function to V DD = 2.4 V. When each comparator is ﬁrst enabled, the comparator output and interrupt ﬂag are not guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt ﬂag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service.

9.20 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as V REF , is 1.23 V±10 %.

9.21 Comparator interrupt

Each comparator has an interrupt ﬂag contained in its conﬁguration register. This ﬂag is set whenever the comparator output changes state. The ﬂag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. If both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the ﬂags to determine which comparator caused the interrupt. Possible comparator conﬁgurations are shown inFigure 22. Fig 21. Comparator input and output connections. Comparator 1 CN1 (P0.4) CIN1A (P0.5) CMPREF VREF OE1 Change Detect CO1 CMF1 Interrupt 002aaa496 CMP1 (P0.6) ECChange Detect CMF2Comparator 2 CN2 (P0.2) CIN2A

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 44 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

9.22 Comparator and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode. If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake up the processor. If the comparator output to a pin is enabled, the pin should be conﬁgured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with theoscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. Comparators consume power in Power-down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparators via PCONA.5, or put the device in Total Power-down mode.

9.23 Keypad interrupt (KBI)

The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can conﬁgure the port via SFRs for different tasks. The Keypad Interrupt Mask Register (KBMASK) is used to deﬁne which input pins connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to deﬁne a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to deﬁne equal or not-equal for the comparison. a. CN1, OE 1=00 b . CN1, OE1 = 0 1 c. CN1, OE 1=10 d . CN1, OE1 = 1 1 e . C N 2=0 f . C N 2=1 Fig 22. Comparator conﬁgurations. CIN1A CMPREF 002aaa490 CO1 CIN1A CMPREF 002aaa491 CO1 CMP1 CIN1A VREF (1.23 V) 002aaa492 CO1 CIN1A VREF (1.23 V) 002aaa493 CO1 CMP1 CIN2A CMPREF 002aaa494 CO2 CIN2A VREF (1.23 V) 002aaa495 CO2

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 45 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. In order to set the ﬂag and cause an interrupt, the pattern on Port 0 must be held longer than 6 CCLKs.

9.24 Watchdog timer

The watchdog timer causes a system reset when it underﬂows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler. The clock source for the prescaler is either the PCLK or the nominal 400 kHz Watchdog oscillator. The watchdog timer can only be reset by a power-on reset. When the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt.Figure 23 shows the watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered-down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from af e wµs to a few seconds. Please refer to the P89LPC912/913/914 User’s Manualfor more details. (1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence. Fig 23. Watchdog timer in Watchdog mode (WDTE = ‘1’). PRE2 PRE1 PRE0 – – WDRUN WDTOF WDCLKWDCON (A7H) CONTROL REGISTER PRESCALER 002aaa423 SHADOW REGISTER FOR WDCON 8-BIT DOWN COUNTER WDL (C1H) Watchdog oscillator PCLK ÷32 MOV WFEED1, #0A5H MOV WFEED2, #05AH RESET see note (1)

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 46 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

9.25 Additional features

9.25.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets.

9.25.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic ‘0’ so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register.

9.26 Flash program memory

9.26.1 General description

The P89LPC912/913/914 Flash memory provides in-circuit electrical erasure and programming. The Flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any Flash sector (256 bytes) or page (16 bytes). The Chip Erase operation will erase the entire program memory. In-Circuit Programming using standard commercial programmers is available. In addition, In-Application Programming (IAP) and byte erase allows code memory to be used for non-volatile data storage. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC912/913/914 Flash reliably stores memory contents even after 100,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. The P89LPC912/913/914 uses V DD as the supply voltage to perform the Program/Erase algorithms.

9.26.2 Features

Programming and erase over the full operating voltage range.
Byte-erase allowing code memory to be used for data storage.
Read/Programming/Erase using ICP .
Any ﬂash program/erase operation in 2 ms.
Programming with industry-standard commercial programmers.
Programmable security for the code in the Flash for each sector.
More than 100,000 minimum erase/program cycles for each byte.
10-year minimum data retention.

9.26.3 Flash organization

The P89LPC912/913/914 program memory consists of four 256 byte sectors. Each sector can be further divided into 16-byte pages. In addition to sector erase, page erase, and byte erase, a 16-byte page register is included which allows from 1 to 16 bytes of a given page to be programmed at the same time, substantially reducing overall programming time. In addition, erasing and reprogramming of user-programmable conﬁguration bytes including UCFG1, the Boot Status Bit, and the Boot Vector is supported.

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 47 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

9.26.4 Flash programming and erasing

Different methods of erasing or programming of the Flash are available. The Flash may be programmed or erased in the end-user application (IAP-Lite) under control of the application’s ﬁrmware. Another option is to use the In-Circuit Programming (ICP) mechanism. This ICP system provides for programming through a serial clock- serial data interface using a commercially available EPROM programmer which supports this device. This device does not provide for direct veriﬁcation of code memory contents. Instead this device provides a 32-bit CRC result on either a sector or the entire 1 kB of user code space.

9.26.5 In-circuit programming (ICP)

In-Circuit Programming is performed without removing the microcontroller from the system. The In-Circuit Programming facility consists of internal hardware resources to facilitate remote programming of the P89LPC912/913/914 through a two-wire serial interface. The Philips In-Circuit Programming facility has made in-circuit programming in an embedded application, using commercially available programmers, possible with a minimum of additional expense in components and circuit board area. The ICP function uses ﬁve pins. Only a small connector (with V DD , VSS ,RST, clock, and data signals) needs to be available to interface your application to a commercial programmer in order to use this feature. Additional details may be found in the P89LPC912/913/914 User’s Manual.

9.26.6 In-application programming (IAP-Lite)

In-Application Programming is performed in the application under the control of the microcontroller’s ﬁrmware. The IAP-Lite facility consists of internal hardware resources to facilitate programming and erasing. The Philips In-Application Programming Lite has made in-application programming in an embedded application possible without additional components. This is accomplished through the use of four SFRs consisting of a control/status register, a data register, and two address registers. Additional details may be found in the P89LPC912/913/914 User’s Manual.

9.26.7 Using ﬂash as data storage

The Flash code memory array of this device supportsindividual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the sector containing the byte has not been secured (a MOVC instruction is not allowed to read code memory contents of a secured sector). Thus any byte in a non-secured sector may be used for non-volatile data storage.

9.26.8 User conﬁguration bytes

Some user-conﬁgurable features of the P89LPC912/913/914 must be deﬁned at power-up and therefore cannot be set by the program after start of execution. These features are conﬁgured through the use of the Flash byte UCFG1. Please see the P89LPC912/913/914 User’s Manual for additional details.

9.26.9 User sector security bytes

There are four User Sector Security Bytes, each corresponding to one sector. Please see theP89LPC912/913/914 User’s Manual for additional details.

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 48 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 10. Limiting values [1] The following applies to Limiting values: a) Stresses above those listed underTable 12 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described inTable 13 “DC electrical characteristics”,T a b l e1 4“ A C characteristics”and Table 15 “AC characteristics (P89LPC912, P89LPC913)” of this speciﬁcation are not implied. b) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. c) Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to VSS unless otherwise noted. Table 12: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit Tamb(bias) operating bias ambient temperature −55 +125 °C Tstg storage temperature range −65 +150 °C Vxtal voltage on XTAL1, XTAL2 pin to VSS , as applicable -V DD + 0.5 V Vn voltage on any other pin (except XTAL1, XTAL2) to VSS −0.5 +5.5 V IOH(I/O) HIGH-level output current per I/O pin - 8 mA IOL(I/O) LOW-level output current per I/O pin - 20 mA II/O(tot)(max)maximum total I/O current - 120 mA Ptot(pack) total power dissipation per package based on package heat transfer, not device power consumption - 1.5 W

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 49 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 11. Static characteristics Table 13: DC electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise speciﬁed. Tamb = −40 °Ct o+ 8 5°C for industrial, unless otherwise speciﬁed. Symbol Parameter Conditions Min Typ[1] Max Unit IDD(oper) power supply current, operating (P89LPC912, P89LPC913)

3.6 V; 12 MHz

[2] - 7 13 mA

3.6 V; 18 MHz [2] -1 1 1 6 m A

IDD(idle) power supply current, Idle mode (P89LPC912, P89LPC913) [2] - 1.5 5.6 mA

3.6 V; 18 MHz [2] -4 6 m A

IDD(oper) power supply current, operating (P89LPC914) 3.6 V; 7.373 MHz [3] -4 8 m A IDD(idle) power supply current, Idle mode (P89LPC914) 3.6 V; 7.373 MHz [3] -1 3 m A IDD(PD) Power supply current, Power-down mode, voltage comparators powered-down 3.6 V [2][3]-- 7 0 µA IDD(TPD) Power supply current, Total Power-down mode (dVDD /dt)r VDD rise rate - - 2 mV/ µs (dVDD /dt)f VDD fall rate - - 50 mV/ µs VRAM RAM keep-alive voltage 1.5 - - V Vth(HL) negative-going threshold voltage (Schmitt input) 0.22VDD 0.4VDD -V Vth(LH) positive-going threshold voltage (Schmitt input) - 0.6V DD 0.7VDD V Vhys hysteresis voltage - 0.2V DD -V VOL LOW-level output voltage, all ports IOL = 20 mA - 0.6 1.0 V IOL = 10 mA - 0.3 0.5 V IOL = 3.2 mA - 0.2 0.3 V VOH HIGH-level output voltage, all ports IOH = −8 mA; push-pull mode VDD − 1.0 - - V IOH = −3.2 mA; push-pull mode VDD − 0.7 V DD − 0.4 - V IOH = −20 µA; quasi-bidirectional mode VDD − 0.3 V DD − 0.2 - V C ig input/output pin capacitance [4] - - 15 pF IIL logical 0 input current, all ports ILI input leakage current, all ports VIN =V ILor VIH [6] -- ±10 µA ITL logical 1-to-0 transition current, all ports VIN = 2.0 V at VDD = 3.6 V R RST internal reset pull-up resistor 10 - 30 k Ω

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 50 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. [1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V. [2] The IDD(oper), IDD(PD) speciﬁcations are measured using an external clock with the following functions disabled: comparators, brownout detect, and watchdog timer (P89LPC912, P89LPC913). [3] The IDD(oper), IDD(PD) speciﬁcations are measured with the following functions disabled: comparators, brownout detect, and watchdog timer (P89LPC914). [4] Pin capacitance is characterized but not tested. [5] Measured with port in quasi-bidirectional mode. [6] Measured with port in high-impedance mode. [7] Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups) [8] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from ‘1’ to ‘0’. This current is highest when V IN is approximately 2 V. VBO brownout trip voltage with BOV = ‘1’, BOPD = ‘0’ 2.4 V < VDD < 3.6 V 2.40 - 2.70 V VREF bandgap reference voltage 1.11 1.23 1.34 V TC (VREF) bandgap temperature coefﬁcient - 10 20 ppm/ Table 13: DC electrical characteristics…continued VDD = 2.4 V to 3.6 V, unless otherwise speciﬁed. Tamb = −40 °Ct o+ 8 5°C for industrial, unless otherwise speciﬁed. Symbol Parameter Conditions Min Typ[1] Max Unit

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 51 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 12. Dynamic characteristics Table 14: AC characteristics VDD = 2.4 V to 3.6 V, unless otherwise speciﬁed. Tamb = −40 °Ct o+ 8 5°C for industrial, unless otherwise speciﬁed.[1] Symbol Parameter Conditions Variable clock fosc =1 2M H z Unit Min Max Min Max fRCOSC internal RC oscillator frequency (nominal f = 7.3728 MHz) trimmed to±1 % at T amb =2 5°C 7.189 7.557 7.189 7.557 MHz fWDOSC internal Watchdog oscillator frequency (nominal f = 400 kHz) 320 520 320 520 kHz Crystal oscillator (P89LPC912, P89LPC913) fosc oscillator frequency 0 12 - - MHz tCLCL clock cycle see Figure 29 8 3 - --n s fCLKP CLKLP active frequency 0 8 - - MHz Glitch ﬁlter glitch rejection, P1.5/RST pin - 50 - 50 ns signal acceptance, P1.5/RST pin 125 - 125 - ns glitch rejection, any pin except P1.5/RST - 15 - 15 ns signal acceptance, any pin except P1.5/RST 50 - 50 - ns External clock (P89LPC912, P89LPC913) tCHCX HIGH time see Figure 29 33 t CLCL − tCLCX 33 - ns tCLCX LOW time see Figure 29 33 t CLCL − tCHCX 33 - ns tCLCH rise time see Figure 29 -8 - 8 n s tCHCL fall time see Figure 29 -8 - 8 n s Shift register (UART mode 0 - P89LPC913, P89LPC914) t XLXL serial port clock cycle time see Figure 28 16 tCLCL - 1333 - ns tQVXH output data set-up to clock rising edge see Figure 28 13 tCLCL - 1083 - ns tXHQX output data hold after clock rising edge see Figure 28 -t CLCL + 20 - 103 ns tXHDX input data hold after clock rising edge see Figure 28 -0 - 0 n s tDVXH input data valid to clock rising edge seeFigure 28 150 - 150 - ns

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 52 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. SPI interface fSPI Operating frequency 2.0 MHz (Slave) 0 CCLK ⁄6 0 2.0 MHz

3.0 MHz (Master) - CCLK ⁄4 - - MHz

tSPICYC Cycle time see Figure 24, 25,26,27

2.0 MHz (Slave) 6⁄CCLK - 500 - ns

3.0 MHz (Master) 4⁄CCLK - --n s

tSPILEAD Enable lead time (Slave) see Figure 26,

2.0 MHz 250 - 250 - ns

tSPILAG Enable lag time (Slave) see Figure 26, tSPICLKH SPICLK high time see Figure 24, 25,26,27 Master 2⁄CCLK - 340 - ns Slave 3⁄CCLK - 190 - ns tSPICLKL SPICLK low time see Figure 24, 25,26,27 Master 2⁄CCLK - 340 - ns Slave 3⁄CCLK - 190 - ns tSPIDSU Data set-up time (Master or Slave) seeFigure 24, 25,26,27 100 - 100 - ns tSPIDH Data hold time (Master or Slave) seeFigure 24, 25,26,27 100 - 100 - ns tSPIA Access time (Slave) see Figure 26, 0 120 0 120 ns tSPIDIS Disable time (Slave) see Figure 26,

2.0 MHz 0 240 - 240 ns

tSPIDV Enable to output data valid see Figure 24, 25,26,27

3.0 MHz 0 167 - 167 ns

t SPIOH Output data hold time see Figure 24, 25,26,27 0- 0 - n s Table 14: AC characteristics…continued VDD = 2.4 V to 3.6 V, unless otherwise speciﬁed. Tamb = −40 °Ct o+ 8 5°C for industrial, unless otherwise speciﬁed.[1] Symbol Parameter Conditions Variable clock fosc =1 2M H z Unit Min Max Min Max

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 53 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. [1] Parameters are valid over operating temperature range unless otherwise speciﬁed. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. tSPIR Rise time see Figure 24, 25,26,27 SPI outputs (SPICLK, MOSI, MISO) - 100 - 100 ns SPI inputs (SPICLK, MOSI, MISO, SS) - 2000 - 2000 ns tSPIF Fall time see Figure 24, 25,26,27 SPI outputs (SPICLK, MOSI, MISO) - 100 - 100 ns SPI inputs (SPICLK, MOSI, MISO, SS) - 2000 - 2000 ns Table 14: AC characteristics…continued VDD = 2.4 V to 3.6 V, unless otherwise speciﬁed. Tamb = −40 °Ct o+ 8 5°C for industrial, unless otherwise speciﬁed.[1] Symbol Parameter Conditions Variable clock fosc =1 2M H z Unit Min Max Min Max

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 54 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Table 15: AC characteristics (P89LPC912, P89LPC913) VDD = 3.0 V to 3.6 V, unless otherwise speciﬁed. Tamb = −40 °Ct o+ 8 5°C for industrial, unless otherwise speciﬁed.[1] Symbol Parameter Conditions Variable clock fosc =1 8M H z Unit Min Max Min Max fRCOSC internal RC oscillator frequency (nominal f = 7.3728 MHz) trimmed to±1 % at T amb =2 5°C 7.189 7.557 7.189 7.557 MHz fWDOSC internal Watchdog oscillator frequency (nominal f = 400 kHz) 320 520 320 520 kHz Crystal oscillator fosc oscillator frequency [2] 0 18 - - MHz tCLCL clock cycle see Figure 29 5 5 - --n s fCLKP CLKLP active frequency 0 8 - - MHz Glitch ﬁlter glitch rejection, P1.5/RST pin - 50 - 50 ns signal acceptance, P1.5/RST pin 125 - 125 - ns glitch rejection, any pin except P1.5/RST - 15 - 15 ns signal acceptance, any pin except P1.5/RST 50 - 50 - ns External clock tCHCX HIGH time see Figure 29 22 t CLCL − tCLCX 22 - ns tCLCX LOW time see Figure 29 22 t CLCL − tCHCX 22 - ns tCLCH rise time see Figure 29 -5 - 5 n s tCHCL fall time see Figure 29 -5 - 5 n s SPI interface f SPI Operating frequency

3.0 MHz (Slave) 0 CCLK ⁄6 0 3 MHz

4.5 MHz (Master) - CCLK ⁄4 - 4.5 MHz tSPICYC Cycle time see Figure 24, 25,26,27

3.0 MHz (Slave) 6⁄CCLK - 333 - ns

4.5 MHz (Master) 4⁄CCLK - 222 - ns

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 55 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. tSPILEAD Enable lead time (Slave) see Figure 26,

3.0 MHz 250 - 250 - ns

tSPILAG Enable lag time (Slave) see Figure 26, tSPICLKH SPICLK high time see Figure 24, 25,26,27 Master 2⁄CCLK - 111 - ns Slave 3⁄CCLK - 167 - ns tSPICLKL SPICLK low time see Figure 24, 25,26,27 Master 2⁄CCLK - 111 - ns Slave 3⁄CCLK - 167 - ns tSPIDSU Data set-up time (Master or Slave) seeFigure 24, 25,26,27 100 - 100 - ns tSPIDH Data hold time (Master or Slave) seeFigure 24, 25,26,27 100 - 100 - ns tSPIA Access time (Slave) see Figure 26, 0 80 0 80 ns tSPIDIS Disable time (Slave) see Figure 26,

3.0 MHz 0 160 - 160 ns

tSPIDV Enable to output data valid see Figure 24, 25,26,27

4.5 MHz 0 111 - 111 ns

t SPIOH Output data hold time see Figure 24, 25,26,27 0- 0 - n s tSPIR Rise time see Figure 24, 25,26,27 SPI outputs (SPICLK, MOSI, MISO) - 100 - 100 ns SPI inputs (SPICLK, MOSI, MISO, SS) - 2000 - 2000 ns Table 15: AC characteristics (P89LPC912, P89LPC913)…continued VDD = 3.0 V to 3.6 V, unless otherwise speciﬁed. Tamb = −40 °Ct o+ 8 5°C for industrial, unless otherwise speciﬁed.[1] Symbol Parameter Conditions Variable clock fosc =1 8M H z Unit Min Max Min Max

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 56 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. [1] Parameters are valid over operating temperature range unless otherwise speciﬁed. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. [2] When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its speciﬁed level. When system power is removed VDD will fall below the minimum speciﬁed operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V DD falls below the minimum speciﬁed operating voltage. tSPIF Fall time see Figure 24, 25,26,27 SPI outputs (SPICLK, MOSI, MISO) - 100 - 100 ns SPI inputs (SPICLK, MOSI, MISO, SS) - 2000 - 2000 ns Table 15: AC characteristics (P89LPC912, P89LPC913)…continued VDD = 3.0 V to 3.6 V, unless otherwise speciﬁed. Tamb = −40 °Ct o+ 8 5°C for industrial, unless otherwise speciﬁed.[1] Symbol Parameter Conditions Variable clock fosc =1 8M H z Unit Min Max Min Max Fig 24. SPI master timing (CPHA = 0). tCLCL tSPICLKH tSPICLKL Master LSB/MSB outMaster MSB/LSB out tSPIDHtSPIDSU tSPICLKL tSPICLKH tSPIF tSPIOH tSPIDV tSPIRtSPIDV tSPIF tSPIF tSPIR tSPIR SS SPICLK (CPOL = 0) (output) 002aaa156 SPICLK (CPOL = 1) (output) MISO (input) MOSI (output) LSB/MSB inMSB/LSB in

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 57 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Fig 25. SPI master timing (CPHA = 1). tCLCL tSPICLKL tSPICLKH Master LSB/MSB outMaster MSB/LSB out tSPIDHtSPIDSU tSPICLKH tSPICLKL tSPIF tSPIOH tSPIDV tSPIDV tSPIR tSPIDV tSPIF tSPIRtSPIF tSPIR SS SPICLK (CPOL = 0) (output) 002aaa157 SPICLK (CPOL = 1) (output) MISO (input) MOSI (output) LSB/MSB inMSB/LSB in Fig 26. SPI slave timing (CPHA = 0). tCLCL tSPICLKH tSPICLKL tSPILEAD tSPICLKH tSPICLKL tSPILAG tSPIDSU tSPIDH tSPIDHtSPIDSU tSPIDSU tSPIR tSPIA tSPIOH tSPIOH tSPIDIS tSPIR Slave MSB/LSB out MSB/LSB in LSB/MSB in Slave LSB/MSB out tSPIDV tSPIOH tSPIDV tSPIRtSPIF tSPIRtSPIF SS SPICLK (CPOL = 0) (input) 002aaa158 SPICLK (CPOL = 1) (input) MISO (output) MOSI (input) Not defined

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 58 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Fig 27. SPI slave timing (CPHA = 1). tCLCL tSPICLKH tSPICLKL tSPILEAD tSPICLKH tSPICLKL tSPILAG tSPIDSU tSPIDH tSPIDHtSPIDSU tSPIR tSPIA tSPIOH tSPIDIS tSPIR Slave MSB/LSB outNot defined MSB/LSB in LSB/MSB in Slave LSB/MSB out tSPIDV tSPIOH tSPIDV tSPIOH tSPIDV tSPIRtSPIF tSPIRtSPIF SS SPICLK (CPOL = 0) (input) 002aaa159 SPICLK (CPOL = 1) (input) MISO (output) MOSI (input) tSPIDSU Fig 28. Shift register mode timing. 0 1 23 456 7 Valid Valid Valid Valid Valid Valid Valid Valid tXLXL 002aaa425 Set TI Set RI tXHQXtQVXH tXHDV tXHDX Clock Output Data Write to SBUF Input Data Clear RI Fig 29. External clock timing. tCHCL tCLCX tCHCX tC tCLCH 002aaa416 0.2 VDD + 0.9 0.2 VDD - 0.1 V VDD - 0.5 V 0.45 V

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 59 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 13. Comparator electrical characteristics [1] This parameter is characterized, but not tested in production. Table 16: Comparator electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise speciﬁed. Tamb = −40 °Ct o+ 8 5°C for industrial, unless otherwise speciﬁed. Symbol Parameter Conditions Min Typ Max Unit VIO offset voltage comparator inputs - - ±20 mV VCR common mode range comparator inputs 0 - V DD − 0.3 V CMRR common mode rejection ratio [1] -- −50 dB response time - 250 500 ns comparator enable to output valid - - 10 µs I IL input leakage current, comparator 0 < VIN <V DD -- ±10 µA

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 60 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 14. Package outline Fig 30. TSSOP14 package outline (SOT402-1). UNIT A 1 A 2 A 3 bp cD (1) E (2) (1)eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 o o0.13 0.10.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT402-1 MO-153 99-12-27 03-02-18 w M bp D Z e 0.25 14 8 q AA 1 A 2 Lp Q detail X L (A )3 H E E c v M A XA y 0 2.5 5 mm scale TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 A max. 1.1 pin 1 index

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 61 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 15. Revision history Table 17: Revision history Rev Date CPCN Description 03 20041217 - Product data (9397 750 14468) Modiﬁcation:

Added 18 MHz information. 02 20031212 - Product data (9397 750 12286); ECN 01-A14930 dated 10 December 2003. 01 20030711 - Objective data (9397 750 11537)

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 — 17 December 2004 62 of 63 Contact information For additional information, please visithttp://www.semiconductors.philips.com. 16. Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17. Deﬁnitions Short-form speciﬁcation —The data in a short-form speciﬁcation is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values deﬁnition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. 18. Disclaimers Life support —These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes —Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speciﬁed. Level Data sheet status[1] Product status[2][3] Deﬁnition I Objective data Development This data sheet contains data from the objective speciﬁcation for product development. Philips Semiconductors reserves the right to change the speciﬁcation in any manner without notice. II Preliminary data Qualiﬁcation This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

© Koninklijke Philips Electronics N.V. 2004. Printed in the U.S.A. All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 17 December 2004 Document order number: 9397 750 14468

Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core

9.2.3 Low speed oscillator option (P89LPC912,

9.2.4 Medium speed oscillator option

9.2.5 High speed oscillator option (P89LPC912,

9.5 External clock input option (P89LPC912,

9.7 CPU Clock (CCLK) modiﬁcation: DIVM register . . . 29

9.15.6 Timer overﬂow toggle output (P89LPC912,

9.17.9 Transmit interrupts with double buffering

th bit (bit 8) in double buffering (Modes 1, 2 and

Product Information

P89LPC914FDH specifications and overview.

Summary

8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM Rev. 03-17 December 2004

Description

8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM Rev. 03-17 December 2004

Source title P89LPC914FDH Datasheet(PDF) - NXP Semiconductors

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