P89C60X2BN/00

P89C60X2 PHILIPS | Alldatasheet

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Technical content

/C0080 /C0115 /C0111/C0110/C0111 /C0115 P89C60X2/61X2 80C51 8-bit Flash microcontroller family 64KB Flash 512B/1024B RAM Product data Supersedes data of 2002 Jul 23

2003 Sep 11

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

22003 Sep 11 853-2400 30250

DESCRIPTION

The Philips microcontrollers described in this data sheet are high-performance static 80C51 designs. They are manufactured in an advanced CMOS process and contain a non-volatile Flash program memory that is programmable in parallel (via a parallel programmer) or In-System Programmable (ISP) via boot loader. They support both 12-clock and 6-clock operation. The P89C60X2 and P89C61X2 contain 512 bytes RAM and 1024 bytes RAM respectively, 32 I/O lines, three 16-bit counter/timers, a six-source, four-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits. In addition, the devices are static designs which offer a wide range of operating frequencies down to zero. Two software selectable modes of power reduction — idle mode and power-down mode — are available. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. Since the design is static, the clock can be stopped without loss of user data. Then the execution can be resumed from the point the clock was stopped. SELECTION TABLE For applications requiring more RAM, as well as more on-chip peripherals, see the P89C66x and P89C51Rx2 data sheets. Type Memory Timers Serial Interfaces RAM ROM OTP Flash # of Timers PWM PCA WD UART I2C CAN SPI ADC bits/ch. I/O Pins Interrupts (External) Program Security Default Clock Rate Optional Clock Rate Max. Freq. at 6-clk / 12-clk (MHz) Freq. Range at 3V (MHz) Freq. Range at 5V (MHz) P89C60X2 512B – – 64K 3 – – /C0110/C0110– – – – 32 6 (2) /C011012–clk 6-clk 20/33 – 0–20/33 P89C61X2 1024B – – 64K 3 – – /C0110/C0110– – – – 32 6 (2) /C011012–clk 6-clk 20/33 – 0–20/33 NOTE: 1. I2C = Inter-Integrated Circuit Bus; CAN = Controller Area Network; SPI = Serial Peripheral Interface; PCA = Programmable Counter Array; ADC = Analog-to-Digital Converter; PWM = Pulse Width Modulation

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 3

FEATURES

• 80C51 Central Processing Unit – 64 kbytes Flash – 512 bytes RAM (P89C60X2) – 1024 bytes RAM (P89C61X2) – Boolean processor – Fully static operation
• In-System Programmable (ISP) Flash memory
• 12-clock operation with selectable 6-clock operation (via software or via parallel programmer)
• Memory addressing capability – Up to 64 kbytes ROM and 64 kbytes RAM
• Power control modes: – Clock can be stopped and resumed – Idle mode – Power-down mode
• Two speed ranges – 0 to 20 MHz with 6-clock operation – 0 to 33 MHz with 12-clock operation
• LQFP, PLCC, and DIP packages
• Dual Data Pointers
• Three security bits
• Four interrupt priority levels
• Six interrupt sources
• Four 8-bit I/O ports
• Full-duplex enhanced UART – Framing error detection – Automatic address recognition
• Three 16-bit timers/counters T0, T1 (standard 80C51) and additional T2 (capture and compare)
• Programmable clock-out pin
• Watchdog timer
• Asynchronous port reset
• Low EMI (inhibit ALE, 6-clock mode)
• Wake-up from Power Down by an external interrupt

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 4

P89C60X2 ORDERING INFORMATION Type number Package Temperature R( °C)Name Description Version Range (°C) P89C60X2BA/00 PLCC44 plastic leaded chip carrier; 44 leads SOT187-2 0 to +70 P89C60X2BN/00 DIP40 plastic dual in-line package; 40 leads SOT129-1 0 to +70 P89C60X2BBD/00 LQFP44 plastic low profile quad flat package; 44 leads SOT389-1 0 to +70 P89C61X2 ORDERING INFORMATION Type number Package Temperature R( °C)Name Description Version Range (°C) ÁÁÁÁÁÁ P89C61X2BA/00 ÁÁÁÁÁ PLCC44 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ plastic lead chip carrier; 44 leads ÁÁÁÁÁ SOT187-2 ÁÁÁÁÁ 0 to +70 P89C61X2BN/00 DIP40 plastic dual in-line package; 40 leads SOT129-1 0 to +70 P89C61X2BBD/00 LQFP44 plastic low profile quad flat package; 44 leads SOT389-1 0 to +70 PART NUMBER DERIVATION Memory Temperature Range Package P89C60X2 9 = Flash 0 = 512 bytes RAM 64 kbytes FLASH 1= 1024 bytes RAM 64 kbytes FLASH X2 = 6-clock mode available B = 0 °C to +70 °C A = PLCC BD = LQFP The following table illustrates the correlation between operating mode, power supply and maximum external clock frequency: Operating Mode Power Supply Maximum Clock Frequency 6-clock 5 V ± 10% 20 MHz 12-clock 5 V ± 10% 33 MHz

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 5

(12-CLK MODE, 6-CLK MODE)

64 KBYTE

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 6

BLOCK DIAGRAM 2 (CPU-ORIENTED) SU01671 PSEN EA / VPP ALE/PROG RST XTAL1 XTAL2 VCC VSS PORT 0 DRIVERS PORT 2 DRIVERS RAM ADDR REGISTER RAM PORT 0 LATCH PORT 2 LATCH FLASH REGISTER B ACC STACK POINTER TMP2 TMP1 ALU TIMING AND CONTROL INSTRUCTION REGISTER PD OSCILLATOR PSW PORT 1 LATCH PORT 3 LATCH PORT 1 DRIVERS PORT 3 DRIVERS PROGRAM ADDRESS REGISTER BUFFER PC INCRE- MENTER PROGRAM COUNTER DPTR’S MULTIPLE SFRs TIMERS 8 16

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 7

PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS SU01062 PLCC 614 0 18 28 Pin Function

1 NIC*

2 P1.0/T2 3 P1.1/T2EX 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1.6 9 P1.7

10 RST

11 P3.0/RxD

12 NIC*

13 P3.1/TxD 14 P3.2/INT0 15 P3.3/INT1 Pin Function 16 P3.4/T0 17 P3.5/T1 18 P3.6/WR 19 P3.7/RD

20 XTAL2

21 XTAL1

23 NIC*

24 P2.0/A8 25 P2.1/A9 26 P2.2/A10 27 P2.3/A11 28 P2.4/A12 29 P2.5/A13 30 P2.6/A14 Pin Function 31 P2.7/A15

32 PSEN

33 ALE

34 NIC*

/VPP 36 P0.7/AD7 37 P0.6/AD6 38 P0.5/AD5 39 P0.4/AD4 40 P0.3/AD3 41 P0.2/AD2 42 P0.1/AD1 43 P0.0/AD0 44 V CC * NO INTERNAL CONNECTION LOW PROFILE QUAD FLAT PACK PIN FUNCTIONS SU01487 LQFP 44 34 12 22 Pin Function 1 P1.5 2 P1.6 3 P1.7

4 RST

5 P3.0/RxD

6 NIC*

7 P3.1/TxD 8 P3.2/INT0 9 P3.3/INT1 10 P3.4/T0 11 P3.5/T1 12 P3.6/WR 13 P3.7/RD

14 XTAL2

15 XTAL1

16 V SS

17 NIC*

18 P2.0/A8 19 P2.1/A9 20 P2.2/A10 21 P2.3/A11 22 P2.4/A12 23 P2.5/A13 24 P2.6/A14 25 P2.7/A15

26 PSEN

27 ALE

28 NIC*

/VPP 30 P0.7/AD7 Pin Function 31 P0.6/AD6 32 P0.5/AD5 33 P0.4/AD4 34 P0.3/AD3 35 P0.2/AD2 36 P0.1/AD1 37 P0.0/AD0 38 V CC

39 NIC*

40 P1.0/T2 41 P1.1/T2EX 42 P1.2 43 P1.3 44 P1.4 * NO INTERNAL CONNECTION PLASTIC DUAL IN-LINE PACKAGE PIN FUNCTIONS 20 21 40T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 P1.7 WR /P3.6 RD /P3.7 XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG EA /VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 V CC DUAL IN-LINE PACKAGE SU01780

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 8

MNEMONIC PLCC DIP LQFP TYPE NAME AND FUNCTION VSS 22 20 16 I Ground: 0 V reference. VCC 44 40 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0-0.7 43–36 39–32 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification and received code bytes during Flash programming. External pull-ups are required during program verification. 1–3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Port 1 also receives the low-order address byte during program memory verification. Alternate functions for Port 1 include: 2 1 40 I/O T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable Clock-Out) 3 2 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control P2.0–P2.7 24–31 21–28 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Some Port 2 pins receive the high order address bits during Flash programming and verification. P3.0–P3.7 11, 13–19 10–17 5, 7–13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: I IL). Port 3 also serves the special features of the 80C51 family, as listed below: 11 10 5 I RxD (P3.0): Serial input port 13 11 7 O TxD (P3.1): Serial output port 14 12 8 I INT0 (P3.2): External interrupt 15 13 9 I INT1 (P3.3): External interrupt 16 14 10 I T0 (P3.4): Timer 0 external input 17 15 11 I T1 (P3.5): Timer 1 external input 18 16 12 O WR (P3.6): External data memory write strobe 19 17 13 O RD (P3.7): External data memory read strobe RST 10 9 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC . ALE/PROG 33 30 27 O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (12-clk) or 1/3 (6-clk Mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG ) during Flash programming. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. PSEN 32 29 26 O Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA /VPP 35 31 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH. If EA is held high, the device executes from internal program memory. This pin also receives the 5 V / 12 V programming supply voltage PP) during Flash programming. If security bit 1 is programmed, EA will be internally latched on Reset.

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 9

MNEMONIC NAME AND FUNCTION TYPELQFPDIPPLCC XTAL1 21 19 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 20 18 14 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5 V or VSS – 0.5 V, respectively.

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 10

SPECIAL FUNCTION REGISTERS (see notes on next page) SYMBOL DESCRIPTION DIRECT ADDRESS BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB RESET VALUE ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H AUXR# Auxiliary 8EH – – – – – – EXTRAM AO xxxxxx00B AUXR1# Auxiliary 1 A2H – – – – GF2 0 – DPS xxx000x0B B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H CKCON Clock Control Register 8FH – WDX2 – – – – – X2 x0xxxxx0B DPTR: Data Pointer (2 bytes) DPH Data Pointer High 83H 00H DPL Data Pointer Low 82H 00H AF AE AD AC AB AA A9 A8 IE* Interrupt Enable A8H EA – ET2 ES ET1 EX1 ET0 EX0 0x000000B BF BE BD BC BB BA B9 B8 IP* Interrupt Priority B8H – – PT2 PS PT1 PX1 PT0 PX0 xx000000B IPH# Interrupt Priority HighB7H – – PT2H PSH PT1H PX1H PT0H PX0H xx000000B 87 86 85 84 83 82 81 80 P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FFH 97 96 95 94 93 92 91 90 P1* Port 1 90H – – – – – – T2EX T2 FFH A7 A6 A5 A4 A3 A2 A1 A0 P2* Port 2 A0H AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 FFH B7 B6 B5 B4 B3 B2 B1 B0 P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TxD RxD FFH PCON# 1 Power Control 87H SMOD1 SMOD0 – POF GF1 GF0 PD IDL 00xx0000B D7 D6 D5 D4 D3 D2 D1 D0 PSW* Program Status Word D0H CY AC F0 RS1 RS0 OV – P 000000x0B RACAP2H# Timer 2 Capture High CBH 00H RACAP2L# Timer 2 Capture Low CAH 00H SADDR# Slave Address A9H 00H SADEN# Slave Address Mask B9H 00H SBUF Serial Data Buffer 99H xxxxxxxxB 9F 9E 9D 9C 9B 9A 99 98 SCON* Serial Control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00H SP Stack Pointer 81H 07H 8F 8E 8D 8C 8B 8A 89 88 TCON* Timer Control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H CF CE CD CC CB CA C9 C8 T2CON* Timer 2 Control C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL 2 00H T2MOD# Timer 2 Mode Control C9H – – – – – – T2OE DCEN xxxxxx00B TH0 Timer High 0 8CH 00H TH1 Timer High 1 8DH 00H TH2# Timer High 2 CDH 00H TL0 Timer Low 0 8AH 00H TL1 Timer Low 1 8BH 00H TL2# Timer Low 2 CCH 00H TMOD Timer Mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H WDTRST Watchdog Timer Reset A6H

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 11

NOTES: Special Function Registers (SFRs) accesses are restricted in the following ways: 1. Do not attempt to access any SFR locations not defined. 2. Accesses to any defined SFR locations must be strictly for the functions for the SFRs. 3. SFR bits labeled ‘–’, ‘0’ or ‘1’ can ONLY be written and read as follows: ‘–’ MUST be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives. ‘0’ MUST be written with ‘0’, and will return a ‘0’ when read. ‘1’ MUST be written with ‘1’, and will return a ‘1’ when read. *: SFRs are bit addressable. #: SFRs are modified from or added to the 80C51 SFRs. –: Reserved bits (see note above). 1: Reset value depends on reset source.

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 12

The P89C60X2/61X2 Flash memory augments EPROM functionality with in-circuit electrical erasure and programming. The Flash can be read and written as bytes. The Chip Erase operation will erase the entire program memory. The Block Erase function can erase any Flash block. In-system programming (ISP) and standard parallel programming are both available. On-chip erase and write timing generation contribute to a user friendly programming interface. The P89C60X2/61X2 Flash reliably stores memory contents even after 10,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The P89C60X2/61X2 uses a +5 V V PP supply to perform the Program/Erase algorithms (12 V tolerant).

• Flash EPROM internal program memory with Block Erase.
• Internal 1-kbyte fixed BootROM, containing low-level in-system programming routines and a default serial loader.
• Loader in BootROM allows in-system programming via the serial port.
• Up to 64 kbytes external program memory if the internal program memory is disabled (EA = 0).
• Programming and erase voltage +5 V (+12 V tolerant).
• Read/Programming/Erase using ISP: – Byte Programming (8 /C0109s). – Typical erase times: Block Erase (4 kbytes) in 3 seconds. Full-chip erase in 15 seconds.
• Parallel programming with 87C51 compatible hardware interface to programmer.
• Programmable security for the code in the Flash.
• 10,000 minimum erase/program cycles for each byte.
• 10-year minimum data retention. FLASH PROGRAMMING AND ERASURE There are two methods of erasing or programming of the Flash memory that may be used. First, the on-chip ISP boot loader may be invoked. Second, the Flash may be programmed or erased using parallel method by using a commercially available EPROM programmer. The parallel programming method used by these devices is similar to that used by EPROM 87C51, but it is not identical, and the commercially available programmer will need to have support for these devices. FLASH MEMORY CHARACTERISTICS Flash User Code Memory Organization The P89C60X2/61X2 contains 64 kbytes Flash user code program memory organized into 4-kbyte blocks (see Figure 1). Boot ROM When the microcontroller programs its Flash memory during ISP, all of the low level details are handled by code that is contained in a 1 kbyte BootROM. BootROM operations include: erase block, program byte, verify byte, program security bit, etc. Clock Mode The clock mode feature sets operating frequency to be 1/12 or 1/6 of the oscillator frequency. The clock mode configuration bit, FX2, is located in the Security Block (See Table 1). FX2, when programmed, will override the SFR clock mode bit (X2) in the CKCON register. If FX2 is erased, then the SFR bit (X2) may be used to select between 6-clock and 12-clock mode.

2003 Sep 11 13

1. Default clock mode after ChipErase is set to 12-clock.

Figure 1. Flash Memory Configuration loader is invoked. The factory default for the Status Byte is FFh. by a full-chip erase operation when using ISP.

2003 Sep 11 14

Figure 2. In-System Programming with a Minimum of Pins of additional expense in components and circuit board area. your application to an external circuit in order to use this feature. allowed to exceed datasheet limits.

1. Direct your browser to the following page:
2. Execute “flashmagic.exe” to install the software

provides auto-echo of received characters. be added to indicate either commands or data for the ISP facility. (decimal). ISP commands are summarized in Table 2. P89C60X2/61X2 before programming data. timing. Record type 02 is provided for this purpose.

2003 Sep 11 15

Table 2. Intel-Hex Records Used by In-System Programming

00 Program Data

01 End of File (EOF), no operation

03 Miscellaneous Write Functions

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 16

RECORD TYPE COMMAND/DATA FUNCTION 03 (cont.) Subfunction Code = 07 (Full Chip Erase) Erases all blocks, security bits, and sets status byte to default values ff = 07 ss = don’t care dd = don’t care Example: :0100000307F5 full chip erase Subfunction Code = 0C (Erase 4k blocks) ff = 0C ss = block code as shown below: block 0, 0k ~ 4k, 00H block 1, 4k ~ 8k, 10H block 2, 8k ~ 12k, 20H block 3, 12k ~ 16k, 30H block 4, 16k ~ 20k, 40H block 5, 20k ~ 24k, 50H block 6, 24k ~ 28k, 60H block 7, 28k ~ 32k, 70H block 8, 32k ~ 36k, 80H block 9, 36k ~ 40k, 90H block 10, 40k ~ 44k, A0H block 11, 44k ~ 48k, B0H block 12, 48k ~ 52k, C0H block 13, 52k ~ 56k, D0H block 14, 56k ~ 60k, E0H block 15, 60k ~ 64k, F0H Example: :020000030C20CF erase 4k block 2 04 Display Device Data or Blank Check – Record type 04 causes the contents of the entire Flash array to be sent out the serial port in a formatted display. This display consists of an address and the contents of 16 bytes starting with that address. No display of the device contents will occur if security bit 2 has been programmed. Data to the serial port is initiated by the reception of any character and terminated by the reception of any character. General Format of Function 04 :05xxxx04sssseeeeffcc Where: 05 = number of bytes (hex) in record xxxx = required field, but value is a “don’t care” 04 = “Display Device Data or Blank Check” function code ssss = starting address eeee = ending address ff = subfunction 00 = display data 01 = blank check 02 = display data in data block (valid addresses: 0001 ~ 0FFFH) cc = checksum Example 1: :0500000440004FFF0069 display 4000–4FFF Example 2: :0500000400000FFF02E7 display data in data block (the data at address 0000 is invalid)

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 17

RECORD TYPE COMMAND/DATA FUNCTION

05 Miscellaneous Read Functions

General Format of Function 05 :02xxxx05ffsscc Where: 02 = number of bytes (hex) in record xxxx = required field, but value is a “don’t care” 05 = “Miscellaneous Read” function code ffss = subfunction and selection code 0000 = read signature byte – manufacturer id (15H) 0001 = read signature byte – device id # 1 (C2H) 0002 = read signature byte – device id # 2 P89C60X2 = EFh P89C61X2 = F0h 0003 = read FX2 bit 0080 = read ROM code revision 0700 = read security bits 0701 = read status byte cc = checksum Example 1: :020000050001F8 read signature byte – device id # 1 Example 2: :020000050003F6 read FX2 bit (bit 7 = 0 represents 12-clk mode, bit 7 = 1 represents 6-clk mode) Example 3: :02000005008079 read ROM code revision (0A: Rev. A; 0B: Rev. B, etc.)

06 Direct Load of Baud Rate

General Format of Function 06 :02xxxx06hhllcc Where: 02 = number of bytes (hex) in record xxxx = required field, but value is a “don’t care” 06 = ”Direct Load of Baud Rate” function code hh = high byte of Timer 2 ll = low byte of Timer 2 cc = checksum Example: :02000006F500F3

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 18

The security feature protects against software piracy and prevents the contents of the FLASH from being read. The Security Lock bits are located in FLASH. The P89C60X2/61X2 has 3 programmable security lock bits that will provide different levels of protection for the on-chip code and data (see Table 3). Unlike the ROM and OTP versions, the security lock bits are independent. LB3 includes the security protection of LB1. Table 3. SECURITY LOCK BITS 1 PROTECTION DESCRIPTION Level PROTECTION DESCRIPTION LB1 MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. LB2 Program verification is disabled LB3 External execution is disabled. NOTE: 1. The security lock bits are independent.

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 19

OSCILLATOR CHARACTERISTICS Using the oscillator, XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the logic symbol. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. However, minimum and maximum high and low times specified in the data sheet must be observed. Clock Control Register (CKCON) This device provides control of the 6-clock/12-clock mode by both an SFR bit (bit X2 in register CKCON) and a Flash bit (bit FX2, located in the Security Block). When X2 is 0, 12-clock mode is activated. By setting this bit to 1, the system is switching to 6-clock mode. Having this option implemented as SFR bit, it can be accessed anytime and changed to either value. Changing X2 from 0 to 1 will result in executing user code at twice the speed, since all system time intervals will be divided by 2. Changing back from 6-clock to 12-clock mode will slow down running code by a factor of The Flash clock control bit (FX2) activates the 6-clock mode when programmed using a parallel programmer, superceding the X2 bit (CKCON.0). Please also see Table 4 below. Table 4. FX2 clock mode bit (can only be set by parallel programmer) X2 bit (CKCON.0) CPU clock mode erased 0 12-clock mode (default) erased 1 6-clock mode programmed X 6-clock mode Programmable Clock-Out Pin A 50% duty cycle clock can be programmed to be output on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed: 1. to input the external clock for Timer/Counter 2, or 2. to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency in 12-clock mode (122 Hz to 8 MHz in 6-clock mode). To configure the Timer/Counter 2 as a clock generator, bit C/T 2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation: Oscillator Frequency n /C0032(65536–RCAP2H, RCAP2L) Where: n = 2 in 6-clock mode, 4 in 12-clock mode. (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will be the same. RESET A reset is accomplished by holding the RST pin HIGH for at least two machine cycles (24 oscillator periods in 12-clock and 12 oscillator periods in 6-clock mode), while the oscillator is running. To insure a reliable power-up reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles, unless it has been set to 6-clock operation using a parallel programmer. LOW POWER MODES Stop Clock Mode The static design enables the clock speed to be reduced down to 0 MHz (stopped). When the oscillator is stopped, the RAM and Special Function Registers retain their values. This mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. For lowest power consumption the Power Down mode is suggested. Idle Mode In idle mode (see Table 5), the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.

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on-chip RAM to retain their values. oscillator to restart and stabilize (normally less than 10 ms). machine cycles before the internal reset algorithm takes control. port pin or to external memory.

1. Pull ALE low while the device is in reset and PSEN
2. Hold ALE low as RST is deactivated.

mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied. reset is the result of a power-on or a warm start after powerdown. unaffected by the VCC level. Table 5. External Pin Status During Idle and Power-Down Modes in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. ignored. Setting the run flag (TRn) does not clear the registers. preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer 0 as for Timer 1. TH0 now controls the “Timer 1” interrupt.

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fact, in any application not requiring an interrupt. TMOD.7 “TRn” control pin is set. when cleared Timer “n” is enabled whenever “TRn” control bit is set. TMOD.6 Set for Counter operation (input from “Tn” input pin). 0 0 8048 Timer: “TLn” serves as 5-bit prescaler. 0 1 16-bit Timer/Counter: “THn” and “TLn” are cascaded; there is no prescaler. into “TLn” each time it overflows. 1 1 (Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits. 1 1 (Timer 1) Timer/Counter 1 stopped. Figure 3. Timer/Counter 0/1 Mode Control (TMOD) Register *d = 6 in 6-clock mode; d = 12 in 12-clock mode. Figure 4. Timer/Counter 0/1 Mode 0: 13-Bit Timer/Counter

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TCON.7 TF1 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. TCON.6 TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter on/off. TCON.5 TF0 Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. TCON.4 TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter on/off. TCON.3 IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. TCON.1 IE0 Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. triggered external interrupts. Figure 5. Timer/Counter 0/1 Control (TCON) Register *d = 6 in 6-clock mode; d = 12 in 12-clock mode. Figure 6. Timer/Counter 0/1 Mode 2: 8-Bit Auto-Reload

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*d = 6 in 6-clock mode; d = 12 in 12-clock mode. Figure 7. Timer/Counter 0 Mode 3: Two 8-Bit Counters Figure 9 (There is no reload value for TL2 and TH2 in this mode. depending on the value of the T2EX pin. generated when either TF2 or EXF2 are 1. In Figure 12 DCEN=1 which enables Timer 2 to count up or down. into the timer registers TL2 and TH2.

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Table 6. Timer 2 Operating Modes

1 X 1 Baud rate generator

when either RCLK or TCLK = 1. in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. TR2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer. 1 = External event counter (falling edge triggered).

2 CP/RL 2

Figure 8. Timer/Counter 2 (T2CON) Control Register

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*n = 6 in 6-clock mode; n = 12 in 12-clock mode. Figure 9. Timer 2 in Capture Mode T2OE T2MOD.1 Timer 2 Output Enable bit.

• User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.

Figure 10. Timer 2 Mode (T2MOD) Control Register

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*n = 6 in 6-clock mode; n = 12 in 12-clock mode. Figure 11. Timer 2 in Auto-Reload Mode (DCEN = 0) *n = 6 in 6-clock mode; n = 12 in 12-clock mode. Figure 12. Timer 2 Auto Reload Mode (DCEN = 1)

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Note availability of additional external interrupt. Figure 13. Timer 2 in Baud Rate Generator Mode Timer 1, the other by Timer 2. The timer can be configured for either “timer” or “counter” operation. In many applications, it is configured for “timer” operation (C/T2=0). n = 16 in 6-clock mode, 32 in 12-clock mode. taken as a 16-bit unsigned integer. rollover in TH2 does not set TF2, and will not generate an interrupt. will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). can be used as an additional external interrupt, if needed. before accessing the Timer 2 or RCAP2 registers.

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Table 7. Timer 2 Generated Commonly Used

375 K 750 K 12 MHz FF FF

n = 16 in 6-clock mode, 32 in 12-clock mode. Table 8. Timer 2 as a Timer Table 9. Timer 2 as a Counter

1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 29

The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (However, if the first byte still hasn’t been read by the time reception of the second byte is complete, one of the bytes will be lost.) The serial port receive and transmit registers are both accessed at Special Function Register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The serial port can operate in 4 modes: Mode 0: Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received (LSB first). The baud rate is fixed at 1/12 the oscillator frequency (in 12-clock mode) or 1/6 the oscillator frequency (in 6-clock mode). Mode 1: 10 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SCON. The baud rate is variable. Mode 2: 11 bits are transmitted (through TxD) or received (through RxD): start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On Transmit, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency (in 12-clock mode) or 1/16 or 1/32 the oscillator frequency (in 6-clock mode). Mode 3: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that weren’t being addressed leave their SM2s set and go on about their business, ignoring the coming data bytes. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. Serial Port Control Register The serial port control and status register is the Special Function Register SCON, shown in Figure 14. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). Baud Rates The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = Oscillator Frequency / 12 (in 12-clock mode) or / 6 (in 6-clock mode). The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Register PCON. If SMOD = 0 (which is the value on reset), and the port pins in 12-clock mode, the baud rate is 1/64 the oscillator frequency. If SMOD = 1, the baud rate is 1/32 the oscillator frequency. In 6-clock mode, the baud rate is 1/32 or 1/16 the oscillator frequency, respectively. Mode 2 Baud Rate = SMOD n /C0032(Oscillator Frequency) Where: n = 64 in 12-clock mode, 32 in 6-clock mode The baud rates in Modes 1 and 3 are determined by the Timer 1 or Timer 2 overflow rate. Using Timer 1 to Generate Baud Rates When Timer 1 is used as the baud rate generator (T2CON.RCLK = 0, T2CON.TCLK = 0), the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: Mode 1, 3 Baud Rate = SMOD n /C0032(Timer 1 Overflow Rate) Where: n = 32 in 12-clock mode, 16 in 6-clock mode The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either “timer” or “counter” operation, and in any of its 3 running modes. In the most typical applications, it is configured for “timer” operation, in the auto-reload mode (high nibble of TMOD = 0010B). In that case the baud rate is given by the formula: Mode 1, 3 Baud Rate = SMOD n /C0032Oscillator Frequency Where: n = 32 in 12-clock mode, 16 in 6-clock mode One can achieve very low baud rates with Timer 1 by leaving the Timer 1 interrupt enabled, and configuring the Timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt to do a 16-bit software reload. Figure 15 lists various commonly used baud rates and how they can be obtained from Timer 1.

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received. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. modes, in any serial transmission. Must be cleared by software. modes, in any serial reception (except see SM2). Must be cleared by software. Figure 14. Serial Port Control (SCON) Register Figure 15. Timer 1 Generated Commonly Used Baud Rates 1/6 the oscillator frequency (6-clock mode). Mode 0, and associated timing. of the transmit shift are shifted to the right one position. left of the MSB, and all positions to the left of that contain zeros.

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 31

shifted to the left one position. The value that comes in from the right is the value that was sampled at the P3.0 pin at S5P2 of the same machine cycle. As data bits come in from the right, 1s shift out to the left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the RX Control block to do one last shift and load SBUF. At S1P1 of the 10th machine cycle after the write to SCON that cleared RI, RECEIVE is cleared as RI is set. More About Mode 1 Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the 80C51 the baud rate is determined by the Timer 1 or Timer 2 overflow rate. Figure 17 shows a simplified functional diagram of the serial port in Mode 1, and associated timings for transmit receive. Transmission is initiated by any instruction that uses SBUF as a destination register. The “write to SBUF” signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SBUF” signal.) The transmission begins with activation of SEND which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 10th divide-by-16 rollover after “write to SBUF.” Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated.: 1. R1 = 0, and 2. Either SM2 = 0, or the received stop bit = 1. If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in RxD. More About Modes 2 and 3 Eleven bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of 0 or 1. On receive, the 9the data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 (12-clock mode) or 1/16 or 1/32 the oscillator frequency (6-clock mode) the oscillator frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1 or Timer 2. Figures 18 and 19 show a functional diagram of the serial port in Modes 2 and 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register. Transmission is initiated by any instruction that uses SBUF as a destination register. The “write to SBUF” signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SBUF” signal.) The transmission begins with activation of SEND, which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 11th divide-by-16 rollover after “write to SUBF.” Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift register. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of R-D. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1. RI = 0, and 2. Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the RxD input.

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Figure 16. Serial Port Mode 0

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Figure 17. Serial Port Mode 1

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Figure 18. Serial Port Mode 2

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Figure 19. Serial Port Mode 3

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 36

In addition to the standard operation modes, the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The UART also fully supports multiprocessor communication. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 20). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 21. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 22. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are “don’t care”. The SADEN mask can be logically ANDed with the SADDR to create the “Given” address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00X0 Slave 1 SADDR = 1100 0000 SADEN = 1111 1110 Given = 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = 1100 0000 SADEN = 1111 1001 Given = 1100 0XX0 Slave 1 SADDR = 1110 0000 SADEN = 1111 1010 Given = 1110 0X0X Slave 2 SADDR = 1110 0000 SADEN = 1111 1100 Given = 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are trended as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature.

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received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. REN SCON.4 Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 SCON.3 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. the stop bit in the other modes, in any serial transmission. Must be cleared by software. *SMOD0 is located at PCON.6. Figure 20. SCON: Serial Port Control Register

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Figure 21. UART Framing Error Detection – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. Figure 22. UART Multiprocessor Communication, Automatic Address Recognition

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Figure 23. Interrupt Sources what controls the request flag, rather than the on-chip hardware. hardware when the service routine is vectored to. The Serial Port Interrupt is generated by the logical OR of RI and TI. and the bit will have to be cleared in software. interrupts can be canceled in software. interrupt can’t be interrupted by any other interrupt source.

1. IE0 (External Int 0) (highest)
2. TF2, EXF2 (Timer 2) (lowest)

simultaneous requests of the same priority level. The IP and IPH registers contain a number of unimplemented bits. be used in other 80C51 Family products. The interrupt flags are sampled at S5P2 of every machine cycle.

1. An interrupt of equal or higher priority level is already in
2. The current (polling) cycle is not the final cycle in the execution

of the instruction in progress.

1. The instruction in progress is RETI or any write to the IE or IP

instruction will be executed before any interrupt is vectored to. interrupt flag was once active but not serviced is not remembered.

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Enable Bit = 1 enables the interrupt. enabled or disabled by setting or clearing its enable bit. IE.6 — Not implemented. Reserved for future use. IE.5 ET2 Timer 2 interrupt enable bit. IE.4 ES Serial Port interrupt enable bit. IE.3 ET1 Timer 1 interrupt enable bit. IE.2 EX1 External interrupt 1 enable bit. IE.1 ET0 Timer 0 interrupt enable bit. IE.0 EX0 External interrupt 0 enable bit. Figure 24. Interrupt Enable (IE) Register IP.7 — Not implemented, reserved for future use. IP.6 — Not implemented, reserved for future use. IP.5 PT2 Timer 2 interrupt priority bit. IP.4 PS Serial Port interrupt priority bit. IP.3 PT1 Timer 1 interrupt priority bit. IP.2 PX1 External interrupt 1 priority bit. IP.1 PT0 Timer 0 interrupt priority bit. IP.0 PX0 External interrupt 0 priority bit. Figure 25. Interrupt Priority (IP) Register IPH.7 — Not implemented, reserved for future use. IPH.6 — Not implemented, reserved for future use. IPH.5 PT2H Timer 2 interrupt priority bit high. IPH.4 PSH Serial Port interrupt priority bit high. IPH.3 PT1H Timer 1 interrupt priority bit high. IPH.2 PX1H External interrupt 1 priority bit high. IPH.1 PT0H Timer 0 interrupt priority bit high. IPH.0 PX0H External interrupt 0 priority bit high. Figure 26. Interrupt Priority HIGH (IPH) Register

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This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP. Figure 27. Interrupt Response Timing Diagram The polling cycle/LCALL sequence is illustrated in Figure 27. being vectored to, as shown in Table 10. the interrupted program continues from where it left off. making future interrupts impossible. is set. Flag bit IEx then requests the interrupt. high for at least one cycle, and then hold it low for at least one cycle. CPU when the service routine is called. shows interrupt response timings. if the instruction is MUL or DIV). than 3 cycles and less than 9 cycles.

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interrupt that was stopped will be completed. Table 10. Interrupt Table AUXR.0 AO Turns off ALE output.

• New Register Name: AUXR1#
• SFR Address: A2H
• Reset Value: xxx000x0B AUXR1 (A2H) 76543210 Where: DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1. Select Reg DPS DPTR0 0 DPTR1 1 The DPS bit status should be saved by software when switching between DPTR0 and DPTR1. The GF2 bit is a general purpose user-defined flag. Note that bit 2 is not writable and is always read as a zero. This allows the DPS bit to be quickly toggled simply by executing an INC AUXR1 instruction without affecting the GF2 bit. DPS DPTR1 DPTR0 DPH (83H) DPL (82H) EXTERNAL DATA MEMORY SU00745A BIT0 AUXR1 Figure 28. DPTR Instructions The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1/bit 0 register. The six instructions that use the DPTR are as follows: INC DPTR Increments the data pointer by 1 MOV DPTR, #data16 Loads the DPTR with a 16-bit constant MOV A, @ A+DPTR Move code byte relative to DPTR to ACC MOVX A, @ DPTR Move external RAM (16-bit address) to ACC MOVX @ DPTR , A Move ACC to external RAM (16-bit address) JMP @ A + DPTR Jump indirect relative to DPTR The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See application note AN458 for more details.

2003 Sep 11 43

expanded RAM (ERAM) (768 bytes for the P89C61X2).

1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are

directly and indirectly addressable.

1. The Upper 128 bytes of RAM (addresses 80H to FFH) are

indirectly addressable only.

1. The Special Function Registers, SFRs, (addresses 80H to FFH)

are directly addressable only.

1. The 256/768-bytes expanded RAM (ERAM, 00H – 1FFH/2FFH)

with the EXTRAM bit cleared, see Figure 29. physically separate from SFR space. use indirect addressing access the Upper 128 bytes of data RAM. rather than P2 (whose address is 0A0H). data memory in the P89C60X2/61X2. and read timing signals. Refer to Figure 30.

0 ALE is emitted at a constant rate of 1/6 the oscillator frequency (12-clock mode; 1/3 fOSC

1 ALE is active only during off-chip memory access.

0 Internal ERAM access using MOVX @Ri/@DPTR

1 External data memory access. — Not implemented, reserved for future use*. of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 29. AUXR: Auxiliary Register

2003 Sep 11 44

128 BYTES

Figure 30. Internal and External Data Memory Address Space with EXTRAM = 0 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. pulse at the RST-pin (see the note below). write 01EH and 0E1h to WDTRST. WDTRST is a write only register.

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 45

ABSOLUTE MAXIMUM RATINGS 1, 2, 3 PARAMETER RATING UNIT Operating temperature under bias 0 to +70 °C Storage temperature range –65 to +150 °C Voltage on EA/VPP pin to VSS 0 to +13.0 V Voltage on any other pin to VSS –0.5 to +6.5 V Maximum IOL per I/O pin 15 mA Power dissipation (based on package heat transfer limitations, not device power consumption)1.5 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C CLOCK FREQUENCY RANGE SYMBOL FIGURE PARAMETER OPERATING MODE POWER SUPPLY VOLTAGE MIN MAX UNIT 1/tCLCL 35 Oscillator frequency6-clock 5 V /C0034 10% 0 20 MHz 12-clock 5 V /C0034 10% 0 33 MHz

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 46

DC ELECTRICAL CHARACTERISTICS Tamb = 0 °C to +70 °C; VCC = 5 V ±10%; VSS = 0 V (20/33 MHz max. CPU clock) SYMBOL PARAMETER TEST CONDITIONS LIMITS UNIT MIN TYP 1 MAX VIH Input high voltage (ports 0, 1, 2, 3, EA) – 0.2 VCC +0.9 VCC +0.5 V VIH1 Input high voltage, XTAL1, RST11 – 0.7 VCC VCC +0.5 V VOL Output low voltage, ports 1, 2, 3 8 VCC = 4.5 V; IOL = 1.6 mA2 – 0.4 V VOL1 Output low voltage, port 0, ALE, PSEN 7, 8 VCC = 4.5 V; IOL = 3.2 mA2 – 0.45 V VOH Output high voltage, ports 1, 2, 3 3 VCC = 4.5 V; IOH = –30 /C0109A VCC – 0.7 – V VOH1 Output high voltage (port 0 in external bus mode), ALE9, PSEN3 VCC = 4.5 V; IOH = –3.2 mA VCC – 0.7 – V IIL Logical 0 input current, ports 1, 2, 3VIN = 0.4 V –1 –75 /C0109A ITL Logical 1-to-0 transition current, ports 1, 2, 36 VIN = 2.0 V; See note 4 – –650 /C0109A ILI Input leakage current, port 0 0.45 < VIN < VCC – 0.3 – ±10 /C0109A ICC Power supply current (see Figure 38): See note 5 Active mode (see Note 5) Idle mode (see Note 5) Power-down mode or clock stopped Tamb = 0°C to 70°C <30 100 /C0109A (see Figure 42 for conditions) Programming and erase mode fOSC = 20MHz 60 mA R RST Internal reset pull-down resistor – 40 225 kΩ C IO Pin capacitance10 (except EA) – – 15 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V OL s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC –0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V. 5. See Figures 39 through 42 for ICC test conditions and Figure 38 for ICC vs. Frequency. 12-clock mode characteristics: Active mode: I CC (MAX) = (8.5 + 0.62 /C0002 FREQ. [MHz])mA Idle mode: I CC (MAX) = (3.5 + 0.18 /C0002 FREQ. [MHz])mA 6. This value applies to Tamb = 0°C to +70°C. 7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15 mA Maximum IOL per 8-bit port: 26 mA Maximum total IOL for all outputs: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1 , except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF (except EA is 25 pF). 11. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection circuitry has been added to the INT0 and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection.

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 47

AC ELECTRICAL CHARACTERISTICS (12-CLOCK MODE) Tamb = 0 °C to +70 °C; VCC = 5 V ± 10%, VSS = 0 V1, 2, 3 SYMBOL FIGURE PARAMETER VARIABLE CLOCK 4 33 MHz CLOCK 4 MIN MAX MIN MAX UNIT 1/tCLCL 35 Oscillator frequency 0 33 MHz tLHLL 31 ALE pulse width 2tCLCL –40 21 ns tAVLL 31 Address valid to ALE low tCLCL –25 5 ns tLLAX 31 Address hold after ALE low tCLCL –25 5 ns tLLIV 31 ALE low to valid instruction in 4tCLCL –65 55 ns tLLPL 31 ALE low to PSEN low tCLCL –25 5 ns tPLPH 31 PSEN pulse width 3tCLCL –45 45 ns tPLIV 31 PSEN low to valid instruction in 3tCLCL –60 30 ns tPXIX 31 Input instruction hold after PSEN 0 0 ns tPXIZ 31 Input instruction float after PSEN tCLCL –25 5 ns tAVIV 31 Address to valid instruction in 5tCLCL –80 70 ns tPLAZ 31 PSEN low to address float 10 10 ns Data Memory tRLRH 32 RD pulse width 6tCLCL –100 82 ns tWLWH 33 WR pulse width 6tCLCL –100 82 ns tRLDV 32 RD low to valid data in 5tCLCL –90 60 ns tRHDX 32 Data hold after RD 0 0 ns tRHDZ 32 Data float after RD 2tCLCL –28 32 ns tLLDV 32 ALE low to valid data in 8tCLCL –150 90 ns tAVDV 32 Address to valid data in 9tCLCL –165 105 ns tLLWL 32, 33 ALE low to RD or WR low 3tCLCL –50 3tCLCL +50 40 140 ns tAVWL 32, 33 Address valid to WR low or RD low 4tCLCL –75 45 ns tQVWX 33 Data valid to WR transition tCLCL –30 0 ns tWHQX 33 Data hold after WR tCLCL –25 5 ns tQVWH 33 Data valid to WR high 7tCLCL –130 80 ns tRLAZ 32 RD low to address float 0 0 ns tWHLH 32, 33 RD or WR high to ALE high tCLCL –25 tCLCL +25 5 55 ns External Clock tCHCX 35 High time 17 tCLCL –tCLCX ns tCLCX 35 Low time 17 tCLCL –tCHCX ns tCLCH 35 Rise time 5 ns tCHCL 35 Fall time 5 ns Shift Register tXLXL 34 Serial port clock cycle time 12tCLCL 360 ns tQVXH 34 Output data setup to clock rising edge 10tCLCL –133 167 ns tXHQX 34 Output data hold after clock rising edge 2tCLCL –80 50 ns tXHDX 34 Input data hold after clock rising edge 0 0 ns tXHDV 34 Clock rising edge to input data valid 10tCLCL –133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are tested to 3.5 MHz, but guaranteed to operate down to 0 Hz.

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 48

AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE) Tamb = 0 °C to +70 °C; VCC = 5 V ± 10%, VSS = 0 V1, 2, 3 SYMBOL FIGURE PARAMETER VARIABLE CLOCK 4 20 MHz CLOCK 4 MIN MAX MIN MAX UNIT 1/tCLCL 35 Oscillator frequency 0 20 MHz tLHLL 31 ALE pulse width tCLCL –40 10 ns tAVLL 31 Address valid to ALE low 0.5tCLCL –20 5 ns tLLAX 31 Address hold after ALE low 0.5tCLCL –20 5 ns tLLIV 31 ALE low to valid instruction in 2tCLCL –65 35 ns tLLPL 31 ALE low to PSEN low 0.5tCLCL –20 5 ns tPLPH 31 PSEN pulse width 1.5tCLCL –45 30 ns tPLIV 31 PSEN low to valid instruction in 1.5tCLCL –60 15 ns tPXIX 31 Input instruction hold after PSEN 0 0 ns tPXIZ 31 Input instruction float after PSEN 0.5tCLCL –20 5 ns tAVIV 31 Address to valid instruction in 2.5tCLCL –80 45 ns tPLAZ 31 PSEN low to address float 10 10 ns Data Memory tRLRH 32 RD pulse width 3tCLCL –100 50 ns tWLWH 33 WR pulse width 3tCLCL –100 50 ns tRLDV 32 RD low to valid data in 2.5tCLCL –90 35 ns tRHDX 32 Data hold after RD 0 0 ns tRHDZ 32 Data float after RD tCLCL –20 5 ns tLLDV 32 ALE low to valid data in 4tCLCL –150 50 ns tAVDV 32 Address to valid data in 4.5tCLCL –165 60 ns tLLWL 32, 33 ALE low to RD or WR low 1.5tCLCL –50 1.5tCLCL +50 25 125 ns tAVWL 32, 33 Address valid to WR low or RD low 2tCLCL –75 25 ns tQVWX 33 Data valid to WR transition 0.5tCLCL –25 0 ns tWHQX 33 Data hold after WR 0.5tCLCL –20 5 ns tQVWH 33 Data valid to WR high 3.5tCLCL –130 45 ns tRLAZ 32 RD low to address float 0 0 ns tWHLH 32, 33 RD or WR high to ALE high 0.5tCLCL –20 0.5tCLCL +20 5 45 ns External Clock tCHCX 35 High time 20 tCLCL –tCLCX ns tCLCX 35 Low time 20 tCLCL –tCHCX ns tCLCH 35 Rise time 5 ns tCHCL 35 Fall time 5 ns Shift Register tXLXL 34 Serial port clock cycle time 6tCLCL 300 ns tQVXH 34 Output data setup to clock rising edge 5tCLCL –133 117 ns tXHQX 34 Output data hold after clock rising edge tCLCL –30 20 ns tXHDX 34 Input data hold after clock rising edge 0 0 ns tXHDV 34 Clock rising edge to input data valid 5tCLCL –133 117 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

2003 Sep 11 49

AVLL = Time for address valid to ALE low. tLLPL =Time for ALE low to PSEN low. Figure 31. External Program Memory Read Cycle Figure 32. External Data Memory Read Cycle

2003 Sep 11 50

Figure 33. External Data Memory Write Cycle Figure 34. Shift Register Mode Timing Figure 35. External Clock Drive

2003 Sep 11 51

AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Figure 36. AC Testing Input/Output OH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 37. Float Waveform Figure 38. ICC vs. FREQ for 12-clock operation

2003 Sep 11 52

Figure 39. ICC Test Condition, Active Mode Figure 40. ICC Test Condition, Idle Mode Figure 41. Clock Signal Waveform for ICC Tests in Active and Idle Modes Figure 42. ICC Test Condition, Power Down Mode

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 53

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 54

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 55

LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm SOT389-1

Philips Semiconductors Product data P89C60X2/61X280C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM

2003 Sep 11 56

REVISION HISTORY

_2 20030911 Preliminary data (9397 750 11927); ECN 853-2400 30250 of 25 August 2003 Modifications:

• Added Watchdog Timer feature
• Added DIP40 package _1 20020723 Preliminary data (9397 750 10131) Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to:  Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Date of release: 09-03 Document order number: 9397 750 11927 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status[1] Objective data Preliminary data Product data Product status[2] [3] Development Qualification Production Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Level I II III