89C535 PHILIPS | Alldatasheet
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/C0109 /C0110 /C0114 89C535/89C536/89C538 CMOS single-chip 8-bit microcontrollers with FLASH program memory Preliminary specification IC20 Data Handbook
1997 June 05
Philips Semiconductors Preliminary specification 89C535/89C536/89C538CMOS single-chip 8-bit microcontrollers with FLASH program memory
21997 Jun 05
DESCRIPTION
The 89C535/89C536/89C538 are Single-Chip 8-Bit Microcontrollers manufactured in advanced CMOS process and are derivatives of the 80C51 microcontroller family. All the devices have the same instruction set as the 80C51. The devices also have four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, two-priority-level, nested interrupt structure, UART and on-chip oscillator and timing circuits. For systems that require extra data memory capability up to 64k bytes, each can be expanded using standard TTL-compatible memories and logic. The 89C535/89C536/89C538 contain a non-volatile FLASH EPROM program memory (8K bytes in 89C535, 16k bytes in the 89C536, and 64k bytes in the 89C538). The devices have 512 bytes of RAM data memory.
FEATURES
- 80C51 Central Processing Unit
- 8k x 8 (89C535) 16k × 8 (89C536) or 64k × 8 (89C538), FLASH EPROM Program Memory
- 512 × 8 RAM, externally expandable to 64k × 8 Data Memory
- Three 16-bit counter/timers
- Up to 3 external interrupt request inputs
- 6 interrupt sources with 2 priority levels
- Four 8-bit I/O ports
- Full-duplex UART
- Power control modes – Idle mode – Power down mode, with wakeup from power down using external interrupt
- 44-pin PLCC and QFP packages LOGIC SYMBOL PORT 0PORT 1PORT 2 PORT 3 ADDRESS AND DATA BUS ADDRESS BUS T2EX RxD TxD INT0 INT1 WR RD SECONDARY FUNCTIONS RST EA /VPP PSEN ALE/PROG VSSVCC XTAL1 XTAL2 SU00830
ORDERING INFORMATION
PART NUMBER MEMORY SIZE TEMPERATURE RANGE ( °C) AND PACKAGE FREQ. (MHz) DRAWING NUMBER P89C535NBA A 8k bytes 0 to +70, 44-pin Plastic Leaded Chip Carrier 33 SOT187-2 P89C536NBA A 16k bytes 0 to +70, 44-pin Plastic Leaded Chip Carrier 33 SOT187-2 P89C536NBB B 16k bytes 0 to +70, 44-pin Plastic Quad Flat Package 33 SOT307-2 P89C538NBA A 64k bytes 0 to +70, 44-pin Plastic Leaded Chip Carrier 33 SOT187-2 P89C538NBB B 64k bytes 0 to +70, 44-pin Plastic Quad Flat Package 33 SOT307-2
Philips Semiconductors Preliminary specification 89C535/89C536/89C538CMOS single-chip 8-bit microcontrollers with FLASH program memory
1997 Jun 05 3
DPTR’S MULTIPLE SFRs TIMERS SU00854 8 16
Philips Semiconductors Preliminary specification 89C535/89C536/89C538CMOS single-chip 8-bit microcontrollers with FLASH program memory
1997 Jun 05 4
CERAMIC AND PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS LCC 614 0 18 28 Pin Function 1V SS 2 P1.0/T2 3 P1.1/T2EX 4 P1.2/ECI 5 P1.3 6 P1.4 7 P1.5 8 P1.6 9 P1.7
10 RST
11 P3.0/RxD
12 NIC*
13 P3.1/TxD 14 P3.2/INT0 15 P3.3/INT1 Pin Function 16 P3.4/T0 17 P3.5/T1 18 P3.6/WR 19 P3.7/RD
20 XTAL2
21 XTAL1
23 V CC
24 P2.0/A8 25 P2.1/A9 26 P2.2/A10 27 P2.3/A11 28 P2.4/A12 29 P2.5/A13 30 P2.6/A14 Pin Function 31 P2.7/A15
32 PSEN
33 ALE/PROG
34 NIC*
/VPP 36 P0.7/AD7 37 P0.6/AD6 38 P0.5/AD5 39 P0.4/AD4 40 P0.3/AD3 41 P0.2/AD2 42 P0.1/AD1 43 P0.0/AD0 44 V CC SU00852A* NO INTERNAL CONNECTION PLASTIC QUAD FLAT PACK PIN FUNCTIONS PQFP 44 34 12 22 Pin Function 1 P1.5 2 P1.6 3 P1.7
4 RST
5 P3.0/RxD
6 NIC*
7 P3.1/TxD 8 P3.2/INT0 9 P3.3/INT1 10 P3.4/T0 11 P3.5/T1 12 P3.6/WR 13 P3.7/RD
14 XTAL2
15 XTAL1
16 V SS
17 V CC
18 P2.0/A8 19 P2.1/A9 20 P2.2/A10 21 P2.3/A11 22 P2.4/A12 23 P2.5/A13 24 P2.6/A14 25 P2.7/A15
26 PSEN
27 ALE/PROG
28 NIC*
/VPP 30 P0.7/AD7 Pin Function 31 P0.6/AD6 32 P0.5/AD5 33 P0.4/AD4 34 P0.3/AD3 35 P0.2/AD2 36 P0.1/AD1 37 P0.0/AD0 38 V CC
39 V SS
40 P1.0/T2 41 P1.1/T2EX 42 P1.2 43 P1.3 44 P1.4 SU00853A* NO INTERNAL CONNECTION
Philips Semiconductors Preliminary specification 89C535/89C536/89C538CMOS single-chip 8-bit microcontrollers with FLASH program memory
1997 Jun 05 5
MNEMONIC LCC QFP TYPE NAME AND FUNCTION VSS 1, 22 16, 39 I Ground: 0V reference. VCC 23, 44 17, 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0–0.7 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification and received code bytes during EEPROM programming. External pull-ups are required during program verification. 1–3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also receives the low-order address byte during program memory verification. Alternate functions for Port 1 include: 2 40 I/O T2 (P1.0): Timer/Counter 2 external count input 3 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture P2.0–P2.7 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. Some Port 2 pins receive the high order address bits during EEPROM programming and verification. P3.0–P3.7 11, 13–19 7–13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below: 11 5 I RxD (P3.0): Serial input port 13 7 O TxD (P3.1): Serial output port 14 8 I INT0 (P3.2): External interrupt 15 9 I INT1 (P3.3): External interrupt 16 10 I T0 (P3.4): Timer 0 external input 17 11 I T1 (P3.5): Timer 1 external input 18 12 O WR (P3.6): External data memory write strobe 19 13 O RD (P3.7): External data memory read strobe RST 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC . ALE/PROG 33 27 O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG ) during EEPROM programming. PSEN 32 26 O Program Store Enable: The read strobe to external program memory. When the processor is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA /VPP 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory. If EA is held high, the device executes from internal program memory. This pin also receives the 12V programming supply voltage (VPP ) during EPROM programming. EA is internally latched on Reset. XTAL1 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 20 14 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5V or VSS – 0.5V, respectively.
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Table 1. Special Function Registers # SFRs are modified from or added to the 80C51 SFRs.
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the internal clock circuitry is through a divide-by-two flip-flop. the data sheet must be observed. machine cycles (24 oscillator periods), while the oscillator is running. CC and RST must come up at the same time for a proper start-up. condition when a voltage above VIH1 (min.) is applied to RESET. which starts the processor in the same manner as a power-on reset. on-chip RAM to retain their values. oscillator to restart and stabilize (normally less than 10ms).
- To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to memory. ONCE Mode The ONCE (“On-Circuit Emulation”) Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the 8XC51FA/FB is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.
Table 2. External Pin Status During Idle and Power-Down Mode
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selected by bits in the T2CON as shown in Table 3. (which vectors to the same location as Timer 2 overflow interrupt. counter keeps on counting T2EX pin transitions or osc/12 pulses.). a timer or counter (C/T2* in T2CON). to be reloaded with the 16-bit value in RCAP2L and RCAP2H. generated when either TF2 or EXF2 are 1. when either RCLK or TCLK = 1. interrupt routine. EXF2 must be cleared by software. in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. TR2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer. 1 = External event counter (falling edge triggered). Figure 1. Timer/Counter 2 (T2CON) Control Register Table 3. Timer 2 Operating Modes
1 X 1 Baud rate generator
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Figure 2. Timer 2 in Capture Mode Figure 3. Timer 2 in Auto-Reload Mode
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Note availability of additional external interrupt. Figure 4. Timer 2 in Baud Rate Generator Mode Table 4. Timer 2 Generated Commonly Used Timer 1, the other by Timer 2. The timer can be configured for either “timer” or “counter” operation. In many applications, it is configured for “timer” operation (C/T2*=0). RCAP2L taken as a 16-bit unsigned integer. rollover in TH2 does not set TF2, and will not generate an interrupt. will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). can be used as an additional external interrupt, if needed.
1997 Jun 05 11
before accessing the Timer 2 or RCAP2 registers.
32 Baud Rate/C0467
Table 5. Timer 2 as a Timer Table 6. Timer 2 as a Counter
- Capture/reload occurs only on timer/counter overflow.
- Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate
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is fixed at 1/12 the oscillator frequency. SCON. The baud rate is variable. respects except baud rate. The baud rate in Mode 3 is variable. other modes by the incoming start bit if REN = 1. 8–Bit Microcontroller Data Handbook, IC20. received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. Given or Broadcast Address. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. other modes, in any serial transmission. Must be cleared by software. the other modes, in any serial reception (except see SM2). Must be cleared by software. Figure 5. SCON: Serial Port Control Register
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0 Level 0 (lowest priority)
1 Level 1 (highest priority)
interrupt that was stopped will be completed. Table 7. Interrupt Table
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Enable Bit = 1 enables the interrupt. enabled or disabled by setting or clearing its enable bit. IE.5 ET2 Timer 2 interrupt enable bit. IE.4 ES Serial Port interrupt enable bit. IE.3 ET1 Timer 1 interrupt enable bit. IE.2 EX1 External interrupt 1 enable bit. IE.1 ET0 Timer 0 interrupt enable bit. IE.0 EX0 External interrupt 0 enable bit. Figure 6. IE Registers IP.7 — Not implemented, reserved for future use. IP.6 — Not implemented, reserved for future use. IP.5 PT2 Timer 2 interrupt priority bit. IP.4 PS Serial Port interrupt priority bit. IP.3 PT1 Timer 1 interrupt priority bit. IP.2 PX1 External interrupt 1 priority bit. IP.1 PT0 Timer 0 interrupt priority bit. IP.0 PX0 External interrupt 0 priority bit. Figure 7. IP Registers
1997 Jun 05 15
- The Lower 128 bytes of RAM (addresses 00H to 7FH) are
directly and indirectly addressable.
- The Upper 128 bytes of RAM (addresses 80H to FFH) are
indirectly addressable only.
- The Special Function Registers, SFRs, (addresses 80H to FFH)
are directly addressable only.
- The 256-bytes expanded RAM (ERAM, 00H – FFH) are indirectly
accessed by move external instruction, MOVX. are physically separate from SFR space. use indirect addressing access the Upper 128 bytes of data RAM. rather than P2 (whose address is 0A0H). logically occupies the first 256-bytes of external data memory. P3.7 (RD#). P2 SFR is output during external addressing. and P3.7 as write and read timing signals. Refer to Figure 8. or R1. This will always access the ERAM.
256 BYTES
128 BYTES
Figure 8. Internal and External Data Memory Address Space
Philips Semiconductors Preliminary specification 89C535/89C536/89C538CMOS single-chip 8-bit microcontrollers with FLASH program memory
1997 Jun 05 16
ABSOLUTE MAXIMUM RATINGS 1, 2, 3 PARAMETER RATING UNIT Operating temperature under bias 0 to +70 °C Storage temperature range –65 to +150 °C Voltage on EA/VPP pin to VSS 0 to +13.0 V Voltage on any other pin to VSS –0.5 to +6.5 V Maximum IOL per I/O pin 15 mA Power dissipation (based on package heat transfer limitations, not device power consumption)1 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
Philips Semiconductors Preliminary specification 89C535/89C536/89C538CMOS single-chip 8-bit microcontrollers with FLASH program memory
1997 Jun 05 17
DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C; 5V ±10%; VSS = 0V SYMBOL PARAMETER TEST LIMITS UNITSYMBOL PARAMETER CONDITIONS MIN MAX UNIT VIH Input high voltage (ports 0, 1, 2, 3, EA) 0.2VCC +0.9 VCC +0.5 V VIH1 Input high voltage, XTAL1, RST 0.7VCC VCC +0.5 V VOL Output low voltage, ports 1, 2, 3 6 VCC = 4.5V IOL = 1.6mA1 0.4 V VOL1 Output low voltage, port 0, ALE, PSEN5, 6 VCC = 4.5V IOL = 3.2mA1 0.4 V VOH Output high voltage, ports 1, 2, 32 VCC = 4.5V IOH = –30µA VCC – 0.7 V VOH1 Output high voltage (port 0 in external bus mode), ALE7, PSEN 2 VCC = 4.5V IOH = –800µA VCC – 0.7 V IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4V –1 –50 µA ITL Logical 1-to-0 transition current, ports 1, 2, 3 VIN = 2.0V See note 3 –650 µA ILI Input leakage current, port 0 0.45 < VIN < VCC – 0.3 ±10 µA ICC Power supply current (see Figure 16): See note 4 Active mode VCC = 5.5V 60 mA Idle mode FREQ = 24 MHz 25 mA Power-down mode or clock stopped ( Fi 20 f diti ) Tamb = 0°C to 70°C 100 µA (see Figure 20 for conditions) R RST Internal reset pull-down resistor 40 225 kΩ NOTES: 1. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOL s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 2. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC –0.7 specification when the address bits are stabilizing. 3. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 4. See Figures 17 through 20 for ICC test conditions. Active mode: ICC(MAX) = 0.9 × FREQ. + 1.1mA Idle mode: I CC(MAX) = 0.18 × FREQ. +1.0mA; See Figure 16. 5. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 6. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15mA Maximum IOL per 8-bit port: 26mA Maximum total IOL for all outputs: 71mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. ALE is tested to VOH1 , except when ALE is off then VOH is the voltage specification. 8. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA is 25pF).
Philips Semiconductors Preliminary specification 89C535/89C536/89C538CMOS single-chip 8-bit microcontrollers with FLASH program memory
1997 Jun 05 18
AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C, VCC = 5V ±10%, VSS = 0V1, 2, 3 VARIABLE CLOCK 33MHz CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 9 Oscillator frequency Speed versions : N (33MHz) 3.5 33 3.5 33 MHz tLHLL 9 ALE pulse width 2tCLCL –40 21 ns tAVLL 9 Address valid to ALE low tCLCL –25 5 ns tLLAX 9 Address hold after ALE low tCLCL –25 5 ns tLLIV 9 ALE low to valid instruction in 4tCLCL –65 55 ns tLLPL 9 ALE low to PSEN low tCLCL –25 5 ns tPLPH 9 PSEN pulse width 3tCLCL –45 45 ns tPLIV 9 PSEN low to valid instruction in 3tCLCL –60 30 ns tPXIX 9 Input instruction hold after PSEN 0 0 ns tPXIZ 9 Input instruction float after PSEN tCLCL –25 5 ns tAVIV 9 Address to valid instruction in 5tCLCL –80 70 ns tPLAZ 9 PSEN low to address float 10 10 ns Data Memory tRLRH 10, 11 RD pulse width 6tCLCL –100 82 ns tWLWH 10, 11 WR pulse width 6tCLCL –100 82 ns tRLDV 10, 11 RD low to valid data in 5tCLCL –90 60 ns tRHDX 10, 11 Data hold after RD 0 0 ns tRHDZ 10, 11 Data float after RD 2tCLCL –28 32 ns tLLDV 10, 11 ALE low to valid data in 8tCLCL –150 90 ns tAVDV 10, 11 Address to valid data in 9tCLCL –165 105 ns tLLWL 10, 11 ALE low to RD or WR low 3tCLCL –50 3tCLCL +50 40 140 ns tAVWL 10, 11 Address valid to WR low or RD low 4tCLCL –75 45 ns tQVWX 10, 11 Data valid to WR transition tCLCL –30 0 ns tWHQX 10, 11 Data hold after WR tCLCL –25 5 ns tQVWH 11 Data valid to WR high 7tCLCL –130 80 ns tRLAZ 10, 11 RD low to address float 0 0 ns tWHLH 10, 11 RD or WR high to ALE high tCLCL –25 tCLCL +25 5 55 ns External Clock tCHCX 13 High time 17 tCLCL –tCLCX ns tCLCX 13 Low time 17 tCLCL –tCHCX ns tCLCH 13 Rise time 5 ns tCHCL 13 Fall time 5 ns Shift Register tXLXL 12 Serial port clock cycle time 12tCLCL 360 ns tQVXH 12 Output data setup to clock rising edge 10tCLCL –133 167 ns tXHQX 12 Output data hold after clock rising edge 2tCLCL –80 50 ns tXHDX 12 Input data hold after clock rising edge 0 0 ns tXHDV 12 Clock rising edge to input data valid 10tCLCL –133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers.
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AVLL = Time for address valid to ALE low. tLLPL =Time for ALE low to PSEN low. Figure 9. External Program Memory Read Cycle Figure 10. External Data Memory Read Cycle
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Figure 11. External Data Memory Write Cycle Figure 12. Shift Register Mode Timing Figure 13. External Clock Drive
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AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Figure 14. AC Testing Input/Output OH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 15. Float Waveform Figure 16. ICC vs. FREQ Valid only within frequency specifications of the device under test
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Figure 17. ICC Test Condition, Active Mode Figure 18. ICC Test Condition, Idle Mode Figure 19. Clock Signal Waveform for ICC Tests in Active and Idle Modes Figure 20. ICC Test Condition, Power Down Mode
Philips Semiconductors Preliminary specification 89C535/89C536/89C538CMOS single-chip 8-bit microcontrollers with FLASH program memory
1997 Jun 05 23
FLASH EPROM PROGRAM MEMORY
- 8K (89C535), 16K (89C536), 64K (89C538) or electrically erasable internal program.
- Up to 64 Kilobyte external program memory if the internal program memory is switched off (EA = 0)..
- Programming and erasing voltage 12V /C00345%
- Command register architecture – Byte Programming (10 us typical) – Auto chip erase 5 seconds typical (including preprogramming time)
- Auto Erase and auto program – DATA polling – Toggle bit
- 100 minimum erase/program cycles
- Advanced CMOS FLASH EPROM memory technology GENERAL DESCRIPTION The 89C535/536/538 FLASH EPROM memory augments EPROM functionality with In–circuit electrical erasure and programming. The 89C535/536/538 uses a command register to manage this functionality. The FLASH EPROM reliably stores memory contents even after 100 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The 89C535/536/538 uses a 12.0V /C00345%V PP supply to perform the Auto Program/Erase algorithms. Automatic Programming The 89C535/536/538 is byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm does not require the system to time out or verify the data programmed. The typical room temperature chip programming time of the 89C535/536/538 is less than 5 seconds. Automatic Chip Erase The device may be erased using the automatic Erase algorithm. The automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internal to the device. Automatic Programming Algorithm The 89C535/536/538 automatic Programming algorithm requires the user to only write a program set–up command and a program command (program data and address). The device automatically times the programming pulse width, provides the program verify, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation. AUTOMATIC ERASE ALGORITHM The 89C535/536/538 Automatic Erase algorithm requires the user to only write an erase set–up command and erase command. The device will automatically pre–program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verify, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the erase operation. Commands are written to the command register. Register contents serve as inputs to an internal state–machine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. For system design simplification, the 89C535/536/538 is designed to support either WE or CE controlled writes. During a system write cycle, addresses are latched on the falling edge of WE or CE, whichever occurs last. Data is latched on the rising edge of WE or CE, whichever occurs first. To simplify the following discussion, the WE pin is used as the write cycle control pin through the rest of this text. All setup and hold times are with respect to the WE signal.
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Figure 21. Erase/Programming/Verification Table 8. Pin Description Table 9. Command Definitions
- PA = Address of memory location to be programmed
- PD = Data to be programmed at location Command Definitions When low voltage is applied to the VPP pin, the contents of the command register default to 00H. Placing high voltage on the VPP pin enables read/write operations. Device operations are selected by writing specific data patterns into the command register. Table 2 defines these 89C535/536/538 register commands. Table 3 defines the bus operations of 89C535/536/538.
Philips Semiconductors Preliminary specification 89C535/89C536/89C538CMOS single-chip 8-bit microcontrollers with FLASH program memory
1997 Jun 05 25
Table 10. OPERATION VPP (1) CE OE WE D00–D07 READ/WRITE Read(2) VPPH VIL VIL VIH DATA OUT(3) Standby(4) VPPH VIH X X Tri–State Write VPPH VIL VIH VIL Data In(5) NOTES: 1. VPPH is the programming voltage specified for the device. 2. Read operation withVPP = VPPH may access array data (if write command is preceded) or silicon ID codes. 3. With VPP at high voltage, the standby current equals ICC +IPP (standby). 4. Refer to Table 38 for valid Data–In during a write operation. 5. X can be V IL or VIH. Set–Up Automatic Chip Erase/Erase Commands The automatic chip erase does not require the device to be entirely pre–programmed prior to executing the Automatic set–up erase command and automatic chip erase command. Upon executing the Automatic chip erase command, the device automatically will program and verify the entire memory for an all–zero data pattern. When the device is automatically verified to contain an all–zero pattern, a self–timed chip erase and verify begins. The erase and verify operations are complete when the data on DQ7 is”1” at which time the device returns to the standby mode. The system is not required to provide any control or timing during these operations. When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verify command is required). The margin voltages are internally generated in the same manner as when the standard erase verify command is used. The Automatic set–up erase command is a command only operation that stages the device for automatic electrical erasure of all bytes in the array. Automatic set–up erase is performed by writing 30H to the command register. To command automatic chip erase, the command 30H must be written again to the command register. The automatic chip erase begins on the rising edge of the WE and terminates when the data on DQ7 is ”1 “ and the data on DQ6 stops toggling for two consecutive read cycles, at which time the device returns to the standby mode. Set–Up Automatic Program/Program Commands The Automatic Set–up Program is a command–only operation that stages the devices for automatic programming. Automatic Set–up Program is performed by writing 40H to the command register. Once the Automatic Set–up Program operation is performed, the next WE pulse causes a transition to an active programming operation. Addresses are internally latched on the falling edge of the WE pulse. Data is internally latched on the rising edge of the WE pulse. The rising edge of WE also begins the programming operation. The system is not required to provide further controls or timings. The device will automatically provide an adequate internally generated program pulse and verify margin. The automatic programming operation is completed when the data read on DQ6 stops toggling for two consecutive read cycles and the data on DQ7 and DQ6 are equivalent to data written to these two bits at which time the device returns to the Read mode (no program verify command is required; but data can be read out if OE is active low). Reset Command A reset command is provided as a means to safely abort the erase– or program–command sequences. Following either set–up command (erase or program) with two consecutive writes of FFH will safely abort the operation. Memory contents will not be altered. Should program–fail or erase–fail happen, two consecutive writes of FFH will reset the device to abort the operation. A valid command must then be written to place the device in the desired state. Write Operation Status Toggle Bit–DQ6 The 89C535/536/538 features a “Toggle Bit” as a method to indicate to the host system that the Auto Program/Erase algorithms are either in progress or completed. While the Automatic Program or Erase algorithm is in progress, successive attempts to read data from the device will result in DQ6 toggling between one and zero. Once the Automatic Program or Erase algorithm is completed, DQ6 will stop toggling and valid data will be read. The toggle bit is valid after the rising edge of the second WE pulse of the two write pulse sequences. Data Polling–D07 The 89C535/536/538 also features DATA Polling as a method to indicate to the host system that the Automatic Program or Erase algorithms are either in progress or completed. While the Automatic Programming algorithm is in operation an attempt to read the device will produce the complement data of the data last written to DQ7. Upon completion of the Automatic Program algorithm an attempt to read the device will produce the true data last written to DQ7. The Data Polling feature is valid after the rising edge of the second WE pulse of the two write pulse sequences. While the Automatic Erase algorithm is in operation, DQ7 will read “0” until the erase operation is completed. Upon completion of the erase operation, the data on DQ7 will read “1”. The DATA Polling feature is valid after the rising edge of the second WE pulse of two writes pulse sequences. The DATA Polling feature is active during Automatic Program/Erase algorithms. Write Operation The data to be programmed into Flash should be inverted when programming. In other words to program the value ‘00’, ‘FF’ should be applied to port P0.
Philips Semiconductors Preliminary specification 89C535/89C536/89C538CMOS single-chip 8-bit microcontrollers with FLASH program memory
1997 Jun 05 26
During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and GND, and between VPP and GND to minimize transient effects. SYMBOL PARAMETER MIN TYP MAX UNIT CONDITION C IN VPPH 14 PF VIN = 0V C OUT VPPH 16 pF VOUT = 0V Command programming/Data programming/Erase Operation DC CHARACTERISTICS Tamb = 0°C to 70°C, VCC = 5V ± 10%, VPP = 12.0V ± 5% SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT ILI Input Leakage Current VIN = GND to VCC 10 µA ILO Output Leakage CurrentVOUT = GND to VCC 10 µA ISB1 Standby VCC Current CE = VIH 1 mA ISB2 CE = VCC ± 0.3 V 1 100 µA ICC1 (Read) Operating VCC Current IOUT = 0 mA, f=1 MHz 30 mA ICC2 IOUT = 0 mA, F=11MHz 50 mA ICC3 (Program) In Programming 50 mA ICC4 (Erase) In Erase 50 mA ICC5 (Program Verify) In Program Verify 50 mA ICC6 (Erase Verify) In erase Verify 50 mA IPP1 (Read) VPP Current VPP =12.6 V 100 µA IPP2 (Program) In Programming 50 mA IPP3 (Erase) In Erase 50 mA IPP4 (Program Verify) In Program Verify 50 mA IPP5 (Erase Verify) In Erase Verify 50 mA VIL Input Voltage –0.5 (Note 5) 0.2VPP – 0.3 V VIH 2.4 VCC +0.3V V (Note 6) VOL Output Voltage Low IOL =2.1mA 0.45 V VOH Output Voltage High IOH =400uA 2.4 V NOTES: 1. VCC must be applied before VPP and removed after VPP. 2. VPP must not exceed 14V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP =12V. 4. Do not alter VPP from VIL to 12V or 12V to VIL when CE=VIL 5. VIL min. = –0.5V for pulse width ≤ 20ns. 6. If VIH is over the specified maximum value, programming operation cannot be guaranteed. 7. All currents are in RMS unless otherwise noted. (Sampled, not 100% tested.).
Philips Semiconductors Preliminary specification 89C535/89C536/89C538CMOS single-chip 8-bit microcontrollers with FLASH program memory
1997 Jun 05 27
Tamb = 0°C to 70°C, VCC = 5V /C0034 10%, VPP = 12V /C0034 5% SYMBOL PARAMETER CONDITION MIN MAX UNIT τVPS VPP setup time 100 ns τOES OE setup time 100 ns τCWC Command programming cycles 150 ns τCEP WE programming pulse width 60 ns τEPH1 WE programming pulse width High 20 ns τCEPH2 WE programming pulse width High 100 ns τAS Address setup time 0 ns τAH1 Address hold time for DATA Polling 0 ns τDS DATA setup time 50 ns τDH DATA hold time 10 ns τCESP CE setup time before DATA polling/toggle bit 100 ns τCES CE setup time 0 ns τCESC CE setup time before command write 100 ns τVPH VPP hold time 100 ns τDF Output disable time (Note 2) 35 ns τDPA DATA polling/toggle bit access time 150 ns τAETC Total erase time in auto chip erase 5(TYP) s τAVT Total programming time in auto verify 15 300 s NOTES: 1. CE and OE must be fixed high during VPP transition from 5V to 12V or from 12V to 5V. 2. τDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. Timing Waveform Automatic Programming One byte of data is programmed. Verifying in fast algorithm and additional programming by external control are not required because these operations are executed automatically by an internal control circuit. Programming completion can be verified by DATA polling and toggle bit checking after automatic verify starts. Device outputs DATA during programming and DATA after programming on Q7. Q0 to Q5(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) are in high impedance.
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Figure 22. Automatic Programming Timing Waveform
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Figure 23. Automatic Chip Erase Timing Waveform
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Figure 24. Reset Timing Waveform polling appears in Q7 during programming or erase.
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Figure 25. Toggle Bit, Data Polling Timing Waveform
Philips Semiconductors Preliminary specification 89C535/89C536/89C538CMOS single-chip 8-bit microcontrollers with FLASH program memory
1997 June 05 32
PLCC44: plastic leaded chip carrier; 44 leads SOT187-2
Philips Semiconductors Preliminary specification 89C535/89C536/89C538CMOS single-chip 8-bit microcontrollers with FLASH program memory
1997 June 05 33
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2
Philips Semiconductors Preliminary specification 89C535/89C536/89C538CMOS single-chip 8-bit microcontrollers with FLASH program memory
1997 June 05 34
Philips Semiconductors Preliminary specification 89C535/89C536/89C538CMOS single-chip 8-bit microcontrollers with FLASH program memory
1997 June 05 35
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Philips Semiconductors
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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. /C0109 /C0110 /C0114