P89C52BP

89C52 PHILIPS | Alldatasheet

Document overview

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Technical content

/C0080/C0104/C0105/C0108/C0105/C0112/C0115 /C0083/C0101/C0109/C0105/C0099/C0111/C0110/C0100/C0117/C0099/C0116/C0111/C0114/C0115 89C51/89C52/89C54/89C58 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash Product data Supersedes data of 1999 Oct 27 IC28 Data Handbook

2002 Jan 15

Philips Semiconductors Product data 89C51/89C52/89C54/89C5880C51 8-bit microcontroller family 4K/8K/16K/32K Flash

22002 Jan 15 853–2148 27548

DESCRIPTION

The 89C51/89C52/89C54/89C58 contain a non-volatile FLASH program memory that is parallel programmable. For devices that are serial programmable (In-System Programmable (ISP) and In-Application Programmable (IAP) with a boot loader), see the 89C51Rx2 or 89C66x datasheets. All three families are Single-Chip 8-bit Microcontrollers manufactured in advanced CMOS process and are derivatives of the 80C51 microcontroller family. All the devices have the same instruction set as the 80C51. SELECTION TABLE FOR FLASH DEVICES MTP devices (this data sheet) ISP/IAP devices (see separate data sheets) 89C51 89C52/54/58 89C51Rx2 89C66x ROM/EPROM memory size 4K 8K/16K/32K 16K–64K 16K–64K RAM size (byte) 128 256 512–1K 512–8K Parallel programming yes yes yes yes In-System Programming (ISP) no no yes yes In-Application Programming (IAP) no no yes yes PWM no no yes yes Programmable Timer/Counter (PCA) no no yes yes Hardware Watchdog Timer no no yes yes Serial Channels UART UART UART UART + I2C MTP = Multi-Time Programming (via parallel programmer) ISP = In-System Programming (via serial interface) IAP = In-Application Programming Please note that the FLASH programming algorithm for these parts has been modified. Please see the Device Comparison table for details. DEVICE COMPARISON TABLE Item Old devices New devices Reason for change Type description P89C5xUBxx / P89C5xUFxx P89C5xBx Letter U dropped for shorter type descriptions (formerly designated speed (0–33 MHz)) Programming algorithm When using parallel programmer, be sure to select P89C5xUxxx devices When using a parallel program- mer, be sure to select P89C5xBx devices (no more letter U). IF DEVICES ARE NOT YET SE- LECTABLE, ASK YOUR VEN- DOR FOR A SOFTWARE UP- DATE. Programming algorithm modifica- tion required by process change! Quad Flat Package type PQFP package (P89C5xUxBB) PQFP package replaced by LQFP package (P89C5xBBD). SEE NEW DIMENSIONS AT THE END OF THIS DATA SHEET. Reduction in package height Package identifiers PLCC = AA PQFP = BB PDIP = PN PLCC = A LQFP = BD PDIP = P Shorter type descriptions Flash memory program and erase cycles 100 program and erase cycles 10,000 program and erase cycles Process change allows more pro- gram and erase cycles Power consumption Active mode: ICC(MAX) = (0.9 /C0032 FREQ. + 20)mA Idle mode: ICC(MAX) = (0.37 /C0032 FREQ. + 1.0)mA Active mode: ICC(MAX) = (0.55 /C0032 FREQ. + 8.0)mA Idle mode: ICC(MAX) = (0.3 /C0032 FREQ. + 2.0)mA Process change allows lower power consumption

Philips Semiconductors Product data 89C51/89C52/89C54/89C5880C51 8-bit microcontroller family 4K/8K/16K/32K Flash

2002 Jan 15 3

FEATURES

• 80C51 Central Processing Unit
• On-chip FLASH Program Memory
• Speed up to 33 MHz
• Fully static operation
• RAM expandable externally up to 64 kbytes
• 4 interrupt priority levels
• 6 interrupt sources
• Four 8-bit I/O ports
• Full-duplex enhanced UART – Framing error detection – Automatic address recognition
• Three 16-bit timers/counters T0, T1 (standard 80C51) and additional T2 (capture and compare)
• Power control modes – Clock can be stopped and resumed – Idle mode – Power down mode
• Programmable clock out
• Second DPTR register
• Asynchronous port reset
• Low EMI (inhibit ALE)
• Wake up from power down by an external interrupt

ORDERING INFORMATION

Type number Package Temperature Voltage Frequency 4K Flash version 8K Flash version 16K Flash version 32K Flash version Name Description Version Range 3 (°C) Range (V) (MHz) P89C51BA P89C52BA P89C54BA P89C58BA PLCC44 plastic leaded chip carrier; 44 leads SOT187-2 0 to +70 5 0 to 33 P89C51BP1 P89C51BN2 P89C52BP1 P89C52BN2 P89C54BP1 P89C54BN2 P89C58BP1 P89C58BN2 DIP40 plastic dual in-line package; 40 leads SOT129-1 0 to +70 5 0 to 33 P89C51BBD P89C52BBD P89C54BBD P89C58BBD LQFP44 plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm SOT389-1 0 to +70 5 0 to 33 NOTES: 1. Philips (except North America) Part Order Number 2. Philips North America Part Order Number. Note that parts will be marked “P89C5xBP”, respectively (x = 1, 2, 4, 8) 3. Industrial temperatures will be released with P89C5xX2 devices (see separate data sheet) PART NUMBER DERIVATION Device number (P89C5x) Temperature range Package P89C51 P89C52 P89C54 P89C58 B = 0 /C0095C to 70 /C0095C BD = LQFP A = PLCC P = PDIP

Philips Semiconductors Product data 89C51/89C52/89C54/89C5880C51 8-bit microcontroller family 4K/8K/16K/32K Flash

2002 Jan 15 4

4K – 32K Byte Code Flash 128 / 256 Byte Data RAM Port 3 Configurable I/Os Port 2 Configurable I/Os Port 1 Configurable I/Os Port 0 Configurable I/Os OscillatorCrystal or Resonator Full-duplex enhanced UART Timer 0 Timer 1 Timer 2

Philips Semiconductors Product data 89C51/89C52/89C54/89C5880C51 8-bit microcontroller family 4K/8K/16K/32K Flash

2002 Jan 15 5

BLOCK DIAGRAM 2 (CPU ORIENTED) SU01066 PSEN EA VPP ALE RST XTAL1 XTAL2 VCC VSS PORT 0 DRIVERS PORT 2 DRIVERS RAM ADDR REGISTER RAM PORT 0 LATCH PORT 2 LATCH FLASH REGISTER B ACC STACK POINTER TMP2 TMP1 ALU TIMING AND CONTROL INSTRUCTION REGISTER PD OSCILLATOR PSW PORT 1 LATCH PORT 3 LATCH PORT 1 DRIVERS PORT 3 DRIVERS PROGRAM ADDRESS REGISTER BUFFER PC INCRE- MENTER PROGRAM COUNTER DPTR’S MULTIPLE SFRs TIMERS 8 16

Philips Semiconductors Product data 89C51/89C52/89C54/89C5880C51 8-bit microcontroller family 4K/8K/16K/32K Flash

2002 Jan 15 6

Dual In-Line Package Pin Functions SU01063 20 21 40T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 RST RxD/P3.0 TxD/P3.1 INT0 /P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 P1.7 WR /P3.6 RD /P3.7 XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE EA /VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 V CC DUAL IN-LINE PACKAGE Ceramic and Plastic Leaded Chip Carrier Pin Functions SU01062 PLCC 614 0 18 28 Pin Function

1 NIC*

2 P1.0/T2 3 P1.1/T2EX 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1.6 9 P1.7

10 RST

11 P3.0/RxD

12 NIC*

13 P3.1/TxD 14 P3.2/INT0 15 P3.3/INT1 Pin Function 16 P3.4/T0 17 P3.5/T1 18 P3.6/WR 19 P3.7/RD

20 XTAL2

21 XTAL1

23 NIC*

24 P2.0/A8 25 P2.1/A9 26 P2.2/A10 27 P2.3/A11 28 P2.4/A12 29 P2.5/A13 30 P2.6/A14 Pin Function 31 P2.7/A15

32 PSEN

33 ALE

34 NIC*

/VPP 36 P0.7/AD7 37 P0.6/AD6 38 P0.5/AD5 39 P0.4/AD4 40 P0.3/AD3 41 P0.2/AD2 42 P0.1/AD1 43 P0.0/AD0 44 V CC * NO INTERNAL CONNECTION Low Profile Quad Flat Pack Pin Functions SU01494 LQFP 44 34 12 22 Pin Function 1 P1.5 2 P1.6 3 P1.7

4 RST

5 P3.0/RxD

6 NIC*

7 P3.1/TxD 8 P3.2/INT0 9 P3.3/INT1 10 P3.4/T0 11 P3.5/T1 12 P3.6/WR 13 P3.7/RD

14 XTAL2

15 XTAL1

16 V SS

17 NIC*

18 P2.0/A8 19 P2.1/A9 20 P2.2/A10 21 P2.3/A11 22 P2.4/A12 23 P2.5/A13 24 P2.6/A14 25 P2.7/A15

26 PSEN

27 ALE

28 NIC*

/VPP 30 P0.7/AD7 Pin Function 31 P0.6/AD6 32 P0.5/AD5 33 P0.4/AD4 34 P0.3/AD3 35 P0.2/AD2 36 P0.1/AD1 37 P0.0/AD0 38 V CC

39 NIC*

40 P1.0/T2 41 P1.1/T2EX 42 P1.2 43 P1.3 44 P1.4 * NO INTERNAL CONNECTION

Philips Semiconductors Product data 89C51/89C52/89C54/89C5880C51 8-bit microcontroller family 4K/8K/16K/32K Flash

2002 Jan 15 7

MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION VSS 20 22 16 I Ground: 0 V reference. VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0–0.7 39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. 1–3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Alternate function for Port 1: 1 2 40 I/O T2 (P1.0): Timer/Counter2 external count input/clockout (see Programmable Clock-Out). 2 3 41 I T2EX (P1.1): Timer/Counter2 reload/capture/direction control. P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. 13–19 7–13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: I IL). Port 3 also serves the special features of the 89C51/89C52/89C54/89C58, as listed below: 10 11 5 I RxD (P3.0): Serial input port 11 13 7 O TxD (P3.1): Serial output port 12 14 8 I INT0 (P3.2): External interrupt 13 15 9 I INT1 (P3.3): External interrupt 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC . ALE 30 33 27 O Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA /VPP 31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to the maximum internal memory boundary. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 0FFFH for 4 k devices, 1FFFH for 8 k devices, 3FFFH for 16 k devices, and 7FFFH for 32 k devices. The value on the EA pin is latched when RST is released and any subsequent changes have no effect. This pin also receives the 5V/12V (±10%) programming supply voltage (VPP ) during FLASH programming. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin (other than VPP ) at any time must not be higher than VCC + 0.5 V or VSS – 0.5 V, respectively.

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Table 1. 89C51/89C52/89C54/89C58 Special Function Registers # SFRs are modified from or added to the 80C51 SFRs.

1. Reset value depends on reset source.
2. Bit will not be affected by reset.

Philips Semiconductors Product data 89C51/89C52/89C54/89C5880C51 8-bit microcontroller family 4K/8K/16K/32K Flash

2002 Jan 15 9

The 89C51/89C52/89C54/89C58 FLASH reliably stores memory contents even after 10,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling.

• FLASH EPROM internal program memory with Chip Erase
• Up to 64 k byte external program memory if the internal program memory is disabled (EA = 0)
• Programmable security bits
• 10,000 minimum erase/program cycles for each byte
• 10 year minimum data retention
• Programming support available from many popular vendors OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. RESET A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on V CC and RST must come up at the same time for a proper start-up. Ports 1, 2, and 3 will asynchronously be driven to their reset condition when a voltage above V IH1 (min.) is applied to RST. The value on the EA pin is latched when RST is deasserted and has no further effect.

2002 Jan 15 10

lowest power consumption the Power Down mode is suggested. which starts the processor in the same manner as a power-on reset. on-chip RAM to retain their values. oscillator to restart and stabilize (normally less than 10ms). one following the instruction that put the device into Power Down. two machine cycles before the internal reset algorithm takes control. port pin or to external memory.

1. Pull ALE low while the device is in reset and PSEN
2. Hold ALE low as RST is deactivated.

mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied. A 50% duty cycle clock can be programmed to come out on P1.0.

1. to input the external clock for Timer/Counter 2, or
2. to output a 50% duty cycle clock ranging from 61Hz to 4MHz at a

TR2 (T2CON.2) also must be set to start the timer. taken as a 16-bit unsigned integer. interrupt. This is similar to when it is used as a baud-rate generator. Clock-Out frequency will be the same. Table 2. External Pin Status During Idle and Power-Down Mode

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in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. shows the Mode 0 operation as it applies to Timer 1. TCON (Figure 3). GATE is in TMOD. ignored. Setting the run flag (TR1) does not clear the registers. Mode 0 operation is the same for the Timer 0 as for Timer 1. 1 (TMOD.7) and one for Timer 0 (TMOD.3). preset by software. The reload leaves TH1 unchanged. Mode 2 operation is the same for Timer/Counter 0. TH0 now controls the “Timer 1” interrupt. fact, in any application not requiring an interrupt. “TRx” control pin is set. when cleared Timer “x” is enabled whenever “TRx” control bit is set. Set for Counter operation (input from “Tx” input pin). 0 0 8048 Timer “TLx” serves as 5-bit prescaler. 0 1 16-bit Timer/Counter “THx” and “TLx” are cascaded; there is no prescaler. into “TLx” each time it overflows. 1 1 (Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits. 1 1 (Timer 1) Timer/Counter 1 stopped. Figure 1. Timer/Counter 0/1 Mode Control (TMOD) Register

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Figure 2. Timer/Counter 0/1 Mode 0: 13-Bit Counter (Timer 1 shown) TCON.7 TF1 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. TCON.6 TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter on/off. TCON.5 TF0 Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. TCON.4 TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter on/off. TCON.3 IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. TCON.1 IE0 Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. triggered external interrupts. Figure 3. Timer/Counter 0/1 Control (TCON) Register

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Figure 4. Timer/Counter 0/1 Mode 2: 8-Bit Auto-Load (Timer 1 shown) Figure 5. Timer/Counter 0 Mode 3: Two 8-Bit Counters

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(which vectors to the same location as Timer 2 overflow interrupt. counter keeps on counting T2EX pin transitions or osc/12 pulses.). or down depending on the value of the T2EX pin. generated when either TF2 or EXF2 are 1. In Figure 5 DCEN=1 which enables Timer 2 to count up or down. into the timer registers TL2 and TH2. when either RCLK or TCLK = 1. in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. TR2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer. 1 = External event counter (falling edge triggered). Figure 1. Timer/Counter 2 (T2CON) Control Register

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Table 3. Timer 2 Operating Modes

1 X 1 Baud rate generator

Figure 2. Timer 2 in Capture Mode — Not implemented, reserved for future use 1. T2OE Timer 2 Output Enable bit. DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.

1. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that

case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 3. Timer 2 Mode (T2MOD) Control Register

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Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0) Figure 5. Timer 2 Auto Reload Mode (DCEN = 1)

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Note availability of additional external interrupt. Figure 6. Timer 2 in Baud Rate Generator Mode Table 4. Timer 2 Generated Commonly Used Timer 1, the other by Timer 2. in registers RCAP2H and RCAP2L, which are preset by software. The timer can be configured for either “timer” or “counter” operation. In many applications, it is configured for “timer” operation (C/T2*=0). RCAP2L taken as a 16-bit unsigned integer. rollover in TH2 does not set TF2, and will not generate an interrupt. will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). can be used as an additional external interrupt, if needed.

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before accessing the Timer 2 or RCAP2 registers. as a timer. Also see Table 6 for set-up of Timer 2 as a counter. Table 5. Timer 2 as a Timer Table 6. Timer 2 as a Counter

1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate

Philips Semiconductors Product data 89C51/89C52/89C54/89C5880C51 8-bit microcontroller family 4K/8K/16K/32K Flash

2002 Jan 15 19

In addition to the standard operation modes, the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The UART also fully supports multiprocessor communication. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 8. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 9. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are “don’t care”. The SADEN mask can be logically ANDed with the SADDR to create the “Given” address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00X0 Slave 1 SADDR = 1100 0000 SADEN = 1111 1110 Given = 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = 1100 0000 SADEN = 1111 1001 Given = 1100 0XX0 Slave 1 SADDR = 1110 0000 SADEN = 1111 1010 Given = 1110 0X0X Slave 2 SADDR = 1110 0000 SADEN = 1111 1100 Given = 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are trended as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature.

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received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. REN SCON.4 Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 SCON.3 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. the stop bit in the other modes, in any serial transmission. Must be cleared by software. *SMOD0 is located at PCON.6. Figure 7. SCON: Serial Port Control Register

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Figure 8. UART Framing Error Detection – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. Figure 9. UART Multiprocessor Communication, Automatic Address Recognition

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Figure 10. 80C51 Interrupt Sources what controls the request flag, rather than the on-chip hardware. hardware when the service routine is vectored to. The Serial Port Interrupt is generated by the logical OR of RI and TI. and the bit will have to be cleared in software. interrupts can be canceled in software. interrupt can’t be interrupted by any other interrupt source.

1. IE0 (External Int 0) (highest)
2. TF2, EXF2 (Timer 2) (lowest)

simultaneous requests of the same priority level. The IP and IPH registers contain a number of unimplemented bits. be used in other 80C51 Family products. The interrupt flags are sampled at S5P2 of every machine cycle.

1. An interrupt of equal or higher priority level is already in
2. The current (polling) cycle is not the final cycle in the execution

of the instruction in progress.

1. The instruction in progress is RETI or any write to the IE or IP

instruction will be executed before any interrupt is vectored to. interrupt flag was once active but not serviced is not remembered.

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Enable Bit = 1 enables the interrupt. enabled or disabled by setting or clearing its enable bit. IE.6 — Not implemented. Reserved for future use. IE.5 ET2 Timer 2 interrupt enable bit. IE.4 ES Serial Port interrupt enable bit. IE.3 ET1 Timer 1 interrupt enable bit. IE.2 EX1 External interrupt 1 enable bit. IE.1 ET0 Timer 0 interrupt enable bit. IE.0 EX0 External interrupt 0 enable bit. Figure 11. Interrupt Enable (IE) Register IP.7 — Not implemented, reserved for future use. IP.6 — Not implemented, reserved for future use. IP.5 PT2 Timer 2 interrupt priority bit. IP.4 PS Serial Port interrupt priority bit. IP.3 PT1 Timer 1 interrupt priority bit. IP.2 PX1 External interrupt 1 priority bit. IP.1 PT0 Timer 0 interrupt priority bit. IP.0 PX0 External interrupt 0 priority bit. Figure 12. Interrupt Priority (IP) Register IPH.7 — Not implemented, reserved for future use. IPH.6 — Not implemented, reserved for future use. IPH.5 PT2H Timer 2 interrupt priority bit high. IPH.4 PSH Serial Port interrupt priority bit high. IPH.3 PT1H Timer 1 interrupt priority bit high. IPH.2 PX1H External interrupt 1 priority bit high. IPH.1 PT0H Timer 0 interrupt priority bit high. IPH.0 PX0H External interrupt 0 priority bit high. Figure 13. Interrupt Priority HIGH (IPH) Register

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This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP. Figure 14. Interrupt Response Timing Diagram The polling cycle/LCALL sequence is illustrated in Figure 14. being vectored to, as shown in Table 7. the interrupted program continues from where it left off. making future interrupts impossible. is set. Flag bit IEx then requests the interrupt. high for at least one cycle, and then hold it low for at least one cycle. CPU when the service routine is called. shows interrupt response timings. if the instruction is MUL or DIV). than 3 cycles and less than 9 cycles.

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interrupt that was stopped will be completed. Table 7. Interrupt Table The AO bit (AUXR.0) in the AUXR register when set disables the ALE output, unless the CPU needs to perform an off-chip memory access. 1 ALE is active only during off-chip memory accesses. — Not implemented, reserved for future use 1.

1. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that

case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 15. AUXR: Auxiliary Register

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code to switch between them.

• New Register Name: AUXR1#
• SFR Address: A2H
• Reset Value: xxxx00x0B AUXR1 Reset Value = xxxx 00x0B Symbol Function GF2 The GF2 bit is a general purpose user-defined flag. Note that bit 2 is not writable and is always read as a zero. This allows the DPS bit to be quickly toggled simply by executing an INC AUXR1 instruction without affecting the GF2 bit. DPS DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1. Select Reg DPS DPTR0 0 DPTR1 1 — Not implemented, reserved for future use 1. SU01561 76543210 Address = A2H Not Bit Addressable 1. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

Figure 16. AUXR1: Auxiliary 1 Register SFRs. See application note AN458 for more details.

Philips Semiconductors Product data 89C51/89C52/89C54/89C5880C51 8-bit microcontroller family 4K/8K/16K/32K Flash

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ABSOLUTE MAXIMUM RATINGS 1, 2, 3 PARAMETER RATING UNIT Operating temperature under bias 0 to +70 or –40 to +85 °C Storage temperature range –65 to +150 °C Voltage on EA/VPP pin to VSS 0 to +13.0 V Voltage on any other pin to VSS –0.5 to +6.5 V Maximum IOL per I/O pin 15 mA Power dissipation (based on package heat transfer limitations, not device power consumption)1.5 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C SYMBOL PARAMETER CLOCK FREQUENCY RANGE –f UNIT MIN MAX 1/tCLCL Oscillator frequency 0 33 MHz

Philips Semiconductors Product data 89C51/89C52/89C54/89C5880C51 8-bit microcontroller family 4K/8K/16K/32K Flash

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DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C; 5 V ±10%; VSS = 0 V TEST LIMITS SYMBOL PARAMETER CONDITIONS MIN TYP 1 MAX UNIT VIH Input high voltage (ports 0, 1, 2, 3, EA) 0.2 VCC +0.9 VCC +0.5 V VIH1 Input high voltage, XTAL1, RST 0.7 VCC VCC +0.5 V VOL Output low voltage, ports 1, 2, 3 8 VCC = 4.5 V IOL = 1.6 mA2 0.4 V VOL1 Output low voltage, port 0, ALE, PSEN 7, 8 VCC = 4.5 V IOL = 3.2 mA2 0.4 V VOH Output high voltage, ports 1, 2, 33 VCC = 4.5 V IOH = –30 µA VCC – 0.7 V VOH1 Output high voltage (port 0 in external bus mode), ALE 9, PSEN3 VCC = 4.5 V IOH = –3.2 mA VCC – 0.7 V IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4 V –1 –75 µA ITL Logical 1-to-0 transition current, ports 1, 2, 36 VIN = 2.0 V See Note 4 –650 µA ILI Input leakage current, port 0 0.45 < VIN < VCC – 0.3 ±10 µA ICC Power supply current (see Figure 25): See Note 5 Active mode (see Note 5) Idle mode (see Note 5) Power-down mode or clock stopped (see Figure 29Tamb = 0°C to 70°C 3 100 µA for conditions) Tamb = –40°C to +85°C 125 µA R RST Internal reset pull-down resistor 40 225 kΩ C IO Pin capacitance10 (except EA) 15 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V OL s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC –0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V. 5. See Figures 26 through 29 for ICC test conditions and Figure 25 for ICC vs Freq. Active mode: ICC(MAX) = (0.56 × FREQ. + 8.0)mA Idle mode: I CC(MAX) = (0.30 × FREQ. +2.0)mA 6. This value applies to Tamb = 0°C to +70°C. 7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80 pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15 mA (*NOTE: This is 85 °C specification.) Maximum IOL per 8-bit port: 26 mA Maximum total IOL for all outputs: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1 , except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF (except EA is 25 pF).

Philips Semiconductors Product data 89C51/89C52/89C54/89C5880C51 8-bit microcontroller family 4K/8K/16K/32K Flash

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AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5 V ±10%, VSS = 0V1, 2, 3 VARIABLE CLOCK 4 33MHz CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 18 Oscillator frequency Speed versions 3.5 33 3.5 33 MHz tLHLL 18 ALE pulse width 2tCLCL –40 21 ns tAVLL 18 Address valid to ALE low tCLCL –25 5 ns tLLAX 18 Address hold after ALE low tCLCL –25 5 ns tLLIV 18 ALE low to valid instruction in 4tCLCL –65 55 ns tLLPL 18 ALE low to PSEN low tCLCL –25 5 ns tPLPH 18 PSEN pulse width 3tCLCL –45 45 ns tPLIV 18 PSEN low to valid instruction in 3tCLCL –60 30 ns tPXIX 18 Input instruction hold after PSEN 0 0 ns tPXIZ 18 Input instruction float after PSEN tCLCL –25 5 ns tAVIV 18 Address to valid instruction in 5tCLCL –80 70 ns tPLAZ 18 PSEN low to address float 10 10 ns Data Memory tRLRH 19, 20 RD pulse width 6tCLCL –100 82 ns tWLWH 19, 20 WR pulse width 6tCLCL –100 82 ns tRLDV 19, 20 RD low to valid data in 5tCLCL –90 60 ns tRHDX 19, 20 Data hold after RD 0 0 ns tRHDZ 19, 20 Data float after RD 2tCLCL –28 32 ns tLLDV 19, 20 ALE low to valid data in 8tCLCL –150 90 ns tAVDV 19, 20 Address to valid data in 9tCLCL –165 105 ns tLLWL 19, 20 ALE low to RD or WR low 3tCLCL –50 3tCLCL +50 40 140 ns tAVWL 19, 20 Address valid to WR low or RD low 4tCLCL –75 45 ns tQVWX 19, 20 Data valid to WR transition tCLCL –30 0 ns tWHQX 19, 20 Data hold after WR tCLCL –25 5 ns tQVWH 20 Data valid to WR high 7tCLCL –130 80 ns tRLAZ 19, 20 RD low to address float 0 0 ns tWHLH 19, 20 RD or WR high to ALE high tCLCL –25 tCLCL +25 5 55 ns External Clock tCHCX 22 High time 17 tCLCL –tCLCX ns tCLCX 22 Low time 17 tCLCL –tCHCX ns tCLCH 22 Rise time 5 ns tCHCL 22 Fall time 5 ns Shift Register tXLXL 21 Serial port clock cycle time 12tCLCL 360 ns tQVXH 21 Output data setup to clock rising edge10tCLCL –133 167 ns tXHQX 21 Output data hold after clock rising edge2tCLCL –80 50 ns tXHDX 21 Input data hold after clock rising edge 0 0 ns tXHDV 21 Clock rising edge to input data valid 10tCLCL –133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are guaranteed to operate down to 0 Hz.

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AVLL = Time for address valid to ALE low. tLLPL =Time for ALE low to PSEN low. Figure 18. External Program Memory Read Cycle Figure 19. External Data Memory Read Cycle

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Figure 20. External Data Memory Write Cycle Figure 21. Shift Register Mode Timing Figure 22. External Clock Drive

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AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Figure 23. AC Testing Input/Output OH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 24. Float Waveform Figure 25. ICC vs. FREQ

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Figure 26. ICC Test Condition, Active Mode Figure 27. ICC Test Condition, Idle Mode Figure 28. Clock Signal Waveform for ICC Tests in Active and Idle Modes Figure 29. ICC Test Condition, Power Down Mode

Philips Semiconductors Product data 89C51/89C52/89C54/89C5880C51 8-bit microcontroller family 4K/8K/16K/32K Flash

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The security feature protects against software piracy and prevents the contents of the FLASH from being read. The Security Lock bits are located in FLASH. The 89C51/89C52/89C54/89C58 has 3 programmable security lock bits that will provide different levels of protection for the on-chip code and data (see Table 8). Unlike the ROM and OTP versions, the security lock bits are independent. LB3 includes the security protection of LB1. Table 8. SECURITY LOCK BITS 1 Level PROTECTION DESCRIPTION LB1 MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. LB2 Program verification is disabled LB3 External execution is disabled. NOTE: 1. The security lock bits are independent.

Philips Semiconductors Product data 89C51/89C52/89C54/89C5880C51 8-bit microcontroller family 4K/8K/16K/32K Flash

2002 Jan 15 35

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

Philips Semiconductors Product data 89C51/89C52/89C54/89C5880C51 8-bit microcontroller family 4K/8K/16K/32K Flash

2002 Jan 15 36

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

Philips Semiconductors Product data 89C51/89C52/89C54/89C5880C51 8-bit microcontroller family 4K/8K/16K/32K Flash

2002 Jan 15 37

LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm SOT389-1

Philips Semiconductors Product data 89C51/89C52/89C54/89C5880C51 8-bit microcontroller family 4K/8K/16K/32K Flash

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REVISION HISTORY

Release date CPCN Modifications to previous release 2002 Jan 15 9397 750 09302 PROGRAMMING ALGORITHM MODIFIED due to process change (see device comparison table). PQFP package replaced by LQFP package (dimensions see end of data sheet). Lower power consumption due to process change. DEVICE COMPARISON TABLE inserted (beginning of data sheet). Selection Table for Flash devices updated and extended. Ordering information table updated. Erase and program cycles increased from 100 to 10,000. 1999 Oct 27 9397 750 06613 Combined data sheet for all four parts (89C51/52/54/58).

Philips Semiconductors Product data 89C51/89C52/89C54/89C5880C51 8-bit microcontroller family 4K/8K/16K/32K Flash

2002 Jan 15 39

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to:  Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 01-02 Document order number: 9397 750 09302 /C0080/C0104/C0105/C0108/C0105/C0112/C0115 /C0083/C0101/C0109/C0105/C0099/C0111/C0110/C0100/C0117/C0099/C0116/C0111/C0114/C0115 Data sheet status[1] Objective data Preliminary data Product data Product status[2] Development Qualification Production Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.