P89C51RD2FA/01

P89C51RD2 PHILIPS | Alldatasheet

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Technical content

/C0080 /C0115 /C0111/C0110/C0111 /C0115 P89C51RA2xx/RB2xx/RC2xx/RD2xx 80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM Preliminary data Supersedes data of 2002 May 20 2002 Jul 18 INTEGRATED CIRCUITS

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

22002 Jul 18

DESCRIPTION

The P89C51RA2/RB2/RC2/RD2xx contains a non-volatile 8KB/16KB/32KB/64KB Flash program memory that is both parallel programmable and serial In-System and In-Application Programmable. In-System Programming (ISP) allows the user to download new code while the microcontroller sits in the application. In-Application Programming (IAP) means that the microcontroller fetches new program code and reprograms itself while in the system. This allows for remote programming over a modem link. A default serial loader (boot loader) program in ROM allows serial In-System programming of the Flash memory via the UART without the need for a loader in the Flash code. For In-Application Programming, the user program erases and reprograms the Flash memory by use of standard routines contained in ROM. The device supports 6-clock/12-clock mode selection by programming a Flash bit using parallel programming or In-System Programming. In addition, an SFR bit (X2) in the clock control register (CKCON) also selects between 6-clock/12-clock mode. Additionally, when in 6-clock mode, peripherals may use either 6 clocks per machine cycle or 12 clocks per machine cycle. This choice is available individually for each peripheral and is selected by bits in the CKCON register. This device is a Single-Chip 8-Bit Microcontroller manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The instruction set is 100% compatible with the 80C51 instruction set. The device also has four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, four-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. The added features of the P89C51RA2/RB2/RC2/RD2xx make it a powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control.

FEATURES

• 80C51 Central Processing Unit
• On-chip Flash Program Memory with In-System Programming (ISP) and In-Application Programming (IAP) capability
• Boot ROM contains low level Flash programming routines for downloading via the UART
• Can be programmed by the end-user application (IAP)
• Parallel programming with 87C51 compatible hardware interface to programmer
• Supports 6-clock/12-clock mode via parallel programmer (default clock mode after ChipErase is 12-clock)
• 6-clock/12-clock mode Flash bit erasable and programmable via ISP
• 6-clock/12-clock mode programmable “on-the-fly” by SFR bit
• Peripherals (PCA, timers, UART) may use either 6-clock or 12-clock mode while the CPU is in 6-clock mode
• Speed up to 20 MHz with 6-clock cycles per machine cycle (40 MHz equivalent performance); up to 33 MHz with 12 clocks per machine cycle
• Fully static operation
• RAM expandable externally to 64 kbytes
• Four interrupt priority levels
• Seven interrupt sources
• Four 8-bit I/O ports
• Full-duplex enhanced UART – Framing error detection – Automatic address recognition
• Power control modes – Clock can be stopped and resumed – Idle mode – Power down mode
• Programmable clock-out pin
• Second DPTR register
• Asynchronous port reset
• Low EMI (inhibit ALE)
• Programmable Counter Array (PCA) – PWM – Capture/compare

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 3

# of Timers PWM PCA WD UART I2C CAN SPI ADC bits/ch. I/O Pins Interrupts (Ext.)/Levels Program Security Default Clock Rate1 Optional Clock Rate1 Reset active low/high? Max. Freq. at 6-clk / 12-clk (MHz) Freq. Range at 3V (MHz) Freq. Range at 5V (MHz) P89C51RD2xx 1K – – 64K 4 √ √ √ √ – – – – 32 7(2)/4 √ 12-clk 6-clk H 20/33 – 0-20/33 P89C51RC2xx 512B – – 32K 4 √ √ √ √ – – – – 32 7(2)/4 √ 12-clk 6-clk H 20/33 – 0-20/33 P89C51RB2xx 512B – – 16K 4 √ √ √ √ – – – – 32 7(2)/4 √ 12-clk 6-clk H 20/33 – 0-20/33 P89C51RA2xx 512B – – 8K 4 √ √ √ √ – – – – 32 7(2)/4 √ 12-clk 6-clk H 20/33 – 0-20/33 NOTE: 1. P89C51Rx2Hxx devices have a 6-clk default clock rate (12-clk optional). Please also see Device Comparison Table. DEVICE COMPARISON TABLE Item 1st generation of Rx2 devices 2nd generation of Rx2 devices (this data sheet) Difference Type description P89C51Rx2 H xx(x) P89C51Rx2xx(x) No more letter ‘H’ Programming algo- rithm When using a parallel programmer, be sure to select P89C51Rx2 H xx(x) devices When using a parallel programmer, be sure to select P89C51Rx2xx(x) de- vices (no more letter ‘H’) Different programming algorithm due to process change Clock mode (I) 6-clk default, OTP configuration bit to program to 12-clk mode using parallel programmer (cannot be programmed back to 6-clk) 12-clk default, Flash configuration bit to program to 6-clk mode using paral- lel programmer or ISP (can be repro- grammed) More flexibility for the end user, more compatibility to older P89C51Rx+ parts Clock mode (II) N/A 6-clock/12-clock mode programmable “on the fly” by SFR bit X2 (CKCON.0) Clock mode can be changed by software Peripheral clock modes N/A Peripherals can be run in 12-clk mode while CPU runs in 6-clk mode More flexibility, lower power con- sumption Flash block structureTwo 8-Kbyte blocks 1–3 16-Kbyte blocks 2–16 4-Kbyte blocks More flexibility

ORDERING INFORMATION

MEMORY TEMPERATURE VOLTAGE FREQUENCY (MHz) PART ORDER NUMBER 1 FLASH RAM RANGE ( °C) AND PACKAGE VOLTAGE RANGE 6-CLOCK MODE 12-CLOCK MODE DWG # 1. P89C51RA2BA/01 8 KB 512 B 0 to +70, PLCC 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2 2. P89C51RA2BBD/01 8 KB 512 B 0 to +70, LQFP 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT389-1 3. P89C51RB2BA/01 16 KB 512 B 0 to +70, PLCC 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2 4. P89C51RB2BBD/01 16 KB 512 B 0 to +70, LQFP 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT389-1 5. P89C51RC2BN/01 32 KB 512 B 0 to +70, PDIP 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT129-1 6. P89C51RC2BA/01 32 KB 512 B 0 to +70, PLCC 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2 7. P89C51RC2FA/01 32 KB 512 B –40 to +85, PLCC 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2 8. P89C51RC2BBD/01 32 KB 512 B 0 to +70, LQFP 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT389-1 9. P89C51RC2FBD/01 32 KB 512 B –40 to +85, LQFP 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT389-1 10. P89C51RD2BN/01 64 KB 1024 B 0 to +70, PDIP 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT129-1 11. P89C51RD2BA/01 64 KB 1024 B 0 to +70, PLCC 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2 12. P89C51RD2BBD/01 64 KB 1024 B 0 to +70, LQFP 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT389-1 13. P89C51RD2FA/01 64 KB 1024 B –40 to +85, PLCC 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2 NOTE: 1. The Part Marking will not include the “/01”.

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 4

(12-CLK MODE, 6-CLK MODE) 8K / 16K / 32K /

64 KBYTE

(PCA) WATCHDOG TIMER

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 5

BLOCK DIAGRAM – CPU ORIENTED SU01065 PSEN EA VPP ALE RST XTAL1 XTAL2 VCC VSS PORT 0 DRIVERS PORT 2 DRIVERS RAM ADDR REGISTER RAM PORT 0 LATCH PORT 2 LATCH FLASH REGISTER B ACC STACK POINTER TMP2 TMP1 ALU TIMING AND CONTROL INSTRUCTION REGISTER PD OSCILLATOR PSW PORT 1 LATCH PORT 3 LATCH PORT 1 DRIVERS PORT 3 DRIVERS PROGRAM ADDRESS REGISTER BUFFER PC INCRE- MENTER PROGRAM COUNTER DPTR’S MULTIPLE SFRs TIMERS P.C.A. 8 16

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 6

Plastic Dual In-Line Package 20 21 40T2/P1.0 T2EX/P1.1 ECI/P1.2 CEX0/P1.3 CEX1/P1.4 CEX2/P1.5 CEX3/P1.6 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 CEX4/P1.7 WR /P3.6 RD /P3.7 XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG EA /VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 V CC DUAL IN-LINE PACKAGE SU00021 Plastic Leaded Chip Carrier LCC 614 0 18 28 Pin Function

1 NIC*

2 P1.0/T2 3 P1.1/T2EX 4 P1.2/ECI 5 P1.3/CEX0 6 P1.4/CEX1 7 P1.5/CEX2 8 P1.6/CEX3 9 P1.7/CEX4

10 RST

11 P3.0/RxD

12 NIC*

13 P3.1/TxD 14 P3.2/INT0 15 P3.3/INT1 Pin Function 16 P3.4/T0 17 P3.5/T1 18 P3.6/WR 19 P3.7/RD

20 XTAL2

21 XTAL1

23 NIC*

24 P2.0/A8 25 P2.1/A9 26 P2.2/A10 27 P2.3/A11 28 P2.4/A12 29 P2.5/A13 30 P2.6/A14 Pin Function 31 P2.7/A15

32 PSEN

33 ALE/PROG

34 NIC*

/VPP 36 P0.7/AD7 37 P0.6/AD6 38 P0.5/AD5 39 P0.4/AD4 40 P0.3/AD3 41 P0.2/AD2 42 P0.1/AD1 43 P0.0/AD0 44 V CC SU00023* NO INTERNAL CONNECTION Plastic Quad Flat Pack LQFP 44 34 12 22 Pin Function 1 P1.5/CEX2 2 P1.6/CEX3 3 P1.7/CEX4

4 RST

5 P3.0/RxD

6 NIC*

7 P3.1/TxD 8 P3.2/INT0 9 P3.3/INT1 10 P3.4/T0 11 P3.5/T1 12 P3.6/WR 13 P3.7/RD

14 XTAL2

15 XTAL1

16 V SS

17 NIC*

18 P2.0/A8 19 P2.1/A9 20 P2.2/A10 21 P2.3/A11 22 P2.4/A12 23 P2.5/A13 24 P2.6/A14 25 P2.7/A15

26 PSEN

27 ALE/PROG

28 NIC*

/VPP 30 P0.7/AD7 Pin Function 31 P0.6/AD6 32 P0.5/AD5 33 P0.4/AD4 34 P0.3/AD3 35 P0.2/AD2 36 P0.1/AD1 37 P0.0/AD0 38 V CC

39 NIC*

40 P1.0/T2 41 P1.1/T2EX 42 P1.2/ECI 43 P1.3/CEX0 44 P1.4/CEX1 SU01400* NO INTERNAL CONNECTION

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 7

TYPE NAME AND FUNCTIONMNEMONIC PDIP PLCC LQFP TYPE NAME AND FUNCTION VSS 20 22 16 I Ground: 0 V reference. VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0–0.7 39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. 1–3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Alternate functions for P89C51RA2/RB2/RC2/RD2xx Port 1 include: 1 2 40 I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout (see Programmable Clock-Out) 2 3 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control 3 4 42 I ECI (P1.2): External Clock Input to the PCA 4 5 43 I/O CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 5 6 44 I/O CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 6 7 1 I/O CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 7 8 2 I/O CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 8 9 3 I/O CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. 13–19 5, 7–13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the P89C51RA2/RB2/RC2/RD2xx, as listed below: 10 11 5 I RxD (P3.0): Serial input port 11 13 7 O TxD (P3.1): Serial output port 12 14 8 I INT0 (P3.2): External interrupt 13 15 9 I INT1 (P3.3): External interrupt 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal resistor to VSS permits a power-on reset using only an external capacitor to VCC . ALE 30 33 27 O Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted twice every machine cycle, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 8

MNEMONIC NAME AND FUNCTIONTYPE PIN NUMBER MNEMONIC NAME AND FUNCTIONTYPE LQFPPLCCPDIP PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA /VPP 31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations. If EA is held high, the device executes from internal program memory. The value on the EA pin is latched when RST is released and any subsequent changes have no effect. This pin also receives the programming supply voltage (VPP ) during Flash programming. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin (other than VPP ) must not be higher than VCC + 0.5 V or less than VSS – 0.5 V.

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Table 1. Special Function Registers # SFRs are modified from or added to the 80C51 SFRs.

1. Reset value depends on reset source.

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Table 1. Special Function Registers (Continued) # SFRs are modified from or added to the 80C51 SFRs. high and low times specified in the data sheet must be observed. standard 80C51 family devices). Also see next page.

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 11

CLOCK CONTROL REGISTER (CKCON) This device provides control of the 6-clock/12-clock mode by means of both an SFR bit (X2) and a Flash bit (FX2, located in the Security Block). The Flash clock control bit, FX2, when programmed (6-clock mode) supercedes the X2 bit (CKCON.0). The CKCON register also provides individual control of the clock rates for the peripherals devices. When running in 6-clock mode each peripheral may be individually clocked from either fosc/6 or fosc/12. When in 12-clock mode, all peripheral devices will use fosc/12. The CKCON register is shown below. BIT SYMBOL FUNCTION CKCON.7 – Reserved. CKCON.6 WDX2 Watchdog clock; 0 = 6 clocks for each WDT clock, 1 = 12 clocks for each WDT clock CKCON.5 PCAX2 PCA clock; 0 = 6 clocks for each PCA clock, 1 = 12 clocks for each PCA clock CKCON.4 SIX2 UART clock; 0 = 6 clocks for each UART clock, 1 = 12 clocks for each UART clock CKCON.3 T2X2 Timer2 clock; 0 = 6 clocks for each Timer2 clock, 1 = 12 clocks for each Timer2 clock CKCON.2 T1X2 Timer1 clock; 0 = 6 clocks for each Timer1 clock, 1 = 12 clocks for each Timer1 clock CKCON.1 T0X2 Timer0 clock; 0 = 6 clocks for each Timer0 clock, 1 = 12 clocks for each Timer0 clock CKCON.0 X2 CPU clock; 1 = 6 clocks for each machine cycle, 0 = 12 clocks for each machine cycle SU01607 T0X2T1X2T2X2SIX2PCAX2WDX2– Not Bit Addressable CKCON Address = 8Fh Reset Value = x0000000B 76543210 Bits 1 through 6 only apply if 6 clocks per machine cycle is chosen (i.e.– Bit 0 = 1). If Bit 0 = 0 (12 clocks per machine cycle) then all peripherals will have 12 clocks per machine cycle as their clock source. Also please note that the clock divider applies to the serial port for modes 0 & 2 (fixed baud rate modes). This is because modes 1 & 3 (variable baud rate modes) use either Timer 1 or Timer 2. Below is the truth table for the peripheral input clock sources. FX2 clock mode bit X2 Peripheral clock mode bit (e.g., T0X2) CPU MODE Peripheral Clock Rate erased 0 x 12-clock (default) 12-clock (default) erased 1 0 6-clock 6-clock erased 1 1 6-clock 12-clock programmed x 0 6-clock 6-clock programmed x 1 6-clock 12-clock RESET A reset is accomplished by holding the RST pin high for at least two machine cycles (12 oscillator periods in 6-clock mode, or 24 oscillator periods in 12-clock mode), while the oscillator is running. To ensure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on V CC and RST must come up at the same time for a proper start-up. Ports 1, 2, and 3 will asynchronously be driven to their reset condition when a voltage above V IH1 (min.) is applied to RST. The value on the EA pin is latched when RST is deasserted and has no further effect.

2002 Jul 18 12

lowest power consumption the Power Down mode is suggested. which starts the processor in the same manner as a power-on reset. on-chip RAM to retain their values. oscillator to restart and stabilize (normally less than 10 ms). one following the instruction that put the device into Power Down. to remain unaffected by the VCC level. two machine cycles before the internal reset algorithm takes control. port pin or to external memory.

1. Pull ALE low while the device is in reset and PSEN is high;
2. Hold ALE low as RST is deactivated.

mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied. A 50% duty cycle clock can be programmed to come out on P1.0.

1. to input the external clock for Timer/Counter 2, or
2. to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a

16 MHz operating frequency in 12-clock mode (122 Hz to 8 MHz in

TR2 (T2CON.2) also must be set to start the timer. taken as a 16-bit unsigned integer. interrupt. This is similar to when it is used as a baud-rate generator. Clock-Out frequency will be the same. Table 2. External Pin Status During Idle and Power-Down Mode

2002 Jul 18 13

in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. ignored. Setting the run flag (TRn) does not clear the registers. preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer 0 as for Timer 1. TH0 now controls the “Timer 1” interrupt. fact, in any application not requiring an interrupt. TMOD.7 “TRn” control pin is set. when cleared Timer “n” is enabled whenever “TRn” control bit is set. TMOD.6 Set for Counter operation (input from “Tn” input pin). 0 0 8048 Timer: “TLn” serves as 5-bit prescaler. 0 1 16-bit Timer/Counter: “THn” and “TLn” are cascaded; there is no prescaler. into “TLn” each time it overflows. 1 1 (Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits. 1 1 (Timer 1) Timer/Counter 1 stopped. Figure 1. Timer/Counter 0/1 Mode Control (TMOD) Register

2002 Jul 18 14

*d = 6 in 6-clock mode; d = 12 in 12-clock mode. Figure 2. Timer/Counter 0/1 Mode 0: 13-Bit Timer/Counter TCON.7 TF1 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. TCON.6 TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter on/off. TCON.5 TF0 Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. TCON.4 TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter on/off. TCON.3 IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. TCON.1 IE0 Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. triggered external interrupts. Figure 3. Timer/Counter 0/1 Control (TCON) Register

2002 Jul 18 15

*d = 6 in 6-clock mode; d = 12 in 12-clock mode. Figure 4. Timer/Counter 0/1 Mode 2: 8-Bit Auto-Reload *d = 6 in 6-clock mode; d = 12 in 12-clock mode. Figure 5. Timer/Counter 0 Mode 3: Two 8-Bit Counters

2002 Jul 18 16

(which vectors to the same location as Timer 2 overflow interrupt. (osc/12 in 12-clock mode).). or down depending on the value of the T2EX pin. generated when either TF2 or EXF2 are 1. In Figure 10 DCEN=1 which enables Timer 2 to count up or down. into the timer registers TL2 and TH2. The external flag EXF2 toggles when Timer 2 underflows or overflows. EXF2 flag does not generate an interrupt in this mode of operation. when either RCLK or TCLK = 1. in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. TR2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer. 1 = External event counter (falling edge triggered).

2 CP/RL 2

Figure 6. Timer/Counter 2 (T2CON) Control Register

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Table 3. Timer 2 Operating Modes

1 X 1 Baud rate generator

• n = 6 in 6-clock mode, or 12 in 12-clock mode.

Figure 7. Timer 2 in Capture Mode T2OE Timer 2 Output Enable bit. DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.

• User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.

Figure 8. Timer 2 Mode (T2MOD) Control Register

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• n = 6 in 6-clock mode, or 12 in 12-clock mode.

Figure 9. Timer 2 in Auto-Reload Mode (DCEN = 0)

• n = 6 in 6-clock mode, or 12 in 12-clock mode.

Figure 10. Timer 2 Auto Reload Mode (DCEN = 1)

2002 Jul 18 19

Note availability of additional external interrupt. Figure 11. Timer 2 in Baud Rate Generator Mode Table 4. Timer 2 Generated Commonly Used Timer 1, the other by Timer 2. in registers RCAP2H and RCAP2L, which are preset by software. The timer can be configured for either “timer” or “counter” operation. In many applications, it is configured for “timer” operation (C/T2=0). RCAP2L taken as a 16-bit unsigned integer. rollover in TH2 does not set TF2, and will not generate an interrupt. will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). can be used as an additional external interrupt, if needed.

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before accessing the Timer 2 or RCAP2 registers. as a timer. Also see Table 6 for set-up of Timer 2 as a counter. Table 5. Timer 2 as a Timer Table 6. Timer 2 as a Counter

1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 21

The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (However, if the first byte still hasn’t been read by the time reception of the second byte is complete, one of the bytes will be lost.) The serial port receive and transmit registers are both accessed at Special Function Register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The serial port can operate in 4 modes: Mode 0: Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received (LSB first). The baud rate is fixed at 1/12 the oscillator frequency in 12-clock mode or 1/6 the oscillator frequency in 6-clock mode. Mode 1: 10 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SCON. The baud rate is variable. Mode 2: 11 bits are transmitted (through TxD) or received (through RxD): start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On Transmit, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency in 12-clock mode or 1/16 or 1/32 the oscillator frequency in 6-clock mode. Mode 3: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that weren’t being addressed leave their SM2s set and go on about their business, ignoring the coming data bytes. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. Serial Port Control Register The serial port control and status register is the Special Function Register SCON, shown in Figure 12. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). Baud Rates The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = Oscillator Frequency / 12 (12-clock mode) or / 6 (6-clock mode). The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Register PCON. If SMOD = 0 (which is the value on reset), and the port pins in 12-clock mode, the baud rate is 1/64 the oscillator frequency. If SMOD = 1, the baud rate is 1/32 the oscillator frequency. In 6-clock mode, the baud rate is 1/32 or 1/16 the oscillator frequency, respectively. Mode 2 Baud Rate = SMOD n /C0032(Oscillator Frequency) Where: n = 64 in 12-clock mode, 32 in 6-clock mode The baud rates in Modes 1 and 3 are determined by the Timer 1 or Timer 2 overflow rate. Using Timer 1 to Generate Baud Rates When Timer 1 is used as the baud rate generator (T2CON.RCLK = 0, T2CON.TCLK = 0), the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: Mode 1, 3 Baud Rate = SMOD n /C0032(Timer 1 Overflow Rate) Where: n = 32 in 12-clock mode, 16 in 6-clock mode The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either “timer” or “counter” operation, and in any of its 3 running modes. In the most typical applications, it is configured for “timer” operation, in the auto-reload mode (high nibble of TMOD = 0010B). In that case the baud rate is given by the formula: Mode 1, 3 Baud Rate = SMOD n /C0032Oscillator Frequency Where: n = 32 in 12-clock mode, 16 in 6-clock mode One can achieve very low baud rates with Timer 1 by leaving the Timer 1 interrupt enabled, and configuring the Timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt to do a 16-bit software reload. Figure 13 lists various commonly used baud rates and how they can be obtained from Timer 1.

2002 Jul 18 22

received. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. modes, in any serial transmission. Must be cleared by software. modes, in any serial reception (except see SM2). Must be cleared by software. Figure 12. Serial Port Control (SCON) Register Figure 13. Timer 1 Generated Commonly Used Baud Rates 1/6 the oscillator frequency (6-clock mode). Mode 0, and associated timing. of the transmit shift are shifted to the right one position. left of the MSB, and all positions to the left of that contain zeros.

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 23

shifted to the left one position. The value that comes in from the right is the value that was sampled at the P3.0 pin at S5P2 of the same machine cycle. As data bits come in from the right, 1s shift out to the left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the RX Control block to do one last shift and load SBUF. At S1P1 of the 10th machine cycle after the write to SCON that cleared RI, RECEIVE is cleared as RI is set. More About Mode 1 Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the 80C51 the baud rate is determined by the Timer 1 or Timer 2 overflow rate. Figure 15 shows a simplified functional diagram of the serial port in Mode 1, and associated timings for transmit receive. Transmission is initiated by any instruction that uses SBUF as a destination register. The “write to SBUF” signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SBUF” signal.) The transmission begins with activation of SEND which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 10th divide-by-16 rollover after “write to SBUF.” Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated.: 1. R1 = 0, and 2. Either SM2 = 0, or the received stop bit = 1. If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in RxD. More About Modes 2 and 3 Eleven bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of 0 or 1. On receive, the 9the data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 (12-clock mode) or 1/16 or 1/32 the oscillator frequency (6-clock mode) the oscillator frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1 or Timer 2. Figures 16 and 17 show a functional diagram of the serial port in Modes 2 and 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register. Transmission is initiated by any instruction that uses SBUF as a destination register. The “write to SBUF” signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SBUF” signal.) The transmission begins with activation of SEND, which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 11th divide-by-16 rollover after “write to SUBF.” Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift register. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of R-D. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1. RI = 0, and 2. Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the RxD input.

2002 Jul 18 24

Figure 14. Serial Port Mode 0

2002 Jul 18 25

Figure 15. Serial Port Mode 1

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Figure 16. Serial Port Mode 2

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Figure 17. Serial Port Mode 3

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 28

In addition to the standard operation the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The UART also fully supports multiprocessor communication as does the standard 80C51 UART. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 18). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 19. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9-bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 20. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are “don’t care”. The SADEN mask can be logically ANDed with the SADDR to create the “Given” address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00X0 Slave 1 SADDR = 1100 0000 SADEN = 1111 1110 Given = 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = 1100 0000 SADEN = 1111 1001 Given = 1100 0XX0 Slave 1 SADDR = 1110 0000 SADEN = 1111 1010 Given = 1110 0X0X Slave 2 SADDR = 1110 0000 SADEN = 1111 1100 Given = 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are trended as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature.

2002 Jul 18 29

frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. Given or Broadcast Address. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. other modes, in any serial transmission. Must be cleared by software. the other modes, in any serial reception (except see SM2). Must be cleared by software. Figure 18. SCON: Serial Port Control Register

2002 Jul 18 30

Figure 19. UART Framing Error Detection – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. Figure 20. UART Multiprocessor Communication, Automatic Address Recognition

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interrupt structure (see Table 7). the IPH register and a description of its bits is shown in Figure 23. priority level interrupt that was stopped will be completed. Table 7. Interrupt Table Enable Bit = 1 enables the interrupt. enabled or disabled by setting or clearing its enable bit. IE.5 ET2 Timer 2 interrupt enable bit. IE.4 ES Serial Port interrupt enable bit. IE.3 ET1 Timer 1 interrupt enable bit. IE.2 EX1 External interrupt 1 enable bit. IE.1 ET0 Timer 0 interrupt enable bit. IE.0 EX0 External interrupt 0 enable bit. Figure 21. IE Registers

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IP.5 PT2 Timer 2 interrupt priority bit. IP.4 PS Serial Port interrupt priority bit. IP.3 PT1 Timer 1 interrupt priority bit. IP.2 PX1 External interrupt 1 priority bit. IP.1 PT0 Timer 0 interrupt priority bit. IP.0 PX0 External interrupt 0 priority bit. Figure 22. IP Registers IPH.5 PT2H Timer 2 interrupt priority bit high. IPH.4 PSH Serial Port interrupt priority bit high. IPH.3 PT1H Timer 1 interrupt priority bit high. IPH.2 PX1H External interrupt 1 priority bit high. IPH.1 PT0H Timer 0 interrupt priority bit high. IPH.0 PX0H External interrupt 0 priority bit high. Figure 23. IPH Registers

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 33

The AO bit (AUXR.0) in the AUXR register when set disables the ALE output unless the CPU needs to perform an off-chip memory access. Reduced EMI Mode AUXR (8EH) 7 6 5432 1 0 AUXR.1 EXTRAM AUXR.0 AO See more detailed description in Figure 38. Dual DPTR The dual DPTR structure (see Figure 24) is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 that allows the program code to switch between them.

• New Register Name: AUXR1#
• SFR Address: A2H
• Reset Value: xxxxxxx0B AUXR1 (A2H) 7 65 43210 – – ENBOOT – GF2 0 – DPS Where: DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1. Select Reg DPS DPTR0 0 DPTR1 1 The DPS bit status should be saved by software when switching between DPTR0 and DPTR1. The GF2 bit is a general purpose user-defined flag. Note that bit 2 is not writable and is always read as a zero. This allows the DPS bit to be quickly toggled simply by executing an INC AUXR1 instruction without affecting the GF2 bit. The ENBOOT bit determines whether the BOOTROM is enabled or disabled. This bit will automatically be set if the status byte is non zero during reset or PSEN is pulled low, ALE floats high, and EA > VIH on the falling edge of reset. Otherwise, this bit will be cleared during reset. DPS DPTR1 DPTR0 DPH (83H) DPL (82H) EXTERNAL DATA MEMORY SU00745A BIT0 AUXR1 Figure 24. DPTR Instructions The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1/bit 0 register. The six instructions that use the DPTR are as follows: INC DPTR Increments the data pointer by 1 MOV DPTR, #data16 Loads the DPTR with a 16-bit constant MOV A, @ A+DPTR Move code byte relative to DPTR to ACC MOVX A, @ DPTR Move external RAM (16-bit address) to ACC MOVX @ DPTR , A Move ACC to external RAM (16-bit address) JMP @ A + DPTR Jump indirect relative to DPTR The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See

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(CEX1), etc. The basic PCA configuration is shown in Figure 25. In the CMOD SFR are three additional bits associated with the PCA. timer overflows. These functions are shown in Figure 26. flags for the PCA timer (CF) and each module (refer to Figure 29). and the module’s capture/compare register. shows the CCAPMn settings for the various PCA functions. these registers are used to control the duty cycle of the output.

16 BITS

Figure 25. Programmable Counter Array (PCA)

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Figure 26. PCA Timer/Counter Figure 27. PCA Interrupt System

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it to be gated off during idle. WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. CPS1 PCA Count Pulse Select bit 1. CPS0 PCA Count Pulse Select bit 0. value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 28. CMOD: PCA Counter Mode Register set. CF may be set by either hardware or software but can only be cleared by software. – Not implemented, reserved for future use*. CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF0 PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 29. CCON: PCA Counter Control Register

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– Not implemented, reserved for future use*. ECOMn Enable Comparator. ECOMn = 1 enables the comparator function. CAPPn Capture Positive, CAPPn = 1 enables positive edge capture. CAPNn Capture Negative, CAPNn = 1 enables negative edge capture. in CCON to be set, flagging an interrupt. PWMn Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. ECCFn Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 30. CCAPMn: PCA Modules Compare/Capture Registers Figure 31. PCA Module Modes (CCAPMn Register) SFR are set then an interrupt will be generated. Refer to Figure 32.

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Figure 32. PCA Capture Mode Figure 33. PCA Compare Mode

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Figure 34. PCA High Speed Output Mode Figure 35. PCA PWM Mode

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Figure 36. PCA Watchdog Timer mode (Module 4 only) still be used for other modes if the watchdog is not needed. generated. This will not cause the RST pin to be driven high.

1. periodically change the compare value so it will never match the
2. periodically change the PCA timer value so it will never match
3. disable the watchdog by clearing the WDTE bit before a match

occurs and then re-enable it. solution is the best option. Figure 37 shows the code for initializing the watchdog timer. WATCHDOG routine in Figure 37.

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; Main program goes here, but CALL WATCHDOG periodically. Figure 37. PCA Watchdog Timer Initialization Code

2002 Jul 18 42

and 256 bytes expanded RAM (ERAM) (768 bytes for the RD2xx).

1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are

directly and indirectly addressable.

1. The Upper 128 bytes of RAM (addresses 80H to FFH) are

indirectly addressable only.

1. The Special Function Registers, SFRs, (addresses 80H to FFH)

are directly addressable only.

1. The 256/768-bytes expanded RAM (ERAM, 00H – 1FFH/2FFH)

with the EXTRAM bit cleared, see Figure 38. physically separate from SFR space. use indirect addressing access the Upper 128 bytes of data RAM. rather than P2 (whose address is 0A0H). data memory in the P89C51RA2/RB2/RC2/89C51RD2. and read timing signals. Refer to Figure 39.

0 ALE is emitted at a constant rate of 1/6 the oscillator frequency (12-clock mode; 1/3 fOSC

1 ALE is active only during off-chip memory access.

0 Internal ERAM access using MOVX @Ri/@DPTR

1 External data memory access. — Not implemented, reserved for future use*. of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 38. AUXR: Auxiliary Register

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128 BYTES

Figure 39. Internal and External Data Memory Address Space with EXTRAM = 0 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. pulse at the RST-pin (see the note below). generate an output RESET pulse at the reset pin (see note below).

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 44

The P89C51RA2/RB2/RC2/RD2xx Flash memory augments EPROM functionality with in-circuit electrical erasure and programming. The Flash can be read and written as bytes. The Chip Erase operation will erase the entire program memory. The Block Erase function can erase any Flash block. In-system programming and standard parallel programming are both available. On-chip erase and write timing generation contribute to a user friendly programming interface. The P89C51RA2/RB2/RC2/RD2xx Flash reliably stores memory contents even after 10,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The P89C51RA2/RB2/RC2/RD2xx uses a +5 V V PP supply to perform the Program/Erase algorithms. FEATURES – IN-SYSTEM PROGRAMMING (ISP) AND IN-APPLICATION PROGRAMMING (IAP)

• Flash EPROM internal program memory with Block Erase.
• Internal 1-kbyte fixed BootROM, containing low-level in-system programming routines and a default serial loader. User program can call these routines to perform In-Application Programming (IAP). The BootROM can be turned off to provide access to the full 64-kbyte Flash memory.
• Boot Vector allows user provided Flash loader code to reside anywhere in the Flash memory space. This configuration provides flexibility to the user.
• Default loader in BootROM allows programming via the serial port without the need for a user provided loader.
• Up to 64-kbyte external program memory if the internal program memory is disabled (EA = 0).
• Programming and erase voltage +5 V (+12 V tolerant).
• Read/Programming/Erase using ISP/IAP: – Byte Programming (8 /C0109s). – Typical quick erase times: Block Erase (4 kbyte) in 3 seconds. Full Chip Erase: – RD2xx (64K) in 11 seconds – RC2 (32K) in 7 seconds – RB2 (16K) in 5 seconds – RA2 (4K) in 4 seconds
• Parallel programming with 87C51 compatible hardware interface to programmer.
• In-system programming (ISP).
• In-application programming (IAP).
• Programmable security for the code in the Flash.
• 10,000 minimum erase/program cycles for each byte.
• 10-year minimum data retention. FLASH PROGRAMMING AND ERASURE In general, there are three methods of erasing or programming of the Flash memory that may be used. First, the Flash may be programmed or erased in the end-user application by calling low-level routines through entry point in the BootROM. The end-user application, though, must be executing code from a different block than the block that is being erased or programmed. Second, the on-chip ISP boot loader may be invoked. This ISP boot loader will, in turn, call low-level routines through the common entry point in the BootROM that can be used by end-user applications. Third, the Flash may be programmed or erased using parallel method by using a commercially available EPROM programmer. The parallel programming method used by these devices is similar to that used by EPROM 87C51, but it is not identical, and the commercially available programmer will need to have support for these devices. FLASH MEMORY SPACES Flash User Code Memory Organization The P89C51RA2/RB2/RC2/RD2xx contains 8KB/16KB/32KB/64KB Flash user code program memory organized into 4-kbyte blocks. ISP and IAP BootROM routines will support the new 4-kbyte block sizes through additional block number assignments while maintaining compatibility with previous 8-kbyte and 16-kbyte block assignments. This memory space is programmable via IAP, ISP, and parallel modes. Status Byte/Boot Vector Block This device includes a 4-kbyte block which contains the Status Byte and Boot Vector (Status Byte Block) . The Status Byte and Boot Vector are programmable via IAP, ISP, and parallel modes. Note that erasing of either the Status Byte and Boot Vector will erase the entire contents of this block. Thus the Status Byte and Boot Vector are erased together but are programmable separately. Security & User Configuration Block This device includes a 4-kbyte block (Security Block) which contains the Security Bits, the 6-clock/12-clock Flash-based clock mode bit FX2, and 4095 user programmable bytes. This block is programmable via IAP, ISP, and parallel modes. Security bits will prevent, as required, parallel programmers from reading or writing, however, IAP or ISP inhibitions will be software controlled. This block may only be erased using full-chip erase functions in ISP, IAP, or parallel mode. This security feature protects against software piracy and prevents the contents of the Flash from being read. The Security bits are located in the Flash. There are three programmable security bits that will provide different levels of protection for the on-chip code and data (See Table 11). The 4095 user programmable bytes are not part of user code memory are intended to be programmed or read through IAP, ISP, or parallel programmer functions. The 6-clock/12-clock Flash-based clock mode bit FX2 will be latched at power-on. This allows the bit to be changed via IAP or ISP and delay taking effect until the next reset. This avoids changing baud rates during ISP operations. Boot ROM When the microcontroller programs its Flash memory, all of the low level details are handled by code that is contained in a 1-kbyte

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1. Default clock mode after ChipErase is set to SFR selection.

Figure 40. Flash Memory Configurations the Boot Vector after erasing and updating the Status Byte.

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Figure 41. In-System Programming with a Minimum of Pins P89C51RA2/RB2/RC2/RD2xx device. of additional expense in components and circuit board area. your application to an external circuit in order to use this feature. allowed to exceed datasheet limits.

1. Direct your browser to the following page:
2. Execute “flashmagic.exe” to install the software

ISP firmware provides auto-echo of received characters. limited to 16 (decimal). ISP commands are summarized in Table 9. program memory is an exception).

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 47

were successfully programmed. For a data record, an “X” indicates that the checksum failed to match, and an “R” character indicates that one of the bytes did not properly program. It is necessary to send a type 02 record (specify oscillator frequency) to the P89C51RA2/RB2/RC2/RD2xx before programming data. The ISP facility was designed to that specific crystal frequencies were not required in order to generate baud rates or time the programming pulses. The user thus needs to provide the P89C51RA2/RB2/RC2/RD2xx with information required to generate the proper timing. Record type 02 is provided for this purpose.

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Table 9. Intel-Hex Records Used by In-System Programming

00 Program Data

01 End of File (EOF), no operation

03 Miscellaneous Write Functions

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

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RECORD TYPE COMMAND/DATA FUNCTION 03 (Cont.) Subfunction Code = 07 (Full Chip Erase) Erases all blocks, security bits, and sets status byte and boot vector to default values ff = 07 ss = don’t care dd = don’t care Example: :0100000307F5 full chip erase Subfunction Code = 0C (Erase 4K Blocks) ff = 0C ss = block code as shown below: Block 0 , 0k~4k , 00H Block 1 , 4k~8k , 10H Block 2 , 8k~12k , 20H (only available on RD2 / RC2 / RB2) Block 3 , 12k~16k , 30H (only available on RD2 / RC2 / RB2) Block 4 , 16k~20k , 40H (only available on RD2 / RC2) Block 5 , 20k~24k , 50H (only available on RD2 / RC2) Block 6 , 24k~28k , 60H (only available on RD2 / RC2) Block 7 , 28k~32k , 70H (only available on RD2 / RC2) Block 8 , 32k~36k , 80H (only available on RD2) Block 9 , 36k~40k , 90H (only available on RD2) Block 10, 40k~44k , A0H (only available on RD2) Block 11, 44k~48k , B0H (only available on RD2) Block 12, 48k~52k , C0H (only available on RD2) Block 13, 52k~56k , D0H (only available on RD2) Block 14, 56k~60k , E0H (only available on RD2) Block 15, 60k~64k , F0H (only available on RD2) Example: :020000030C20CF (Erase 4k block #2) 04 Display Device Data or Blank Check – Record type 04 causes the contents of the entire Flash array to be sent out the serial port in a formatted display. This display consists of an address and the contents of 16 bytes starting with that address. No display of the device contents will occur if security bit 2 has been programmed. Data to the serial port is initiated by the reception of any character and terminated by the reception of any character. General Format of Function 04 :05xxxx04sssseeeeffcc Where: 05 = number of bytes (hex) in record xxxx = required field, but value is a “don’t care” 04 = “Display Device Data or Blank Check” function code ssss = starting address eeee = ending address ff = subfunction 00 = display data 01 = blank check 02 = display data in data block (valid addresses: 0001~0FFFH) cc = checksum Example 1: :0500000440004FFF0069 display 4000–4FFF Example 2: :0500000400000FFF02E7 display data in data block (the data at address 0000 is invalid)

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

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RECORD TYPE COMMAND/DATA FUNCTION

05 Miscellaneous Read Functions (Selection)

General Format of Function 05 :02xxxx05ffsscc Where: 02 = number of bytes (hex) in record xxxx = required field, but value is a “don’t care” 05 = “Miscellaneous Read” function code ffss = subfunction and selection code 0000 = read signature byte – manufacturer id (15H) 0001 = read signature byte – device id # 1 (C2H) 0002 = read signature byte – device id # 2 0003 = read FX2 bit 0080 = read ROM Code Revision 0700 = read security bits 0701 = read status byte 0702 = read boot vector cc = checksum Example 1: :020000050001F8 read signature byte – device id # 1 Example 2: :020000050003F6 read FX2 bit (bit7=0 represent 12–clock mode, bit7=1 represent 6–clock mode) Example 3: :02000005008079 read ROM Code Revision (0A: Rev. A, 0B:Rev. B)

06 Direct Load of Baud Rate

General Format of Function 06 :02xxxx06hhllcc Where: 02 = number of bytes (hex) in record xxxx = required field, but value is a “don’t care” 06 = ”Direct Load of Baud Rate” function code hh = high byte of Timer 2 ll = low byte of Timer 2 cc = checksum Example: :02000006F500F3

07 Program Data in Data Block

:nnaaaa07dd....ddcc Where: nn = number of bytes (hex) in record aaaa = memory address of first byte in record (the valid address:0001~0FFFH) dd....dd = data bytes cc = checksum Example: :10008007AF5F67F0602703E0322CFA92007780C3F6

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to the nearest megahertz. For example, set R0 to 11 for 11.0592 MHz. WDT if the WDT was not running. Table 10. IAP calls

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 52

ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ PROGRAM SECURITY BITS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Parameter: R0 = osc freq (integer) R1 = 05h or R1 = 85h (WDT feed) DPH = 00h DPL = 00h , security bit #1 DPL = 01h , security bit #2 DPL = 02h , security bit #3 Return Parameter: ACC = 00 if pass , !=0 if fail ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ PROGRAM STATUS BYTE ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Parameter: R0 = osc freq (integer) R1 = 06h or R1 = 86h (WDT feed) DPH = 00h DPL = 00H - program status byte ACC = status byte Return Parameter: ACC = 00 if pass , !=0 if fail ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ PROGRAM BOOT VECTOR ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Parameter: R0 = osc freq (integer) R1 = 06h or R1 = 86h (WDT feed) DPH = 00h DPL = 01H - program boot vector ACC = boot vector Return Parameter: ACC = 00 if pass , !=0 if fail ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ PROGRAM 6–CLK/12–CLK CONFIGURATION BIT (New function) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Parameter: R0 = osc freq (integer) R1 = 06h or R1 = 86h (WDT feed) DPH = 00h DPL = 02H - program config bit ACC = 80H (MSB = 6clk/12clk bit) Return Parameter: ACC = 00 if pass , !=0 if fail ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ PROGRAM DATA BLOCK (New function) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Parameter: R0 = osc freq (integer) R1 = 0Dh or R1 = 8Dh (WDT feed) DPTR = address of byte to program (valid addresses = 0001h~0FFFh) ACC = data Return Parameter: ACC = 00 if pass , !=0 if fail ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ READ DEVICE DATA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Parameter: R0 = osc freq (integer) R1 = 03h or R1 = 83h (WDT feed) DPTR = address of byte to read Return Parameter: ACC = value of byte read ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ READ DATA BLOCK (New function) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Parameter: R0 = osc freq (integer) R1 = 0Eh or R1 = 8Eh (WDT feed) DPTR = address of byte to read (valid addresses = 0001h~0FFFh) Return Parameter: ACC = value of byte read ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ READ MANUFACTURER ID ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Parameter: R0 = osc freq (integer) R1 = 00h or R1 = 80h (WDT feed) DPH = 00h DPL = 00h - read manufacturer ID Return Parameter: ACC = value of byte read

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 53

ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ READ DEVICE ID #1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Parameter: R0 = osc freq (integer) R1 = 00h or R1 = 80h (WDT feed) DPH = 00h DPL = 01h - read device ID #1 Return Parameter: ACC = value of byte read ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ READ DEVICE ID #2 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Parameter: R0 = osc freq (integer) R1 = 00h or R1 = 80h (WDT feed) DPH = 00h DPL = 02h - read device ID #2 Return Parameter: ACC = value of byte read ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ READ SECURITY BITS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Parameter: R0 = osc freq (integer) R1 = 07h or R1 = 87h (WDT feed) DPH = 00h DPL = 00h - read lock byte Return Parameter: ACC = value of byte read ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ READ STATUS BYTE ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Parameter: R0 = osc freq (integer) R1 = 07h or R1 = 87h (WDT feed) DPH = 00h DPL = 01h - read status byte Return Parameter: ACC = value of byte read ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ READ BOOT VECTOR ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Parameter: R0 = osc freq (integer) R1 = 07h or R1 = 87h (WDT feed) DPH = 00h DPL = 02h - read boot vector Return Parameter: ACC = value of byte read ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ READ CONFIG (New function) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Parameter: R0 = osc freq (integer) R1 = 00h or R1 = 80h (WDT feed) DPH = 00h DPL = 03h - read config byte Return Parameter: ACC = value of byte read ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ READ REVISION (New function) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Parameter: R0 = osc freq (integer) R1 = 00h or R1 = 80h (WDT feed) DPH = 00h DPL = 80h - read revision of ROM Code Return Parameter: ACC = value of byte read

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 54

The security feature protects against software piracy and prevents the contents of the Flash from being read. The Security Lock bits are located in Flash. The P89C51RA2/RB2/RC2/RD2xx has three programmable security lock bits that will provide different levels of protection for the on-chip code and data (see Table 11). Table 11. SECURITY LOCK BITS 1 PROTECTION DESCRIPTION LEVEL LB1 LB2 LB3 PROTECTION DESCRIPTION 1 0 0 0 MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. 2 1 0 0 Block erase is disabled. Erase or programming of the status byte or boot vector is disabled. 3 1 1 0 Verify of code memory is disabled. 4 1 1 1 External execution is disabled. NOTE: 1. Security bits are independent of each other. Full-chip erase may be performed regardless of the state of the security bits. 2. Any other combination of lock bits is undefined. 3. Setting LBx doesn’t prevent programming of unprogrammed bits.

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 55

ABSOLUTE MAXIMUM RATINGS 1, 2, 3 PARAMETER RATING UNIT Operating temperature under bias 0 to +70 or –40 to +85 °C Storage temperature range –65 to +150 °C Voltage on EA/VPP pin to VSS 0 to +13.0 V Voltage on any other pin to VSS –0.5 to +6.5 V Maximum IOL per I/O pin 15 mA Power dissipation (based on package heat transfer limitations, not device power consumption)1.5 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 56

DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C; VCC = 5 V ± 10%; VSS = 0 V SYMBOL PARAMETER TEST LIMITS UNITSYMBOL PARAMETER CONDITIONS MIN TYP 1 MAX UNIT VIH Input high voltage (ports 0, 1, 2, 3, EA) 0.2VCC +0.9 VCC +0.5 V VIH1 Input high voltage, XTAL1, RST 0.7VCC VCC +0.5 V VOL Output low voltage, ports 1, 2, 38 VCC = 4.5 V IOL = 1.6 mA2 0.4 V VOL1 Output low voltage, port 0, ALE, PSEN7, 8 VCC = 4.5 V IOL = 3.2 mA2 0.45 V VOH Output high voltage, ports 1, 2, 33 VCC = 4.5 V IOH = –30 µA VCC – 0.7 V VOH1 Output high voltage (port 0 in external bus mode), ALE 9, PSEN3 VCC = 4.5 V IOH = –3.2 mA VCC – 0.7 V IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4 V –1 –75 µA ITL Logical 1-to-0 transition current, ports 1, 2, 36 VIN = 2.0 V See Note 4 –650 µA ILI Input leakage current, port 0 0.45 < VIN < VCC – 0.3 ±10 µA ICC Power supply current (see Figure 49): See Note 5 Active mode (see Note 5) Idle mode (see Note 5) Power-down mode or clock stopped (see Fi 55 f diti ) Tamb = 0°C to 70°C < 30 100 µA Figure 55 for conditions) Tamb = –40°C to +85°C < 40 125 µA Programming and erase mode fosc = 20 MHz 60 mA R RST Internal reset pull-down resistor 40 225 kΩ C IO Pin capacitance10 (except EA) 15 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V OL s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC –0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V. 5. See Figures 52 through 55 for ICC test conditions and Figure 49 for ICC vs Freq. Active mode: ICC(MAX) = (10.5 + 0.9 × FREQ.[MHz])mA in 12-clock mode Idle mode: I CC(MAX) = (2.5 + 0.33 × FREQ.[MHz])mA in 12-clock mode 6. This value applies to Tamb = 0°C to +70°C. 7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15 mA (*NOTE: This is 85 °C specification.) Maximum IOL per 8-bit port: 26 mA Maximum total IOL for all outputs: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1 , except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF (except EA is 25 pF).

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 57

AC ELECTRICAL CHARACTERISTICS (12-CLOCK MODE) Tamb = 0 °C to +70 °C or –40 °C to +85 °C; VCC = 5 V ± 10%, VSS = 0 V1, 2, 3 VARIABLE CLOCK 4 33 MHz CLOCK 4 SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 42 Oscillator frequency 0 33 MHz tLHLL 42 ALE pulse width 2tCLCL –40 21 ns tAVLL 42 Address valid to ALE low tCLCL –25 5 ns tLLAX 42 Address hold after ALE low tCLCL –25 5 ns tLLIV 42 ALE low to valid instruction in 4tCLCL –65 55 ns tLLPL 42 ALE low to PSEN low tCLCL –25 5 ns tPLPH 42 PSEN pulse width 3tCLCL –45 45 ns tPLIV 42 PSEN low to valid instruction in 3tCLCL –60 30 ns tPXIX 42 Input instruction hold after PSEN 0 0 ns tPXIZ 42 Input instruction float after PSEN tCLCL –25 5 ns tAVIV 42 Address to valid instruction in 5tCLCL –80 70 ns tPLAZ 42 PSEN low to address float 10 10 ns Data Memory tRLRH 43, 44 RD pulse width 6tCLCL –100 82 ns tWLWH 43, 44 WR pulse width 6tCLCL –100 82 ns tRLDV 43, 44 RD low to valid data in 5tCLCL –90 60 ns tRHDX 43, 44 Data hold after RD 0 0 ns tRHDZ 43, 44 Data float after RD 2tCLCL –28 32 ns tLLDV 43, 44 ALE low to valid data in 8tCLCL –150 90 ns tAVDV 43, 44 Address to valid data in 9tCLCL –165 105 ns tLLWL 43, 44 ALE low to RD or WR low 3tCLCL –50 3tCLCL +50 40 140 ns tAVWL 43, 44 Address valid to WR low or RD low 4tCLCL –75 45 ns tQVWX 43, 44 Data valid to WR transition tCLCL –30 0 ns tWHQX 43, 44 Data hold after WR tCLCL –25 5 ns tQVWH 44 Data valid to WR high 7tCLCL –130 80 ns tRLAZ 43, 44 RD low to address float 0 0 ns tWHLH 43, 44 RD or WR high to ALE high tCLCL –25 tCLCL +25 5 55 ns External Clock tCHCX 46 High time 17 tCLCL –tCLCX ns tCLCX 46 Low time 17 tCLCL –tCHCX ns tCLCH 46 Rise time 5 ns tCHCL 46 Fall time 5 ns Shift Register tXLXL 45 Serial port clock cycle time 12tCLCL 360 ns tQVXH 45 Output data setup to clock rising edge 10tCLCL –133 167 ns tXHQX 45 Output data hold after clock rising edge 2tCLCL –80 50 ns tXHDX 45 Input data hold after clock rising edge 0 0 ns tXHDV 45 Clock rising edge to input data valid 10tCLCL –133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are tested to 3.5 MHz, but guaranteed to operate down to 0 Hz.

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 58

AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE) Tamb = 0 °C to +70 °C or –40 °C to +85 °C; VCC = 5 V ± 10%, VSS = 0 V1, 2, 3 VARIABLE CLOCK 4 20 MHz CLOCK 4 SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 42 Oscillator frequency 0 20 MHz tLHLL 42 ALE pulse width tCLCL –40 10 ns tAVLL 42 Address valid to ALE low 0.5tCLCL –20 5 ns tLLAX 42 Address hold after ALE low 0.5tCLCL –20 5 ns tLLIV 42 ALE low to valid instruction in 2tCLCL –65 35 ns tLLPL 42 ALE low to PSEN low 0.5tCLCL –20 5 ns tPLPH 42 PSEN pulse width 1.5tCLCL –45 30 ns tPLIV 42 PSEN low to valid instruction in 1.5tCLCL –60 15 ns tPXIX 42 Input instruction hold after PSEN 0 0 ns tPXIZ 42 Input instruction float after PSEN 0.5tCLCL –20 5 ns tAVIV 42 Address to valid instruction in 2.5tCLCL –80 45 ns tPLAZ 42 PSEN low to address float 10 10 ns Data Memory tRLRH 43, 44 RD pulse width 3tCLCL –100 50 ns tWLWH 43, 44 WR pulse width 3tCLCL –100 50 ns tRLDV 43, 44 RD low to valid data in 2.5tCLCL –90 35 ns tRHDX 43, 44 Data hold after RD 0 0 ns tRHDZ 43, 44 Data float after RD tCLCL –20 5 ns tLLDV 43, 44 ALE low to valid data in 4tCLCL –150 50 ns tAVDV 43, 44 Address to valid data in 4.5tCLCL –165 60 ns tLLWL 43, 44 ALE low to RD or WR low 1.5tCLCL –50 1.5tCLCL +50 25 125 ns tAVWL 43, 44 Address valid to WR low or RD low 2tCLCL –75 25 ns tQVWX 43, 44 Data valid to WR transition 0.5tCLCL –25 0 ns tWHQX 43, 44 Data hold after WR 0.5tCLCL –20 5 ns tQVWH 44 Data valid to WR high 3.5tCLCL –130 45 ns tRLAZ 43, 44 RD low to address float 0 0 ns tWHLH 43, 44 RD or WR high to ALE high 0.5tCLCL –20 0.5tCLCL +20 5 45 ns External Clock tCHCX 46 High time 20 tCLCL –tCLCX ns tCLCX 46 Low time 20 tCLCL –tCHCX ns tCLCH 46 Rise time 5 ns tCHCL 46 Fall time 5 ns Shift Register tXLXL 45 Serial port clock cycle time 6tCLCL 300 ns tQVXH 45 Output data setup to clock rising edge 5tCLCL –133 117 ns tXHQX 45 Output data hold after clock rising edge tCLCL –30 20 ns tXHDX 45 Input data hold after clock rising edge 0 0 ns tXHDV 45 Clock rising edge to input data valid 5tCLCL –133 117 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

2002 Jul 18 59

AVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low. Figure 42. External Program Memory Read Cycle Figure 43. External Data Memory Read Cycle

2002 Jul 18 60

Figure 44. External Data Memory Write Cycle Figure 45. Shift Register Mode Timing Figure 46. External Clock Drive

2002 Jul 18 61

AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Figure 47. AC Testing Input/Output OH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 48. Float Waveform Figure 49. ICC vs. FREQ

2002 Jul 18 62

AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Figure 50. AC Testing Input/Output and begins to float when a 100mV change from the loaded VOH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 51. Float Waveform

2002 Jul 18 63

Figure 52. ICC Test Condition, Active Mode, Tamb = 25°C. Figure 53. I CC Test Condition, Idle Mode, Tamb = 25°C. Figure 54. Clock Signal Waveform for ICC Tests in Active Figure 55. I CC Test Condition, Power Down Mode.

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 64

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 65

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 66

LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm SOT389-1

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 67

REVISION HISTORY

ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ

2002 July 18

ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 9397 750 10129 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Modified ordering information table ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ

2002 May 20

ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 9397 750 09843 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Initial release

Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

2002 Jul 18 68

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to:  Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 07-02 Document order number: 9397 750 10129 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status[1] Objective data Preliminary data Product data Product status[2] Development Qualification Production Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.