P89C51RC2FA

89C51RB2 PHILIPS | Alldatasheet

Document overview

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Technical content

/C0080 /C0115 /C0111/C0110/C0111 /C0115 89C51RB2/89C51RC2/89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM Preliminary specification IC28 Data Handbook

1999 Sep 23

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

21999 Sep 23

DESCRIPTION

The 89C51RB2/RC2/RD2 device contains a non-volatile 16kB/32kB/64kB Flash program memory that is both parallel programmable and serial In-System and In-Application Programmable. In-System Programming (ISP) allows the user to download new code while the microcontroller sits in the application. In-Application Programming (IAP) means that the microcontroller fetches new program code and reprograms itself while in the system. This allows for remote programming over a modem link. A default serial loader (boot loader) program in ROM allows serial In-System programming of the Flash memory via the UART without the need for a loader in the Flash code. For In-Application Programming, the user program erases and reprograms the Flash memory by use of standard routines contained in ROM. This device executes one machine cycle in 6 clock cycles, hence providing twice the speed of a conventional 80C51. An OTP configuration bit lets the user select conventional 12 clock timing if desired. This device is a Single-Chip 8-Bit Microcontroller manufactured in advanced CMOS process and is a derivative of the 80C51 microcontroller family. The instruction set is 100% compatible with the 80C51 instruction set. The device also has four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, four-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. The added features of the P89C51RB2/RC2/RD2 makes it a powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control.

FEATURES

• 80C51 Central Processing Unit
• On-chip Flash Program Memory with In-System Programming (ISP) and In-Application Programming (IAP) capability
• Boot ROM contains low level Flash programming routines for downloading via the UART
• Can be programmed by the end-user application (IAP)
• 6 clocks per machine cycle operation (standard)
• 12 clocks per machine cycle operation (optional)
• Speed up to 20 MHz with 6 clock cycles per machine cycle (40 MHz equivalent performance); up to 33 MHz with 12 clocks per machine cycle
• Fully static operation
• RAM expandable externally to 64 kB
• 4 level priority interrupt
• 8 interrupt sources
• Four 8-bit I/O ports
• Full-duplex enhanced UART – Framing error detection – Automatic address recognition
• Power control modes – Clock can be stopped and resumed – Idle mode – Power down mode
• Programmable clock out
• Second DPTR register
• Asynchronous port reset
• Low EMI (inhibit ALE)
• Programmable Counter Array (PCA) – PWM – Capture/compare

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23 3

ORDERING INFORMATION

(EXCEPT NORTH AMERICA) PHILIPS NORTH MEMORY TEMPERATURE VOLTAGE FREQUENCY (MHz) AMERICA) PART ORDER NUMBER PART MARKING AMERICA PART ORDER NUMBER FLASH RAM RANGE ( °C) AND PACKAGE VOLTAGE RANGE 6 CLOCK MODE

12 CLOCK

DWG # 1 P89C51RB2HBP P89C51RB2BP 16 kB 512 B 0 to +70, PDIP 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT129-1 2 P89C51RB2HFP P89C51RB2FP 16 kB 512 B –40 to +85, PDIP 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT129-1 3 P89C51RB2HBA P89C51RB2BA 16 kB 512 B 0 to +70, PLCC 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2 4 P89C51RB2HFA P89C51RB2FA 16 kB 512 B –40 to +85, PLCC 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2 5 P89C51RB2HBB P89C51RB2BB 16 kB 512 B 0 to +70, PQFP 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT307-2 6 P89C51RB2HFB P89C51RB2FB 16 kB 512 B –40 to +85, PQFP 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT307-2 7 P89C51RC2HBP P89C51RC2BP 32 kB 512 B 0 to +70, PDIP 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT129-1 8 P89C51RC2HFP P89C51RC2FP 32 kB 512 B –40 to +85, PDIP 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT129-1 9 P89C51RC2HBA P89C51RC2BA 32 kB 512 B 0 to +70, PLCC 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2 10 P89C51RC2HFA P89C51RC2FA 32 kB 512 B –40 to +85, PLCC 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2 11 P89C51RC2HBB P89C51RC2BB 32 kB 512 B 0 to +70, PQFP 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT307-2 12 P89C51RC2HFB P89C51RC2FB 32 kB 512 B –40 to +85, PQFP 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT307-2 13 P89C51RD2HBP P89C51RD2BP 64 kB 1 kB 0 to +70, PDIP 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT129-1 14 P89C51RD2HFP P89C51RD2FP 64 kB 1 kB –40 to +85, PDIP 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT129-1 15 P89C51RD2HBA P89C51RD2BA 64 kB 1 kB 0 to +70, PLCC 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2 16 P89C51RD2HFA P89C51RD2FA 64 kB 1 kB –40 to +85, PLCC 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2 17 P89C51RD2HBB P89C51RD2BB 64 kB 1 kB 0 to +70, PQFP 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT307-2 18 P89C51RD2HFB P89C51RD2FB 64 kB 1 kB –40 to +85, PQFP 4.5–5.5 V 0 to 20 MHz 0 to 33 MHz SOT307-2

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23 4

DPTR’S MULTIPLE SFRs TIMERS P.C.A. 8 16

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23 5

Plastic Dual In-Line Package 20 21 40T2/P1.0 T2EX/P1.1 ECI/P1.2 CEX0/P1.3 CEX1/P1.4 CEX2/P1.5 CEX3/P1.6 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 CEX4/P1.7 WR /P3.6 RD /P3.7 XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG EA /VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 V CC DUAL IN-LINE PACKAGE SU00021 Plastic Leaded Chip Carrier LCC 614 0 18 28 Pin Function

1 NIC*

2 P1.0/T2 3 P1.1/T2EX 4 P1.2/ECI 5 P1.3/CEX0 6 P1.4/CEX1 7 P1.5/CEX2 8 P1.6/CEX3 9 P1.7/CEX4

10 RST

11 P3.0/RxD

12 NIC*

13 P3.1/TxD 14 P3.2/INT0 15 P3.3/INT1 Pin Function 16 P3.4/T0 17 P3.5/T1 18 P3.6/WR 19 P3.7/RD

20 XTAL2

21 XTAL1

23 NIC*

24 P2.0/A8 25 P2.1/A9 26 P2.2/A10 27 P2.3/A11 28 P2.4/A12 29 P2.5/A13 30 P2.6/A14 Pin Function 31 P2.7/A15

32 PSEN

33 ALE/PROG

34 NIC*

/VPP 36 P0.7/AD7 37 P0.6/AD6 38 P0.5/AD5 39 P0.4/AD4 40 P0.3/AD3 41 P0.2/AD2 42 P0.1/AD1 43 P0.0/AD0 44 V CC SU00023* NO INTERNAL CONNECTION Plastic Quad Flat Pack PQFP 44 34 12 22 Pin Function 1 P1.5/CEX2 2 P1.6/CEX3 3 P1.7/CEX4

4 RST

5 P3.0/RxD

6 NIC*

7 P3.1/TxD 8 P3.2/INT0 9 P3.3/INT1 10 P3.4/T0 11 P3.5/T1 12 P3.6/WR 13 P3.7/RD

14 XTAL2

15 XTAL1

16 V SS

17 NIC*

18 P2.0/A8 19 P2.1/A9 20 P2.2/A10 21 P2.3/A11 22 P2.4/A12 23 P2.5/A13 24 P2.6/A14 25 P2.7/A15

26 PSEN

27 ALE/PROG

28 NIC*

/VPP 30 P0.7/AD7 Pin Function 31 P0.6/AD6 32 P0.5/AD5 33 P0.4/AD4 34 P0.3/AD3 35 P0.2/AD2 36 P0.1/AD1 37 P0.0/AD0 38 V CC

39 NIC*

40 P1.0/T2 41 P1.1/T2EX 42 P1.2/ECI 43 P1.3/CEX0 44 P1.4/CEX1 SU00024* NO INTERNAL CONNECTION

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23 6

TYPE NAME AND FUNCTIONMNEMONIC PDIP PLCC PQFP TYPE NAME AND FUNCTION VSS 20 22 16 I Ground: 0 V reference. VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0–0.7 39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. 1–3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins except P1.6 and P1.7 which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Alternate functions for 89C51RB2/RC2/RD2 Port 1 include: 1 2 40 I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout (see Programmable Clock-Out) 2 3 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control 3 4 42 I ECI (P1.2): External Clock Input to the PCA 4 5 43 I/O CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 5 6 44 I/O CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 6 7 1 I/O CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 7 8 2 I/O CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 8 9 3 I/O CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. 13–19 5, 7–13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 89C51RB2/RC2/RD2, as listed below: 10 11 5 I RxD (P3.0): Serial input port 11 13 7 O TxD (P3.1): Serial output port 12 14 8 I INT0 (P3.2): External interrupt 13 15 9 I INT1 (P3.3): External interrupt 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC . ALE 30 33 27 O Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted twice every machine cycle, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23 7

MNEMONIC NAME AND FUNCTIONTYPE PIN NUMBER MNEMONIC NAME AND FUNCTIONTYPE PQFPPLCCPDIP PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA /VPP 31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations. If EA is held high, the device executes from internal program memory. The value on the EA pin is latched when RST is released and any subsequent changes have no effect. This pin also receives the programming supply voltage (VPP ) during Flash programming. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin (other than VPP ) must not be higher than VCC + 0.5 V or less than VSS – 0.5 V.

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Table 1. Special Function Registers # SFRs are modified from or added to the 80C51 SFRs.

1. Reset value depends on reset source.

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Table 1. Special Function Registers (Continued) # SFRs are modified from or added to the 80C51 SFRs. high and low times specified in the data sheet must be observed. cannot be changed back to 6 clock mode. IH1 (min.) is applied to RESET.

1999 Sep 23 10

lowest power consumption the Power Down mode is suggested. which starts the processor in the same manner as a power-on reset. on-chip RAM to retain their values. oscillator to restart and stabilize (normally less than 10 ms). one following the instruction that put the device into Power Down. reset is the result of a power-on or a warm start after powerdown. unaffected by the VCC level.

• When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. ONCE  Mode The ONCE (“On-Circuit Emulation”) Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the device is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied. Programmable Clock-Out A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed: 1. to input the external clock for Timer/Counter 2, or 2. to output a 50% duty cycle clock ranging from 122 Hz to 8 MHz at a 16 MHz operating frequency (61 Hz to 4 MHz in 12 clock mode). To configure the Timer/Counter 2 as a clock generator, bit C/T 2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation: Oscillator Frequency n /C0032(65536RCAP2H, RCAP2L) n = 2 in 6 clock mode 4 in 12 clock mode Where (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will be the same.

Table 2. External Pin Status During Idle and Power-Down Mode

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(which vectors to the same location as Timer 2 overflow interrupt. (osc/12 in 12 clock mode).). or down depending on the value of the T2EX pin. generated when either TF2 or EXF2 are 1. In Figure 5 DCEN=1 which enables Timer 2 to count up or down. into the timer registers TL2 and TH2. The external flag EXF2 toggles when Timer 2 underflows or overflows. EXF2 flag does not generate an interrupt in this mode of operation. when either RCLK or TCLK = 1. in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. TR2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer. 1 = External event counter (falling edge triggered). Figure 1. Timer/Counter 2 (T2CON) Control Register

1999 Sep 23 12

Table 3. Timer 2 Operating Modes

1 X 1 Baud rate generator

• n = 6 in 6 clock mode, or 12 in 12 clock mode.

Figure 2. Timer 2 in Capture Mode T2OE Timer 2 Output Enable bit. DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.

• User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.

Figure 3. Timer 2 Mode (T2MOD) Control Register

1999 Sep 23 13

• n = 6 in 6 clock mode, or 12 in 12 clock mode.

Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0)

• n = 6 in 6 clock mode, or 12 in 12 clock mode.

Figure 5. Timer 2 Auto Reload Mode (DCEN = 1)

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Note availability of additional external interrupt. Figure 6. Timer 2 in Baud Rate Generator Mode Table 4. Timer 2 Generated Commonly Used Timer 1, the other by Timer 2. in registers RCAP2H and RCAP2L, which are preset by software. The timer can be configured for either “timer” or “counter” operation. In many applications, it is configured for “timer” operation (C/T2*=0). at the oscillator frequency in 6 clock mode (OSC /2 in 12 clock mode). RCAP2L taken as a 16-bit unsigned integer. rollover in TH2 does not set TF2, and will not generate an interrupt. will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). can be used as an additional external interrupt, if needed.

1999 Sep 23 15

before accessing the Timer 2 or RCAP2 registers. as a timer. Also see Table 6 for set-up of Timer 2 as a counter. Table 5. Timer 2 as a Timer Table 6. Timer 2 as a Counter

1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23 16

The UART operates in all of the usual modes that are described in the first section of Data Handbook IC20, 80C51-Based 8-Bit Microcontrollers. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The UART also fully supports multiprocessor communication as does the standard 80C51 UART. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 8. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9-bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 9. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are “don’t care”. The SADEN mask can be logically ANDed with the SADDR to create the “Given” address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00X0 Slave 1 SADDR = 1100 0000 SADEN = 1111 1110 Given = 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = 1100 0000 SADEN = 1111 1001 Given = 1100 0XX0 Slave 1 SADDR = 1110 0000 SADEN = 1111 1010 Given = 1110 0X0X Slave 2 SADDR = 1110 0000 SADEN = 1111 1100 Given = 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are trended as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature.

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frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. Given or Broadcast Address. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. other modes, in any serial transmission. Must be cleared by software. the other modes, in any serial reception (except see SM2). Must be cleared by software. Figure 7. SCON: Serial Port Control Register

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Figure 8. UART Framing Error Detection – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. Figure 9. UART Multiprocessor Communication, Automatic Address Recognition

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the IPH register and a description of its bits is shown in Figure 12. priority level interrupt that was stopped will be completed. Table 7. Interrupt Table Enable Bit = 1 enables the interrupt. enabled or disabled by setting or clearing its enable bit. IE.5 ET2 Timer 2 interrupt enable bit. IE.4 ES Serial Port interrupt enable bit. IE.3 ET1 Timer 1 interrupt enable bit. IE.2 EX1 External interrupt 1 enable bit. IE.1 ET0 Timer 0 interrupt enable bit. IE.0 EX0 External interrupt 0 enable bit. Figure 10. IE Registers

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IP.5 PT2 Timer 2 interrupt priority bit. IP.4 PS Serial Port interrupt priority bit. IP.3 PT1 Timer 1 interrupt priority bit. IP.2 PX1 External interrupt 1 priority bit. IP.1 PT0 Timer 0 interrupt priority bit. IP.0 PX0 External interrupt 0 priority bit. Figure 11. IP Registers IPH.5 PT2H Timer 2 interrupt priority bit high. IPH.4 PSH Serial Port interrupt priority bit high. IPH.3 PT1H Timer 1 interrupt priority bit high. IPH.2 PX1H External interrupt 1 priority bit high. IPH.1 PT0H Timer 0 interrupt priority bit high. IPH.0 PX0H External interrupt 0 priority bit high. Figure 12. IPH Registers

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23 21

The AO bit (AUXR.0) in the AUXR register when set disables the ALE output. Reduced EMI Mode AUXR (8EH) 7 6 5432 1 0 AUXR.1 EXTRAM AUXR.0 AO Turns off ALE output. Dual DPTR The dual DPTR structure (see Figure 13) is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 that allows the program code to switch between them.

• New Register Name: AUXR1#
• SFR Address: A2H
• Reset Value: xxxxxxx0B AUXR1 (A2H) 7 65 43210 – – ENBOOT – GF2 0 – DPS Where: DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1. Select Reg DPS DPTR0 0 DPTR1 1 The DPS bit status should be saved by software when switching between DPTR0 and DPTR1. The GF2 bit is a general purpose user-defined flag. Note that bit 2 is not writable and is always read as a zero. This allows the DPS bit to be quickly toggled simply by executing an INC AUXR1 instruction without affecting the GF2 bit. The ENBOOT bit determines whether the BOOTROM is enabled or disabled. This bit will automatically be set if the status byte is non zero during reset or PSEN is pulled low, ALE floats high, and EA > VIH on the falling edge of reset. Otherwise, this bit will be cleared during reset. DPS DPTR1 DPTR0 DPH (83H) DPL (82H) EXTERNAL DATA MEMORY SU00745A BIT0 AUXR1 Figure 13. DPTR Instructions The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1/bit 0 register. The six instructions that use the DPTR are as follows: INC DPTR Increments the data pointer by 1 MOV DPTR, #data16 Loads the DPTR with a 16-bit constant MOV A, @ A+DPTR Move code byte relative to DPTR to ACC MOVX A, @ DPTR Move external RAM (16-bit address) to ACC MOVX @ DPTR , A Move ACC to external RAM (16-bit address) JMP @ A + DPTR Jump indirect relative to DPTR The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See

1999 Sep 23 22

width modulator. Each module has a pin associated with it in port 1. Module 0 is connected to P1.3(CEX0), module 1 to P1.4(CEX1), etc. The basic PCA configuration is shown in Figure 14. In the CMOD SFR are three additional bits associated with the PCA. timer overflows. These functions are shown in Figure 15. flags for the PCA timer (CF) and each module (refer to Figure 18). and the module’s capture/compare register. shows the CCAPMn settings for the various PCA functions. these registers are used to control the duty cycle of the output.

16 BITS

Figure 14. Programmable Counter Array (PCA)

1999 Sep 23 23

Figure 15. PCA Timer/Counter Figure 16. PCA Interrupt System

1999 Sep 23 24

it to be gated off during idle. WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. CPS1 PCA Count Pulse Select bit 1. CPS0 PCA Count Pulse Select bit 0. new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 17. CMOD: PCA Counter Mode Register set. CF may be set by either hardware or software but can only be cleared by software. – Not implemented, reserved for future use*. CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF0 PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 18. CCON: PCA Counter Control Register

1999 Sep 23 25

– Not implemented, reserved for future use*. ECOMn Enable Comparator. ECOMn = 1 enables the comparator function. CAPPn Capture Positive, CAPPn = 1 enables positive edge capture. CAPNn Capture Negative, CAPNn = 1 enables negative edge capture. in CCON to be set, flagging an interrupt. PWMn Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. ECCFn Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 19. CCAPMn: PCA Modules Compare/Capture Registers Figure 20. PCA Module Modes (CCAPMn Register) SFR are set then an interrupt will be generated. Refer to Figure 21.

1999 Sep 23 26

Figure 21. PCA Capture Mode Figure 22. PCA Compare Mode

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Figure 23. PCA High Speed Output Mode Figure 24. PCA PWM Mode

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Figure 25. PCA Watchdog Timer m(Module 4 only) still be used for other modes if the watchdog is not needed. generated. This will not cause the RST pin to be driven high.

1. periodically change the compare value so it will never match the
2. periodically change the PCA timer value so it will never match
3. disable the watchdog by clearing the WDTE bit before a match

occurs and then re-enable it. solution is the best option. Figure 26 shows the code for initializing the watchdog timer. WATCHDOG routine in Figure 26.

1999 Sep 23 29

; Main program goes here, but CALL WATCHDOG periodically. Figure 26. PCA Watchdog Timer Initialization Code

1999 Sep 23 30

256 bytes expanded RAM (ERAM) (768 bytes for the RD2).

1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are

directly and indirectly addressable.

1. The Upper 128 bytes of RAM (addresses 80H to FFH) are

indirectly addressable only.

1. The Special Function Registers, SFRs, (addresses 80H to FFH)

are directly addressable only.

1. The 256/768-bytes expanded RAM (ERAM, 00H – 1FFH/2FFH)

with the EXTRAM bit cleared, see Figure 27. physically separate from SFR space. use indirect addressing access the Upper 128 bytes of data RAM. rather than P2 (whose address is 0A0H). timing signals. Refer to Figure 28. 0 ALE is emitted at a constant rate of 1/3 the oscillator frequency (6 clock mode; 1/6 fOSC in 12 clock mode). 1 ALE is active only during a MOVX or MOVC instruction.

0 Internal ERAM access using MOVX @Ri/@DPTR

1 External data memory access. — Not implemented, reserved for future use*. bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 27. AUXR: Auxiliary Register

1999 Sep 23 31

128 BYTES

Figure 28. Internal and External Data Memory Address Space with EXTRAM = 0 output reset HIGH pulse at the RST-pin (see the note below). should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

of this specification is not implied.

1. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
2. Programming is guaranteed from 0°C to Tmax for all devices.

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

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DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C; 5 V ±10%; VSS = 0 V SYMBOL PARAMETER TEST LIMITS UNITSYMBOL PARAMETER CONDITIONS MIN TYP 1 MAX UNIT VIH Input high voltage (ports 0, 1, 2, 3, EA) 0.2VCC +0.9 VCC +0.5 V VIH1 Input high voltage, XTAL1, RST 0.7VCC VCC +0.5 V VOL Output low voltage, ports 1, 2, 38 VCC = 4.5 V IOL = 1.6 mA2 0.4 V VOL1 Output low voltage, port 0, ALE, PSEN7, 8 VCC = 4.5 V IOL = 3.2 mA2 0.4 V VOH Output high voltage, ports 1, 2, 33 VCC = 4.5 V IOH = –30 µA VCC – 0.7 V VOH1 Output high voltage (port 0 in external bus mode), ALE 9, PSEN3 VCC = 4.5 V IOH = –3.2 mA VCC – 0.7 V IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4 V –1 –75 µA ITL Logical 1-to-0 transition current, ports 1, 2, 36 VIN = 2.0 V See Note 4 –650 µA ILI Input leakage current, port 0 0.45 < VIN < VCC – 0.3 ±10 µA ICC Power supply current (see Figure 36): See Note 5 Active mode (see Note 5) Idle mode (see Note 5) Power-down mode or clock stopped (see Fi 42 f diti ) Tamb = 0°C to 70°C <1 40 µA Figure 42 for conditions) Tamb = –40°C to +85°C 50 µA R RST Internal reset pull-down resistor 40 225 kΩ C IO Pin capacitance10 (except EA) 15 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOL s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC –0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V. 5. See Figures 39 through 42 for ICC test conditions and Figure 36 for ICC vs Freq. 6. This value applies to Tamb = 0°C to +70°C. 7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15 mA (*NOTE: This is 85 °C specification.) Maximum IOL per 8-bit port: 26 mA Maximum total IOL for all outputs: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1 , except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF (except EA is 25 pF). 11. Programming is guaranteed from 0°C to Tmax for all devices.

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23 33

AC ELECTRICAL CHARACTERISTICS (6 CLOCK MODE) Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5 V ±10%, VSS = 0V1, 2, 3 VARIABLE CLOCK 4 20 MHz CLOCK 4 SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 29 Oscillator frequency 0 20 0 20 MHz tLHLL 29 ALE pulse width tCLCL –40 10 ns tAVLL 29 Address valid to ALE low 0.5tCLCL –20 5 ns tLLAX 29 Address hold after ALE low 0.5tCLCL –20 5 ns tLLIV 29 ALE low to valid instruction in 2tCLCL –65 35 ns tLLPL 29 ALE low to PSEN low 0.5tCLCL –20 5 ns tPLPH 29 PSEN pulse width 1.5tCLCL –45 30 ns tPLIV 29 PSEN low to valid instruction in 1.5tCLCL –60 15 ns tPXIX 29 Input instruction hold after PSEN 0 0 ns tPXIZ 29 Input instruction float after PSEN 0.5tCLCL –20 5 ns tAVIV 29 Address to valid instruction in 2.5tCLCL –80 45 ns tPLAZ 29 PSEN low to address float 10 10 ns Data Memory tRLRH 30, 31 RD pulse width 3tCLCL –100 50 ns tWLWH 30, 31 WR pulse width 3tCLCL –100 50 ns tRLDV 30, 31 RD low to valid data in 2.5tCLCL –90 35 ns tRHDX 30, 31 Data hold after RD 0 0 ns tRHDZ 30, 31 Data float after RD tCLCL –20 5 ns tLLDV 30, 31 ALE low to valid data in 4tCLCL –150 50 ns tAVDV 30, 31 Address to valid data in 4.5tCLCL –165 60 ns tLLWL 30, 31 ALE low to RD or WR low 1.5tCLCL –50 1.5tCLCL +50 25 125 ns tAVWL 30, 31 Address valid to WR low or RD low 2tCLCL –75 25 ns tQVWX 30, 31 Data valid to WR transition 0.5tCLCL –25 0 ns tWHQX 30, 31 Data hold after WR 0.5tCLCL –20 5 ns tQVWH 31 Data valid to WR high 3.5tCLCL –130 45 ns tRLAZ 30, 31 RD low to address float 0 0 ns tWHLH 30, 31 RD or WR high to ALE high 0.5tCLCL –20 0.5tCLCL +20 5 45 ns External Clock tCHCX 33 High time 20 tCLCL –tCLCX ns tCLCX 33 Low time 20 tCLCL –tCHCX ns tCLCH 33 Rise time 5 ns tCHCL 33 Fall time 5 ns Shift Register tXLXL 32 Serial port clock cycle time 6tCLCL 300 ns tQVXH 32 Output data setup to clock rising edge 5tCLCL –133 117 ns tXHQX 32 Output data hold after clock rising edge tCLCL –30 20 ns tXHDX 32 Input data hold after clock rising edge 0 0 ns tXHDV 32 Clock rising edge to input data valid 5tCLCL –133 117 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23 34

AC ELECTRICAL CHARACTERISTICS (12 CLOCK MODE) Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5 V ±10%, VSS = 0 V1, 2, 3 VARIABLE CLOCK 4 33 MHz CLOCK 4 SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 29 Oscillator frequency 0 33 0 33 MHz tLHLL 29 ALE pulse width 2tCLCL –40 21 ns tAVLL 29 Address valid to ALE low tCLCL –25 5 ns tLLAX 29 Address hold after ALE low tCLCL –25 5 ns tLLIV 29 ALE low to valid instruction in 4tCLCL –65 55 ns tLLPL 29 ALE low to PSEN low tCLCL –25 5 ns tPLPH 29 PSEN pulse width 3tCLCL –45 45 ns tPLIV 29 PSEN low to valid instruction in 3tCLCL –60 30 ns tPXIX 29 Input instruction hold after PSEN 0 0 ns tPXIZ 29 Input instruction float after PSEN tCLCL –25 5 ns tAVIV 29 Address to valid instruction in 5tCLCL –80 70 ns tPLAZ 29 PSEN low to address float 10 10 ns Data Memory tRLRH 30, 31 RD pulse width 6tCLCL –100 82 ns tWLWH 30, 31 WR pulse width 6tCLCL –100 82 ns tRLDV 30, 31 RD low to valid data in 5tCLCL –90 60 ns tRHDX 30, 31 Data hold after RD 0 0 ns tRHDZ 30, 31 Data float after RD 2tCLCL –28 32 ns tLLDV 30, 31 ALE low to valid data in 8tCLCL –150 90 ns tAVDV 30, 31 Address to valid data in 9tCLCL –165 105 ns tLLWL 30, 31 ALE low to RD or WR low 3tCLCL –50 3tCLCL +50 40 140 ns tAVWL 30, 31 Address valid to WR low or RD low 4tCLCL –75 45 ns tQVWX 30, 31 Data valid to WR transition tCLCL –30 0 ns tWHQX 30, 31 Data hold after WR tCLCL –25 5 ns tQVWH 31 Data valid to WR high 7tCLCL –130 80 ns tRLAZ 30, 31 RD low to address float 0 0 ns tWHLH 30, 31 RD or WR high to ALE high tCLCL –25 tCLCL +25 5 55 ns External Clock tCHCX 33 High time 17 tCLCL –tCLCX ns tCLCX 33 Low time 17 tCLCL –tCHCX ns tCLCH 33 Rise time 5 ns tCHCL 33 Fall time 5 ns Shift Register tXLXL 32 Serial port clock cycle time 12tCLCL 360 ns tQVXH 32 Output data setup to clock rising edge 10tCLCL –133 167 ns tXHQX 32 Output data hold after clock rising edge 2tCLCL –80 50 ns tXHDX 32 Input data hold after clock rising edge 0 0 ns tXHDV 32 Clock rising edge to input data valid 10tCLCL –133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are tested to 3.5 MHz, but guaranteed to operate down to 0 Hz.

1999 Sep 23 35

AVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low. Figure 29. External Program Memory Read Cycle Figure 30. External Data Memory Read Cycle

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Figure 31. External Data Memory Write Cycle Figure 32. Shift Register Mode Timing Figure 33. External Clock Drive

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AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Figure 34. AC Testing Input/Output OH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 35. Float Waveform Figure 36. ICC vs. FREQ AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Figure 37. AC Testing Input/Output

1999 Sep 23 38

and begins to float when a 100mV change from the loaded VOH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 38. Float Waveform Figure 39. ICC Test Condition, Active Mode. Figure 40. ICC Test Condition, Idle Mode. Figure 41. Clock Signal Waveform for ICC Tests in Active Figure 42. ICC Test Condition, Power Down Mode.

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23 39

The 89C51RB2/RC2/RD2 Flash memory augments EPROM functionality with in-circuit electrical erasure and programming. The Flash can be read and written as bytes. The Chip Erase operation will erase the entire program memory. The Block Erase function can erase any Flash block. In-system programming and standard parallel programming are both available. On-chip erase and write timing generation contribute to a user friendly programming interface. The 89C51RB2/RC2/RD2 Flash reliably stores memory contents even after 1000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The 89C51RB2/RC2/RD2 uses a +5 V V PP supply to perform the Program/Erase algorithms.

• Flash EPROM internal program memory with Block Erase.
• Internal 1 kB fixed boot ROM, containing low-level in-system programming routines and a default serial loader. User program can call these routines to perform In-Application Programming (IAP). The Boot ROM can be turned off to provide access to the full 64 kB Flash memory.
• Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space. This configuration provides flexibility to the user.
• Default loader in Boot ROM allows programming via the serial port without the need for a user provided loader.
• Up to 64 kB external program memory if the internal program memory is disabled (EA = 0).
• Programming and erase voltage +5 V or +12 V.
• Read/Programming/Erase: – Byte-wise read (100 ns access time). – Byte Programming (20 /C0109s). – Typical erase times: Block Erase (8 kB or 16 kB) in 3 seconds. Full Erase (64 kB) in 3 seconds.
• Parallel programming with 87C51 compatible hardware interface to programmer.
• In-system programming.
• Programmable security for the code in the Flash.
• 1000 minimum erase/program cycles for each byte.
• 10-year minimum data retention. CAPABILITIES OF THE PHILIPS 89C51 FLASH-BASED MICROCONTROLLERS Flash organization The 89C51RB2/RC2/RD2 contains 16KB/32KB/64Kbytes of Flash program memory. This memory is organized as 5 separate blocks. The first two blocks are 8 kB in size, filling the program memory space from address 0 through 3FFF hex. The final three blocks are 16 kB in size and occupy addresses from 4000 through FFFF hex. Figure 43 depicts the Flash memory configurations. Flash Programming and Erasure There are three methods of erasing or programming of the Flash memory that may be used. First, the Flash may be programmed or erased in the end-user application by calling low-level routines through a common entry point in the Boot ROM. The end-user application, though, must be executing code from a different block than the block that is being erased or programmed. Second, the on-chip ISP boot loader may be invoked. This ISP boot loader will, in turn, call low-level routines through the same common entry point in the Boot ROM that can be used by the end-user application. Third, the Flash may be programmed or erased using the parallel method by using a commercially available EPROM programmer. The parallel programming method used by these devices is similar to that used by EPROM 87C51, but it is not identical, and the commercially available programmer will need to have support for these devices. Boot ROM When the microcontroller programs its own Flash memory, all of the low level details are handled by code that is permanently contained in a 1 kB Boot ROM that is separate from the Flash memory. A user program simply calls the common entry point with appropriate parameters in the Boot ROM to accomplish the desired operation. Boot ROM operations include things like: erase block, program byte, verify byte, program security lock bit, etc. The Boot ROM overlays the program memory space at the top of the address space from FC00 to FFFF hex, when it is enabled. The Boot ROM may be turned off so that the upper 1 kB of Flash program memory are accessible for execution.

1999 Sep 23 40

Figure 43. Flash Memory Configurations the 89C51RB2/RC2/RD2 examines the contents of the Status Byte. written with the Boot Vector set to the custom boot loader.

1999 Sep 23 41

Figure 44. In-System Programming with a Minimum of Pins of additional expense in components and circuit board area. your application to an external circuit in order to use this feature. allowed to exceed datasheet limits. firmware provides auto-echo of received characters. be added to indicate either commands or data for the ISP facility. (decimal). ISP commands are summarized in Table 8. 89C51RB2/RC2/RD2 before programming data. proper timing. Record type 02 is provided for this purpose. (www.semiconductors.philips.com) for additional information.

1999 Sep 23 42

Table 8. Intel-Hex Records Used by In-System Programming

00 Program Data

01 End of File (EOF), no operation

02 Specify Oscillator Frequency

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23 43

RECORD TYPE COMMAND/DATA FUNCTION

03 Miscellaneous Write Functions

:nnxxxx03ffssddcc Where: nn = number of bytes (hex) in record xxxx = required field, but value is a “don’t care” 03 = Write Function ff = subfunction code ss = selection code dd = data input (as needed) cc = checksum Subfunction Code = 01 (Erase Blocks) ff = 01 ss = block code as shown below: block 0, 0k to 8k, 00H block 1, 8k to 16k, 20H block 2, 16k to 32k, 40H block 3, 32k to 48k, 80H block 4, 48k to 64k, C0H Example: :0200000301C03A erase block 4 Subfunction Code = 04 (Erase Boot Vector and Status Byte) ff = 04 ss = don’t care dd = don’t care Example: :020000030400F7 erase boot vector and status byte Subfunction Code = 05 (Program Security Bits) ff = 05 ss = 00 program security bit 1 (inhibit writing to Flash) 01 program security bit 2 (inhibit Flash verify) 02 program security bit 3 (disable eternal memory) Example: :020000030501F5 program security bit 2 Subfunction Code = 06 (Program Status Byte or Boot Vector) ff = 06 ss = 00 program status byte 01 program boot vector Example: :030000030601FCF7 program boot vector with 0FCH Subfunction Code = 07 (Full Chip Erase) Erases all blocks, security bits, and sets status and boot vector to default values ff = 07 ss = don’t care dd = don’t care Example: :0100000307F5 full chip erase 04 Display Device Data or Blank Check – Record type 04 causes the contents of the entire Flash array to be sent out the serial port in a formatted display. This display consists of an address and the contents of 16 bytes starting with that address. No display of the device contents will occur if security bit 2 has been programmed. The dumping of the device data to the serial port is terminated by the reception of any character. General Format of Function 04 :05xxxx04sssseeeeffcc Where: 05 = number of bytes (hex) in record xxxx = required field, but value is a “don’t care” 04 = “Display Device Data or Blank Check” function code ssss = starting address eeee = ending address ff = subfunction 00 = display data 01 = blank check cc = checksum Example: :0500000440004FFF0069 display 4000–4FFF

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23 44

RECORD TYPE COMMAND/DATA FUNCTION

05 Miscellaneous Read Functions

General Format of Function 05 :02xxxx05ffsscc Where: 02 = number of bytes (hex) in record xxxx = required field, but value is a “don’t care” 05 = “Miscellaneous Read” function code ffss = subfunction and selection code 0000 = read signature byte – manufacturer id (15H) 0001 = read signature byte – device id # 1 (C2H) 0002 = read signature byte – device id # 2 0700 = read security bits 0701 = read status byte 0702 = read boot vector cc = checksum Example: :020000050001F8 read signature byte – device id # 1

06 Direct Load of Baud Rate

General Format of Function 06 :02xxxx06hhllcc Where: 02 = number of bytes (hex) in record xxxx = required field, but value is a “don’t care” 06 = ”Direct Load of Baud Rate” function code hh = high byte of Timer 2 ll = low byte of Timer 2 cc = checksum Example: :02000006F50003

1999 Sep 23 45

to the nearest megahertz. For example, set R0 to 11 for 11.0592 MHz. Table 9. IAP calls

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23 46

READ MANUFACTURER ID Input Parameters: R0 = osc freq (integer) R1 = 00h DPH = 00h DPL = 00h (manufacturer ID) Return Parameter ACC = value of byte read READ DEVICE ID # 1 Input Parameters: R0 = osc freq (integer) R1 = 00h DPH = 00h DPL = 01h (device ID # 1) Return Parameter ACC = value of byte read READ DEVICE ID # 2 Input Parameters: R0 = osc freq (integer) R1 = 00h DPH = 00h DPL = 02h (device ID # 2) Return Parameter ACC = value of byte read READ SECURITY BITS Input Parameters: R0 = osc freq (integer) R1 = 07h DPH = 00h DPL = 00h (security bits) Return Parameter ACC = value of byte read READ STATUS BYTE Input Parameters: R0 = osc freq (integer) R1 = 07h DPH = 00h DPL = 01h (status byte) Return Parameter ACC = value of byte read READ BOOT VECTOR Input Parameters: R0 = osc freq (integer) R1 = 07h DPH = 00h DPL = 02h (boot vector) Return Parameter ACC = value of byte read FULL CHIP ERASE Input Parameters: R0 = osc frequency R1 = 08h DPH = don’t care DPL = don’t care Return Parameter none

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23 47

The security feature protects against software piracy and prevents the contents of the Flash from being read. The Security Lock bits are located in Flash. The 89C51RB2/RC2/RD2 has 3 programmable security lock bits that will provide different levels of protection for the on-chip code and data (see Table 10). Table 10. SECURITY LOCK BITS 1 PROTECTION DESCRIPTION LB1 LB2 LB3 PROTECTION DESCRIPTION X X X MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. 1 X X Block erase is disabled. Erase or programming of the status byte or boot vector is disabled. X 1 X Verify of code memory is disabled. X X 1 External execution is disabled. NOTE: 1. Security bits are independent of each other. Full-chip erase may be performed regardless of the state of the security bits.

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23 48

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23 49

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23 50

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23 51

Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23 52

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 09-99 Document order number: 9397–750–06427 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.