P87LPC764HDH

P87LPC764BN112 PHILIPS | Alldatasheet

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Technical content

/C0080 /C0115 /C0111/C0110/C0111 /C0115 P87LPC764 Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP Product data Supersedes data of 2001 Oct 26

2003 Sep 03

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

12003 Sep 03 853-2401 30269

The P87LPC764 is a 20-pin single-chip microcontroller designed for low pin count applications demanding high-integration, low cost solutions over a wide range of performance requirements. A member of the Philips low pin count family, the P87LPC764 offers programmable oscillator configurations for high and low speed crystals or RC operation, wide operating voltage range, programmable port output configurations, selectable Schmitt trigger inputs, LED drive outputs, and a built-in watchdog timer. The P87LPC764 is based on an accelerated 80C51 processor architecture that executes instructions at twice the rate of standard 80C51 devices.

FEATURES

• An accelerated 80C51 CPU provides instruction cycle times of 300–600 ns for all instructions except multiply and divide when executing at 20 MHz. Execution at up to 20 MHz when V
• 4.5 V to 5.5 V for P87LPC764HDH.
• 2.7 V to 6.0 V operating range for digital functions.
• 4 kbytes EPROM code memory.
• 128 byte RAM data memory.
• 32 byte customer code EPROM allows serialization of devices, storage of setup parameters, etc.
• Two 16-bit counter/timers. Each timer may be configured to toggle a port output upon timer overflow.
• Two analog comparators.
• Full duplex UART.
• I2C communication port.
• Eight keypad interrupt inputs, plus two additional external interrupt inputs.
• Four interrupt priority levels.
• Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog timeout time is selectable from 8 values.
• Active low reset. On-chip power-on reset allows operation with no external reset components.
• Low voltage reset. One of two preset low voltage levels may be selected to allow a graceful system shutdown when power fails. May optionally be configured as an interrupt.
• Oscillator Fail Detect. The watchdog timer has a separate fully on-chip oscillator, allowing it to perform an oscillator fail detect function.
• Configurable on-chip oscillator with frequency range and RC oscillator options (selected by user programmed EPROM bits). The RC oscillator option allows operation with no external oscillator components.
• Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only.
• Selectable Schmitt trigger port inputs.
• LED drive capability (20 mA) on all port pins.
• Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times.
• 15 I/O pins minimum. Up to 18 I/O pins using on-chip oscillator and reset options.
• Only power and ground connections are required to operate the P87LPC764 when fully on-chip oscillator and reset options are selected.
• Serial EPROM programming allows simple in-circuit production coding. Two EPROM security bits prevent reading of sensitive application programs.
• Idle and Power Down reduced power modes. Improved wakeup from Power Down mode (a low interrupt input starts execution). Typical Power Down current is 1 µA.
• 20-pin DIP, SO, and TSSOP packages.

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 2

ORDERING INFORMATION

Name Description Frequency Temperature Range (°C) Version P87LPC764BD/01 SO20 plastic small outline package; 20 leads; body width 7.5 mm

20 MHz (5 V),

10 MHz (3 V)

P87LPC764BD SO20 plastic small outline package; 20 leads; body width 7.5 mm P87LPC764BDH/01 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm

20 MHz (5 V)

P87LPC764BDH TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm P87LPC764BN DIP20 plastic dual in-line package; 20 leads (300 mil)20 MHz (5 V), P87LPC764FN DIP20 plastic dual in-line package; 20 leads (300 mil)20 MHz (5 V), –40 to +85 SOT146-1 P87LPC764FD SO20 plastic small outline package; 20 leads; body width 7.5 mm –40 to +85 SOT163-1 P87LPC764FDH TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm –40 to +85 SOT360-1 P87LPC764HDH TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm

16 MHz (5 V) –40 to +125 SOT360-1

Part type Internal RC oscillator P87LPC764BD/01, BDH/01 ±2.5% to 5% P87LPC764BDH, HDH ±10% P87LPC764BD, BN, FN, FD, FDH ±25% NOTE: 1. Please see AC and DC characteristics for more details. PIN CONFIGURATION, 20-PIN DIP, SO, AND TSSOP PACKAGES SU01149 20CMP2/P0.0 P1.7 P1.6 RST /P1.5 VSS X1/P2.1 X2/CLKOUT/P2.0 INT1/P1.4 SDA/INT0/P1.3 SCL/T0/P1.2 P0.1/CIN2B P0.2/CIN2A P0.3/CIN1B P0.4/CIN1A P0.5/CMPREF VDD P0.6/CMP1 P1.0/TxD P0.7/T1 P1.1/RxD10

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 3

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 4

TIMER 0, 1 I2C UART ACCELERATED 80C51 CPU WATCHDOG TIMER AND OSCILLATOR PORT 0 CONFIGURABLE I/OS

128 BYTE

(POWER-ON RESET, BROWNOUT RESET) CONFIGURABLE OSCILLATORCRYSTAL OR RESONATOR ON-CHIP RC OSCILLATOR

2003 Sep 03 5

4 K BYTES ON-CHIP

128 BYTES ON-CHIP DATA

are accessed via the MOVX instruction as if they were in external data memory. Figure 1. P87LPC764 Program and Data Memory Map

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 6

MNEMONIC PIN NO. TYPE NAME AND FUNCTION 16–20 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. Port 0 latches are configured in the quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined by the PRHI bit in the UCFG1 configuration byte. The operation of port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. The Keyboard Interrupt feature operates with port 0 pins. Port 0 also provides various special functions as described below. 1 O P0.0 CMP2 Comparator 2 output. 20 I P0.1 CIN2B Comparator 2 positive input B. 19 I P0.2 CIN2A Comparator 2 positive input A. 18 I P0.3 CIN1B Comparator 1 positive input B. 17 I P0.4 CIN1A Comparator 1 positive input A. 16 I P0.5 CMPREF Comparator reference (negative) input. 14 O P0.6 CMP1 Comparator 1 output. 13 I/O P0.7 T1 Timer/counter 1 external count input or overflow output. P1.0–P1.7 2–4, 8–12 I/O Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for three pins as noted below. Port 1 latches are configured in the quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined by the PRHI bit in the UCFG1 configuration byte. The operation of the configurable port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. Port 1 also provides various special functions as described below. 12 O P1.0 TxD Transmitter output for the serial port. 11 I P1.1 RxD Receiver input for the serial port.

10 I/O

P1.2 T0 Timer/counter 0 external count input or overflow output. SCL I2C serial clock input/output. When configured as an output, P1.2 is open drain, in order to conform to I2C specifications. 9 I I/O P1.3 INT0 External interrupt 0 input. SDA I2C serial data input/output. When configured as an output, P1.3 is open drain, in order to conform to I2C specifications. 8 I P1.4 INT1 External interrupt 1 input. 4 I P1.5 RST External Reset input (if selected via EPROM configuration). A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. When used as a port pin, P1.5 is a Schmitt trigger input only. P2.0–P2.1 6, 7 I/O Port 2: Port 2 is a 2-bit I/O port with a user-configurable output type. Port 2 latches are configured in the quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined by the PRHI bit in the UCFG1 configuration byte. The operation of port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. Port 2 also provides various special functions as described below. 7 O P2.0 X2 Output from the oscillator amplifier (when a crystal oscillator option is selected via the EPROM configuration). CLKOUT CPU clock divided by 6 clock output when enabled via SFR bit and in conjunction with internal RC oscillator or external clock input. 6 I P2.1 X1 Input to the oscillator circuit and internal clock generator circuits (when selected via the EPROM configuration). VSS 5 I Ground : 0V reference. VDD 15 I Power Supply: This is the power supply voltage for normal operation as well as Idle and Power Down modes.

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 7

SPECIAL FUNCTION REGISTERS Name Description SFR Address Bit Functions and Addresses MSB LSB Reset Value E7 E6 E5 E4 E3 E2 E1 E0 ACC* Accumulator E0h 00h AUXR1# Auxiliary Function RegisterA2h KBF BOD BOI LPEP SRST 0 – DPS 02h1 F7 F6 F5 F4 F3 F2 F1 F0 B* B register F0h 00h CMP1# Comparator 1 control register ACh – – CE1 CP1 CN1 OE1 CO1 CMF1 00h1 CMP2# Comparator 2 control register ADh – – CE2 CP2 CN2 OE2 CO2 CMF2 00h1 DIVM# CPU clock divide-by-M control 95h 00h DPTR: Data pointer (2 bytes) DPH Data pointer high byte 83h 00h DPL Data pointer low byte 82h 00h CF CE CD CC CB CA C9 C8 I2CFG#* I2C configuration registerC8h/RD SLAVEN MASTRQ 0 TIRUN – – CT1 CT0 00h1 C8h/WR SLAVEN MASTRQ CLRTI TIRUN – – CT1 CT0 DF DE DD DC DB DA D9 D8 I2CON#* I2C control register D8h/RD RDAT ATN DRDY ARL STR STP MASTER – 80h1 D8h/WR CXA IDLE CDR CARL CSTR CSTP XSTR XSTP I2DAT# I2C data register D9h/RD RDAT 0 0 0 0 0 0 0 80h D9h/WR XDAT x x x x x x x AF AE AD AC AB AA A9 A8 IEN0* Interrupt enable 0 A8h EA EWD EBO ES ET1 EX1 ET0 EX0 00h EF EE ED EC EB EA E9 E8 IEN1#* Interrupt enable 1 E8h ETI – EC1 – – EC2 EKB EI2 00h1 BF BE BD BC BB BA B9 B8 IP0* Interrupt priority 0 B8h – PWD PBO PS PT1 PX1 PT0 PX0 00h1 IP0H# Interrupt priority 0 high byteB7h – PWDH PBOH PSH PT1H PX1H PT0H PX0H 00h1 FF FE FD FC FB FA F9 F8 IP1* Interrupt priority 1 F8h PTI – PC1 – – PC2 PKB PI2 00h1 IP1H# Interrupt priority 1 high byteF7h PTIH – PC1H – – PC2H PKBH PI2H 00h1 KBI# Keyboard Interrupt 86h 00h 87 86 85 84 83 82 81 80 P0* Port 0 80h T1 CMP1 CMPREF CIN1A CIN1B CIN2A CIN2B CMP2 Note 2 97 96 95 94 93 92 91 90 P1* Port 1 90h (P1.7) (P1.6) RST INT1 INT0 T0 RxD TxD Note 2 A7 A6 A5 A4 A3 A2 A1 A0 P2* Port 2 A0h – – – – – – X1 X2 Note 2 P2M1# Port 2 output mode 1 A4h P2S P1S P0S ENCLK T1OE T0OE (P2M1.1) (P2M1.0) 00h P2M2# Port 2 output mode 2 A5h – – – – – – (P2M2.1) (P2M2.0) 00h1 PCON Power control register 87h SMOD1 SMOD0 BOF POF GF1 GF0 PD IDL Note 3

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 8

Bit Functions and Addresses MSB LSB SFR AddressDescription D7 D6 D5 D4 D3 D2 D1 D0 PSW* Program status word D0h CY AC F0 RS1 RS0 OV F1 P 00h PT0AD# Port 0 digital input disableF6h 00h 9F 9E 9D 9C 9B 9A 99 98 SCON* Serial port control 98h SM0 SM1 SM2 REN TB8 RB8 TI RI 00h SBUF Serial port data buffer register 99h xxh SADDR# Serial port address registerA9h 00h SADEN# Serial port address enableB9h 00h SP Stack pointer 81h 07h 8F 8E 8D 8C 8B 8A 89 88 TCON* Timer 0 and 1 control 88h TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00h TH0 Timer 0 high byte 8Ch 00h TH1 Timer 1 high byte 8Dh 00h TL0 Timer 0 low byte 8Ah 00h TL1 Timer 1 low byte 8Bh 00h TMOD Timer 0 and 1 mode 89h GATE C/T M1 M0 GATE C/T M1 M0 00h WDCON# Watchdog control register A7h – – WDOVF WDRUN WDCLK WDS2 WDS1 WDS0 Note 4 WDRST# Watchdog reset register A6h xxh NOTES: * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. 1. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other purposes in future derivatives. The reset value shown in the table for these bits is 0. 2. I/O port values at reset are determined by the PRHI bit in the UCFG1 configuration byte. 3. The PCON reset value is x x BOF POF–0 0 0 0b. The BOF and POF flags are not affected by reset. The POF flag is set by hardware upon power up. The BOF flag is set by the occurrence of a brownout reset/interrupt and upon power up. 4. The WDCON reset value is xx11 0000b for a Watchdog reset, xx01 0000b for all other reset causes if the watchdog is enabled, and xx00 0000b for all other reset causes if the watchdog is disabled.

2003 Sep 03 9

are described in the Oscillator section. must have the digital outputs and the digital inputs disabled. read as 0 by any instruction that accesses the port. configured to cause an interrupt when the output value changes. The overall connections to both comparators are shown in Figure 3. CPn, CNn, and OEn. These configurations are shown in Figure 4. interrupt flag are not guaranteed to be stable for 10 microseconds. CMPn.7, 6 — Reserved for future use. Should not be set to 1 by user programs. CMPn.5 CEn Comparator enable. When set by software, the corresponding comparator function is enabled. Comparator output is stable 10 microseconds after CEn is first set. 1, CINnB is selected as the positive comparator input. enabled (CEn = 1). This output is asynchronous to the CPU clock. comparator is disabled (CEn = 0). software and when the comparator is disabled (CEn = 0). Figure 2. Comparator Control Registers (CMP1 and CMP2)

2003 Sep 03 10

Figure 3. Comparator Input and Output Connections Figure 4. Comparator Configurations

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 11

Internal Reference Voltage An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as V ref, is 1.28 V ±10%. Comparator Interrupt Each comparator has an interrupt flag CMFn contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The interrupt will be generated when the corresponding enable bit ECn in the IEN1 register is set and the interrupt system is enabled via the EA bit in the IEN0 register. Comparators and Power Reduction Modes Either or both comparators may remain enabled when Power Down or Idle mode is activated. The comparators will continue to function in the power reduction mode. If a comparator interrupt is enabled, a change of the comparator output state will generate an interrupt and wake up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in power down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. Comparators consume power in Power Down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. Comparator Configuration Example The code shown in Figure 5 is an example of initializing one comparator. Comparator 1 is configured to use the CIN1A and CMPREF inputs, outputs the comparator result to the CMP1 pin, and generates an interrupt when the comparator output changes. The interrupt routine used for the comparator must clear the interrupt flag (CMF1 in this case) before returning. SU01189 CmpInit: mov PT0AD,#30h ; Disable digital inputs on pins that are used ; for analog functions: CIN1A, CMPREF. anl P0M2,#0cfh ; Disable digital outputs on pins that are used orl P0M1,#30h ; for analog functions: CIN1A, CMPREF. mov CMP1,#24h ; Turn on comparator 1 and set up for: ; – Positive input on CIN1A. ; – Negative input from CMPREF pin. ; – Output to CMP1 pin enabled. call delay10us ; The comparator has to start up for at ; least 10 microseconds before use. anl CMP1,#0feh ; Clear comparator 1 interrupt flag. setb EC1 ; Enable the comparator 1 interrupt. The ; priority is left at the current value. setb EA ; Enable the interrupt system (if needed). ret ; Return to caller. Figure 5.

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 12

The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main features of the bus are:

• Bidirectional data transfer between masters and slaves.
• Serial addressing of slaves (no added wiring).
• Acknowledgment after each transferred byte.
• Multimaster bus.
• Arbitration between simultaneously transmitting masters without corruption of serial data on bus. The I2C subsystem includes hardware to simplify the software required to drive the I2C bus. The hardware is a single bit interface which in addition to including the necessary arbitration and framing error checks, includes clock stretching and a bus timeout timer. The interface is synchronized to software either through polled loops or interrupts. Refer to the application note AN422, entitled “Using the 8XC751 Microcontroller as an I 2C Bus Master” for additional discussion of the 8xC76x I2C interface and sample driver routines. The P87LPC764 I2C implementation duplicates that of the 87C751 and 87C752 except for the following details:
• The interrupt vector addresses for both the I2C interrupt and the Timer I interrupt.
• The I2C SFR addresses (I2CON, I2CFG, I2DAT).
• The location of the I2C interrupt enable bit and the name of the SFR it is located within (EI2 is Bit 0 in IEN1).
• The location of the Timer I interrupt enable bit and the name of the SFR it is located within (ETI is Bit 7 in IEN1).
• The I2C and Timer I interrupts have a settable priority. Timer I is used to both control the timing of the I2C bus and also to detect a “bus locked” condition, by causing an interrupt when nothing happens on the I 2C bus for an inordinately long period of time while a transmission is in progress. If this interrupt occurs, the program has the opportunity to attempt to correct the fault and resume I 2C operation. Six time spans are important in I2C operation and are insured by timer I:
• The MINIMUM HIGH time for SCL when this device is the master.
• The MINIMUM LOW time for SCL when this device is a master. This is not very important for a single-bit hardware interface like this one, because the SCL low time is stretched until the software responds to the I 2C flags. The software response time normally meets or exceeds the MIN LO time. In cases where the software responds within MIN HI + MIN LO) time, timer I will ensure that the minimum time is met.
• The MINIMUM SCL HIGH TO SDA HIGH time in a stop condition.
• The MINIMUM SDA HIGH TO SDA LOW time between I2C stop and start conditions (4.7ms, see I2C specification).
• The MINIMUM SDA LOW TO SCL LOW time in a start condition.
• The MAXIMUM SCL CHANGE time while an I2C frame is in progress. A frame is in progress between a start condition and the following stop condition. This time span serves to detect a lack of software response on this device as well as external I problems. SCL “stuck low” indicates a faulty master or slave. SCL “stuck high” may mean a faulty device, or that noise induced onto the I 2C bus caused all masters to withdraw from I2C arbitration. The first five of these times are 4.7 ms (see I2C specification) and are covered by the low order three bits of timer I. Timer I is clocked by the P87LPC764 CPU clock. Timer I can be pre-loaded with one of four values to optimize timing for different oscillator frequencies. At lower frequencies, software response time is increased and will degrade maximum performance of the I 2C bus. See special function register I2CFG description for prescale values (CT0, CT1). The MAXIMUM SCL CHANGE time is important, but its exact span is not critical. The complete 10 bits of timer I are used to count out the maximum time. When I 2C operation is enabled, this counter is cleared by transitions on the SCL pin. The timer does not run between I2C frames (i.e., whenever reset or stop occurred more recently than the last start). When this counter is running, it will carry out after 1020 to 1023 machine cycles have elapsed since a change on SCL. A carry out causes a hardware reset of the I2C interface and generates an interrupt if the Timer I interrupt is enabled. In cases where the bus hang-up is due to a lack of software response by this device, the reset releases SCL and allows I 2C operation among other devices to continue. Timer I is enabled to run, and will reset the I2C interface upon overflow, if the TIRUN bit in the I2CFG register is set. The Timer I interrupt may be enabled via the ETI bit in IEN1, and its priority set by the PTIH and PTI bits in the IP1H and IP1 registers respectively. I2C Interrupts If I2C interrupts are enabled (EA and EI2 are both set to 1), an I2C interrupt will occur whenever the ATN flag is set by a start, stop, arbitration loss, or data ready condition (refer to the description of ATN following). In practice, it is not efficient to operate the I 2C interface in this fashion because the I2C interrupt service routine would somehow have to distinguish between hundreds of possible conditions. Also, since I 2C can operate at a fairly high rate, the software may execute faster if the code simply waits for the I2C interface. Typically, the I2C interrupt should only be used to indicate a start condition at an idle slave device, or a stop condition at an idle master device (if it is waiting to use the I2C bus). This is accomplished by enabling the I2C interrupt only during the aforementioned conditions. Reading I2CON RDAT The data from SDA is captured into “Receive DATa” whenever a rising edge occurs on SCL. RDAT is also available (with seven low-order zeros) in the I2DAT register. The difference between reading it here and there is that reading I2DAT clears DRDY, allowing the I 2C to proceed on to another bit. Typically, the first seven bits of a received byte are read from I2DAT, while the 8th is read here. Then I2DAT can be written to send the Acknowledge bit and clear DRDY. ATN “ATteNtion” is 1 when one or more of DRDY, ARL, STR, or STP is 1. Thus, ATN comprises a single bit that can be tested to release the I2C service routine from a “wait loop.” DRDY “Data ReaDY” (and thus ATN) is set when a rising edge occurs on SCL, except at idle slave. DRDY is cleared by writing CDR = 1, or by writing or reading the I2DAT register. The following low period on SCL is stretched until the program responds by clearing DRDY.

2003 Sep 03 13

I2CON.7 RDAT Read: the most recently received data bit. “ CXA Write: clears the transmit active flag. I2CON.6 ATN Read: ATN = 1 if any of the flags DRDY, ARL, STR, or STP = 1. I2CON.5 DRDY Read: Data Ready flag, set when there is a rising edge on SCL. “ CDR Write: writing a 1 to this bit clears the DRDY flag. I2CON.4 ARL Read: Arbitration Loss flag, set when arbitration is lost while in the transmit mode. “ CARL Write: writing a 1 to this bit clears the CARL flag. I2CON.3 STR Read: Start flag, set when a start condition is detected at a master or non-idle slave. “ CSTR Write: writing a 1 to this bit clears the STR flag. I2CON.2 STP Read: Stop flag, set when a stop condition is detected at a master or non-idle slave. “ CSTP Write: writing a 1 to this bit clears the STP flag. I2CON.1 MASTER Read: indicates whether this device is currently as bus master. “ XSTR Write: writing a 1 to this bit causes a repeated start condition to be generated. “ XSTP Write: writing a 1 to this bit causes a stop condition to be generated. Figure 6. I2C Control Register (I2CON) I2DAT also clears DRDY and the Transmit Active state. Figure 7. I2C Data Register (I2DAT)

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 14

ARL “Arbitration Loss” is 1 when transmit Active was set, but this device lost arbitration to another transmitter. Transmit Active is cleared when ARL is 1. There are four separate cases in which ARL is set. 1. If the program sent a 1 or repeated start, but another device sent a 0, or a stop, so that SDA is 0 at the rising edge of SCL. (If the other device sent a stop, the setting of ARL will be followed shortly by STP being set.) 2. If the program sent a 1, but another device sent a repeated start, and it drove SDA low before SCL could be driven low. (This type of ARL is always accompanied by STR = 1.) 3. In master mode, if the program sent a repeated start, but another device sent a 1, and it drove SCL low before this device could drive SDA low. 4. In master mode, if the program sent stop, but it could not be sent because another device sent a 0. STR “STaRt” is set to a 1 when an I 2C start condition is detected at a non-idle slave or at a master. (STR is not set when an idle slave becomes active due to a start bit; the slave has nothing useful to do until the rising edge of SCL sets DRDY.) STP “SToP” is set to 1 when an I 2C stop condition is detected at a non-idle slave or at a master. (STP is not set for a stop condition at an idle slave.) MASTER “MASTER” is 1 if this device is currently a master on the I2C. MASTER is set when MASTRQ is 1 and the bus is not busy (i.e., if a start bit hasn’t been received since reset or a “Timer I” time-out, or if a stop has been received since the last start). MASTER is cleared when ARL is set, or after the software writes MASTRQ = 0 and then XSTP = 1. Writing I2CON Typically, for each bit in an I 2C message, a service routine waits for ATN = 1. Based on DRDY, ARL, STR, and STP, and on the current bit position in the message, it may then write I2CON with one or more of the following bits, or it may read or write the I2DAT register. CXA Writing a 1 to “Clear Xmit Active” clears the Transmit Active state. (Reading the I2DAT register also does this.) Regarding Transmit Active Transmit Active is set by writing the I2DAT register, or by writing I2CON with XSTR = 1 or XSTP = 1. The I2C interface will only drive the SDA line low when Transmit Active is set, and the ARL bit will only be set to 1 when Transmit Active is set. Transmit Active is cleared by reading the I2DAT register, or by writing I2CON with CXA = 1. Transmit Active is automatically cleared when ARL is 1. IDLE Writing 1 to “IDLE” causes a slave’s I 2C hardware to ignore the I2C until the next start condition (but if MASTRQ is 1, then a stop condition will cause this device to become a master). CDR Writing a 1 to “Clear Data Ready” clears DRDY. (Reading or writing the I2DAT register also does this.) CARL Wr iting a 1 to “Clear Arbitration Loss” clears the ARL bit. CSTR Writing a 1 to “Clear STaRt” clears the STR bit. CSTP Writing a 1 to “Clear SToP” clears the STP bit. Note that if one or more of DRDY, ARL, STR, or STP is 1, the low time of SCL is stretched until the service routine responds by clearing them. XSTR Writing 1s to “Xmit repeated STaRt” and CDR tells the I 2C hardware to send a repeated start condition. This should only be at a master. Note that XSTR need not and should not be used to send an “initial” (non-repeated) start; it is sent automatically by the I2C hardware. Writing XSTR = 1 includes the effect of writing I2DAT with XDAT = 1; it sets Transmit Active and releases SDA to high during the SCL low time. After SCL goes high, the I 2C hardware waits for the suitable minimum time and then drives SDA low to make the start condition. XSTP Writing 1s to “Xmit SToP” and CDR tells the I hardware to send a stop condition. This should only be done at a master. If there are no more messages to initiate, the service routine should clear the MASTRQ bit in I2CFG to 0 before writing XSTP with 1. Writing XSTP = 1 includes the effect of writing I2DAT with XDAT = 0; it sets Transmit Active and drives SDA low during the SCL low time. After SCL goes high, the I hardware waits for the suitable minimum time and then releases SDA to high to make the stop condition.

2003 Sep 03 15

start condition is sent and DRDY is set (thus making ATN = 1 and generating an I2C interrupt). When a master wishes to release mastership status of the I2C, it writes a 1 to XSTP in I2CON. MASTRQ is cleared by an I2C time-out. I2CFG.5 CLRTI Writing a 1 to this bit clears the Timer I overflow flag. This bit position always reads as a 0. and MASTER, this bit determines operational modes as shown in Table 1. I2CFG.2, 3 — Reserved for future use. Should not be set to 1 by user programs. controls both of these parameters, and also the timing for stop and start conditions. Figure 8. I2C Configuration Register (I2CFG) on the response is that it must not exceed the Timer I time-out. minimum SCL high and low times will be 5.25 µs. pre-loaded into Timer I is 8 minus the machine cycle count).

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Table 1. Interaction of TIRUN with SLAVEN, MASTRQ, and MASTER application wants to ignore the I2C at certain times, it should write SLAVEN, MASTRQ, and TIRUN all to zero. All 0 1 The I2C interface is disabled. not, so that there is no checking for I2C being “hung.” This configuration can be used for very slow I2C operation. Start and Stop conditions. This is the normal state for I2C operation. Table 2. CT1, CT0 Values request of higher priority level is serviced. only used to resolve simultaneous requests of the same priority level. each interrupt may wake up the CPU from Power Down mode. Table 3. Summary of Interrupts

2003 Sep 03 17

those present on the standard 80C51 microcontroller. is set, causing an interrupt request. the CPU when the service routine is called. level sensitive, it simply tracks the input pin level. Reduction Modes for details. Figure 9. Interrupt Sources, Interrupt Enables, and Power Down Wakeup Sources

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oscillator and reset configurations are chosen. Table 4. These are: quasi-bidirectional (standard 80C51 port registers for each port choose the output type for each port pin. Table 4. Port Output Configuration Settings quasi-bidirectional output that serve different purposes. port pin below its input threshold. order to pull the port pin high quickly. Then it turns off again. The quasi-bidirectional port configuration is shown in Figure 10.

2 CPU

Figure 10. Quasi-Bidirectional Output

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The open drain port configuration is shown in Figure 11. is needed from a port output. The push-pull port configuration is shown in Figure 12. and is not using the external reset input function RST. options are described in the Oscillator section. current for all ports which must not be exceeded. All ports pins of the P87LPC764 have slew rate controlled outputs. This is to limit noise generated by quickly switching output signals. The slew rate is factory set to approximately 10 ns rise and fall times. functions are shown in Figure 13. and P1.5 always have a Schmitt trigger input. Figure 11. Open Drain Output Figure 12. Push-Pull Output

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P2M1.7 P2S When P2S = 1, this bit enables Schmitt trigger inputs on Port 2. P2M1.6 P1S When P1S = 1, this bit enables Schmitt trigger inputs on Port 1. P2M1.5 P0S When P0S = 1, this bit enables Schmitt trigger inputs on Port 0. output is enabled on the X2 pin (P2.0). Refer to the Oscillator section for details. one half of the Timer 1 overflow rate. Refer to the Timer/Counters section for details. one half of the Timer 0 overflow rate. Refer to the Timer/Counterssection for details. P2.1 and P2.0 respectively, as shown in Table 4. Figure 13. Port 2 Mode Register 1 (P2M1) manage power consumption yet also need to be convenient to use. mode. Refer to the section on Power Reduction Modes for details.

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Figure 14. Keyboard Interrupt KBI.7 KBI.7 When set, enables P0.7 as a cause of a Keyboard Interrupt. KBI.6 KBI.6 When set, enables P0.6 as a cause of a Keyboard Interrupt. KBI.5 KBI.5 When set, enables P0.5 as a cause of a Keyboard Interrupt. KBI.4 KBI.4 When set, enables P0.4 as a cause of a Keyboard Interrupt. KBI.3 KBI.3 When set, enables P0.3 as a cause of a Keyboard Interrupt. KBI.2 KBI.2 When set, enables P0.2 as a cause of a Keyboard Interrupt. KBI.1 KBI.1 When set, enables P0.1 as a cause of a Keyboard Interrupt. KBI.0 KBI.0 When set, enables P0.0 as a cause of a Keyboard Interrupt. (KBF) is located at bit 7 of AUXR1. Figure 15. Keyboard Interrupt Register (KBI)

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20 MHz; ceramic resonators; and on-chip RC oscillator. This option supports an external crystal in the range of 20 kHz to 100 kHz. Table 5 shows capacitor values that may be used with a quartz crystal in this mode. Table 5. Recommended oscillator capacitors for use with the low frequency oscillator option This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration. Table 6 shows capacitor values that may be used with a quartz crystal in this mode. Table 6. Recommended oscillator capacitors for use with the medium frequency oscillator option

1 MHz 15 pF 15 pF 33 pF 15 pF 22 pF 47 pF

4 MHz 15 pF 15 pF 33 pF 15 pF 15 pF 33 pF

This option supports an external crystal in the range of 4 to 20 MHz. Ceramic resonators are also supported in this configuration. Table 7 shows capacitor values that may be used with a quartz crystal in this mode. Table 7. Recommended oscillator capacitors for use with the high frequency oscillator option

4 MHz 15 pF 33 pF 47 pF 15 pF 33 pF 68 pF

8 MHz 15 pF 15 pF 33 pF 15 pF 33 pF 47 pF

16 MHz – – – 15 pF 15 pF 33 pF

20 MHz – – – 15 pF 15 pF 33 pF

enabled when the on-chip RC oscillator is used.

20 MHz when V

pin may be enabled when the external clock input is used. on-chip RC oscillator or external clock input options are selected. This allows external devices to synchronize to the P87LPC764. when the external clock input option is selected.

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IMPORTANT FOR LOW FREQUENCY CRYSTALS (SEE TEXT). Figure 16. Using the Crystal Oscillator THE EXTERNAL CLOCK INPUT MODE. Figure 17. Using an External Clock Input

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Figure 18. Block Diagram of Oscillator Control oscillator rate by a programmable divider, under program control. determined by the previously described CLKR function. program at any time without interrupting code execution. hardware functions: Power-On Detect and Brownout Detect. both be enabled (via the EA and EBO bits in IEN0). by software. This flag will remain set until cleared by software.

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faster than 2 mV/µs in order to insure a proper reset. (BOV = 0), the brownout detect voltage is 3.8 V. setting the control bit BOD in the AUXR1 register (AUXR1.6). will remain set until cleared by software. entered by setting the IDL bit in the PCON register (see Figure 19). setting the PD bit in the PCON register (see Figure 19). it is recommended to wake up the processor via Reset in this case. DD drops below the brownout voltage. PCON.7 SMOD1 When set, this bit doubles the UART baud rate for modes 1, 2, and 3. SCON.7 is the FE (Framing Error) flag. See Figure 28 for additional information. to the Power Monitoring Functions section for additional information. PCON.3 GF1 General purpose flag 1. May be read or written by user software, but has no effect on operation. PCON.2 GF0 General purpose flag 0. May be read or written by user software, but has no effect on operation. Power Down mode is terminated (see text). Figure 19. Power Control Register (PCON)

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Table 8. Sources of Wakeup from Power Down Mode External Interrupt 0 or 1 The corresponding interrupt must be enabled. Comparator 1 or 2 The comparator(s) must be enabled and properly set up. The corresponding interrupt must be enabled. Watchdog Timer Reset The watchdog timer must be enabled via the WDTE bit in the UCFG1 EPROM configuration byte. set (brownout interrupt disabled). (brownout interrupt enabled). The corresponding interrupt must be enabled. Reset Input The external reset input must be enabled.

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always provides a reset when power is initially applied to the device. low, the P87LPC764 is held in reset until the signal goes high. detect because it uses an independent, fully on-chip oscillator. Figure 20. Using pin P1.5 as general purpose input pin or as low-active reset pin Figure 21. Block Diagram Showing Reset Sources

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upward compatible with the standard 80C51 Timer 0 and Timer 1. pins upon timer overflow has been added. a description of the CPU clock. a 1-to-0 transition at its corresponding external input pin, T0 or T1. it should be held for at least one full machine cycle. 1, and 2 are the same for both Timers/Counters. Mode 3 is different. The four operating modes are described in the following text. the TR1 control pin is set. When cleared, Timer 1 is enabled when the TR1 control bit is set. Set for Counter operation (input from T1 input pin). TMOD.5, 4 M1, M0 Mode Select for Timer 1 (see table below). the TR0 control pin is set. When cleared, Timer 0 is enabled when the TR0 control bit is set. Set for Counter operation (input from T0 input pin). TMOD.1, 0 M1, M0 Mode Select for Timer 0 (see table below). 0 0 8048 Timer “TLn” serves as 5-bit prescaler. 0 1 16-bit Timer/Counter “THn” and “TLn” are cascaded; there is no prescaler. 1 0 8-bit auto-reload Timer/Counter. THn holds a value which is loaded into TLn when it overflows. text). Timer 1 in this mode is stopped. Figure 22. Timer/Counter Mode Control Register (TMOD)

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TCON (Figure 23). The GATE bit is in the TMOD register. ignored. Setting the run flag (TRn) does not clear the registers. Figure 24. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3). interrupt is processed, or by software. TCON.6 TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off. processor vectors to the interrupt routine, or by software. TCON.4 TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off. hardware when the interrupt is processed, or by software. hardware when the interrupt is processed, or by software. Figure 23. Timer/Counter Control Register (TCON) Figure 24. Timer/Counter 0 or 1 in Mode 0 (13-Bit Counter)

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operation is the same for Timer 0 and Timer 1. counters. The logic for Mode 3 on Timer 0 is shown in Figure 27. TH0 now controls the “Timer 1” interrupt. Mode 3 is provided for applications that require an extra 8-bit timer. application not requiring an interrupt. Figure 25. Timer/Counter 0 or 1 in Mode 1 (16-Bit Counter) Figure 26. Timer/Counter 0 or 1 in Mode 2 (8-Bit Auto-Reload)

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Figure 27. Timer/Counter 0 Mode 3 (Two 8-Bit Counters) overflow when this mode is turned on. include Framing Error detection and automatic address recognition. reading SBUF accesses a physically separate receive register. fixed at 1/6 of the CPU clock frequency. start bit (logical 0), 8 data bits (LSB first), and a stop bit (logical 1). determined by the Timer 1 overflow rate. example, the parity bit (P, in the PSW) could be moved into TB8. frequency, as determined by the SMOD1 bit in PCON. and is determined by the Timer 1 overflow rate. other modes by the incoming start bit if REN = 1.

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receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). 0, SCON.7 is the SM0 bit. If SMOD0 = 1, SCON.7 is the FE bit. the need for monitoring it for every character individually. cleared by software. The SMOD0 bit in the PCON register must be 1 for this bit to be accessible. to be accessible. See FE bit above. SCON. 6 SM1 With SM0, defines the serial port mode (see table below). will not be activated if a valid stop bit was not received. In Mode 0, SM2 should be 0. SCON.4 REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. SCON.3 TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. was received. In Mode 0, RB8 is not used. of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Figure 28. Serial Port Control Register (SCON)

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The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = CPU clock/6. SMOD1 = 1, the baud rate is 1/16 of the CPU clock frequency. can be obtained using Timer 1 as the baud rate generator. Table 9. Baud Rates, Timer Values, and CPU Clock Frequencies for SMOD1 = 0

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Table 10. Baud Rates, Timer Values, and CPU Clock Frequencies for SMOD1 = 1

1. Tables 6 and 7 apply to UART modes 1 and 3 (variable rate modes), and show CPU clock rates in MHz for standard baud rates from 2400 to
2. Table 6 shows timer settings and CPU clock rates with the SMOD1 bit in the PCON register = 0 (the default after reset), while Table 7
3. The tables show all potential CPU clock frequencies up to 20 MHz that may be used for baud rates from 9600 baud to 115.2k baud. Other

CPU clock frequencies that would give only lower baud rates are not shown.

1. Table entries marked with an asterisk (*) indicate standard crystal and ceramic resonator frequencies that may be obtained from many

sources without special ordering.

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 35

Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received: 8 data bits (LSB first). The baud rate is fixed at 1/6 the CPU clock frequency. Figure 29 shows a simplified functional diagram of the serial port in Mode 0, and associated timing. Transmission is initiated by any instruction that uses SBUF as a destination register. The “write to SBUF” signal at S6P2 also loads a 1 into the 9th position of the transmit shift register and tells the TX Control block to commence a transmission. The internal timing is such that one full machine cycle will elapse between “write to SBUF” and activation of SEND. SEND enables the output of the shift register to the alternate output function line of P1.1 and also enable SHIFT CLOCK to the alternate output function line of P1.0. SHIFT CLOCK is low during S3, S4, and S5 of every machine cycle, and high during S6, S1, and S2. At S6P2 of every machine cycle in which SEND is active, the contents of the transmit shift are shifted to the right one position. As data bits shift out to the right, zeros come in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position, is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control block to do one last shift and then deactivate SEND and set T1. Both of these actions occur at S1P1 of the 10th machine cycle after “write to SBUF.” Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2 of the next machine cycle, the RX Control unit writes the bits 11111110 t o the receive shift register, and in the next clock phase activates RECEIVE. RECEIVE enable SHIFT CLOCK to the alternate output function line of P1.0. SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle. At S6P2 of every machine cycle in which RECEIVE is active, the contents of the receive shift register are shifted to the left one position. The value that comes in from the right is the value that was sampled at the P1.1 pin at S5P2 of the same machine cycle. As data bits come in from the right, 1s shift out to the left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the RX Control block to do one last shift and load SBUF. At S1P1 of the 10th machine cycle after the write to SCON that cleared RI, RECEIVE is cleared as RI is set. More About UART Mode 1 Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the P87LPC764 the baud rate is determined by the Timer 1 overflow rate. Figure 30 shows a simplified functional diagram of the serial port in Mode 1, and associated timings for transmit receive. Transmission is initiated by any instruction that uses SBUF as a destination register. The “write to SBUF” signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SBUF” signal.) The transmission begins with activation of SEND which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 10th divide-by-16 rollover after “write to SBUF.” Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated.: 1. R1 = 0, and 2. Either SM2 = 0, or the received stop bit = 1. If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in RxD.

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Figure 29. Serial Port Mode 0

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Figure 30. Serial Port Mode 1

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 38

More About UART Modes 2 and 3 Eleven bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of 0 or 1. On receive, the 9the data bit goes into RB8 in SCON. The baud rate is programmable to either 1/16 or 1/32 of the CPU clock frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1. Figures 31 and 32 show a functional diagram of the serial port in Modes 2 and 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register. Transmission is initiated by any instruction that uses SBUF as a destination register. The “write to SBUF” signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SBUF” signal.) The transmission begins with activation of SEND, which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 11th divide-by-16 rollover after “write to SBUF.” Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift register. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of R–D. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1. RI = 0, and 2. Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the RxD input. Multiprocessor Communications UART modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received or transmitted. When data is received, the 9th bit is stored in RB8. The UART can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. One way to use this feature in multiprocessor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that follow. The slaves that weren’t being addressed leave their SM2 bits set and go on about their business, ignoring the subsequent data bytes. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit, although this is better done with the Framing Error flag. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.

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Figure 31. Serial Port Mode 2

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Figure 32. Serial Port Mode 3

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address which the master will use for addressing each of the slaves. standard UART drivers which do not make use of this feature. generate an interrupt. The watchdog timer is shown in Figure 33. Figure 34. When the watchdog function is enabled, the WDCON initialization can be completed. timer will time out and reset the CPU. a power on reset, brownout reset, or external reset. mov WDRST,#1eh ; First part of watchdog feed sequence. mov WDRST,#0e1h ; Second part of watchdog feed sequence. does not occur prior to that time. and code execution will resume after the oscillator is stable.

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8 MSBs

8 TO 1 MUX

Figure 33. Block Diagram of the Watchdog Timer WDCON.7, 6 — Reserved for future use. Should not be set to 1 by user programs. WDRUN = 0. This bit is forced to 1 (watchdog running) if the WDTE configuration bit = 1. oscillator) if the WDTE configuration bit = 1. WDCON.2–0 WDS2–0 Watchdog rate select. WDCON Reset Value:/C0083 30h for a watchdog reset. /C0083 10h for other rest sources if the watchdog is enabled via the WDTE configuration bit. /C0083 00h for other reset sources if the watchdog is disabled via the WDTE configuration bit. Figure 34. Watchdog Timer Control Register (WDCON)

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relate to several chip features. AUXR1 is described in Figure 35. AUXR1 to avoid accidental software resets. processor can specify the address used with certain instructions. to software unless the DPS bit is toggled.

• INC DPTR Increments the Data Pointer by 1.
• JMP @A+DPTR Jump indirect relative to DPTR value.
• MOV DPTR, #data16 Load the Data Pointer with a 16-bit constant.
• MOVC A, @A+DPTR Move code byte relative to DPTR to the accumulator.
• MOVX A, @DPTR Move data byte the accumulator to data memory relative to DPTR.
• MOVX @DPTR, A Move data byte from data memory relative to DPTR to the accumulator. Also, any instruction that reads or manipulates the DPH and DPL registers (the upper and lower bytes of the current DPTR) will be affected by the setting of DPS. The MOVX instructions have limited application for the P87LPC764 since the part does not have an external data bus. However, they may be used to access EPROM configuration information (see EPROM Characteristics section). Bit 2 of AUXR1 is permanently wired as a logic 0. This is so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register. BIT SYMBOL FUNCTION AUXR1.7 KBF Keyboard Interrupt Flag. Set when any pin of port 0 that is enabled for the Keyboard Interrupt function goes low. Must be cleared by software. AUXR1.6 BOD Brown Out Disable. When set, turns off brownout detection and saves power. See Power Monitoring Functions section for details. AUXR1.5 BOI Brown Out Interrupt. When set, prevents brownout detection from causing a chip reset and allows the brownout detect function to be used as an interrupt. See the Power Monitoring Functions section for details. AUXR1.4 LPEP Low Power EPROM control bit. Allows power savings in low voltage systems. Set by software. Can only be cleared by power-on or brownout reset. See the Power Reduction Modes section for details. AUXR1.3 SRST Software Reset. When set by software, resets the 87LPC764 as if a hardware reset occurred. AUXR1.2 — This bit contains a hard-wired 0. Allows toggling of the DPS bit by incrementing AUXR1, without interfering with other bits in the register. AUXR1.1 — Reserved for future use. Should not be set to 1 by user programs. AUXR1.0 DPS Data Pointer Select. Chooses one of two Data Pointers for use by the program. See text for details. DPS SU01184 —0SRSTLPEPBOIBODKBF 01234567 AUXR1 Reset Value: 00h Not Bit Addressable Address: A2h

Figure 35. AUXR1 Register

2003 Sep 03 44

using the DPTR register for addressing. date, or other application information. MOVX instruction at the addresses shown in the figure. still be used to generate an interrupt. UCFG1.5 PRHI Port reset high. When 1, ports reset to a high state. When 0, ports reset to a low state. detect voltage is 3.8V. This is described in the Power Monitoring Functions section. this division applies to peripheral timing as well. other than those shown below should not be used. They are reserved for future use. 1 1 1 External clock input on X1 (default setting for an unprogrammed part). 0 1 1 Internal RC oscillator, 6 MHz. For tolerance, see AC Electrical Characteristics table. 0 1 0 Low frequency crystal, 20 kHz to 100 kHz. 0 0 1 Medium frequency crystal or resonator, 100 kHz to 4 MHz. 0 0 0 High frequency crystal or resonator, 4 MHz to 20 MHz. Figure 36. EPROM System Configuration Byte 1 (UCFG1)

2003 Sep 03 45

UCFG2.7, 6 SB2, SB1 EPROM security bits. See table entitled, “EPROM Security Bits” for details. UCFG2.5–0 — Reserved for future use. Figure 37. EPROM System Configuration Byte 2 (UCFG2) EPROM verify is also disabled. Table 11. EPROM Security Bits 1 1 Both security bits unprogrammed. No program security features enabled. EPROM is programmable and verifiable. 1 0 Only security bit 1 programmed. Further EPROM programming is disabled. Security bit 2 may still be programmed. 0 1 Only security bit 2 programmed. This combination is not supported. 0 0 Both security bits programmed. All EPROM verification and programming are disabled.

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

of this specification are not implied.

1. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 46

DC ELECTRICAL CHARACTERISTICS (FOR P87LPC764BD, BN, BDH, FN, FD, FDH, BD/01, BDH/01) VDD = 2.7 V to 6.0 V unless otherwise specified; Tamb = 0°C to +70°C or –40°C to +85°C, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS MIN TYP 1 MAX UNIT IDD Power supply current operating 5.0 V, 20 MHz11 15 25 mAIDD Power su ly current, o erating 3.0 V, 10 MHz11 4 7 mA IID Power supply current Idle mode 5.0 V, 20 MHz11 6 10 mAIID Power su ly current, Idle mode 3.0 V, 10 MHz11 2 4 mA IPD Power supply current Power Down mode 5.0 V11 1 10 µAIPD Power su ly current, Power Down mode 3.0 V11 1 5 µA VRAM RAM keep-alive voltage 1.5 V VIL1 Negative going threshold (Schmitt input) –0.5 0.3 VDD V VIH Input high voltage (TTL input) 0.2 VDD +0.9 VDD +0.5 V VIH1 Positive going threshold (Schmitt input) 0.7 VDD VDD +0.5 V HYS Hysteresis voltage 0.2 VDD V VOL Output low voltage all ports5, 9 IOL = 3.2 mA, VDD = 2.7 V 0.4 V VOL1 Output low voltage all ports5, 9 IOL = 20 mA, VDD = 2.7 V 1.0 V VOH Output high voltage allports3 IOH = –20 µA, VDD = 2.7 V VDD –0.7 VVOH Out ut high voltage, all orts3 IOH = –30 µA, VDD = 4.5 V VDD –0.7 V VOH1 Output high voltage, all ports4 IOH = –1.0 mA, VDD = 2.7 V VDD –0.7 V C IO Input/Output pin capacitance10 15 pF IIL Logical 0 input current, all ports8 VIN = 0.4 V –50 µA ILI Input leakage current, all ports7 VIN = VIL or VIH ±2 µA ITL Logical 1 to 0 transition current allports3, 6 VIN = 1.5 V at VDD = 3.0 V –30 –250 µAITL Logical 1 to 0 transition current, all orts3, 6 VIN = 2.0 V at VDD = 5.5 V –150 –650 µA R RST Internal reset pull-up resistor14 40 225 kΩ VBOLOW Brownout trip voltage with BOV = 112 2.35 2.69 V VBOHI Brownout trip voltage with BOV = 0 3.45 3.99 V VREF Reference voltage 1.11 1.26 1.41 V tC (VREF ) Temperature coefficient tbd ppm/°C SS Supply sensitivity tbd %/V NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V. 2. See other Figures for details. Active mode: I CC(MAX) = tbd Idle mode: ICC(MAX) = tbd 3. Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups). Does not apply to open drain pins. 4. Ports in PUSH-PULL mode. Does not apply to open drain pins. 5. In all output modes except high impedance mode. 6. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. This current is highest when V IN is approximately 2 V. 7. Measured with port in high impedance mode. Parameter is guaranteed but not tested at cold temperature. 8. Measured with port in quasi-bidirectional mode. 9. Under steady state (non-transient) conditions, I OL must be externally limited as follows: Maximum IOL per port pin: 20 mA Maximum total IOL for all outputs: 80 mA Maximum total IOH for all outputs: 5 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 10. Pin capacitance is characterized but not tested. 11. The IDD , IID, and IPD specifications are measured using an external clock with the following functions disabled: comparators, brownout detect, and watchdog timer. For VDD = 3 V, LPEP = 1. Refer to the appropriate figures on the following pages for additional current drawn by each of these functions and detailed graphs for other frequency and voltage combinations. 12. Devices initially operating at VDD = 2.7V or above and at fOSC = 10 MHz or less are guaranteed to continue to execute instructions correctly at the brownout trip point. Initial power-on operation below VDD = 2.7 V is not guaranteed. 13. Devices initially operating at VDD = 4.0 V or above and at fOSC = 20 MHz or less are guaranteed to continue to execute instructions correctly at the brownout trip point. Initial power-on operation below VDD = 4.0 V and FOSC > 10 MHz is not guaranteed. 14. This internal resistor is disconnected if P1.5 is used as a general purpose input pin instead of the reset pin.

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 47

COMPARATOR ELECTRICAL CHARACTERISTICS (FOR P87LPC764BD, BN, BDH, FN, FD, FDH, BD/01, BDH/01) VDD = 3.0 V to 6.0 V unless otherwise specified; Tamb = 0°C to +70°C or –40°C to +85°C, unless otherwise specified SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIO Offset voltage comparator inputs1 ±10 mV VCR Common mode range comparator inputs 0 VDD –0.3 V CMRR Common mode rejection ratio1 –50 dB Response time 250 500 ns Comparator enable to output valid 10 µs IIL Input leakage current, comparator 0 < VIN < VDD ±10 µA NOTE: 1. This parameter is guaranteed by characterization, but not tested in production.

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 48

AC ELECTRICAL CHARACTERISTICS (FOR P87LPC764BD, BDH, BN, FN, FD, FDH) Tamb = 0°C to +70°C or –40°C to +85°C, VDD = 2.7 V to 6.0 V unless otherwise specified; VSS = 0 V1,2,3 SYMBOL FIGURE PARAMETER LIMITS UNITSYMBOL FIGURE PARAMETER MIN MAX UNIT External Clock fosc 39 Oscillator frequency (VDD = 4.0 V to 6.0 V) 0 20 MHz fosc 39 Oscillator frequency (VDD = 2.7 V to 6.0 V) 0 10 MHz tC 39 Clock period and CPU timing cycle 1/fosc – ns fosc(tol) On-chip RC oscillator tolerance. Applies to P87LPC764BDH5 10 10 % fosc(tol) On-chip RC oscillator tolerance, all other devices 25 25 % tCLCX 39 Clock low-time4 fOSC = 20 MHz 20 – ns tCLCX 39 fOSC = 10 MHz 40 – ns tCHCX 39 Clock high-time4 fOSC = 20 MHz 20 – ns tCHCX 39 fOSC = 10 MHz 40 – ns Shift Register tXLXL 38 Serial port clock cycle time 6tC – ns tQVXH 38 Output data setup to clock rising edge 5tC – 133 – ns tXHQX 38 Output data hold after clock rising edge 1tC – 80 – ns tXHDV 38 Input data setup to clock rising edge – 5tC – 133 ns tXHDX 38 Input data hold after clock rising edge 0 – ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for all outputs = 80 pF. 3. Parts are guaranteed to operate down to 0 Hz. 4. Applies only to an external clock source, not when a crystal is connected to the X1 and X2 pins. 5. For availability of other devices with this specification, please contact Philips sales office.

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 49

AC ELECTRICAL CHARACTERISTICS (FOR P87LPC764BD/01, BDH/01) Tamb = 0°C to +70°C, VDD = 2.7 V to 6.0 V unless otherwise specified; VSS = 0 V1,2,3 SYMBOL FIGURE PARAMETER LIMITS UNITSYMBOL FIGURE PARAMETER MIN MAX UNIT External Clock fosc 39 Oscillator frequency (VDD = 4.0 V to 6.0 V) 0 20 MHz fosc 39 Oscillator frequency (VDD = 2.7 V to 6.0 V) 0 10 MHz tC 39 Clock period and CPU timing cycle 1/fosc – ns tCLCX 39 Clock low-time1 fosc = 20 MHz 20 – ns tCLCX 39 fosc = 10 MHz 40 – ns tCHCX 39 Clock high-time1 fosc = 20 MHz 20 – ns tCHCX 39 fosc = 10 MHz 40 – ns Internal RC Oscillator fosc(cal) On-chip RC oscillator calibration2 fosc(RC) = 6 MHz –1 +1 % fosc(tol) On-chip RC oscillator, 0 °C to +50°C 3,4 tol. fosc(RC) = 6 MHz –2.5 +2.5 % fosc(tol) On-chip RC oscillator, 0 °C to +70°C 3 tol. fosc(RC) = 6 MHz –55 +2.5 % Shift Register tXLXL 38 Serial port clock cycle time 6tC – ns tQVXH 38 Output data setup to clock rising edge 5tC – 133 – ns tXHQX 38 Output data hold after clock rising edge 1tC – 80 – ns tXHDV 38 Input data setup to clock rising edge – 5tC – 133 ns tXHDX 38 Input data hold after clock rising edge 0 – ns NOTES: 1. Applies only to an external clock source, not when a crystal is connected to the X1 and X2 pins. 2. Tested at V DD = 5.0 V and room temperature. 3. These parameters are characterized but not tested. 4. +/– 2.5% accuracy enables serial communication over the UART with the internal Oscillator. 5. Min frequency at hot temperature.

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 50

DC ELECTRICAL CHARACTERISTICS (FOR P87LPC764HDH) VDD = 4.5 V to 5.5 V; Tamb = –40°C to +125°C. SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS MIN TYP 1 MAX UNIT IDD Power supply current, operating 5.0 V, 20 MHz11 15 25 mA IID Power supply current, Idle mode 5.0 V, 20 MHz11 6 10 mA IPD Power supply current, Power Down mode5.0 V11 1 10 µA VRAM RAM keep-alive voltage 1.5 V VIL1 Negative going threshold (Schmitt input) –0.5 0.3 VDD V VIH Input high voltage (TTL input) 0.2 VDD +0.9 VDD +0.5 V VIH1 Positive going threshold (Schmitt input) 0.7 VDD VDD +0.5 V HYS Hysteresis voltage 0.2 VDD V VOL Output low voltage all ports5, 9 IOL = 3.2 mA, VDD = 2.7 V 0.4 V VOL1 Output low voltage all ports5, 9 IOL = 20 mA, VDD = 2.7 V 1.0 V VOH Output high voltage, all ports3 IOH = –30 µA, VDD = 4.5 V VDD –0.7 V VOH1 Output high voltage, all ports4 IOH = –1.0 mA, VDD = 2.7 V VDD –0.7 V C IO Input/Output pin capacitance10 15 pF IIL Logical 0 input current, all ports8 VIN = 0.4 V –50 µA ILI Input leakage current, all ports7 VIN = VIL or VIH ±2 µA ITL Logical 1 to 0 transition current, all ports3, 6 VIN = 2.0 V at VDD = 5.5 V –150 –650 µA R RST Internal reset pull-up resistor14 40 225 kΩ VBOLOW Brownout trip voltage with BOV = 112 2.35 2.69 V VBOHI Brownout trip voltage with BOV = 0 3.45 3.99 V VREF Reference voltage 1.11 1.26 1.41 V tC (VREF ) Temperature coefficient tbd ppm/°C SS Supply sensitivity tbd %/V NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V. 2. See other Figures for details. Active mode: I CC(MAX) = tbd Idle mode: ICC(MAX) = tbd 3. Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups). Does not apply to open drain pins. 4. Ports in PUSH-PULL mode. Does not apply to open drain pins. 5. In all output modes except high impedance mode. 6. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. This current is highest when VIN is approximately 2 V. 7. Measured with port in high impedance mode. Parameter is guaranteed but not tested at cold temperature. 8. Measured with port in quasi-bidirectional mode. 9. Under steady state (non-transient) conditions, I OL must be externally limited as follows: Maximum IOL per port pin: 20 mA Maximum total IOL for all outputs: 80 mA Maximum total IOH for all outputs: 5 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 10. Pin capacitance is characterized but not tested. 11. The IDD , IID, and IPD specifications are measured using an external clock with the following functions disabled: comparators, brownout detect, and watchdog timer. For VDD = 3 V, LPEP = 1. Refer to the appropriate figures on the following pages for additional current drawn by each of these functions and detailed graphs for other frequency and voltage combinations. 12. Devices initially operating at VDD = 2.7V or above and at fOSC = 10 MHz or less are guaranteed to continue to execute instructions correctly at the brownout trip point. Initial power-on operation below VDD = 2.7 V is not guaranteed. 13. Devices initially operating at VDD = 4.0 V or above and at fOSC = 20 MHz or less are guaranteed to continue to execute instructions correctly at the brownout trip point. Initial power-on operation below VDD = 4.0 V and FOSC > 10 MHz is not guaranteed. 14. This internal resistor is disconnected if P1.5 is used as a general purpose input pin instead of the reset pin.

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 51

COMPARATOR ELECTRICAL CHARACTERISTICS (FOR P87LPC764HDH) VDD = 4.5 V to 5.5 V; Tamb = –40°C to +125°C SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIO Offset voltage comparator inputs1 ±20 mV VCR Common mode range comparator inputs 0 VDD –0.3 V CMRR Common mode rejection ratio1 –50 dB Response time 250 500 ns Comparator enable to output valid 10 µs IIL Input leakage current, comparator 0 < VIN < VDD ±10 µA NOTE: 1. This parameter is guaranteed by characterization, but not tested in production.

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 52

AC ELECTRICAL CHARACTERISTICS (FOR P87LPC764HDH) VDD = 4.5 V to 5.5 V; Tamb = –40°C to +125°C ; VSS = 0 V1,2,3 SYMBOL FIGURE PARAMETER LIMITS UNITSYMBOL FIGURE PARAMETER MIN MAX UNIT External Clock fosc 39 0 16 MHz tC 39 Clock period and CPU timing cycle 1/fosc ns fosc(tol) on-chip RC oscillator tolerance –10 +10 % tCHCX 39 Clock high-time4 fOSC = 16 MHz 25 ns tCLCX 39 Clock low-time4 fOSC = 16 MHz 25 ns Shift Register tXLXL 38 Serial port clock cycle time 6tC ns tQVXH 38 Output data setup to clock rising edge 5tC – 133 ns tXHQX 38 Output data hold after clock rising edge 1tC – 80 ns tXHDV 38 Input data setup to clock rising edge 5tC – 133 ns tXHDX 38 Input data hold after clock rising edge 0 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for all outputs = 80 pF. 3. Parts are guaranteed to operate down to 0 Hz. 4. Applies only to an external clock source, not when a crystal is connected to the X1 and X2 pins. 5. For availability of other devices with this specification, please contact Philips sales office.

2003 Sep 03 53

Figure 38. Shift Register Mode Timing Figure 39. External Clock Timing Figure 40. Typical Idd versus frequency (low frequency Figure 41. Typical Idd versus frequency (medium frequency

2003 Sep 03 54

Figure 42. Typical Idd versus frequency (high frequency Figure 43. Typical Active Idd versus frequency (external clock, Figure 44. Typical Active Idd versus frequency (external clock, Figure 45. Typical Idle Idd versus frequency (external clock, Figure 46. Typical Idle Idd versus frequency (external clock,

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 55

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 56

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 57

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 58

REVISION HISTORY

_11 20030903 Product data (9397 750 11121); ECN 853-2401 30269 Modifications:

• Added BD/01, BDH/01 and HDH part types _10 20011026 Preliminary data (9397 750 09017); previous release

Philips Semiconductors Product data P87LPC764Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP

2003 Sep 03 59

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to:  Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Date of release: 09-03 Document order number: 9397 750 11121 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status[1] Objective data Preliminary data Product data Product status[2] [3] Development Qualification Production Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Level I II III