P87LPC759

P87LPC759 PHILIPS | Alldatasheet

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/C0080 /C0115 /C0111/C0110/C0111 /C0115 P87LPC759 Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP Preliminary data 2002 Mar 21 INTEGRATED CIRCUITS

Philips Semiconductors Preliminary data P87LPC759Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP

2002 Mar 21 i

Philips Semiconductors Preliminary data P87LPC759Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP

12002 Mar 21

The P87LPC759 is a 14-pin single-chip microcontroller designed for low pin count applications demanding high-integration, low cost solutions over a wide range of performance requirements. A member of the Philips low pin count family, the P87LPC759 offers programmable oscillator configurations for high and low speed crystals or RC operation, wide operating voltage range, programmable port output configurations, selectable Schmitt trigger inputs, LED drive outputs, and a built-in watchdog timer. The P87LPC759 is based on an accelerated 80C51 processor architecture that executes instructions at twice the rate of standard 80C51 devices.

FEATURES

• An accelerated 80C51 CPU provides instruction cycle times of 300–600 ns for all instructions except multiply and divide when executing at 20 MHz. Execution at up to 20 MHz when V DD = 4.5 V to 6.0 V, 10 MHz when VDD = 2.7 V to 6.0 V
• 2.7 V to 6.0 V operating range for digital functions
• 1 kbyte EPROM code memory
• 64 byte RAM data memory
• Two 16-bit counter/timers. One timer may be configured to toggle a port output upon timer overflow
• Four keypad interrupt inputs, plus one additional external interrupt input
• Four interrupt priority levels
• Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog timeout time is selectable from 8 values
• Active low reset. On-chip power-on reset allows operation with no external reset components
• Low voltage reset. One of two preset low voltage levels may be selected to allow a graceful system shutdown when power fails. May optionally be configured as an interrupt
• Oscillator Fail Detect. The watchdog timer has a separate fully on-chip oscillator, allowing it to perform an oscillator fail detect function
• Configurable on-chip oscillator with frequency range and RC oscillator options (selected by user programmed EPROM bits). The RC oscillator option allows operation with no external oscillator components
• Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only
• Selectable Schmitt trigger port inputs
• LED drive capability (20 mA) on all port pins
• Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times
• Nine I/O pins minimum. Up to 12 I/O pins using on-chip oscillator and reset options
• Only power and ground connections are required to operate the P87LPC759 when fully on-chip oscillator and reset options are selected
• Serial EPROM programming allows simple in-circuit production coding. Two EPROM security bits prevent reading of sensitive application programs
• Idle and Power Down reduced power modes. Improved wakeup from Power Down mode (a low interrupt input starts execution). Typical Power Down current is 1 /C0109A
• 14-pin DIP package

ORDERING INFORMATION

Part Number Temperature Range °C and Package Frequency Drawing Number P87LPC759BN 0 to +70, plastic dual in-line package; 14 leads (300 mil)20 MHz (5 V),

10 MHz (3 V)

14P1.7 RST /P1.5 VSS X1/P2.1 X2/CLKOUT/P2.0 INT0/P1.3 T0/P1.2 P0.3 P0.4 P0.5 VDD P0.6 P1.0 P1.18

Philips Semiconductors Preliminary data P87LPC759Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP

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Philips Semiconductors Preliminary data P87LPC759Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP

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TIMER 0, 1 ACCELERATED 80C51 CPU WATCHDOG TIMER AND OSCILLATOR PORT 0 CONFIGURABLE I/OS

64 BYTE

1 KBYTE

(POWER-ON RESET, BROWNOUT RESET) CONFIGURABLE OSCILLATOR CRYSTAL OR RESONATOR ON-CHIP RC OSCILLATOR

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1 KBYTE ON-CHIP

64 BYTES ON-CHIP DATA

1. The P87LPC759 does not support access to external data memory. However, the User Configuration Bytes are accessed via the MOVX

instruction as if they were in external data memory. Figure 1. P87LPC759 Program and Data Memory Map

Philips Semiconductors Preliminary data P87LPC759Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP

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MNEMONIC PIN NO. TYPE NAME AND FUNCTION P0.3–P0.6 10, 12–14 I/O Port 0: Port 0 is a 4-bit I/O port with a user-configurable output type. Port 0 latches are con- figured in the quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined by the PRHI bit in the UCFG1 configuration byte. The operation of port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electri- cal Characteristics for details. The Keyboard Interrupt feature operates with port 0 pins. P1.0–P1.3 P1.5, P1.7 1–2 6–9 I/O Port 1: Port 1 is an 6-bit I/O port with a user-configurable output type, except for three pins as noted below. Port 1 latches are configured in the quasi-bidirectional mode and have ei- ther ones or zeros written to them during reset, as determined by the PRHI bit in the UCFG1 configuration byte. The operation of the configurable port 1 pins as inputs and outputs de- pends upon the port configuration selected. Each of the configurable port pins are pro- grammed independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. Port 1 also provides various special functions as described below.

7 I/O

O P1.2 T0 Timer/counter 0 external count input or overflow output. When configured as an output, P1.2 is open drain. 6 I O P1.3 INT0 External interrupt 0 input. When configured as an output, P1.3 is open drain. 2 I P1.5 RST External Reset input (if selected via EPROM configuration). A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. When used as a port pin, P1.5 is a Schmitt trigger input only. P2.0–P2.1 4, 5 I/O Port 2: Port 2 is a 2-bit I/O port with a user-configurable output type. Port 2 latches are con- figured in the quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined by the PRHI bit in the UCFG1 configuration byte. The operation of port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electri- cal Characteristics for details. Port 2 also provides various special functions as described below. 5 O P2.0 X2 Output from the oscillator amplifier (when a crystal oscillator option is selected via the EPROM configuration). CLKOUT CPU clock divided by 6 clock output when enabled via SFR bit and in conjunction with internal RC oscillator or external clock input. 4 I P2.1 X1 Input to the oscillator circuit and internal clock generator circuits (when selected via the EPROM configuration). VSS 3 I Ground: 0 V reference. VDD 11 I Power Supply: This is the power supply voltage for normal operation as well as Idle and Power Down modes.

Philips Semiconductors Preliminary data P87LPC759Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP

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SPECIAL FUNCTION REGISTERS Name Description SFR Address Bit Functions and Addresses MSB LSB Reset Value E7 E6 E5 E4 E3 E2 E1 E0 ACC* Accumulator E0h 00h AUXR1# Auxiliary Function Register A2h KBF BOD BOI LPEP SRST 0 – DPS 02h1 F7 F6 F5 F4 F3 F2 F1 F0 B* B register F0h 00h DIVM# CPU clock divide-by-M control 95h 00h DPTR: Data pointer (2 bytes) DPH Data pointer high byte 83h 00h DPL Data pointer low byte 82h 00h DF DE DD DC DB DA D9 D8 AF AE AD AC AB AA A9 A8 IEN0* Interrupt enable 0 A8h EA EWD EBO – ET1 – ET0 EX0 00h EF EE ED EC EB EA E9 E8 IEN1#* Interrupt enable 1 E8h – – – – – – EKB – 00h1 BF BE BD BC BB BA B9 B8 IP0* Interrupt priority 0 B8h – PWD PBO – PT1 – PT0 PX0 00h1 IP0H# Interrupt priority 0 high byte B7h – PWDH PBOH – PT1H – PT0H PX0H 00h1 FF FE FD FC FB FA F9 F8 IP1* Interrupt priority 1 F8h – – – – – – PKB – 00h1 IP1H# Interrupt priority 1 high byte KBI# Keyboard Interrupt 86h 00h 87 86 85 84 83 82 81 80 97 96 95 94 93 92 91 90 P1* Port 1 90h (P1.7) – RST – INT0 T0 – – Note 2 A7 A6 A5 A4 A3 A2 A1 A0 P2* Port 2 A0h – – – – – – X1 X2 Note 2 P0M1# Port 0 output mode 1 84h – (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) – – – 00h P0M2# Port 0 output mode 2 85h – (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) – – – 00h P1M1# Port 1 output mode 1 91h (P1M1.7) – – – – – (P1M1.1) (P1M1.0) 00h1 P1M2# Port 1 output mode 2 92h (P1M2.7) – – – – – (P1M2.1) (P1M2.0) 00h1 P2M1# Port 2 output mode 1 A4h P2S P1S P0S ENCLK – T0OE (P2M1.1) (P2M1.0) 00h P2M2# Port 2 output mode 2 A5h – – – – – – (P2M2.1) (P2M2.0) 00h1 PCON Power control register 87h SMOD1 SMOD0 BOF POF GF1 GF0 PD IDL Note 3 D7 D6 D5 D4 D3 D2 D1 D0 PSW* Program status word D0h CY AC F0 RS1 RS0 OV F1 P 00h SP Stack pointer 81h 07h 8F 8E 8D 8C 8B 8A 89 88 TCON* Timer 0 and 1 control 88h TF1 TR1 TF0 TR0 – – IE0 IT0 00h TH0 Timer 0 high byte 8Ch 00h

Philips Semiconductors Preliminary data P87LPC759Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP

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Bit Functions and Addresses MSB LSB SFR AddressDescription TH1 Timer 1 high byte 8Dh 00h TL0 Timer 0 low byte 8Ah 00h TL1 Timer 1 low byte 8Bh 00h TMOD Timer 0 and 1 mode 89h – – M1 M0 GATE C/T M1 M0 00h WDCON# Watchdog control registerA7h – – WDOVF WDRUN WDCLK WDS2 WDS1 WDS0 Note 4 WDRST# Watchdog reset register A6h XXh NOTES: * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. 1. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other purposes in future derivatives. The reset value shown in the table for these bits is 0. 2. I/O port values at reset are determined by the PRHI bit in the UCFG1 configuration byte. 3. The PCON reset value is x x BOF POF–0 0 0 0b. The BOF and POF flags are not affected by reset. The POF flag is set by hardware upon power up. The BOF flag is set by the occurrence of a brownout reset/interrupt and upon power up. 4. The WDCON reset value is xx11 0000b for a Watchdog reset, xx01 0000b for all other reset causes if the watchdog is enabled, and xx00 0000b for all other reset causes if the watchdog is disabled.

Philips Semiconductors Preliminary data P87LPC759Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP

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standard 80C51 microcontroller. is set, causing an interrupt request. by the CPU when the service routine is called. level sensitive, it simply tracks the input pin level. Reduction Modes for details. Figure 2. Interrupt Sources, Interrupt Enables, and Power Down Wakeup Sources

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oscillator and reset configurations are chosen. Table 2. These are: quasi-bidirectional (standard 80C51 port registers for each port choose the output type for each port pin. Table 2. Port Output Configuration Settings quasi-bidirectional output that serve different purposes. port pin below its input threshold. The quasi-bidirectional port configuration is shown in Figure 3.

2 CPU

Figure 3. Quasi-Bidirectional Output

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The open drain port configuration is shown in Figure 4. is needed from a port output. The push-pull port configuration is shown in Figure 5. options are described in the Oscillator section. output current for all ports which must not be exceeded. All ports pins of the P87LPC759 have slew rate controlled outputs. This is to limit noise generated by quickly switching output signals. functions are shown in Figure 6. Figure 4. Open Drain Output Figure 5. Push-Pull Output

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P2M1.7 P2S When P2S = 1, this bit enables Schmitt trigger inputs on Port 2. P2M1.6 P1S When P1S = 1, this bit enables Schmitt trigger inputs on Port 1. P2M1.5 P0S When P0S = 1, this bit enables Schmitt trigger inputs on Port 0. output is enabled on the X2 pin (P2.0). Refer to the Oscillator section for details. one half of the Timer 0 overflow rate. Refer to the Timer/Counters section for details.

1. See Table 2, Port Output Configuration Settings.

Figure 6. Port 2 Mode Register 1 (P2M1) manage power consumption yet also need to be convenient to use. mode. Refer to the section on Power Reduction Modes for details.

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Figure 7. Keyboard Interrupt KBI.6 KBI.6 When set, enables P0.6 as a cause of a Keyboard Interrupt. KBI.5 KBI.5 When set, enables P0.5 as a cause of a Keyboard Interrupt. KBI.4 KBI.4 When set, enables P0.4 as a cause of a Keyboard Interrupt. KBI.3 KBI.3 When set, enables P0.3 as a cause of a Keyboard Interrupt. (KBF) is located at bit 7 of AUXR1. Figure 8. Keyboard Interrupt Register (KBI)

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20 MHz; ceramic resonators; and on-chip RC oscillator. Table 3. Recommended oscillator capacitors for use with the low frequency oscillator option 4 MHz. Ceramic resonators are also supported in this configuration. Table 4. Recommended oscillator capacitors for use with the medium frequency oscillator option

1 MHz 15 pF 15 pF 33 pF

4 MHz 15 pF 15 pF 33 pF

This option supports an external crystal in the range of 4 to 20 MHz. Ceramic resonators are also supported in this configuration. Table 5. Recommended oscillator capacitors for use with the high frequency oscillator option

4 MHz 15 pF 33 pF 47 pF 15 pF 33 pF 68 pF

8 MHz 15 pF 15 pF 33 pF 15 pF 33 pF 47 pF

16 MHz – – – 15 pF 15 pF 33 pF

20 MHz – – – 15 pF 15 pF 33 pF

20 MHz when V

on-chip RC oscillator or external clock input options are selected. This allows external devices to synchronize to the P87LPC759. when the external clock input option is selected.

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IMPORTANT FOR LOW FREQUENCY CRYSTALS (SEE TEXT). Figure 9. Using the Crystal Oscillator THE EXTERNAL CLOCK INPUT MODE. Figure 10. Using an External Clock Input

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Figure 11. Block Diagram of Oscillator Control oscillator rate by a programmable divider, under program control. determined by the previously described CLKR function. hardware functions: Power-On Detect and Brownout Detect. both be enabled (via the EA and EBO bits in IEN0).

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faster than 2 mV/µs in order to insure a proper reset. (BOV = 0), the brownout detect voltage is 3.8 V. setting the control bit BOD in the AUXR1 register (AUXR1.6). will remain set until cleared by software. entered by setting the IDL bit in the PCON register (see Figure 12). setting the PD bit in the PCON register (see Figure 12). be put into reset as soon as VDD drops below the brownout voltage. Down. These include the Brownout Detect and Watchdog Timer. to the Power Monitoring Functions section for additional information. PCON.3 GF1 General purpose flag 1. May be read or written by user software, but has no effect on operation. PCON.2 GF0 General purpose flag 0. May be read or written by user software, but has no effect on operation. Power Down mode is terminated (see text). Figure 12. Power Control Register (PCON)

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Table 6. Sources of Wakeup from Power Down Mode External Interrupt 0 The interrupt must be enabled. Watchdog Timer Reset The watchdog timer must be enabled via the WDTE bit in the UCFG1 EPROM configuration byte. set (brownout interrupt disabled). (brownout interrupt enabled). The corresponding interrupt must be enabled. Reset Input The external reset input must be enabled.

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always provides a reset when power is initially applied to the device. low, the P87LPC759 is held in reset until the signal goes high. detect because it uses an independent, fully on-chip oscillator. Figure 13. Using pin P1.5 as general purpose input pin or as low-active reset pin Figure 14. Block Diagram Showing Reset Sources

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upward compatible with the standard 80C51 Timer 0 and Timer 1. toggle the T0 pin upon timer overflow has been added. a description of the CPU clock. operating modes, which are selected by bit-pairs (M1, M0) in TMOD. TMOD.7, 6 – Reserved. Must be written with zeros only. TMOD.5, 4 M1, M0 Mode Select for Timer 1 (see table below). the TR0 control pin is set. When cleared, Timer 0 is enabled when the TR0 control bit is set. Set for Counter operation (input from T0 input pin). TMOD.1, 0 M1, M0 Mode Select for Timer 0 (see table below). 0 0 8048 Timer “TLn” serves as 5-bit prescaler. 0 1 16-bit Timer/Counter “THn” and “TLn” are cascaded; there is no prescaler. 1 0 8-bit auto-reload Timer/Counter. THn holds a value which is loaded into TLn when it overflows. text). Timer 1 in this mode is stopped. Figure 15. Timer/Counter Mode Control Register (TMOD)

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and 18 show Mode 0 operation. TCON (Figure 16). The GATE bit is in the TMOD register (TMOD.3). ignored. Setting the run flag (TRn) does not clear the registers. interrupt is processed, or by software. TCON.6 TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off. processor vectors to the interrupt routine, or by software. TCON.4 TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off. TCON.3, 2 – Reserved (must be 0). hardware when the interrupt is processed, or by software. Figure 16. Timer/Counter Control Register (TCON) Figure 17. Timer/Counter 0 in Mode 0 (13-Bit Timer/Counter)

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Figure 18. Timer 1 in Mode 0 (13-Bit Timer) Timer 1 (see Figures 21 and 22). counters. The logic for Mode 3 on Timer 0 is shown in Figure 23.

1. Thus, TH0 now controls the “Timer 1” interrupt.

Mode 3 is provided for applications that require an extra 8-bit timer. application not requiring an interrupt. Figure 19. Timer/Counter 0 in Mode 1 (16-Bit Timer/Counter) Figure 20. Timer 1 in Mode 1 (16-Bit Timer)

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Figure 21. Timer/Counter 0 in Mode 2 (8-Bit Auto-Reload) Figure 22. Timer 1 in Mode 2 (8-Bit Auto-Reload) Figure 23. Timer/Counter 0 Mode 3 (Two 8-Bit Timer/Counters)

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overflow when this mode is turned on. initialization can be completed. timer will time out and reset the CPU. a power on reset, brownout reset, or external reset. does not occur prior to that time.

8 MSBs

8 TO 1 MUX

Figure 24. Block Diagram of the Watchdog Timer

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WDCON.7, 6 — Reserved for future use. Should not be set to 1 by user programs. WDRUN = 0. This bit is forced to 1 (watchdog running) if the WDTE configuration bit = 1. oscillator) if the WDTE configuration bit = 1. WDCON.2–0 WDS2–0 Watchdog rate select. WDCON Reset Value:/C0083 30h for a watchdog reset. /C0083 10h for other rest sources if the watchdog is enabled via the WDTE configuration bit. /C0083 00h for other reset sources if the watchdog is disabled via the WDTE configuration bit. Figure 25. Watchdog Timer Control Register (WDCON)

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AUXR1 to avoid accidental software resets. processor can specify the address used with certain instructions. to software unless the DPS bit is toggled.

• INC DPTR Increments the Data Pointer by 1.
• JMP @A+DPTR Jump indirect relative to DPTR value.
• MOV DPTR, #data16 Load the Data Pointer with a 16-bit constant.
• MOVC A, @A+DPTR Move code byte relative to DPTR to the accumulator.
• MOVX A, @DPTR Move data byte the accumulator to data memory relative to DPTR.
• MOVX @DPTR, A Move data byte from data memory relative to DPTR to the accumulator. Also, any instruction that reads or manipulates the DPH and DPL registers (the upper and lower bytes of the current DPTR) will be affected by the setting of DPS. The MOVX instructions have limited application for the P87LPC759 since the part does not have an external data bus. However, they may be used to access EPROM configuration information (see EPROM Characteristics section). Bit 2 of AUXR1 is permanently wired as a logic 0. This is so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register. SU01551 BIT SYMBOL FUNCTION AUXR1.7 KBF Keyboard Interrupt Flag. Set when any pin of port 0 that is enabled for the Keyboard Interrupt function goes low. Must be cleared by software. AUXR1.6 BOD Brown Out Disable. When set, turns off brownout detection and saves power. See Power Monitoring Functions section for details. AUXR1.5 BOI Brown Out Interrupt. When set, prevents brownout detection from causing a chip reset and allows the brownout detect function to be used as an interrupt. See the Power Monitoring Functions section for details. AUXR1.4 LPEP Low Power EPROM control bit. Allows power savings in low voltage systems. Set by software. Can only be cleared by power-on or brownout reset. See the Power Reduction Modes section for details. AUXR1.3 SRST Software Reset. When set by software, resets the 87LPC760 as if a hardware reset occurred. AUXR1.2 — This bit contains a hard-wired 0. Allows toggling of the DPS bit by incrementing AUXR1, without interfering with other bits in the register. AUXR1.1 — Reserved for future use. Should not be set to 1 by user programs. AUXR1.0 DPS Data Pointer Select. Chooses one of two Data Pointers for use by the program. See text for details. DPS—0SRSTLPEPBOIBODKBF 01234567 AUXR1 Reset Value: 00h Not Bit Addressable Address: A2h

Figure 26. AUXR1 Register

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and used by an EPROM programming system to identify the device. MOVC instruction, using the DPTR register for addressing. still be used to generate an interrupt. UCFG1.5 PRHI Port reset high. When 1, ports reset to a high state. When 0, ports reset to a low state. detect voltage is 3.8V. This is described in the Power Monitoring Functions section. this division applies to peripheral timing as well. other than those shown below should not be used. They are reserved for future use. 1 1 1 External clock input on X1 (default setting for an unprogrammed part). 0 1 1 Internal RC oscillator, 6 MHz. For tolerance, see AC Electrical Characteristics table. 0 1 0 Low frequency crystal, 20 kHz to 100 kHz. 0 0 1 Medium frequency crystal or resonator, 100 kHz to 4 MHz. 0 0 0 High frequency crystal or resonator, 4 MHz to 20 MHz. Figure 27. EPROM System Configuration Byte 1 (UCFG1) UCFG2.7, 6 SB2, SB1 EPROM security bits. See table entitled, “EPROM Security Bits” for details. UCFG2.5–0 — Reserved for future use. Figure 28. EPROM System Configuration Byte 2 (UCFG2)

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programmed, EPROM verify is also disabled. Table 7. EPROM Security Bits 1 1 Both security bits unprogrammed. No program security features enabled. EPROM is programmable and verifiable. 1 0 Only security bit 1 programmed. Further EPROM programming is disabled. Security bit 2 may still be programmed. 0 1 Only security bit 2 programmed. This combination is not supported. 0 0 Both security bits programmed. All EPROM verification and programming are disabled.

Philips Semiconductors Preliminary data P87LPC759Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP

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Operating temperature under bias –55 to +125 °C Storage temperature range –65 to +150 °C Voltage on RST/VPP pin to VSS 0 to +11.0 V Voltage on any other pin to VSS –0.5 to VDD +0.5V V Maximum IOL per I/O pin 20 mA Power dissipation (based on package heat transfer, not device power consumption) 1.5 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification are not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.

Philips Semiconductors Preliminary data P87LPC759Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP

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DC ELECTRICAL CHARACTERISTICS VDD = 2.7 V to 6.0 V unless otherwise specified; Tamb = 0°C to +70°C, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS MIN TYP 1,2 MAX UNIT IDD Power supply current operating 5.0 V, 20 MHz11 – 15 25 mAIDD Power su ly current, o erating 3.0 V, 10 MHz11 – 4 7 mA IRC Power supply current operating RC Osc 5.0 V, 6 MHz11 – 4 – mAIRC Power su ly current, o erating RC Osc. 3.0 V, 6 MHz11 – 2 – mA IID Power supply current Idle mode 5.0 V, 20 MHz11 – 6 10 mAIID Power su ly current, Idle mode 3.0 V, 10 MHz11 – 2 4 mA IPD Power supply current Power Down mode 5.0 V11 – 1 10 µAIPD Power su ly current, Power Down mode 3.0 V11 – 1 5 µA VRAM RAM keep-alive voltage 1.5 – – V VIL1 Negative going threshold (Schmitt input) –0.5 – 0.3 VDD V VIH Input high voltage (TTL input) 0.2 VDD +0.9 – VDD +0.5 V VIH1 Positive going threshold (Schmitt input) 0.7VDD – VDD +0.5 V HYS Hysteresis voltage – 0.2 VDD – V VOL Output low voltage all ports5, 9 IOL = 3.2 mA, VDD = 2.7 V – – 0.4 V VOL1 Output low voltage all ports5, 9 IOL = 20 mA, VDD = 2.7 V – – 1.0 V VOH Output high voltage allports3 IOH = –20 µA, VDD = 2.7 V VDD –0.7 – – VVOH Out ut high voltage, all orts3 IOH = –30 µA, VDD = 4.5 V VDD –0.7 – – V VOH1 Output high voltage, all ports4 IOH = –1.0 mA, VDD = 2.7 V VDD –0.7 – – V C IO Input/Output pin capacitance10 – – 15 pF IIL Logical 0 input current, all ports8 VIN = 0.4 V – – –50 µA ILI Input leakage current, all ports7 VIN = VIL or VIH – – ±2 µA ITL Logical 1 to 0 transition current allports3, 6 VIN = 1.5 V at VDD = 3.0 V –30 – –250 µAITL Logical 1 to 0 transition current, all orts3, 6 VIN = 2.0 V at VDD = 5.5 V –150 – –650 µA R RST Internal reset pull-up resistor 40 – 225 kΩ VBOLOW Brownout trip voltage with BOV = 112 2.35 – 2.69 V VBOHI Brownout trip voltage with BOV = 0 3.45 – 3.99 V NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V. 2. See other Figures for details. 3. Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups). Does not apply to open drain pins. 4. Ports in PUSH-PULL mode. Does not apply to open drain pins. 5. In all output modes except high impedance mode. 6. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. This current is highest when V IN is approximately 2 V. 7. Measured with port in high impedance mode. Parameter is guaranteed but not tested at cold temperature. 8. Measured with port in quasi-bidirectional mode. 9. Under steady state (non-transient) conditions, I OL must be externally limited as follows: Maximum IOL per port pin: 20 mA Maximum total IOL for all outputs: 80 mA Maximum total IOH for all outputs: 5 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 10. Pin capacitance is characterized but not tested. 11. The IDD , IID, and IPD specifications are measured using an external clock with the following functions disabled: comparators, brownout detect, and watchdog timer. For VDD = 3 V, LPEP = 1. Refer to the appropriate figures on the following pages for additional current drawn by each of these functions and detailed graphs for other frequency and voltage combinations. 12. Devices initially operating at VDD = 2.7 V or above, and at fOSC = 10 MHz or less, are guaranteed to continue to execute instructions correctly at the brownout trip point. Initial power-on operation below VDD = 2.7 V is not guaranteed. 13. Devices initially operating at VDD = 4.0 V or above and at fOSC = 20 MHz or less are guaranteed to continue to execute instructions correctly at the brownout trip point. Initial power-on operation below VDD = 4.0 V and fOSC > 10 MHz is not guaranteed.

Philips Semiconductors Preliminary data P87LPC759Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP

2002 Mar 21 31

AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C, VDD = 2.7 V to 6.0 V unless otherwise specified; VSS = 0 V1, 2, 3 SYMBOL FIGURE PARAMETER LIMITS UNITSYMBOL FIGURE PARAMETER MIN MAX UNIT External Clock fC 29 Oscillator frequency (VDD = 4.0 V to 6.0 V) 0 20 MHz fC 29 Oscillator frequency (VDD = 2.7 V to 6.0 V) 0 10 MHz tC 29 Clock period and CPU timing cycle 1/fC – ns fCLCX 29 Clock low-time1 fOSC = 20 MHz 20 – ns fCLCX 29 fOSC = 10 MHz 40 – ns fCHCX 29 Clock high-time1 fOSC = 20 MHz 20 – ns fCHCX 29 fOSC = 10 MHz 40 – ns Internal RC Oscillator fCTOL On-chip RC oscillator tolerance fRCoSC = 6 MHz –10 +10 % Shift Register tXLXL Serial port clock cycle time 6tC – ns tQVXH Output data setup to clock rising edge 5tC – 133 – ns tXHQX Output data hold after clock rising edge 1tC – 80 – ns tXHDV Input data setup to clock rising edge – 5tC – 133 ns tXHDX Input data hold after clock rising edge 0 – ns NOTES: 1. Applies only to an external clock source, not when a crystal is connected to the X1 and X2 pins. 2. Tested at V DD = 5.0 V and room temperature. 3. These parameters are characterized but not tested.

2002 Mar 21 32

Figure 29. External Clock Timing Figure 30. Typical Idd versus frequency (low frequency Figure 31. Typical Idd versus frequency (medium frequency Figure 32. Typical Idd versus frequency (high frequency Figure 33. Typical Active Idd versus frequency (external clock,

2002 Mar 21 33

Figure 34. Typical Active Idd versus frequency (external clock, Figure 35. Typical Idle Idd versus frequency (external clock, Figure 36. Typical Idle Idd versus frequency (external clock,

Philips Semiconductors Preliminary data P87LPC759Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP

2002 Mar 21 34

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

Philips Semiconductors Preliminary data P87LPC759Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP

2002 Mar 21 35

REVISION HISTORY

2002 Mar xx 9397 750 Initial release

Philips Semiconductors Preliminary data P87LPC759Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP

2002 Mar 21 36

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to:  Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 03-02 Document order number: 9397 750 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status[1] Objective data Preliminary data Product data Product status[2] Development Qualification Production Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.