P87C51RC2BA

P87C51RA2 PHILIPS | Alldatasheet

Document overview

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Technical content

/C0080 /C0115 /C0111/C0110/C0111 /C0115 P87C51RA2/RB2/RC2/RD2 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP, 512B/512B/512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) Product data Supersedes data of 2002 Oct 28 2003 Jan 24 INTEGRATED CIRCUITS

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

22003 Jan 24 853–2391 29335

DESCRIPTION

The devices are Single-Chip 8-Bit Microcontrollers manufactured in an advanced CMOS process and are derivatives of the 80C51 microcontroller family. The instruction set is 100% compatible with the 80C51 instruction set. The devices support 6-clock/12-clock mode selection by programming an OTP bit (OX2) using parallel programming. In addition, an SFR bit (X2) in the clock control register (CKCON) also selects between 6-clock/12-clock mode. The devices also have four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, four-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. The added features of the P87C51RA2/RB2/RC2/RD2 make it a powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control.

FEATURES

• 80C51 Central Processing Unit – 8 kbytes OTP (87C51RA2) – 16 kbytes OTP (87C51RB2) – 32 kbytes OTP (87C51RC2) – 64 kbytes OTP (87C51RD2) – 512 byte RAM (87C51RA2/RB2/RC2) – 1 kbyte RAM (87C51RD2) – Boolean processor – Fully static operation – Low voltage (2.7 V to 5.5 V at 16 MHz) operation
• 12-clock operation with selectable 6-clock operation (via software or via parallel programmer)
• Memory addressing capability – Up to 64 kbytes ROM and 64 kbytes RAM
• Power control modes: – Clock can be stopped and resumed – Idle mode – Power-down mode
• CMOS and TTL compatible
• Two speed ranges at VCC = 5 V – 0 to 30 MHz with 6-clock operation – 0 to 33 MHz with 12-clock operation
• Parallel programming with 87C51 compatible hardware interface to programmer
• RAM expandable externally to 64 kbytes
• Programmable Counter Array (PCA) – PWM – Capture/compare
• PLCC, LQFP, or DIP package
• Extended temperature ranges
• Dual Data Pointers
• Security bits (3 bits)
• Encryption array - 64 bytes
• Seven interrupt sources
• 4 interrupt priority levels
• Four 8-bit I/O ports
• Full-duplex enhanced UART – Framing error detection – Automatic address recognition
• Three 16-bit timers/counters T0, T1 (standard 80C51) and additional T2 (capture and compare)
• Programmable clock-out pin
• Asynchronous port reset
• Low EMI (inhibit ALE, slew rate controlled outputs, and 6-clock mode)
• Wake-up from Power Down by an external interrupt

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 3

# of Timers PWM PCA WD UART I2C CAN SPI ADC bits/ch. I/O Pins Interrupts (Ext.)/Levels Program Security Default Clock Rate Optional Clock Rate Reset active low/high? Max. Freq. at 6-clk / 12-clk (MHz) Freq. Range at 3V (MHz) Freq. Range at 5V (MHz) P87C51RD2 1K – 64K – 4 √ √ √ √ – – – – 32 7(2)/4 √ 12-clk 6-clk H 30/33 0-16 0-30/33 P87C51RC2 512B – 32K – 4 √ √ √ √ – – – – 32 7(2)/4 √ 12-clk 6-clk H 30/33 0-16 0-30/33 P87C51RB2 512B – 16K – 4 √ √ √ √ – – – – 32 7(2)/4 √ 12-clk 6-clk H 30/33 0-16 0-30/33 P87C51RA2 512B – 8K – 4 √ √ √ √ – – – – 32 7(2)/4 √ 12-clk 6-clk H 30/33 0-16 0-30/33

ORDERING INFORMATION

(EXCEPT NORTH AMERICA ) MEMORY TEMPERATURE RANGE (°C) VOLTAGE RANGE DWG #() PART ORDER NUMBER PART MARKING OTP RAM (°C) AND PACKAGE VOLTAGE RANGE DWG # P87C51RA2BA 8 KB 512B 0 to +70, PLCC 2.7 to 5.5 V SOT187-2 P87C51RA2FA 8 KB 512B –40 to +85, PLCC 2.7 to 5.5 V SOT187-2 P87C51RA2BBD 8 KB 512B 0 to +70, LQFP 2.7 to 5.5 V SOT389-1 P87C51RB2BA 16 KB 512B 0 to +70, PLCC 2.7 to 5.5 V SOT187-2 P87C51RB2FA 16 KB 512B –40 to +85, PLCC 2.7 to 5.5 V SOT187-2 P87C51RB2BBD 16 KB 512B 0 to +70, LQFP 2.7 to 5.5 V SOT389-1 P87C51RB2BN 16 KB 512B 0 to +70, DIP40 2.7 to 5.5 V SOT129-1 P87C51RB2FN 16 KB 512B –40 to +85, DIP40 2.7 to 5.5 V SOT129-1 P87C51RC2BA 32 KB 512B 0 to +70, PLCC 2.7 to 5.5 V SOT187-2 P87C51RC2FA 32 KB 512B –40 to +85, PLCC 2.7 to 5.5 V SOT187-2 P87C51RC2BBD 32 KB 512B 0 to +70, LQFP 2.7 to 5.5 V SOT389-1 P87C51RC2BN 32 KB 512B 0 to +70, DIP40 2.7 to 5.5 V SOT129-1 P87C51RC2FN 32 KB 512B –40 to +85, DIP40 2.7 to 5.5 V SOT129-1 P87C51RD2BA 64 KB 1 KB 0 to +70, PLCC 2.7 to 5.5 V SOT187-2 P87C51RD2FA 64 KB 1 KB –40 to +85, PLCC 2.7 to 5.5 V SOT187-2 P87C51RD2BBD 64 KB 1 KB 0 to +70, LQFP 2.7 to 5.5 V SOT389-1 P87C51RD2FBD 64 KB 1 KB –40 to +85, LQFP 2.7 to 5.5 V SOT389-1 P87C51RD2BN 64 KB 1 KB 0 to +70, DIP40 2.7 to 5.5 V SOT129-1

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 4

(12-CLK MODE, 6-CLK MODE) 8K / 16K / 32K /

64 KBYTE

(PCA) WATCHDOG TIMER

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

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BLOCK DIAGRAM (CPU-ORIENTED) SU01658 PSEN EA VPP ALE RST XTAL1 XTAL2 VCC VSS PORT 0 DRIVERS PORT 2 DRIVERS RAM ADDR REGISTER RAM PORT 0 LATCH PORT 2 LATCH OTP MEMORY REGISTER B ACC STACK POINTER TMP2 TMP1 ALU TIMING AND CONTROL INSTRUCTION REGISTER PD OSCILLATOR PSW PORT 1 LATCH PORT 3 LATCH PORT 1 DRIVERS PORT 3 DRIVERS PROGRAM ADDRESS REGISTER BUFFER PC INCRE- MENTER PROGRAM COUNTER DPTR’S MULTIPLE SFRs TIMERS P.C.A. 8 16

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

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Plastic Dual In-Line Package 20 21 40T2/P1.0 T2EX/P1.1 ECI/P1.2 CEX0/P1.3 CEX1/P1.4 CEX2/P1.5 CEX3/P1.6 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 CEX4/P1.7 WR /P3.6 RD /P3.7 XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG EA /VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 V CC DUAL IN-LINE PACKAGE SU00021 Plastic Leaded Chip Carrier LCC 614 0 18 28 Pin Function

1 NIC*

2 P1.0/T2 3 P1.1/T2EX 4 P1.2/ECI 5 P1.3/CEX0 6 P1.4/CEX1 7 P1.5/CEX2 8 P1.6/CEX3 9 P1.7/CEX4

10 RST

11 P3.0/RxD

12 NIC*

13 P3.1/TxD 14 P3.2/INT0 15 P3.3/INT1 Pin Function 16 P3.4/T0 17 P3.5/T1 18 P3.6/WR 19 P3.7/RD

20 XTAL2

21 XTAL1

23 NIC*

24 P2.0/A8 25 P2.1/A9 26 P2.2/A10 27 P2.3/A11 28 P2.4/A12 29 P2.5/A13 30 P2.6/A14 Pin Function 31 P2.7/A15

32 PSEN

33 ALE/PROG

34 NIC*

/VPP 36 P0.7/AD7 37 P0.6/AD6 38 P0.5/AD5 39 P0.4/AD4 40 P0.3/AD3 41 P0.2/AD2 42 P0.1/AD1 43 P0.0/AD0 44 V CC SU00023* NO INTERNAL CONNECTION Plastic Quad Flat Pack LQFP 44 34 12 22 Pin Function 1 P1.5/CEX2 2 P1.6/CEX3 3 P1.7/CEX4

4 RST

5 P3.0/RxD

6 NIC*

7 P3.1/TxD 8 P3.2/INT0 9 P3.3/INT1 10 P3.4/T0 11 P3.5/T1 12 P3.6/WR 13 P3.7/RD

14 XTAL2

15 XTAL1

16 V SS

17 NIC*

18 P2.0/A8 19 P2.1/A9 20 P2.2/A10 21 P2.3/A11 22 P2.4/A12 23 P2.5/A13 24 P2.6/A14 25 P2.7/A15

26 PSEN

27 ALE/PROG

28 NIC*

/VPP 30 P0.7/AD7 Pin Function 31 P0.6/AD6 32 P0.5/AD5 33 P0.4/AD4 34 P0.3/AD3 35 P0.2/AD2 36 P0.1/AD1 37 P0.0/AD0 38 V CC

39 NIC*

40 P1.0/T2 41 P1.1/T2EX 42 P1.2/ECI 43 P1.3/CEX0 44 P1.4/CEX1 SU01400* NO INTERNAL CONNECTION

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

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TYPE NAME AND FUNCTIONMNEMONIC PDIP PLCC LQFP TYPE NAME AND FUNCTION VSS 20 22 16 I Ground: 0 V reference. VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0–0.7 39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. 1–3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Alternate functions for P87C51RA2/RB2/RC2/RD2 Port 1 include: 1 2 40 I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout (see Programmable Clock-Out) 2 3 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control 3 4 42 I ECI (P1.2): External Clock Input to the PCA 4 5 43 I/O CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 5 6 44 I/O CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 6 7 1 I/O CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 7 8 2 I/O CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 8 9 3 I/O CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. 13–19 5, 7–13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the P87C51RA2/RB2/RC2/RD2, as listed below: 10 11 5 I RxD (P3.0): Serial input port 11 13 7 O TxD (P3.1): Serial output port 12 14 8 I INT0 (P3.2): External interrupt 13 15 9 I INT1 (P3.3): External interrupt 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal resistor to VSS permits a power-on reset using only an external capacitor to VCC . ALE 30 33 27 O Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted twice every machine cycle, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

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MNEMONIC NAME AND FUNCTIONTYPE PIN NUMBER MNEMONIC NAME AND FUNCTIONTYPE LQFPPLCCPDIP PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA /VPP 31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations. If EA is held high, the device executes from internal program memory. The value on the EA pin is latched when RST is released and any subsequent changes have no effect. This pin also receives the programming supply voltage (VPP ) during programming. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin (other than VPP ) must not be higher than VCC + 0.5 V or less than VSS – 0.5 V.

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

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SPECIAL FUNCTION REGISTERS SYMBOL DESCRIPTION DIRECT ADDRESS BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB RESET VALUE ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H AUXR# Auxiliary 8EH – – – – – – EXTRAM AO xxxxxx00B AUXR1# Auxiliary 1 A2H – – – – GF2 0 – DPS xxxxxxx0B B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H CCAP0H# Module 0 Capture High FAH xxxxxxxxB CCAP1H# Module 1 Capture High FBH xxxxxxxxB CCAP2H# Module 2 Capture High FCH xxxxxxxxB CCAP3H# Module 3 Capture High FDH xxxxxxxxB CCAP4H# Module 4 Capture High FEH xxxxxxxxB CCAP0L# Module 0 Capture Low EAH xxxxxxxxB CCAP1L# Module 1 Capture Low EBH xxxxxxxxB CCAP2L# Module 2 Capture Low ECH xxxxxxxxB CCAP3L# Module 3 Capture Low EDH xxxxxxxxB CCAP4L# Module 4 Capture Low EEH xxxxxxxxB CCAPM0# Module 0 Mode DAH – ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM1# Module 1 Mode DBH – ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM2# Module 2 Mode DCH – ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM3# Module 3 Mode DDH – ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM4# Module 4 Mode DEH – ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B DF DE DD DC DB DA D9 D8 CCON*# PCA Counter Control D8H CF CR – CCF4 CCF3 CCF2 CCF1 CCF0 00x00000B CH# PCA Counter High F9H 00H CKCON# Clock control 8FH – – – – – – – X2 x0000000B CL# PCA Counter Low E9H 00H CMOD# PCA Counter Mode D9H CIDL WDTE – – – CPS1 CPS0 ECF 00xxx000B DPTR: Data Pointer (2 bytes) DPH Data Pointer High 83H 00H DPL Data Pointer Low 82H 00H AF AE AD AC AB AA A9 A8 IE* Interrupt Enable 0 A8H EA EC ET2 ES ET1 EX1 ET0 EX0 00H BF BE BD BC BB BA B9 B8 IP* Interrupt Priority B8H – PPC PT2 PS PT1 PX1 PT0 PX0 x0000000B B7 B6 B5 B4 B3 B2 B1 B0 IPH# Interrupt Priority HighB7H – PPCH PT2H PSH PT1H PX1H PT0H PX0H x0000000B 87 86 85 84 83 82 81 80 P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FFH 97 96 95 94 93 92 91 90 P1* Port 1 90H CEX4 CEX3 CEX2 CEX1 CEX0 ECI T2EX T2 FFH A7 A6 A5 A4 A3 A2 A1 A0 P2* Port 2 A0H AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 FFH B7 B6 B5 B4 B3 B2 B1 B0 P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TxD RxD FFH PCON# 1 Power Control 87H SMOD1 SMOD0 – POF GF1 GF0 PD IDL 00xxx000B * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. – Reserved bits. 1. Reset value depends on reset source.

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 10

SPECIAL FUNCTION REGISTERS (Continued) SYMBOL DESCRIPTION DIRECT ADDRESS BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB RESET VALUE D7 D6 D5 D4 D3 D2 D1 D0 PSW* Program Status Word D0H CY AC F0 RS1 RS0 OV F1 P 00000000B RCAP2H# Timer 2 Capture High CBH 00H RCAP2L# Timer 2 Capture Low CAH 00H SADDR# Slave Address A9H 00H SADEN# Slave Address Mask B9H 00H SBUF Serial Data Buffer 99H xxxxxxxxB 9F 9E 9D 9C 9B 9A 99 98 SCON* Serial Control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00H SP Stack Pointer 81H 07H 8F 8E 8D 8C 8B 8A 89 88 TCON* Timer Control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H CF CE CD CC CB CA C9 C8 T2CON* Timer 2 Control C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL 2 00H T2MOD# Timer 2 Mode Control C9H – – – – – – T2OE DCEN xxxxxx00B TH0 Timer High 0 8CH 00H TH1 Timer High 1 8DH 00H TH2# Timer High 2 CDH 00H TL0 Timer Low 0 8AH 00H TL1 Timer Low 1 8BH 00H TL2# Timer Low 2 CCH 00H TMOD Timer Mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H WDTRST Watchdog Timer Reset A6H * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. – Reserved bits. OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. Minimum and maximum high and low times specified in the data sheet must be observed. This device is configured at the factory to operate using 12 clock periods per machine cycle, referred to in this datasheet as “12-clock mode”. It may be optionally configured on commercially available parallel programming equipment or via software to operate at 6 clocks per machine cycle, referred to in this datasheet as “6-clock mode”. (This yields performance equivalent to twice that of standard 80C51 family devices). Also see next page.

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(CKCON.0). The CKCON register is shown below in Figure 1. Figure 1. Clock control (CKCON) register (variable baud rate modes) use either Timer 1 or Timer 2. Below is the truth table for the CPU clock mode. IH1 (min.) is applied to RST.

2003 Jan 24 12

lowest power consumption the Power Down mode is suggested. which starts the processor in the same manner as a power-on reset. on-chip RAM to retain their values. oscillator to restart and stabilize (normally less than 10 ms). one following the instruction that put the device into Power Down. to remain unaffected by the VCC level. two machine cycles before the internal reset algorithm takes control. port pin or to external memory.

1. Pull ALE low while the device is in reset and PSEN is high;
2. Hold ALE low as RST is deactivated.

mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied. A 50% duty cycle clock can be programmed to come out on P1.0.

1. to input the external clock for Timer/Counter 2, or
2. to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a

16 MHz operating frequency in 12-clock mode (122 Hz to 8 MHz in

TR2 (T2CON.2) also must be set to start the timer. taken as a 16-bit unsigned integer. interrupt. This is similar to when it is used as a baud-rate generator. Clock-Out frequency will be the same. Table 2. External Pin Status During Idle and Power-Down Mode

2003 Jan 24 13

in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. ignored. Setting the run flag (TRn) does not clear the registers. preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer 0 as for Timer 1. TH0 now controls the “Timer 1” interrupt. fact, in any application not requiring an interrupt. TMOD.7 “TRn” control pin is set. when cleared Timer “n” is enabled whenever “TRn” control bit is set. TMOD.6 Set for Counter operation (input from “Tn” input pin). 0 0 8048 Timer: “TLn” serves as 5-bit prescaler. 0 1 16-bit Timer/Counter: “THn” and “TLn” are cascaded; there is no prescaler. into “TLn” each time it overflows. 1 1 (Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits. 1 1 (Timer 1) Timer/Counter 1 stopped. Figure 2. Timer/Counter 0/1 Mode Control (TMOD) Register

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*d = 6 in 6-clock mode; d = 12 in 12-clock mode. Figure 3. Timer/Counter 0/1 Mode 0: 13-Bit Timer/Counter TCON.7 TF1 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. TCON.6 TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter on/off. TCON.5 TF0 Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. TCON.4 TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter on/off. TCON.3 IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. TCON.1 IE0 Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. triggered external interrupts. Figure 4. Timer/Counter 0/1 Control (TCON) Register

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*d = 6 in 6-clock mode; d = 12 in 12-clock mode. Figure 5. Timer/Counter 0/1 Mode 2: 8-Bit Auto-Reload *d = 6 in 6-clock mode; d = 12 in 12-clock mode. Figure 6. Timer/Counter 0 Mode 3: Two 8-Bit Counters

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(which vectors to the same location as Timer 2 overflow interrupt. (osc/12 in 12-clock mode).). or down depending on the value of the T2EX pin. generated when either TF2 or EXF2 are 1. In Figure 5 DCEN=1 which enables Timer 2 to count up or down. into the timer registers TL2 and TH2. The external flag EXF2 toggles when Timer 2 underflows or overflows. EXF2 flag does not generate an interrupt in this mode of operation. when either RCLK or TCLK = 1. in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. TR2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer. 1 = External event counter (falling edge triggered).

2 CP/RL 2

Figure 1. Timer/Counter 2 (T2CON) Control Register

2003 Jan 24 17

Table 3. Timer 2 Operating Modes

1 X 1 Baud rate generator

• n = 6 in 6-clock mode, or 12 in 12-clock mode.

Figure 2. Timer 2 in Capture Mode T2OE Timer 2 Output Enable bit. DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.

• User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.

Figure 3. Timer 2 Mode (T2MOD) Control Register

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• n = 6 in 6-clock mode, or 12 in 12-clock mode.

Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0)

• n = 6 in 6-clock mode, or 12 in 12-clock mode.

Figure 5. Timer 2 Auto Reload Mode (DCEN = 1)

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Note availability of additional external interrupt. Figure 6. Timer 2 in Baud Rate Generator Mode Table 4. Timer 2 Generated Commonly Used Timer 1, the other by Timer 2. in registers RCAP2H and RCAP2L, which are preset by software. The timer can be configured for either “timer” or “counter” operation. In many applications, it is configured for “timer” operation (C/T2=0). RCAP2L taken as a 16-bit unsigned integer. rollover in TH2 does not set TF2, and will not generate an interrupt. will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). can be used as an additional external interrupt, if needed.

2003 Jan 24 20

before accessing the Timer 2 or RCAP2 registers. as a timer. Also see Table 6 for set-up of Timer 2 as a counter. Table 5. Timer 2 as a Timer Table 6. Timer 2 as a Counter

1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 21

The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (However, if the first byte still hasn’t been read by the time reception of the second byte is complete, one of the bytes will be lost.) The serial port receive and transmit registers are both accessed at Special Function Register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The serial port can operate in 4 modes: Mode 0: Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received (LSB first). The baud rate is fixed at 1/12 the oscillator frequency in 12-clock mode or 1/6 the oscillator frequency in 6-clock mode. Mode 1: 10 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SCON. The baud rate is variable. Mode 2: 11 bits are transmitted (through TxD) or received (through RxD): start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On Transmit, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency in 12-clock mode or 1/16 or 1/32 the oscillator frequency in 6-clock mode. Mode 3: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that weren’t being addressed leave their SM2s set and go on about their business, ignoring the coming data bytes. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. Serial Port Control Register The serial port control and status register is the Special Function Register SCON, shown in Figure 7. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). Baud Rates The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = Oscillator Frequency / 12 (12-clock mode) or / 6 (6-clock mode). The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Register PCON. If SMOD = 0 (which is the value on reset), and the port pins in 12-clock mode, the baud rate is 1/64 the oscillator frequency. If SMOD = 1, the baud rate is 1/32 the oscillator frequency. In 6-clock mode, the baud rate is 1/32 or 1/16 the oscillator frequency, respectively. Mode 2 Baud Rate = SMOD n /C0032(Oscillator Frequency) Where: n = 64 in 12-clock mode, 32 in 6-clock mode The baud rates in Modes 1 and 3 are determined by the Timer 1 or Timer 2 overflow rate. Using Timer 1 to Generate Baud Rates When Timer 1 is used as the baud rate generator (T2CON.RCLK = 0, T2CON.TCLK = 0), the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: Mode 1, 3 Baud Rate = SMOD n /C0032(Timer 1 Overflow Rate) Where: n = 32 in 12-clock mode, 16 in 6-clock mode The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either “timer” or “counter” operation, and in any of its 3 running modes. In the most typical applications, it is configured for “timer” operation, in the auto-reload mode (high nibble of TMOD = 0010B). In that case the baud rate is given by the formula: Mode 1, 3 Baud Rate = SMOD n /C0032Oscillator Frequency Where: n = 32 in 12-clock mode, 16 in 6-clock mode One can achieve very low baud rates with Timer 1 by leaving the Timer 1 interrupt enabled, and configuring the Timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt to do a 16-bit software reload. Figure 8 lists various commonly used baud rates and how they can be obtained from Timer 1.

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received. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. modes, in any serial transmission. Must be cleared by software. modes, in any serial reception (except see SM2). Must be cleared by software. Figure 7. Serial Port Control (SCON) Register Figure 8. Timer 1 Generated Commonly Used Baud Rates 1/6 the oscillator frequency (6-clock mode). Mode 0, and associated timing. of the transmit shift are shifted to the right one position. left of the MSB, and all positions to the left of that contain zeros.

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 23

shifted to the left one position. The value that comes in from the right is the value that was sampled at the P3.0 pin at S5P2 of the same machine cycle. As data bits come in from the right, 1s shift out to the left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the RX Control block to do one last shift and load SBUF. At S1P1 of the 10th machine cycle after the write to SCON that cleared RI, RECEIVE is cleared as RI is set. More About Mode 1 Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the 80C51 the baud rate is determined by the Timer 1 or Timer 2 overflow rate. Figure 10 shows a simplified functional diagram of the serial port in Mode 1, and associated timings for transmit receive. Transmission is initiated by any instruction that uses SBUF as a destination register. The “write to SBUF” signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SBUF” signal.) The transmission begins with activation of SEND which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 10th divide-by-16 rollover after “write to SBUF.” Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated.: 1. R1 = 0, and 2. Either SM2 = 0, or the received stop bit = 1. If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in RxD. More About Modes 2 and 3 Eleven bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of 0 or 1. On receive, the 9the data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 (12-clock mode) or 1/16 or 1/32 the oscillator frequency (6-clock mode) the oscillator frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1 or Timer 2. Figures 11 and 12 show a functional diagram of the serial port in Modes 2 and 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register. Transmission is initiated by any instruction that uses SBUF as a destination register. The “write to SBUF” signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SBUF” signal.) The transmission begins with activation of SEND, which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 11th divide-by-16 rollover after “write to SUBF.” Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift register. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of R-D. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1. RI = 0, and 2. Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the RxD input.

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Figure 9. Serial Port Mode 0

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Figure 10. Serial Port Mode 1

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Figure 11. Serial Port Mode 2

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Figure 12. Serial Port Mode 3

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 28

The UART operates in all of the usual modes that are described in the first section of Data Handbook IC20, 80C51-Based 8-Bit Microcontrollers. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The UART also fully supports multiprocessor communication as does the standard 80C51 UART. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 13. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9-bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 14. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are “don’t care”. The SADEN mask can be logically ANDed with the SADDR to create the “Given” address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00X0 Slave 1 SADDR = 1100 0000 SADEN = 1111 1110 Given = 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = 1100 0000 SADEN = 1111 1001 Given = 1100 0XX0 Slave 1 SADDR = 1110 0000 SADEN = 1111 1010 Given = 1110 0X0X Slave 2 SADDR = 1110 0000 SADEN = 1111 1100 Given = 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are trended as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature.

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Figure 13. UART Framing Error Detection – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. Figure 14. UART Multiprocessor Communication, Automatic Address Recognition

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the IPH register and a description of its bits is shown in Figure 17. priority level interrupt that was stopped will be completed. Table 7. Interrupt Table Enable Bit = 1 enables the interrupt. enabled or disabled by setting or clearing its enable bit. IE.5 ET2 Timer 2 interrupt enable bit. IE.4 ES Serial Port interrupt enable bit. IE.3 ET1 Timer 1 interrupt enable bit. IE.2 EX1 External interrupt 1 enable bit. IE.1 ET0 Timer 0 interrupt enable bit. IE.0 EX0 External interrupt 0 enable bit. Figure 15. IE Registers

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IP.5 PT2 Timer 2 interrupt priority bit. IP.4 PS Serial Port interrupt priority bit. IP.3 PT1 Timer 1 interrupt priority bit. IP.2 PX1 External interrupt 1 priority bit. IP.1 PT0 Timer 0 interrupt priority bit. IP.0 PX0 External interrupt 0 priority bit. Figure 16. IP Registers IPH.5 PT2H Timer 2 interrupt priority bit high. IPH.4 PSH Serial Port interrupt priority bit high. IPH.3 PT1H Timer 1 interrupt priority bit high. IPH.2 PX1H External interrupt 1 priority bit high. IPH.1 PT0H Timer 0 interrupt priority bit high. IPH.0 PX0H External interrupt 0 priority bit high. Figure 17. IPH Registers

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

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The AO bit (AUXR.0) in the AUXR register when set disables the ALE output unless the CPU needs to perform an off-chip memory access. Reduced EMI Mode AUXR (8EH) 7 6 5432 1 0 AUXR.1 EXTRAM AUXR.0 AO See more detailed description in Figure 32. Dual DPTR The dual DPTR structure (see Figure 18) is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 that allows the program code to switch between them.

• New Register Name: AUXR1#
• SFR Address: A2H
• Reset Value: xxxxxxx0B AUXR1 (A2H) 7 65 43210 Where: DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1. Select Reg DPS DPTR0 0 DPTR1 1 The DPS bit status should be saved by software when switching between DPTR0 and DPTR1. The GF2 bit is a general purpose user-defined flag. Note that bit 2 is not writable and is always read as a zero. This allows the DPS bit to be quickly toggled simply by executing an INC AUXR1 instruction without affecting the GF2 bit. DPS DPTR1 DPTR0 DPH (83H) DPL (82H) EXTERNAL DATA MEMORY SU00745A BIT0 AUXR1 Figure 18. DPTR Instructions The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1/bit 0 register. The six instructions that use the DPTR are as follows: INC DPTR Increments the data pointer by 1 MOV DPTR, #data16 Loads the DPTR with a 16-bit constant MOV A, @ A+DPTR Move code byte relative to DPTR to ACC MOVX A, @ DPTR Move external RAM (16-bit address) to ACC MOVX @ DPTR , A Move ACC to external RAM (16-bit address) JMP @ A + DPTR Jump indirect relative to DPTR The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See Application Note AN458 for more details.

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(CEX1), etc. The basic PCA configuration is shown in Figure 19. In the CMOD SFR are three additional bits associated with the PCA. timer overflows. These functions are shown in Figure 20. flags for the PCA timer (CF) and each module (refer to Figure 23). and the module’s capture/compare register. shows the CCAPMn settings for the various PCA functions. these registers are used to control the duty cycle of the output.

16 BITS

Figure 19. Programmable Counter Array (PCA)

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Figure 20. PCA Timer/Counter Figure 21. PCA Interrupt System

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it to be gated off during idle. WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. CPS1 PCA Count Pulse Select bit 1. CPS0 PCA Count Pulse Select bit 0. value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 22. CMOD: PCA Counter Mode Register set. CF may be set by either hardware or software but can only be cleared by software. – Not implemented, reserved for future use*. CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF0 PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 23. CCON: PCA Counter Control Register

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– Not implemented, reserved for future use*. ECOMn Enable Comparator. ECOMn = 1 enables the comparator function. CAPPn Capture Positive, CAPPn = 1 enables positive edge capture. CAPNn Capture Negative, CAPNn = 1 enables negative edge capture. in CCON to be set, flagging an interrupt. PWMn Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. ECCFn Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 24. CCAPMn: PCA Modules Compare/Capture Registers Figure 25. PCA Module Modes (CCAPMn Register) SFR are set then an interrupt will be generated. Refer to Figure 26.

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Figure 26. PCA Capture Mode Figure 27. PCA Compare Mode

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Figure 28. PCA High Speed Output Mode Figure 29. PCA PWM Mode

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Figure 30. PCA Watchdog Timer mode (Module 4 only) still be used for other modes if the watchdog is not needed. generated. This will not cause the RST pin to be driven high.

1. periodically change the compare value so it will never match the
2. periodically change the PCA timer value so it will never match
3. disable the watchdog by clearing the WDTE bit before a match

occurs and then re-enable it. solution is the best option. Figure 31 shows the code for initializing the watchdog timer. WATCHDOG routine in Figure 31.

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; Main program goes here, but CALL WATCHDOG periodically. Figure 31. PCA Watchdog Timer Initialization Code

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and 256 bytes expanded RAM (ERAM) (768 bytes for the RD2).

1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are

directly and indirectly addressable.

1. The Upper 128 bytes of RAM (addresses 80H to FFH) are

indirectly addressable only.

1. The Special Function Registers, SFRs, (addresses 80H to FFH)

are directly addressable only.

1. The 256/768-bytes expanded RAM (ERAM, 00H – 1FFH/2FFH)

with the EXTRAM bit cleared, see Figure 32. physically separate from SFR space. use indirect addressing access the Upper 128 bytes of data RAM. rather than P2 (whose address is 0A0H). data memory in the P87C51RA2/RB2/RC2/RD2. and read timing signals. Refer to Figure 33.

0 ALE is emitted at a constant rate of 1/6 the oscillator frequency (12-clock mode; 1/3 fOSC

1 ALE is active only during off-chip memory access.

0 Internal ERAM access using MOVX @Ri/@DPTR

1 External data memory access. — Not implemented, reserved for future use*. of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 32. AUXR: Auxiliary Register

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128 BYTES

Figure 33. Internal and External Data Memory Address Space with EXTRAM = 0 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. pulse at the RST-pin (see the note below). generate an output RESET pulse at the reset pin (see note below).

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

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ABSOLUTE MAXIMUM RATINGS 1, 2, 3 PARAMETER RATING UNIT Operating temperature under bias 0 to +70 or –40 to +85 °C Storage temperature range –65 to +150 °C Voltage on EA/VPP pin to VSS 0 to +13.0 V Voltage on any other pin to VSS 4 –0.5 to +6.0 V Maximum IOL per I/O pin 15 mA Power dissipation (based on package heat transfer limitations, not device power consumption)1.5 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 4. Transient voltage only. AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C CLOCK FREQUENCY RANGE SYMBOL FIGURE PARAMETER OPERATING MODE POWER SUPPLY VOLTAGE MIN MAX UNIT 1/tCLCL 38 Oscillator frequency6-clock 5 V /C0034 10% 0 30 MHz 6-clock 2.7 V to 5.5 V 0 16 MHz 12-clock 5 V /C0034 10% 0 33 MHz 12-clock 2.7 V to 5.5 V 0 16 MHz

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 44

DC ELECTRICAL CHARACTERISTICS Tamb = 0 °C to +70 °C or –40 °C to +85 °C; VCC = 2.7 V to 5.5 V; VSS = 0 V (16 MHz max. CPU clock) SYMBOL PARAMETER TEST CONDITIONS LIMITS UNIT MIN TYP 1 MAX 2.7 V < VCC < 4.0 V –0.5 0.7 VCC V VIH Input high voltage (ports 0, 1, 2, 3, EA) 0.2 VCC +0.9 VCC +0.5 V VIH1 Input high voltage, XTAL1, RST11 0.7 VCC VCC +0.5 V VOL Output low voltage, ports 1, 2, 8 VCC = 2.7 V; IOL = 1.6 mA2 – 0.4 V VOL1 Output low voltage, port 0, ALE, PSEN8, 7 VCC = 2.7 V; IOL = 3.2 mA2 – 0.4 V VOH Output high voltage, ports 1, 2, 3 3 VCC = 2.7 V; IOH = –20 /C0109A VCC – 0.7 – V VCC = 4.5 V; IOH = –30 /C0109A VCC – 0.7 – V VOH1 Output high voltage (port 0 in external bus mode), ALE9, PSEN3 VCC = 2.7 V; IOH = –3.2 mA VCC – 0.7 – V IIL Logical 0 input current, ports 1, 2, 3VIN = 0.4 V –1 –50 /C0109A ITL Logical 1-to-0 transition current, ports 1, 2, 36 VIN = 2.0 V; See note 4 – –650 /C0109A ILI Input leakage current, port 0 0.45 < VIN < VCC – 0.3 – ±10 /C0109A ICC Power supply current (see Figure 41 and Source Code): Active mode @ 16 MHz /C0109A Idle mode @ 16 MHz /C0109A Power-down mode or clock stopped (see Figure 37 for conditions) 12 Tamb = 0°C to 70°C 2 30 /C0109A Tamb = –40°C to +85°C 3 50 /C0109A VRAM RAM keep-alive voltage 1.2 V R RST Internal reset pull-down resistor 40 225 kΩ C IO Pin capacitance10 (except EA) – 15 pF NOTES: 1. Typical ratings are not guaranteed. Values listed are based on tests conducted on limited number of samples at room temperature. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOL s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC –0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V. 5. See Figures 43 through 46 for ICC test conditions and Figure 41 for ICC vs. Frequency 12-clock mode characteristics: Active mode (operating): ICC = 1.0 mA + 1.1 mA × FREQ.[MHz] Active mode (reset): ICC = 7.0 mA + 0.6 mA /C0032 FREQ.[MHz] Idle mode: I CC = 1.0 mA + 0.22 mA /C0032 FREQ.[MHz] 6. This value applies to Tamb = 0 °C to +70 °C. For Tamb = –40 °C to +85 °C, ITL = –750 /C0109A. 7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15 mA (*NOTE: This is 85 °C specification.) Maximum IOL per 8-bit port: 26 mA Maximum total IOL for all outputs: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1 , except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF (except EA is 25 pF). 11. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection circuitry has been added to the INT0 and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection. max. 30 /C0109A;

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 45

DC ELECTRICAL CHARACTERISTICS Tamb = 0 °C to +70 °C or –40 °C to +85 °C; VCC = 5 V ±10% ; VSS = 0 V (30/33 MHz max. CPU clock) SYMBOL PARAMETER TEST CONDITIONS LIMITS UNIT MIN TYP 1 MAX VIH Input high voltage (ports 0, 1, 2, 3, EA) 0.2 VCC +0.9 VCC +0.5 V VIH1 Input high voltage, XTAL1, RST11 0.7 VCC VCC +0.5 V VOL Output low voltage, ports 1, 2, 3 8 VCC = 4.5 V; IOL = 1.6 mA2 – 0.4 V VOL1 Output low voltage, port 0, ALE, PSEN 7, 8 VCC = 4.5 V; IOL = 3.2 mA2 – 0.4 V VOH Output high voltage, ports 1, 2, 3 3 VCC = 4.5 V; IOH = –30 /C0109A VCC – 0.7 – V VOH1 Output high voltage (port 0 in external bus mode), ALE9, PSEN3 VCC = 4.5 V; IOH = –3.2 mA VCC – 0.7 – V IIL Logical 0 input current, ports 1, 2, 3VIN = 0.4 V –1 –50 /C0109A ITL Logical 1-to-0 transition current, ports 1, 2, 36 VIN = 2.0 V; See note 4 – –650 /C0109A ILI Input leakage current, port 0 0.45 < VIN < VCC – 0.3 – ±10 /C0109A ICC Power supply current Active mode (see Note 5) Idle mode (see Note 5) Power-down mode or clock stopped (see Figure 46 for conditions) Tamb = 0°C to 70°C 2 30 /C0109A Tamb = –40°C to +85°C 3 50 /C0109A VRAM RAM keep-alive voltage 1.2 V R RST Internal reset pull-down resistor 40 225 kΩ C IO Pin capacitance10 (except EA) – 15 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOL s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC –0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V. 5. See Figures 43 through 46 for ICC test conditions and Figure 41 for ICC vs. Frequency. 12-clock mode characteristics: Active mode (operating): ICC = 1.0 mA + 1.1 mA × FREQ.[MHz] Active mode (reset): ICC = 7.0 mA + 0.6 mA /C0032 FREQ.[MHz] Idle mode: I CC = 1.0 mA + 0.22 mA /C0032 FREQ.[MHz] 6. This value applies to Tamb = 0°C to +70°C. For Tamb = –40°C to +85°C, ITL = –750 µΑ. 7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15 mA (*NOTE: This is 85 °C specification.) Maximum IOL per 8-bit port: 26 mA Maximum total IOL for all outputs: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1 , except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF (except EA is 25 pF). 11. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection circuitry has been added to the INT0 and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection.

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 46

AC ELECTRICAL CHARACTERISTICS (12-CLOCK MODE, 5 V ±10% OPERATION) Tamb = 0 °C to +70 °C or –40 °C to +85 °C ; VCC = 5 V ±10%, VSS = 0 V1,2,3,4 Symbol Figure Parameter Limits 16 MHz Clock Unit MIN MAX MIN MAX 1/tCLCL 38 Oscillator frequency 0 33 MHz tLHLL 34 ALE pulse width 2 tCLCL –8 117 ns tAVLL 34 Address valid to ALE low tCLCL –13 49.5 ns tLLAX 34 Address hold after ALE low tCLCL –20 42.5 ns tLLIV 34 ALE low to valid instruction in 4 tCLCL –35 215 ns tLLPL 34 ALE low to PSEN low tCLCL –10 52.5 ns tPLPH 34 PSEN pulse width 3 tCLCL –10 177.5 ns tPLIV 34 PSEN low to valid instruction in 3 tCLCL –35 152.5 ns tPXIX 34 Input instruction hold after PSEN 0 0 ns tPXIZ 34 Input instruction float after PSEN tCLCL –10 52.5 ns tAVIV 34 Address to valid instruction in 5 tCLCL –35 277.5 ns tPLAZ 34 PSEN low to address float 10 10 ns Data Memory tRLRH 35 RD pulse width 6 tCLCL –20 355 ns tWLWH 36 WR pulse width 6 tCLCL –20 355 ns tRLDV 35 RD low to valid data in 5 tCLCL –35 277.5 ns tRHDX 35 Data hold after RD 0 0 ns tRHDZ 35 Data float after RD 2 tCLCL –10 115 ns tLLDV 35 ALE low to valid data in 8 tCLCL –35 465 ns tAVDV 35 Address to valid data in 9 tCLCL –35 527.5 ns tLLWL 35, 36 ALE low to RD or WR low 3 tCLCL –15 3 tCLCL +15 172.5 202.5 ns tAVWL 35, 36 Address valid to WR low or RD low 4 tCLCL –15 235 ns tQVWX 36 Data valid to WR transition tCLCL –25 37.5 ns tWHQX 36 Data hold after WR tCLCL –15 47.5 ns tQVWH 36 Data valid to WR high 7 tCLCL –5 432.5 ns tRLAZ 35 RD low to address float 0 0 ns tWHLH 35, 36 RD or WR high to ALE high tCLCL –10 tCLCL +10 52.5 72.5 ns External Clock tCHCX 38 High time 0.32 tCLCL tCLCL – tCLCX ns tCLCX 38 Low time 0.32 tCLCL tCLCL – tCHCX ns tCLCH 38 Rise time 5 ns tCHCL 38 Fall time 5 ns Shift register tXLXL 37 Serial port clock cycle time 12 tCLCL 750 ns tQVXH 37 Output data setup to clock rising edge 10 tCLCL –25 600 ns tXHQX 37 Output data hold after clock rising edge 2 tCLCL –15 110 ns tXHDX 37 Input data hold after clock rising edge 0 0 ns tXHDV 37 Clock rising edge to input data valid5 10 tCLCL –133 492 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all outputs = 80 pF 3. Interfacing the microcontroller to devices with float time up to 45 ns is permitted. This limited bus contention will not cause damage to port 0 drivers. 4. Parts are guaranteed by design to operate down to 0 Hz. 5. Below 16 MHz this parameter is 8 t CLCL – 133.

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 47

AC ELECTRICAL CHARACTERISTICS (12-CLOCK MODE, 2.7 V TO 5.5 V OPERATION) Tamb = 0 °C to +70 °C or –40 °C to +85 °C ; VCC = 2.7 V to 5.5 V, VSS = 0 V1,2,3,4 Symbol Figure Parameter Limits 16 MHz Clock Unit MIN MAX MIN MAX 1/tCLCL 38 Oscillator frequency 0 16 MHz tLHLL 34 ALE pulse width 2tCLCL –10 115 ns tAVLL 34 Address valid to ALE low tCLCL –15 47.5 ns tLLAX 34 Address hold after ALE low tCLCL –25 37.5 ns tLLIV 34 ALE low to valid instruction in 4 tCLCL –55 195 ns tLLPL 34 ALE low to PSEN low tCLCL –15 47.5 ns tPLPH 34 PSEN pulse width 3 tCLCL –15 172.5 ns tPLIV 34 PSEN low to valid instruction in 3 tCLCL –55 132.5 ns tPXIX 34 Input instruction hold after PSEN 0 0 ns tPXIZ 34 Input instruction float after PSEN tCLCL –10 52.5 ns tAVIV 34 Address to valid instruction in 5 tCLCL –50 262.5 ns tPLAZ 34 PSEN low to address float 10 10 ns Data Memory tRLRH 35 RD pulse width 6 tCLCL –25 350 ns tWLWH 36 WR pulse width 6 tCLCL –25 350 ns tRLDV 35 RD low to valid data in 5 tCLCL –50 262.5 ns tRHDX 35 Data hold after RD 0 0 ns tRHDZ 35 Data float after RD 2 tCLCL –20 105 ns tLLDV 35 ALE low to valid data in 8 tCLCL –55 445 ns tAVDV 35 Address to valid data in 9 tCLCL –50 512.5 ns tLLWL 35, 36 ALE low to RD or WR low 3 tCLCL –20 3 tCLCL +20 167.5 207.5 ns tAVWL 35, 36 Address valid to WR low or RD low 4 tCLCL –20 230 ns tQVWX 36 Data valid to WR transition tCLCL –30 32.5 ns tWHQX 36 Data hold after WR tCLCL –20 42.5 ns tQVWH 36 Data valid to WR high 7 tCLCL –10 427.5 ns tRLAZ 35 RD low to address float 0 0 ns tWHLH 35, 36 RD or WR high to ALE high tCLCL –15 tCLCL +15 47.5 77.5 ns External Clock tCHCX 38 High time 0.32 tCLCL tCLCL – tCLCX ns tCLCX 38 Low time 0.32 tCLCL tCLCL – tCHCX ns tCLCH 38 Rise time 5 ns tCHCL 38 Fall time 5 ns Shift register tXLXL 37 Serial port clock cycle time 12 tCLCL 750 ns tQVXH 37 Output data setup to clock rising edge 10 tCLCL –25 600 ns tXHQX 37 Output data hold after clock rising edge 2 tCLCL –15 110 ns tXHDX 37 Input data hold after clock rising edge 0 0 ns tXHDV 37 Clock rising edge to input data valid5 10 tCLCL –133 492 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all outputs = 80 pF 3. Interfacing the microcontroller to devices with float time up to 45 ns is permitted. This limited bus contention will not cause damage to port 0 drivers. 4. Parts are guaranteed by design to operate down to 0 Hz. 5. Below 16 MHz this parameter is 8 t CLCL – 133.

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 48

AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE, 5 V ±10% OPERATION) Tamb = 0 °C to +70 °C or –40 °C to +85 °C ; VCC = 5 V ±10%, VSS = 0 V1,2,3,4,5 Symbol Figure Parameter Limits 16 MHz Clock Unit MIN MAX MIN MAX 1/tCLCL 38 Oscillator frequency 0 30 MHz tLHLL 34 ALE pulse width tCLCL –8 54.5 ns tAVLL 34 Address valid to ALE low 0.5 tCLCL –13 18.25 ns tLLAX 34 Address hold after ALE low 0.5 tCLCL –20 11.25 ns tLLIV 34 ALE low to valid instruction in 2 tCLCL –35 90 ns tLLPL 34 ALE low to PSEN low 0.5 tCLCL –10 21.25 ns tPLPH 34 PSEN pulse width 1.5 tCLCL –10 83.75 ns tPLIV 34 PSEN low to valid instruction in 1.5 tCLCL –35 58.75 ns tPXIX 34 Input instruction hold after PSEN 0 0 ns tPXIZ 34 Input instruction float after PSEN 0.5 tCLCL –10 21.25 ns tAVIV 34 Address to valid instruction in 2.5 tCLCL –35 121.25 ns tPLAZ 34 PSEN low to address float 10 10 ns Data Memory tRLRH 35 RD pulse width 3 tCLCL –20 167.5 ns tWLWH 36 WR pulse width 3 tCLCL –20 167.5 ns tRLDV 35 RD low to valid data in 2.5 tCLCL –35 121.25 ns tRHDX 35 Data hold after RD 0 0 ns tRHDZ 35 Data float after RD tCLCL –10 52.5 ns tLLDV 35 ALE low to valid data in 4 tCLCL –35 215 ns tAVDV 35 Address to valid data in 4.5 tCLCL –35 246.25 ns tLLWL 35, 36 ALE low to RD or WR low 1.5 tCLCL –15 1.5 tCLCL +15 78.75 108.75 ns tAVWL 35, 36 Address valid to WR low or RD low 2 tCLCL –15 110 ns tQVWX 36 Data valid to WR transition 0.5 tCLCL –25 6.25 ns tWHQX 36 Data hold after WR 0.5 tCLCL –15 16.25 ns tQVWH 36 Data valid to WR high 3.5 tCLCL –5 213.75 ns tRLAZ 35 RD low to address float 0 0 ns tWHLH 35, 36 RD or WR high to ALE high 0.5 tCLCL –10 0.5 tCLCL +10 21.25 41.25 ns External Clock tCHCX 38 High time 0.4 tCLCL tCLCL – tCLCX ns tCLCX 38 Low time 0.4 tCLCL tCLCL – tCHCX ns tCLCH 38 Rise time 5 ns tCHCL 38 Fall time 5 ns Shift register tXLXL 37 Serial port clock cycle time 6 tCLCL 375 ns tQVXH 37 Output data setup to clock rising edge 5 tCLCL –25 287.5 ns tXHQX 37 Output data hold after clock rising edge tCLCL –15 47.5 ns tXHDX 37 Input data hold after clock rising edge 0 0 ns tXHDV 37 Clock rising edge to input data valid6 5 tCLCL –133 179.5 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN =100 pF, load capacitance for all outputs = 80 pF 3. Interfacing the microcontroller to devices with float time up to 45ns is permitted. This limited bus contention will not cause damage to port 0 drivers. 4. Parts are guaranteed by design to operate down to 0 Hz. 5. Data shown in the table are the best mathematical models for the set of measured values obtained in tests. If a particular parameter calculated at a customer specified frequency has a negative value, it should be considered equal to zero. 6. Below 16 MHz this parameter is 4 t CLCL – 133

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 49

AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE, 2.7 V TO 5.5 V OPERATION) Tamb = 0 °C to +70 °C or –40 °C to +85 °C ; VCC =2.7 V to 5.5 V, VSS = 0 V1,2,3,4,5 Symbol Figure Parameter Limits 16 MHz Clock Unit MIN MAX MIN MAX 1/tCLCL 38 Oscillator frequency 0 16 MHz tLHLL 34 ALE pulse width tCLCL –10 52.5 ns tAVLL 34 Address valid to ALE low 0.5 tCLCL –15 16.25 ns tLLAX 34 Address hold after ALE low 0.5 tCLCL –25 6.25 ns tLLIV 34 ALE low to valid instruction in 2 tCLCL –55 70 ns tLLPL 34 ALE low to PSEN low 0.5 tCLCL –15 16.25 ns tPLPH 34 PSEN pulse width 1.5 tCLCL –15 78.75 ns tPLIV 34 PSEN low to valid instruction in 1.5 tCLCL –55 38.75 ns tPXIX 34 Input instruction hold after PSEN 0 0 ns tPXIZ 34 Input instruction float after PSEN 0.5 tCLCL –10 21.25 ns tAVIV 34 Address to valid instruction in 2.5 tCLCL –50 101.25 ns tPLAZ 34 PSEN low to address float 10 10 ns Data Memory tRLRH 35 RD pulse width 3 tCLCL –25 162.5 ns tWLWH 36 WR pulse width 3 tCLCL –25 162.5 ns tRLDV 35 RD low to valid data in 2.5 tCLCL –50 106.25 ns tRHDX 35 Data hold after RD 0 0 ns tRHDZ 35 Data float after RD tCLCL –20 42.5 ns tLLDV 35 ALE low to valid data in 4 tCLCL –55 195 ns tAVDV 35 Address to valid data in 4.5 tCLCL –50 231.25 ns tLLWL 35, 36 ALE low to RD or WR low 1.5 tCLCL –20 1.5 tCLCL +20 73.75 113.75 ns tAVWL 35, 36 Address valid to WR low or RD low 2 tCLCL –20 105 ns tQVWX 36 Data valid to WR transition 0.5 tCLCL –30 1.25 ns tWHQX 36 Data hold after WR 0.5 tCLCL –20 11.25 ns tQVWH 36 Data valid to WR high 3.5 tCLCL –10 208.75 ns tRLAZ 35 RD low to address float 0 0 ns tWHLH 35, 36 RD or WR high to ALE high 0.5 tCLCL –15 0.5 tCLCL +15 16.25 46.25 ns External Clock tCHCX 38 High time 0.4 tCLCL tCLCL – tCLCX ns tCLCX 38 Low time 0.4 tCLCL tCLCL – tCHCX ns tCLCH 38 Rise time 5 ns tCHCL 38 Fall time 5 ns Shift register tXLXL 37 Serial port clock cycle time 6 tCLCL 375 ns tQVXH 37 Output data setup to clock rising edge 5 tCLCL –25 287.5 ns tXHQX 37 Output data hold after clock rising edge tCLCL –15 47.5 ns tXHDX 37 Input data hold after clock rising edge 0 0 ns tXHDV 37 Clock rising edge to input data valid6 5 tCLCL –133 179.5 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN =100 pF, load capacitance for all outputs = 80 pF 3. Interfacing the microcontroller to devices with float time up to 45ns is permitted. This limited bus contention will not cause damage to port 0 drivers. 4. Parts are guaranteed by design to operate down to 0 Hz. 5. Data shown in the table are the best mathematical models for the set of measured values obtained in tests. If a particular parameter calculated at a customer specified frequency has a negative value, it should be considered equal to zero. 6. Below 16 MHz this parameter is 4 t CLCL – 133

2003 Jan 24 50

AVLL = Time for address valid to ALE low. tLLPL =Time for ALE low to PSEN low. Figure 34. External Program Memory Read Cycle Figure 35. External Data Memory Read Cycle

2003 Jan 24 51

Figure 36. External Data Memory Write Cycle Figure 37. Shift Register Mode Timing Figure 38. External Clock Drive

2003 Jan 24 52

AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Figure 39. AC Testing Input/Output OH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 40. Float Waveform Figure 41. ICC vs. FREQ for 12-clock operation

2003 Jan 24 53

Figure 42. Source code used in measuring IDD operational

2003 Jan 24 54

Figure 43. ICC Test Condition, Active Mode Figure 44. ICC Test Condition, Idle Mode Figure 45. Clock Signal Waveform for ICC Tests in Active and Idle Modes Figure 46. ICC Test Condition, Power Down Mode

2003 Jan 24 55

width and number of the ALE/PROG pulses. circuit configuration for normal program memory verification. Figure 47. Note that the device is running with a 4 to 6MHz device is executing internal address and program data transfers. low 5 times as shown in Figure 48. programmed, verification cycles will produce only encrypted data. required on port 0 for this operation. data. The encryption table itself cannot be read out. which satisfies the timing specifications, is suitable. programmed, in addition to the above, verify mode is disabled. above apply and all external program memory execution is disabled. 64 bytes of encryption array are initially unprogrammed (all 1s).  Trademark phrase of Intel Corporation.

2003 Jan 24 56

Table 8. EPROM Programming Modes

1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. VCC = 5 V±10% during programming and verification.
3. Security bit one is output on P0.7.

Security bit two is output on P0.6. Security bit three is output on P0.3. 12.75 V. Each programming pulse is low for 100 µs (±10 µs) and high for a minimum of 10 µs. Table 9. Program Security Bits for EPROM Devices

2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes

3 P P U Same as 2, also verify is disabled. 4 P P P Same as 3, external execution is disabled. Internal data RAM is not accessible.

1. P – programmed. U – unprogrammed.
2. Any other combination of the security bits is not defined.

2003 Jan 24 57

5 PULSES TO GROUND

Figure 47. Programming Configuration

5 PULSES

Figure 48. PROG Waveform

0 ENABLE

Figure 49. Program Verification

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• FOR PROGRAMMING CONFIGURATION SEE FIGURE 47.

FOR VERIFICATION CONDITIONS SEE FIGURE 49. Figure 50. EPROM Programming and Verification

2003 Jan 24 59

are programmed, in addition to the above, verify mode is disabled. 64 bytes of encryption array are initially unprogrammed (all 1s). Table 10. Program Security Bits 1 U U No Program Security features enabled. is sampled and latched on Reset, and further programming of the EPROM is disabled.

1. P – programmed. U – unprogrammed.
2. Any other combination of the security bits is not defined.
3. 64 byte ROM encryption key
4. External MOVC is disabled, and

Security Bit 2:When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. Encryption: /C0086No /C0086Yes If Yes, must send key file.

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 60

ROM CODE SUBMISSION FOR 16K ROM DEVICES (87C51RB2) When submitting ROM code for the 16K ROM devices, the following must be specified: 1. 16 kbyte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS CONTENT BIT(S) COMMENT 0000H to 3FFFH DATA 7:0 User ROM Data 4000H to 403FH KEY 7:0 ROM Encryption Key FFH = no encryption 4040H SEC 0 ROM Security Bit 1 0 = enable security 1 = disable security 4040H SEC 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1:/C0086Enabled /C0086Disabled Security Bit #2:/C0086Enabled /C0086Disabled Encryption: /C0086No /C0086Yes If Yes, must send key file.

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 61

ROM CODE SUBMISSION FOR 32K ROM DEVICES (87C51RC2) When submitting ROM code for the 32K ROM devices, the following must be specified: 1. 32 kbyte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS CONTENT BIT(S) COMMENT 0000H to 7FFFH DATA 7:0 User ROM Data 8000H to 803FH KEY 7:0 ROM Encryption Key FFH = no encryption 8040H SEC 0 ROM Security Bit 1 0 = enable security 1 = disable security 8040H SEC 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1:/C0086Enabled /C0086Disabled Security Bit #2:/C0086Enabled /C0086Disabled Encryption: /C0086No /C0086Yes If Yes, must send key file.

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 62

ROM CODE SUBMISSION FOR 64K ROM DEVICE (87C51RD2) When submitting ROM code for the 64K ROM devices, the following must be specified: 1. 64 kbyte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS CONTENT BIT(S) COMMENT 0000H to FFFFH DATA 7:0 User ROM Data 10000H to 1003FH KEY 7:0 ROM Encryption Key FFH = no encryption 10040H SEC 0 ROM Security Bit 1 0 = enable security 1 = disable security 10040H SEC 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1:/C0086Enabled /C0086Disabled Security Bit #2:/C0086Enabled /C0086Disabled Encryption: /C0086No /C0086Yes If Yes, must send

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 63

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 64

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 65

LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm SOT389-1

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 66

REVISION HISTORY

_3 20030124 Product data (9397 750 10994); ECN 853-2391 29335 dated 07 Jan 2003. Modifications:

• Updated ordering information table. _2 20021028 Product data (9397 750 10393); ECN 853-2391 29117 dated 28 Oct 2002.

Philips Semiconductors Product data P87C51RA2/RB2/RC2/RD280C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)

2003 Jan 24 67

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to:  Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Date of release: 01-03 Document order number: 9397 750 10994 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status[1] Objective data Preliminary data Product data Product status[2] [3] Development Qualification Production Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Level I II III