P87C51RC+4B

8XC54 PHILIPS | Alldatasheet

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Technical content

/C0080 /C0115 /C0111/C0110/C0111 /C0115 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA + 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz) Product specification Replaces datasheet 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA + of 1999 Apr 01

2000 Aug 07

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

22000 Aug 07 853-2068 24292

DESCRIPTION

Three different Single-Chip 8-Bit Microcontroller families are presented in this datasheet:

• 8XC54/8XC58
• 80C51FA/8XC51FA/8XC51FB/8XC51FC
• 80C51RA+/8XC51RA+/8XC51RB+/8XC51RC+/8XC51RD+ For applications requiring 4K ROM/EPROM, see the 8XC51/80C31 8-bit CMOS (low voltage, low power, and high speed) microcontroller families datasheet. All the families are Single-Chip 8-Bit Microcontrollers manufactured in advanced CMOS process and are derivatives of the 80C51 microcontroller family. All the devices have the same instruction set as the 80C51. These devices provide architectural enhancements that make them applicable in a variety of applications for general control systems. ROM/EPROM Memory Size (X by 8) RAM Size (X by 8) Programmable Timer Counter (PCA) Hardware Watch Dog Timer 80C31/8XC51 0K/4K 128 No No 8XC54/58 0K/8K/16K/32K 256 No No 80C51FA/8XC51FA/FB/FC 0K/8K/16K/32K 256 Yes No 80C51RA+/8XC51RA+/RB+/RC+ 0K/8K/16K/32K 512 Yes Yes 8XC51RD+ 64K 1024 Yes Yes The ROMless devices, 80C51FA, and 80C51RA+ can address up to 64K of external memory. All the devices have four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, four-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. For systems that require extra memory capability up to 64k bytes, each can be expanded using standard TTL-compatible memories and logic. Its added features make it an even more powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control. It also has a more versatile serial channel that facilitates multiprocessor communications.

FEATURES

• 80C51 Central Processing Unit
• Speed up to 33 MHz
• Full static operation
• Operating voltage range: 2.7 V to 5.5 V @ 16 MHz
• Security bits: – ROM – 2 bits – OTP–EPROM – 3 bits
• Encryption array – 64 bytes
• RAM expandable to 64K bytes
• 4 level priority interrupt
• 6 or7 interrupt sources, depending on device
• Four 8-bit I/O ports
• Full-duplex enhanced UART – Framing error detection – Automatic address recognition
• Power control modes – Clock can be stopped and resumed – Idle mode – Power down mode
• Programmable clock out
• Second DPTR register
• Asynchronous port reset
• Low EMI (inhibit ALE)

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

2000 Aug 07 3

DPTR’S MULTIPLE SFRs TIMERS P.C.A. (FA & RA+ only) SU00831B 8 16

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

2000 Aug 07 4

DUAL IN-LINE PACKAGE PIN FUNCTIONS 20 21 40T2/P1.0 T2EX/P1.1 ECI/P1.2 CEX0/P1.3 CEX1/P1.4 CEX2/P1.5 CEX3/P1.6 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 CEX4/P1.7 WR /P3.6 RD /P3.7 XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG EA /VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 V CC DUAL IN-LINE PACKAGE SU00021 PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS LCC 614 0 18 28 Pin Function

1 NIC*

2 P1.0/T2 3 P1.1/T2EX 4 P1.2/ECI 5 P1.3/CEX0 6 P1.4/CEX1 7 P1.5/CEX2 8 P1.6/CEX3 9 P1.7/CEX4

10 RST

11 P3.0/RxD

12 NIC*

13 P3.1/TxD 14 P3.2/INT0 15 P3.3/INT1 Pin Function 16 P3.4/T0 17 P3.5/T1 18 P3.6/WR 19 P3.7/RD

20 XTAL2

21 XTAL1

23 NIC*

24 P2.0/A8 25 P2.1/A9 26 P2.2/A10 27 P2.3/A11 28 P2.4/A12 29 P2.5/A13 30 P2.6/A14 Pin Function 31 P2.7/A15

32 PSEN

33 ALE/PROG

34 NIC*

/VPP 36 P0.7/AD7 37 P0.6/AD6 38 P0.5/AD5 39 P0.4/AD4 40 P0.3/AD3 41 P0.2/AD2 42 P0.1/AD1 43 P0.0/AD0 44 V CC SU00023* NO INTERNAL CONNECTION PLASTIC QUAD FLAT PACK PIN FUNCTIONS PQFP 44 34 12 22 Pin Function 1 P1.5/CEX2 2 P1.6/CEX3 3 P1.7/CEX4

4 RST

5 P3.0/RxD

6 NIC*

7 P3.1/TxD 8 P3.2/INT0 9 P3.3/INT1 10 P3.4/T0 11 P3.5/T1 12 P3.6/WR 13 P3.7/RD

14 XTAL2

15 XTAL1

16 V SS

17 NIC*

18 P2.0/A8 19 P2.1/A9 20 P2.2/A10 21 P2.3/A11 22 P2.4/A12 23 P2.5/A13 24 P2.6/A14 25 P2.7/A15

26 PSEN

27 ALE/PROG

28 NIC*

/VPP 30 P0.7/AD7 Pin Function 31 P0.6/AD6 32 P0.5/AD5 33 P0.4/AD4 34 P0.3/AD3 35 P0.2/AD2 36 P0.1/AD1 37 P0.0/AD0 38 V CC

39 NIC*

40 P1.0/T2 41 P1.1/T2EX 42 P1.2/ECI 43 P1.3/CEX0 44 P1.4/CEX1 SU00024* NO INTERNAL CONNECTION

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

2000 Aug 07 5

MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION VSS 20 22 16 I Ground: 0 V reference. VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0–0.7 39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification and received code bytes during EPROM programming. External pull-ups are required during program verification. 1–3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Port 1 also receives the low-order address byte during program memory verification. Alternate functions for 8XC51FX and 8XC51RX+ Port 1 include: 1 2 40 I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout (see Programmable Clock-Out) 2 3 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control 3 4 42 I ECI (P1.2): External Clock Input to the PCA 4 5 43 I/O CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 5 6 44 I/O CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 6 7 1 I/O CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 7 8 2 I/O CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 8 9 3 I/O CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Some Port 2 pins receive the high order address bits during EPROM programming and verification. 13–19 7–13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: I IL). Port 3 also serves the special features of the 80C51 family, as listed below: 10 11 5 I RxD (P3.0): Serial input port 11 13 7 O TxD (P3.1): Serial output port 12 14 8 I INT0 (P3.2): External interrupt 13 15 9 I INT1 (P3.3): External interrupt 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC . ALE/PROG 30 33 27 O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG ) during EPROM programming. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

2000 Aug 07 6

PIN DESCRIPTIONS (Continued) PIN NUMBER MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA /VPP 31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations starting with 0000H. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 8k Devices (IFFFH), 16k Devices (3FFFH) or 32k Devices (7FFFH). Since the RD+ has 64k Internal Memory, the RD+ will execute only from internal memory when EA is held high. This pin also receives the 12.75 V programming supply voltage (VPP ) during EPROM programming. If security bit 1 is programmed, EA will be internally latched on Reset. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5 V or VSS – 0.5 V, respectively.

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

2000 Aug 07 7

8XC54/58 ORDERING INFORMATION MEMORY SIZE 16K × 8 MEMORY SIZE 32K × 8 TEMPERATURE RANGE °C AND PACKAGE VOLTAGE RANGE FREQ. (MHz) DWG. ROM P80C54SBPN P80C58SBPN 0 to +70 Plastic Dual In line Package2.7 V to 0t o1 6 SOT129 1OTP P87C54SBPN P87C58SBPN 0 to +70, Plastic D ual In-line Package 5.5 V 0 to 16 SOT129 -1 ROM P80C54SBAA P80C58SBAA 0 to +70 Plastic Leaded Chip Carrier 2.7 V to 0t o1 6 SOT187 2OTP P87C54SBAA P87C58SBAA 0 to +70, Plastic Leaded Chip Carrier 5.5 V 0 to 16 SOT187 -2 ROM P80C54SBBB P80C58SBBB 0 to +70 Plastic Quad Flat Pack 2.7 V to 0t o1 6 SOT307 2OTP P87C54SBBB P87C58SBBB 0 to +70, Plastic Q uad Flat Pack 5.5 V 0 to 16 SOT307 -2 ROM P80C54SFPN P80C58SFPN 40 to +85 Plastic Dual In line Package2.7 V to 0t o1 6 SOT129 1OTP P87C54SFPN P87C58SFPN –40 to +85, Plastic D ual In-line Package 5.5 V 0 to 16 SOT129 -1 ROM P80C54SFA A P80C58SFA A 40 to +85 Plastic Leaded Chip Carrier 2.7 V to 0t o1 6 SOT187 2OTP P87C54SFA A P87C58SFA A –40 to +85, Plastic Leaded Chip Carrier 5.5 V 0 to 16 SOT187 -2 ROM P80C54SFBB P80C58SFBB 40 to +85 Plastic Quad Flat Pack 2.7 V to 0t o1 6 SOT307 2OTP P87C54SFBB P87C58SFBB –40 to +85, Plastic Q uad Flat Pack 5.5 V 0 to 16 SOT307 -2 ROM P80C54UBAA P80C58UBAA 0 to +70 Plastic Leaded Chip Carrier 5V 0t o3 3 SOT187 2OTP P87C54UBAA P87C58UBAA 0 to +70, Plastic Leaded Chip Carrier 5 V 0 to 33 SOT187 -2 ROM P80C54UBPN P80C58UBPN 0 to +70 Plastic Dual In line Package 5V 0t o3 3 SOT129 1OTP P87C54UBPN P87C58UBPN 0 to +70, Plastic D ual In-line Package 5 V 0 to 33 SOT129 -1 ROM P80C54UBBB P80C58UBBB 0 to +70 Plastic Quad Flat Pack 5V 0t o3 3 SOT307 2OTP P87C54UBBB P87C58UBBB 0 to +70, Plastic Q uad Flat Pack 5 V 0 to 33 SOT307 -2 ROM P80C54UFA A P80C58UFA A 40 to +85 Plastic Leaded Chip Carrier 5V 0t o3 3 SOT187 2OTP P87C54UFA A P87C58UFA A –40 to +85, Plastic Leaded Chip Carrier 5 V 0 to 33 SOT187 -2 ROM P80C54UFPN P80C58UFPN 40 to +85 Plastic Dual In line Package 5V 0t o3 3 SOT129 1OTP P87C54UFPN P87C58UFPN –40 to +85, Plastic D ual In-line Package 5 V 0 to 33 SOT129 -1 ROM P80C54UFBB P80C58UFBB 40 to +85 Plastic Quad Flat Pack 5V 0t o3 3 SOT307 2OTP P87C54UFBB P87C58UFBB –40 to +85, Plastic Q uad Flat Pack 5 V 0 to 33 SOT307 -2 Note: For Multi Time Programmable devices, See P89C51RX+ Flash datasheet.

80C51 8-bit microcontroller family Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33MHz)

82000 Aug 07

8XC51FA/FB/FC AND 80C51FA ORDERING INFORMATION MEMORY SIZE 8K × 8 MEMORY SIZE 16K × 8 MEMORY SIZE 32K × 8 ROMless TEMPERATURE RANGE °C AND PACKAGE VOLTAGE RANGE FREQ. (MHz) DWG. ROM P83C51FA–4N P83C51FB–4N P83C51FC–4N P80C51FA 4N 0 to +70 40 Pin Plastic Dual In line Pkg27 Vt o55 V 0t o1 6 SOT129 1OTP P87C51FA–4N P87C51FB–4N P87C51FC–4N P80C51FA –4N 0 to +70, 40-Pin Plastic D ual In-line Pkg. 2.7V to 5.5V 0 to 16 SOT129 -1 ROM P83C51FA–4A P83C51FB–4A P83C51FC–4A P80C51FA 4A 0 to +70 44 Pin Plastic Leaded Chip Carrier 27 Vt o55 V 0t o1 6 SOT187 2OTP P87C51FA–4A P87C51FB–4A P87C51FC–4A P80C51FA –4A 0 to +70, 44-Pin Plastic Leaded Chip Carrier 2.7V to 5.5V 0 to 16 SOT187 -2 ROM P83C51FA–4B P83C51FB–4B P83C51FC–4B P80C51FA 4B 0 to +70 44 Pin Plastic Quad Flat Pack27 Vt o55 V 0t o1 6 SOT307 2OTP P87C51FA–4B P87C51FB–4B P87C51FC–4B P80C51FA –4B 0 to +70, 44-Pin Plastic Q uad Flat Pack 2.7V to 5.5V 0 to 16 SOT307 -2 ROM P83C51FA–5N P83C51FB–5N P83C51FC–5N P80C51FA 5N 40 to +85 40 Pin Plastic Dual In line Pkg27 Vt o55 V 0t o1 6 SOT129 1OTP P87C51FA–5N P87C51FB–5N P87C51FC–5N P80C51FA –5N –40 to +85, 40-Pin Plastic D ual In-line Pkg. 2.7V to 5.5V 0 to 16 SOT129 -1 ROM P83C51FA–5A P83C51FB–5A P83C51FC–5A P80C51FA 5A 40 to +85 44 Pin Plastic Leaded Chip Carrier 27 Vt o55 V 0t o1 6 SOT187 2OTP P87C51FA–5A P87C51FB–5A P87C51FC–5A P80C51FA –5A –40 to +85, 44-Pin Plastic Leaded Chip Carrier 2.7V to 5.5V 0 to 16 SOT187 -2 ROM P83C51FA–5B P83C51FB–5B P83C51FC–5B P80C51FA 5B 40 to +85 44 Pin Plastic Quad Flat Pack27 Vt o55 V 0t o1 6 SOT307 2OTP P87C51FA–5B P87C51FB–5B P87C51FC–5B P80C51FA –5B –40 to +85, 44-Pin Plastic Q uad Flat Pack 2.7V to 5.5V 0 to 16 SOT307 -2 ROM P83C51FA–IN P83C51FB–IN P83C51FC–IN P80C51FA IN 0 to +70 40 Pin Plastic Dual In line Pkg 5V 0t o3 3 SOT129 1OTP P87C51FA–IN P87C51FB–IN P87C51FC–IN P80C51FA –IN 0 to +70, 40-Pin Plastic D ual In-line Pkg. 5V 0 to 33 SOT129 -1 ROM P83C51FA–IA P83C51FB–IA P83C51FC–IA P80C51FA IA 0 to +70 44 Pin Plastic Leaded Chip Carrier 5V 0t o3 3 SOT187 2OTP P87C51FA–IA P87C51FB–IA P87C51FC–IA P80C51FA –IA 0 to +70, 44-Pin Plastic Leaded Chip Carrier 5V 0 to 33 SOT187 -2 ROM P83C51FA–IB P83C51FB–IB P83C51FC–IB P80C51FA IB 0 to +70 44 Pin Plastic Quad Flat Pack 5V 0t o3 3 SOT307 2OTP P87C51FA–IB P87C51FB–IB P87C51FC–IB P80C51FA –IB 0 to +70, 44-Pin Plastic Q uad Flat Pack 5V 0 to 33 SOT307 -2 ROM P83C51FA–JN P83C51FB–JN P83C51FC–JN P80C51FA JN 40 to +85 40 Pin Plastic Dual In line Pkg 5V 0t o3 3 SOT129 1OTP P87C51FA–JN P87C51FB–JN P87C51FC–JN P80C51FA –JN –40 to +85, 40-Pin Plastic D ual In-line Pkg. 5V 0 to 33 SOT129 -1 ROM P83C51FA–JA P83C51FB–JA P83C51FC–JA P80C51FA JA 40 to +85 44 Pin Plastic Leaded Chip Carrier 5V 0t o3 3 SOT187 2OTP P87C51FA–JA P87C51FB–JA P87C51FC–JA P80C51FA –JA –40 to +85, 44-Pin Plastic Leaded Chip Carrier 5V 0 to 33 SOT187 -2 ROM P83C51FA–JB P83C51FB–JB P83C51FC–JB P80C51FA JB 40 to +85 44 Pin Plastic Quad Flat Pack 5V 0t o3 3 SOT307 2OTP P87C51FA–JB P87C51FB–JB P87C51FC–JB P80C51FA –JB –40 to +85, 44-Pin Plastic Q uad Flat Pack 5V 0 to 33 SOT307 -2 Note: For Multi Time Programmable devices, See P89C51RX+ Flash datasheet.

80C51 8-bit microcontroller family Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33MHz)

92000 Aug 07

87C51RA+/RB+/RC+/RD+ AND 80C51RA+ ORDERING INFORMATION MEMORY SIZE 8K × 8 MEMORY SIZE 16K × 8 MEMORY SIZE 32K × 8 MEMORY SIZE 64K × 8 ROMless TEMPERATURE RANGE °C AND PACKAGE VOLTAGE RANGE FREQ. (MHz) DWG. ROM P83C51RA+4N P83C51RB+4N P83C51RC+4N P83C51RD+4N P80C51RA+4N 0 to +70, 27 Vt o55 V 0t o1 6 SOT129 1 OTP P87C51RA+4N P87C51RB+4N P87C51RC+4N P87C51RD+4N P80C51RA +4N , 40-Pin Plastic Dual In-line Pkg.2.7V to 5.5V 0 to 16 SOT129 -1 ROM P83C51RA+4A P83C51RB+4A P83C51RC+4A P83C51RD+4A P80C51RA+4A 0 to +70, 27 Vt o55 V 0t o1 6 SOT187 2 OTP P87C51RA+4A P87C51RB+4A P87C51RC+4A P87C51RD+4A P80C51RA +4A , 44-Pin Plastic Leaded Chip Carrier2.7V to 5.5V 0 to 16 SOT187 -2 ROM P83C51RA+4B P83C51RB+4B P83C51RC+4B P83C51RD+4B P80C51RA+4B 0 to +70, 27 Vt o55 V 0t o1 6 SOT307 2 OTP P87C51RA+4B P87C51RB+4B P87C51RC+4B P87C51RD+4B P80C51RA +4B , 44-Pin Plastic Quad Flat Pack2.7V to 5.5V 0 to 16 SOT307 -2 ROM P83C51RA+5N P83C51RB+5N P83C51RC+5N P83C51RD+5N P80C51RA+5N –40 to +85, 27 Vt o55 V 0t o1 6 SOT129 1 OTP P87C51RA+5N P87C51RB+5N P87C51RC+5N P87C51RD+5N P80C51RA +5N , 40-Pin Plastic Dual In-line Pkg.2.7V to 5.5V 0 to 16 SOT129 -1 ROM P83C51RA+5A P83C51RB+5A P83C51RC+5A P83C51RD+5A P80C51RA+5A –40 to +85, 27 Vt o55 V 0t o1 6 SOT187 2 OTP P87C51RA+5A P87C51RB+5A P87C51RC+5A P87C51RD+5A P80C51RA +5A , 44-Pin Plastic Leaded Chip Carrier2.7V to 5.5V 0 to 16 SOT187 -2 ROM P83C51RA+5B P83C51RB+5B P83C51RC+5B P83C51RD+5B P80C51RA+5B –40 to +85, 27 Vt o55 V 0t o1 6 SOT307 2 OTP P87C51RA+5B P87C51RB+5B P87C51RC+5B P87C51RD+5B P80C51RA +5B , 44-Pin Plastic Quad Flat Pack2.7V to 5.5V 0 to 16 SOT307 -2 ROM P83C51RA+IN P83C51RB+IN P83C51RC+IN P83C51RD+IN P80C51RA+IN 0 to +70, 5V 0t o3 3 SOT129 1 OTP P87C51RA+IN P87C51RB+IN P87C51RC+IN P87C51RD+IN P80C51RA +IN , 40-Pin Plastic Dual In-line Pkg.5V 0 to 33 SOT129 -1 ROM P83C51RA+IA P83C51RB+IA P83C51RC+IA P83C51RD+IA P80C51RA+IA 0 to +70, 5V 0t o3 3 SOT187 2 OTP P87C51RA+IA P87C51RB+IA P87C51RC+IA P87C51RD+IA P80C51RA +IA , 44-Pin Plastic Leaded Chip Carrier5V 0 to 33 SOT187 -2 ROM P83C51RA+IB P83C51RB+IB P83C51RC+IB P83C51RD+IB P80C51RA+IB 0 to +70, 5V 0t o3 3 SOT307 2 OTP P87C51RA+IB P87C51RB+IB P87C51RC+IB P87C51RD+IB P80C51RA +IB , 44-Pin Plastic Quad Flat Pack 5V 0 to 33 SOT307 -2 ROM P83C51RA+JN P83C51RB+JN P83C51RC+JN P83C51RD+JN P80C51RA+JN –40 to +85, 5V 0t o3 3 SOT129 1 OTP P87C51RA+JN P87C51RB+JN P87C51RC+JN P87C51RD+JN P80C51RA +JN , 40-Pin Plastic Dual In-line Pkg.5V 0 to 33 SOT129 -1 ROM P83C51RA+JA P83C51RB+JA P83C51RC+JA P83C51RD+JA P80C51RA+JA –40 to +85, 5V 0t o3 3 SOT187 2 OTP P87C51RA+JA P87C51RB+JA P87C51RC+JA P87C51RD+JA P80C51RA +JA , 44-Pin Plastic Leaded Chip Carrier5V 0 to 33 SOT187 -2 ROM P83C51RA+JB P83C51RB+JB P83C51RC+JB P83C51RD+JB P80C51RA+JB –40 to +85, 5V 0t o3 3 SOT307-2 OTP P87C51RA+JB P87C51RB+JB P87C51RC+JB P87C51RD+JB P80C51RA+JB , 44-Pin Plastic Quad Flat Pack 5V 0 to 33 SOT307 -2 Note: For Multi Time Programmable devices, See P89C51RX+ Flash datasheet.

2000 Aug 07 10

Table 1. 8XC54/58 Special Function Registers # SFRs are modified from or added to the 80C51 SFRs.

1. Reset value depends on reset source.
2. Bit will not be affected by Reset.
3. LPEP – Low Power OTP–EPROM only operation.

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Table 2. 8XC51FA/FB/FC, 8XC51RA+/RB+/RC+/RD+ Special Function Registers # SFRs are modified from or added to the 80C51 SFRs.

1. Reset value depends on reset source.
2. Bit will not be affected by Reset.
3. LPEP – Low Power OTP–EPROM only operation.

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Table 2. 8XC51FA/FB/FC, 8XC51RA+/RB+/RC+/RD+ Special Function Registers (Continued) # SFRs are modified from or added to the 80C51 SFRs. the internal clock circuitry is through a divide-by-two flip-flop. the data sheet must be observed. machine cycles (24 oscillator periods), while the oscillator is running. CC and RST must come up at the same time for a proper start-up. IH1 (min.) is applied to RESET.

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lowest power consumption the Power Down mode is suggested. which starts the processor in the same manner as a power-on reset. on-chip RAM to retain their values. oscillator to restart and stabilize (normally less than 10ms). one following the instruction that put the device into Power Down. reset is the result of a power-on or a warm start after powerdown. unaffected by the VCC level.

• When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. ONCE  Mode The ONCE (“On-Circuit Emulation”) Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the device is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied. Programmable Clock-Out A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed: 1. to input the external clock for Timer/Counter 2, or 2. to output a 50% duty cycle clock ranging from 61Hz to 4MHz at a 16MHz operating frequency. To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation: Oscillator Frequency 4 /C0032(65536RCAP2H, RCAP2L) Where (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will be the same.

Table 3. External Pin Status During Idle and Power-Down Mode

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Figure 2. (There is no reload value for TL2 and TH2 in this mode. or down depending on the value of the T2EX pin. generated when either TF2 or EXF2 are 1. In Figure 5 DCEN=1, which enables Timer 2 to count up or down. into the timer registers TL2 and TH2. when either RCLK or TCLK = 1. in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. TR2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer. 1 = External event counter (falling edge triggered). Figure 1. Timer/Counter 2 (T2CON) Control Register

2000 Aug 07 15

Table 4. Timer 2 Operating Modes

1 X 1 Baud rate generator

Figure 2. Timer 2 in Capture Mode T2OE Timer 2 Output Enable bit. DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.

• User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.

Figure 3. Timer 2 Mode (T2MOD) Control Register

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Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0) Figure 5. Timer 2 Auto Reload Mode (DCEN = 1)

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Note availability of additional external interrupt. Figure 6. Timer 2 in Baud Rate Generator Mode Table 5. Timer 2 Generated Commonly Used Timer 1, the other by Timer 2. The timer can be configured for either “timer” or “counter” operation. In many applications, it is configured for “timer” operation (C/T2*=0). RCAP2L taken as a 16-bit unsigned integer. rollover in TH2 does not set TF2, and will not generate an interrupt. will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). can be used as an additional external interrupt, if needed.

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before accessing the Timer 2 or RCAP2 registers. Table 6. Timer 2 as a Timer Table 7. Timer 2 as a Counter

1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33MHz)

2000 Aug 07 19

The UART operates in all of the usual modes that are described in the first section of Data Handbook IC20, 80C51-Based 8-Bit Microcontrollers. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The UART also fully supports multiprocessor communication as does the standard 80C51 UART. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 8. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 9. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are “don’t care”. The SADEN mask can be logically ANDed with the SADDR to create the “Given” address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00X0 Slave 1 SADDR = 1100 0000 SADEN = 1111 1110 Given = 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = 1100 0000 SADEN = 1111 1001 Given = 1100 0XX0 Slave 1 SADDR = 1110 0000 SADEN = 1111 1010 Given = 1110 0X0X Slave 2 SADDR = 1110 0000 SADEN = 1111 1100 Given = 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are trended as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature.

2000 Aug 07 20

frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. Given or Broadcast Address. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. other modes, in any serial transmission. Must be cleared by software. the other modes, in any serial reception (except see SM2). Must be cleared by software. Figure 7. SCON: Serial Port Control Register

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Figure 8. UART Framing Error Detection – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. Figure 9. UART Multiprocessor Communication, Automatic Address Recognition

2000 Aug 07 22

the IPH register and a description of its bits is shown in Figure 12. priority level interrupt that was stopped will be completed. Table 8. Interrupt Table Enable Bit = 1 enables the interrupt. enabled or disabled by setting or clearing its enable bit. IE.6 EC PCA interrupt enable bit for FX and RX+ only – otherwise it is not implemented. IE.5 ET2 Timer 2 interrupt enable bit. IE.4 ES Serial Port interrupt enable bit. IE.3 ET1 Timer 1 interrupt enable bit. IE.2 EX1 External interrupt 1 enable bit. IE.1 ET0 Timer 0 interrupt enable bit. IE.0 EX0 External interrupt 0 enable bit. Figure 10. IE Registers

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IP.7 — Not implemented, reserved for future use. IP.6 PPC PCA interrupt priority bit for FX and RX+ only, otherwise it is not implemented. IP.5 PT2 Timer 2 interrupt priority bit. IP.4 PS Serial Port interrupt priority bit. IP.3 PT1 Timer 1 interrupt priority bit. IP.2 PX1 External interrupt 1 priority bit. IP.1 PT0 Timer 0 interrupt priority bit. IP.0 PX0 External interrupt 0 priority bit. Figure 11. IP Registers IPH.7 — Not implemented, reserved for future use. IPH.6 PPCH PCA interrupt priority bit high for FX and RX+ only, otherwise it is not implemented. IPH.5 PT2H Timer 2 interrupt priority bit high. IPH.4 PSH Serial Port interrupt priority bit high. IPH.3 PT1H Timer 1 interrupt priority bit high. IPH.2 PX1H External interrupt 1 priority bit high. IPH.1 PT0H Timer 0 interrupt priority bit high. IPH.0 PX0H External interrupt 0 priority bit high. Figure 12. IPH Registers

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33MHz)

2000 Aug 07 24

The AO bit (AUXR.0) in the AUXR register when set disables the ALE output. Reduced EMI Mode AUXR (8EH) 7 6 5432 1 0 AUXR.1 EXTRAM (RX+ only) AUXR.0 AO Turns off ALE output. Dual DPTR The dual DPTR structure (see Figure 13) is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 that allows the program code to switch between them.

• New Register Name: AUXR1#
• SFR Address: A2H
• Reset Value: xxxx00x0B 76543210 – – – LPEP GF3 0 – DPS Where: DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1. Select Reg DPS DPTR0 0 DPTR1 1 The DPS bit status should be saved by software when switching between DPTR0 and DPTR1. The GF3 bit is a general purpose user–defined flag. Note that bit 2 is not writable and is always read as a zero. This allows the DPS bit to be quickly toggled simply by executing an INC DPTR instruction without affecting the GF3 or LPEP bits. DPS DPTR1 DPTR0 DPH (83H) DPL (82H) EXTERNAL DATA MEMORY SU00745A BIT0 AUXR1 Figure 13. DPTR Instructions The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1/bit 0 register. The six instructions that use the DPTR are as follows: INC DPTR Increments the data pointer by 1 MOV DPTR, #data16 Loads the DPTR with a 16-bit constant MOV A, @ A+DPTR Move code byte relative to DPTR to ACC MOVX A, @ DPTR Move external RAM (16-bit address) to ACC MOVX @ DPTR , A Move ACC to external RAM (16-bit address) JMP @ A + DPTR Jump indirect relative to DPTR The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See application note AN458 for more details.

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width modulator. Each module has a pin associated with it in port 1. Module 0 is connected to P1.3(CEX0), module 1 to P1.4(CEX1), etc. The basic PCA configuration is shown in Figure 14. In the CMOD SFR are three additional bits associated with the PCA. timer overflows. These functions are shown in Figure 15. flags for the PCA timer (CF) and each module (refer to Figure 18). and the module’s capture/compare register. ECOM (CCAPMn.6) when set enables the comparator function. these registers are used to control the duty cycle of the output.

16 BITS

Figure 14. Programmable Counter Array (PCA)

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Figure 15. PCA Timer/Counter Figure 16. PCA Interrupt System

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it to be gated off during idle. WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. CPS1 PCA Count Pulse Select bit 1. CPS0 PCA Count Pulse Select bit 0. new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 17. CMOD: PCA Counter Mode Register set. CF may be set by either hardware or software but can only be cleared by software. – Not implemented, reserved for future use*. CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF0 PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 18. CCON: PCA Counter Control Register

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– Not implemented, reserved for future use*. ECOMn Enable Comparator. ECOMn = 1 enables the comparator function. CAPPn Capture Positive, CAPPn = 1 enables positive edge capture. CAPNn Capture Negative, CAPNn = 1 enables negative edge capture. in CCON to be set, flagging an interrupt. PWMn Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. ECCFn Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 19. CCAPMn: PCA Modules Compare/Capture Registers Figure 20. PCA Module Modes (CCAPMn Register) SFR are set then an interrupt will be generated. Refer to Figure 21.

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Figure 21. PCA Capture Mode Figure 22. PCA Compare Mode

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Figure 23. PCA High Speed Output Mode Figure 24. PCA PWM Mode

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Figure 25. PCA Watchdog Timer m(Module 4 only) generated. This will not cause the RST pin to be driven high.

1. periodically change the compare value so it will never match the
2. periodically change the PCA timer value so it will never match
3. disable the watchdog by clearing the WDTE bit before a match

occurs and then re-enable it. astray, a match will eventually occur and cause an internal reset. Figure 26 shows the code for initializing the watchdog timer. WATCHDOG routine in Figure 26.

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; Main program goes here, but CALL WATCHDOG periodically. Figure 26. PCA Watchdog Timer Initialization Code

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(768 for RD+) expanded RAM (EXTRAM).

1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are

directly and indirectly addressable.

1. The Upper 128 bytes of RAM (addresses 80H to FFH) are

indirectly addressable only.

1. The Special Function Registers, SFRs, (addresses 80H to FFH)

are directly addressable only.

1. The 256-bytes (768 for RD+) expanded RAM ((EXTRAM

MOVX, and with the EXTRAM bit cleared, see Figure 27. physically separate from SFR space. use indirect addressing access the Upper 128 bytes of data RAM. rather than P2 (whose address is 0A0H). for RD+) of external data memory. P3.6 and P3.7 as write and read timing signals. Refer to Figure 28. generate either read or write signals on P3.6 (#WR) and P3.7 (#RD). not be located in the EXTRAM. 0 ALE is emitted at a constant rate of 1/6 the oscillator frequency. 1 ALE is active only during a MOVX or MOVC instruction.

0 Internal ERAM (00H–FFH) (00H–2FFH for RD+) access using MOVX @Ri/@DPTR

1 External data memory access. — Not implemented, reserved for future use*. bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 27. AUXR: Auxiliary Register (RX+ only)

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256 BYTES

128 BYTES

Figure 28. Internal and External Data Memory Address Space with EXTRAM = 0 be executed within the time required to prevent a WDT reset. resistor the watchdog timer will not function.

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33MHz)

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ABSOLUTE MAXIMUM RATINGS 1, 2, 3 PARAMETER RATING UNIT Operating temperature under bias 0 to +70 or –40 to +85 °C Storage temperature range –65 to +150 °C Voltage on EA/VPP pin to VSS 0 to +13.0 V Voltage on any other pin to VSS –0.5 to +6.5 V Maximum IOL per I/O pin 15 mA Power dissipation (based on package heat transfer limitations, not device power consumption)1.5 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C CLOCK FREQUENCY RANGE –f SYMBOL FIGURE PARAMETER MIN MAX UNIT 1/tCLCL 33 Oscillator frequency Speed versions : 4:5:S (16MHz) I:J:U (33MHz) MHz MHz

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33MHz)

2000 Aug 07 36

DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 2.7V to 5.5V, VSS = 0V (16MHz devices) SYMBOL PARAMETER TEST LIMITS UNITSYMBOL PARAMETER CONDITIONS MIN TYP 1 MAX UNIT V Input low voltage VIL Input low voltage VIH Input high voltage (ports 0, 1, 2, 3, EA) 0.2VCC +0.9 VCC +0.5 V VIH1 Input high voltage, XTAL1, RST 0.7VCC VCC +0.5 V VOL Output low voltage, ports 1, 2 8 VCC = 2.7V IOL = 1.6mA2 0.4 V VOL1 Output low voltage, port 0, ALE, PSEN8, 7 VCC = 2.7V IOL = 3.2mA2 0.4 V VO Output high voltageports 1 2 33 VCC = 2.7V IOH = –20µA VCC – 0.7 V VOH O utput high voltage, ports 1, 2, 3 3 VCC = 4.5V IOH = –30µA VCC – 0.7 V VOH1 Output high voltage (port 0 in external bus mode), ALE 9, PSEN3 VCC = 2.7V IOH = –3.2mA VCC – 0.7 V IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4V –1 –50 µA ITL Logical 1-to-0 transition current, ports 1, 2, 36 VIN = 2.0V See note 4 –650 µA ILI Input leakage current, port 0 0.45 < VIN < VCC – 0.3 ±10 µA ICC Power supply current (see Figure 36): See note 5 Active mode @ 16MHz (all except 8XC51RD+) 87C51RD+ mA mA Idle mode @ 16MHz 4 mA Power-down mode or clock stopped (see Figure 40 f diti ) Tamb = 0°C to 70°C 3 50 µA for conditions) Tamb = –40°C to +85°C 75 µA R RST Internal reset pull-down resistor 40 225 kΩ C IO Pin capacitance10 (except EA) 15 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V OL s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC –0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. See Figures 37 through 40 for ICC test conditions, and Figure 36 for ICC vs Freq. Idle mode: I CC = (0.18 × FREQ. +1.01)mA 6. This value applies to Tamb = 0°C to +70°C. For Tamb = –40°C to +85°C, ITL = –750µA. 7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15mA (*NOTE: This is 85 °C specification.) Maximum IOL per 8-bit port: 26mA Maximum total IOL for all outputs: 71mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1 , except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA is 25pF).

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33MHz)

2000 Aug 07 37

DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, 33MHz devices; 5V ±10%; VSS = 0V SYMBOL PARAMETER TEST LIMITS UNITSYMBOL PARAMETER CONDITIONS MIN TYP 1 MAX UNIT VIH Input high voltage (ports 0, 1, 2, 3, EA) 0.2VCC +0.9 VCC +0.5 V VIH1 Input high voltage, XTAL1, RST 0.7VCC VCC +0.5 V VOL Output low voltage, ports 1, 2, 3 8 VCC = 4.5V IOL = 1.6mA2 0.4 V VOL1 Output low voltage, port 0, ALE, PSEN7, 8 VCC = 4.5V IOL = 3.2mA2 0.4 V VOH Output high voltage, ports 1, 2, 33 VCC = 4.5V IOH = –30µA VCC – 0.7 V VOH1 Output high voltage (port 0 in external bus mode), ALE 9, PSEN3 VCC = 4.5V IOH = –3.2mA VCC – 0.7 V IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4V –1 –50 µA ITL Logical 1-to-0 transition current, ports 1, 2, 36 VIN = 2.0V See note 4 –650 µA ILI Input leakage current, port 0 0.45 < VIN < VCC – 0.3 ±10 µA ICC Power supply current (see Figure 36): See note 5 Active mode (see Note 5) Idle mode (see Note 5) Power-down mode or clock stopped ( Fi 40 f diti ) Tamb = 0°C to 70°C 3 50 µA (see Figure 40 for conditions) Tamb = –40°C to +85°C 75 µA R RST Internal reset pull-down resistor 40 225 kΩ C IO Pin capacitance10 (except EA) 15 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V OL s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC –0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. See Figures 37 through 40 for ICC test conditions and Figure 36 for ICC vs Freq. Idle mode: I CC(MAX) = (0.18 × FREQ. +1.0)mA 6. This value applies to Tamb = 0°C to +70°C. For Tamb = –40°C to +85°C, ITL = –750µA. 7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15mA (*NOTE: This is 85 °C specification.) Maximum IOL per 8-bit port: 26mA Maximum total IOL for all outputs: 71mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1 , except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA is 25pF).

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33MHz)

2000 Aug 07 38

AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = +2.7V to +5.5V, VSS = 0V1, 2, 3 16MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 29 Oscillator frequency5 Speed versions : 4; 5;S 3.5 16 MHz tLHLL 29 ALE pulse width 85 2tCLCL –40 ns tAVLL 29 Address valid to ALE low 22 tCLCL –40 ns tLLAX 29 Address hold after ALE low 32 tCLCL –30 ns tLLIV 29 ALE low to valid instruction in 150 4tCLCL –100 ns tLLPL 29 ALE low to PSEN low 32 tCLCL –30 ns tPLPH 29 PSEN pulse width 142 3tCLCL –45 ns tPLIV 29 PSEN low to valid instruction in 82 3tCLCL –105 ns tPXIX 29 Input instruction hold after PSEN 0 0 ns tPXIZ 29 Input instruction float after PSEN 37 tCLCL –25 ns tAVIV 5 29 Address to valid instruction in 207 5tCLCL –105 ns tPLAZ 29 PSEN low to address float 10 10 ns Data Memory tRLRH 30, 31 RD pulse width 275 6tCLCL –100 ns tWLWH 30, 31 WR pulse width 275 6tCLCL –100 ns tRLDV 30, 31 RD low to valid data in 147 5tCLCL –165 ns tRHDX 30, 31 Data hold after RD 0 0 ns tRHDZ 30, 31 Data float after RD 65 2tCLCL –60 ns tLLDV 30, 31 ALE low to valid data in 350 8tCLCL –150 ns tAVDV 30, 31 Address to valid data in 397 9tCLCL –165 ns tLLWL 30, 31 ALE low to RD or WR low 137 239 3tCLCL –50 3tCLCL +50 ns tAVWL 30, 31 Address valid to WR low or RD low 122 4tCLCL –130 ns tQVWX 30, 31 Data valid to WR transition 13 tCLCL –50 ns tWHQX 30, 31 Data hold after WR 13 tCLCL –50 ns tQVWH 31 Data valid to WR high 287 7tCLCL –150 ns tRLAZ 30, 31 RD low to address float 0 0 ns tWHLH 30, 31 RD or WR high to ALE high 23 103 tCLCL –40 tCLCL +40 ns External Clock tCHCX 33 High time 20 20 tCLCL –tCLCX ns tCLCX 33 Low time 20 20 tCLCL –tCHCX ns tCLCH 33 Rise time 20 20 ns tCHCL 33 Fall time 20 20 ns Shift Register tXLXL 32 Serial port clock cycle time 750 12tCLCL ns tQVXH 32 Output data setup to clock rising edge 492 10tCLCL –133 ns tXHQX 32 Output data hold after clock rising edge 8 2tCLCL –117 ns tXHDX 32 Input data hold after clock rising edge 0 0 ns tXHDV 32 Clock rising edge to input data valid 492 10tCLCL –133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. See application note AN457 for external memory interface. 5. Parts are guaranteed to operate down to 0Hz.

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33MHz)

2000 Aug 07 39

AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3 VARIABLE CLOCK 4 33MHz CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT tLHLL 29 ALE pulse width 2tCLCL –40 21 ns tAVLL 29 Address valid to ALE low tCLCL –25 5 ns tLLAX 29 Address hold after ALE low tCLCL –25 ns tLLIV 29 ALE low to valid instruction in 4tCLCL –65 55 ns tLLPL 29 ALE low to PSEN low tCLCL –25 5 ns tPLPH 29 PSEN pulse width 3tCLCL –45 45 ns tPLIV 29 PSEN low to valid instruction in 3tCLCL –60 30 ns tPXIX 29 Input instruction hold after PSEN 0 0 ns tPXIZ 29 Input instruction float after PSEN tCLCL –25 5 ns tAVIV 29 Address to valid instruction in 5tCLCL –80 70 ns tPLAZ 29 PSEN low to address float 10 10 ns Data Memory tRLRH 30, 31 RD pulse width 6tCLCL –100 82 ns tWLWH 30, 31 WR pulse width 6tCLCL –100 82 ns tRLDV 30, 31 RD low to valid data in 5tCLCL –90 60 ns tRHDX 30, 31 Data hold after RD 0 0 ns tRHDZ 30, 31 Data float after RD 2tCLCL –28 32 ns tLLDV 30, 31 ALE low to valid data in 8tCLCL –150 90 ns tAVDV 30, 31 Address to valid data in 9tCLCL –165 105 ns tLLWL 30, 31 ALE low to RD or WR low 3tCLCL –50 3tCLCL +50 40 140 ns tAVWL 30, 31 Address valid to WR low or RD low 4tCLCL –75 45 ns tQVWX 30, 31 Data valid to WR transition tCLCL –30 0 ns tWHQX 30, 31 Data hold after WR tCLCL –25 5 ns tQVWH 31 Data valid to WR high 7tCLCL –130 80 ns tRLAZ 30, 31 RD low to address float 0 0 ns tWHLH 30, 31 RD or WR high to ALE high tCLCL –25 tCLCL +25 5 55 ns External Clock tCHCX 33 High time 0.38tCLCL tCLCL –tCLCX ns tCLCX 33 Low time 0.38tCLCL tCLCL –tCHCX ns tCLCH 33 Rise time 5 ns tCHCL 33 Fall time 5 ns Shift Register tXLXL 32 Serial port clock cycle time 12tCLCL 360 ns tQVXH 32 Output data setup to clock rising edge 10tCLCL –133 167 ns tXHQX 32 Output data hold after clock rising edge2tCLCL –80 ns tXHDX 32 Input data hold after clock rising edge 0 0 ns tXHDV 32 Clock rising edge to input data valid 10tCLCL –133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. For frequencies equal or less than 16MHz, see 16MHz “AC Electrical Characteristics”, page 38. 5. Parts are guaranteed to operate down to 0Hz.

2000 Aug 07 40

AVLL = Time for address valid to ALE low. tLLPL =Time for ALE low to PSEN low. Figure 29. External Program Memory Read Cycle Figure 30. External Data Memory Read Cycle

2000 Aug 07 41

Figure 31. External Data Memory Write Cycle Figure 32. Shift Register Mode Timing Figure 33. External Clock Drive

2000 Aug 07 42

AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Figure 34. AC Testing Input/Output OH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 35. Float Waveform Figure 36. ICC vs. FREQ

2000 Aug 07 43

Figure 37. ICC Test Condition, Active Mode Figure 38. ICC Test Condition, Idle Mode Figure 39. Clock Signal Waveform for ICC Tests in Active and Idle Modes Figure 40. ICC Test Condition, Power Down Mode

2000 Aug 07 44

width and number of the ALE/PROG pulses. circuit configuration for normal program memory verification. Figure 41. Note that the device is running with a 4 to 6MHz device is executing internal address and program data transfers. low 5 times as shown in Figure 42. programmed, verification cycles will produce only encrypted data. required on port 0 for this operation. data. The encryption table itself cannot be read out. which satisfies the timing specifications, is suitable. are programmed, in addition to the above, verify mode is disabled. above apply and all external program memory execution is disabled. 64 bytes of encryption array are initially unprogrammed (all 1s).  Trademark phrase of Intel Corporation.

2000 Aug 07 45

Table 9. EPROM Programming Modes

1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. VCC = 5V±10% during programming and verification.

12.75V. Each programming pulse is low for 100µs (±10µs) and high for a minimum of 10µs. Table 10. Program Security Bits for EPROM Devices

2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes

3 P P U Same as 2, also verify is disabled. 4 P P P Same as 3, external execution is disabled.

1. P – programmed. U – unprogrammed.
2. Any other combination of the security bits is not defined.

2000 Aug 07 46

5 PULSES TO GROUND

Figure 41. Programming Configuration

5 PULSES

Figure 42. PROG Waveform

0 ENABLE

Figure 43. Program Verification

2000 Aug 07 47

• FOR PROGRAMMING CONFIGURATION SEE FIGURE 41.

FOR VERIFICATION CONDITIONS SEE FIGURE 43. Figure 44. EPROM Programming and Verification

2000 Aug 07 48

programmed, in addition to the above, verify mode is disabled. 64 bytes of encryption array are initially unprogrammed (all 1s). Table 11. Program Security Bits 1 U U No Program Security features enabled. is sampled and latched on Reset, and further programming of the EPROM is disabled.

1. P – programmed. U – unprogrammed.
2. Any other combination of the security bits is not defined.
3. 64 byte ROM encryption key
4. External MOVC is disabled, and

Security Bit 2:When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. Encryption: /C0086No /C0086Yes If Yes, must send key file.

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33MHz)

2000 Aug 07 49

ROM CODE SUBMISSION FOR 16K ROM DEVICES (80C54, 83C51FB AND 83C51RB+) When submitting ROM code for the 16K ROM devices, the following must be specified: 1. 16k byte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS CONTENT BIT(S) COMMENT 0000H to 3FFFH DATA 7:0 User ROM Data 4000H to 403FH KEY 7:0 ROM Encryption Key FFH = no encryption 4040H SEC 0 ROM Security Bit 1 0 = enable security 1 = disable security 4040H SEC 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1:/C0086Enabled /C0086Disabled Security Bit #2:/C0086Enabled /C0086Disabled Encryption: /C0086No /C0086Yes If Yes, must send key file.

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33MHz)

2000 Aug 07 50

ROM CODE SUBMISSION FOR 32K ROM DEVICES (80C58, 83C51FC, AND 83C51RC+) When submitting ROM code for the 32K ROM devices, the following must be specified: 1. 32k byte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS CONTENT BIT(S) COMMENT 0000H to 7FFFH DATA 7:0 User ROM Data 8000H to 803FH KEY 7:0 ROM Encryption Key FFH = no encryption 8040H SEC 0 ROM Security Bit 1 0 = enable security 1 = disable security 8040H SEC 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1:/C0086Enabled /C0086Disabled Security Bit #2:/C0086Enabled /C0086Disabled Encryption: /C0086No /C0086Yes If Yes, must send key file.

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33MHz)

2000 Aug 07 51

ROM CODE SUBMISSION FOR 64K ROM DEVICE (83C51RD+) When submitting ROM code for the 64K ROM devices, the following must be specified: 1. 64k byte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS CONTENT BIT(S) COMMENT 0000H to FFFFH DATA 7:0 User ROM Data 10000H to 1003FH KEY 7:0 ROM Encryption Key FFH = no encryption 10040H SEC 0 ROM Security Bit 1 0 = enable security 1 = disable security 10040H SEC 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1:/C0086Enabled /C0086Disabled Security Bit #2:/C0086Enabled /C0086Disabled Encryption: /C0086No /C0086Yes If Yes, must send

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33MHz)

2000 Aug 07 52

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33MHz)

2000 Aug 07 53

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33MHz)

2000 Aug 07 54

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33MHz)

2000 Aug 07 55

Philips Semiconductors Product specification 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33MHz)

2000 Aug 07 56

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 08-00 Document order number: 9397 750 07405 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.