Power Management

P87702DRHBRQ1

Texas Instruments

Dual Buck Converter and 5-V Boost With Diagnostic Functions

Manufacturer: Texas Instruments

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ADVANCE□INFORMATION Output Current (mA) Efficiency (%) 1 10 100 1000 5000 100 Exce VIN=3.3V, VOUT=1.2V VIN=3.3V, VOUT=1.8V VIN=3.3V, VOUT=2.3V Copyright © 2017, Texas Instruments Incorporated SW_B0VIN_B0 VIN_B1 VANA VIN FB_B0 VOUT0 LOAD SDA (EN3) SCL (EN2) nINT CLKIN (GPO2) GNDs EN1 SW_B1 FB_B1 VOUT1 PG0 VMON1 VMON2 PG1 (GPO1) WDI WD_RESET SW_BST VOUT_BST VOUT2 LOAD LOAD GPO0 NRST Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. LP87702-Q1 SNVSAL1 – DECEMBER 2017 LP87702-Q1DualBuckConverterand5-VBoostWithDiagnosticFunctions

1 Features

1• Qualified for Automotive Applications

AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature
Two High-Efficiency Step-Down DC-DC Regulators: – Maximum Output Current 3.5 A – Auto PWM/PFM and Forced-PWM Operations – Output Voltage = 0.7 V to 3.36 V
5-V Boost Regulator: – Maximum Output Current 600 mA
2-MHz, 3-MHz or 4-MHz Switching Frequency
Two Inputs for External Voltage Monitoring
Two Programmable Power-Good Signals
Dedicated Reference Voltage for Diagnostics
Window Watchdog With Reset Output
External Clock Input to Synchronize Switching
Spread-Spectrum Mode
Programmable Start-up and Shutdown Delays and Sequencing With Enable Signal
Configurable General Purpose Outputs (GPOs)
I2C-Compatible Interface Supporting Standard (100 kHz), Fast (400 kHz), Fast+ (1 MHz), and High-Speed (3.4 MHz) Modes
Interrupt Function with Programmable Masking
Output Short-Circuit and Overload Protection
Overtemperature Warning and Protection
Overvoltage Protection (OVP) and Undervoltage Lockout (UVLO)

2 Applications

Automotive Radar, Camera and Cluster Power

Applications

3 Description

The LP87702-Q1 is designed to meet the power management requirements of the latest platform needs especially in automotive radar, camera and cluster applications. The device contains two step- down DC-DC converters, a 5-V boost converter, two voltage monitoring inputs for external power supplies, window watchdog and general purpose digital output signals. The device is controlled by an I2C-compatible serial interface and by enable signals. The automatic PWM/PFM (AUTO mode) operation gives high efficiency over a wide output current range for both boost and buck regulators. The LP87702-Q1 supports remote voltage sensing for buck regulators to compensate IR drop between the regulator output and the point-of-load thus improving the accuracy of the output voltage. In addition the switching clock can be forced to PWM mode and also synchronized to an external clock to minimize the disturbances. The LP87702-Q1 device supports buck regulator load current measurement without the addition of external current sense resistors. In addition, the LP87702-Q1 device supports programmable start-up and shutdown delays and sequences including general purpose digital output signals synchronized to the enable signal. During start-up and voltage change, the device controls the output slew rate to minimize output voltage overshoot and the inrush current. Device Information PART NUMBER PACKAGE BODY SIZE (NOM) LP87702-Q1 VQFN (32) 5.00 mm × 5.00 mm Simplified Schematic Buck Efficiency vs Output Current

11.2 Receiving Notification of Documentation Updates 81

12 Mechanical, Packaging, and Orderable

4 Revision History

December 2017 *

ADVANCE□INFORMATION 2 3 4 5 61 7 20 19 18 1723 2122 GPO0 NRST VIN_B1 VIN_B1 SW_B1 PGND_B1 PGND_B1 SCL (EN2) SDA (EN3) CLK(GPO2) PGND_B0 PGND_B0 WD_RESET VANA AGND FB_B1 FB_B0 SW_B0 SW_B0 VIN_B0 VIN_B0 THERMAL PAD 16SW_B1 26 15 PG0 VMON1 VMON2 PGND_BST VOUT_BST SW_BST EN1 WDI PG1 (GPO1) nINT LP87702-Q1 www.ti.com SNVSAL1 – DECEMBER 2017 Product Folder Links: LP87702-Q1 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

5 Pin Configuration and Functions

32-Pin VQFN With Thermal Pad Top View

ADVANCE□INFORMATION LP87702-Q1 SNVSAL1 – DECEMBER 2017 www.ti.com Product Folder Links: LP87702-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Pin Functions PIN TYPE DESCRIPTION NUMBER NAME 1 nINT D/O Open-drain interrupt output. Active LOW. 2 FB_B0 A Output voltage feedback for Buck0. 3 FB_B1 A Output voltage feedback for Buck1. 4 AGND G Ground. 5 VANA P Supply voltage for analog and digital blocks. Must be connected to same node with VIN_Bx.

6 WD_RESET D/O Reset output from window watchdog

7 WDI D/I Digital input signal for window watchdog

8 VOUT_BST P/O Boost output. 9 SW_BST P/I Boost input. 10 PGND_BST P/G Power ground for boost. 11 NRST D/I Reset signal for the device. 12 GPO0 D/O General purpose digital output 0. 13, 14 VIN_B1 P/I Input for Buck1. The separate power pins VIN_Bx are not connected together internally - VIN_Bx pins must be connected together in the application and be locally bypassed. 15, 16 SW_B1 P/O Buck1 switch node. 17, 18 PGND_B1 P/G Power Ground for Buck1. 19 EN1 D/I Programmable Enable 1 signal. 20 SCL D/I Serial interface clock input for I2C access. Connect a pullup resistor. Alternative function is programmable enable 2 signal. 21 SDA D/I/O Serial interface data input and output for I2C access. Connect a pullup resistor. Alternative function is programmable enable 3 signal.

22 CLKIN D/I/O

External clock input. Alternative function is general purpose digital output 2 (GPO2). Second alternative function is watchdog disable (WD_DIS). Watchdog disable is not supported in P87702D. 23, 24 PGND_B0 P/G Power ground for Buck0. 25, 26 SW_B0 P/O Buck0 switch node. 27, 28 VIN_B0 P/I Input for Buck0. The separate power pins VIN_Bx are not connected together internally - VIN_Bx pins must be connected together in the application and be locally bypassed. 29 PG0 D/O Programmable power-good indication signal. 30 VMON1 A/I Voltage monitoring input 1. 31 VMON2 A/I Voltage monitoring input 2. 32 PG1 D/O Programmable power-good indication signal. Alternative function is general purpose digital output 1 (GPO1). Thermal pad N/A G A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin

ADVANCE□INFORMATION LP87702-Q1 www.ti.com SNVSAL1 – DECEMBER 2017 Product Folder Links: LP87702-Q1 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground.

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT VIN_B0, VIN_B1, SW_BST, VANA Voltage on input power connections –0.3 6 V SW_B0, SW_B1 Voltage on buck switch nodes –0.3 (VIN_Bx + 0.3 V) with 6-V maximum V FB_B0, FB_B1 Voltage on buck voltage sense nodes –0.3 (VANA + 0.3 V) with 6-V maximum V VOUT_BST Voltage on boost output –0.3 6 V SCL (EN2), SDA (EN3), VMON1, VMON2 Voltage on voltage monitoring pins –0.3 (VANA + 0.3 V) with 6-V maximum V NRST, EN1, nINT Voltage on logic pins (input or output pins) –0.3 6 V PG0, PG1 (GPO1), GPO0, CLKIN (GPO2), WDI, WD_RESET Voltage on logic pins (input or output pins) –0.3 (VANA + 0.3 V) with 6-V maximum V VIN_B0, VIN_B1, SW_B0, SW_B1, PGND_B0, PGND_B1 Current on power pins (average current over 100 k hour lifetime, TJ = TBD°C) TBD A / pin Junction temperature, TJ-MAX −40 150 °C Storage temperature, Tstg –65 150 °C Maximum lead temperature (soldering, 10 seconds) 260 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 VCharged-device model (CDM), per AEC Q100-011 All pins ±500 Corner pins (1, 8, 9, 16, 17, 24, 25, 32) ±750

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT INPUT VOLTAGE VIN_B0, VIN_B1, SW_BST, VANA Voltage on input power connections 2.8 5.5 V VMON1, VMON2 Voltage on voltage monitoring pins 0 5.5 V NRST, EN1, EN2, EN3, nINT Voltage on logic pins (input or output pins) 0 5.5 PG0, PG1 (GPO1), GPO0, CLKIN (GPO2), WDI, WD_RESET Voltage on logic pins (input or output pins) 0 VANA V SCL, SDA Voltage on I2C interface, Standard (100 kHz), Fast (400 kHz), Fast+ (1 MHz), and High-Speed (3.4 MHz) Modes 0 1.95 V Voltage on I2C interface, Standard (100 kHz), Fast (400 kHz), and Fast+ (1 MHz) Modes 0 VANA with 3.6-V maximum V TEMPERATURE Junction temperature, TJ −40 140 °C Ambient temperature, TA −40 125 °C

ADVANCE□INFORMATION LP87702-Q1 SNVSAL1 – DECEMBER 2017 www.ti.com Product Folder Links: LP87702-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) RHB (VQFN) UNIT

32 PINS

RθJA Junction-to-ambient thermal resistance 31.7 °C/W RθJCtop Junction-to-case (top) thermal resistance 17.1 °C/W RθJB Junction-to-board thermal resistance 5.6 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 5.6 °C/W RθJCbot Junction-to-case (bottom) thermal resistance 1.1 °C/W (1) All voltage values are with respect to network ground. (2) Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified, but do represent the most likely norm. (3) The maximum output current can be limited by the forward current limit ILIM FWD. The maximum output current is also limited by the junction temperature and maximum average current over lifetime. The power dissipation inside the die increases the junction temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient temperature.

6.5 Electrical Characteristics

Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVOUT_Bx, VVOUT_BST, and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.3 V, VOUT_BST = 5 V and VOUT_Bx = 1 V, unless otherwise noted(1) (2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EXTERNAL COMPONENTS CIN_BUCK Input filtering capacitance for buck regulators Effective capacitance, connected from VIN_Bx to PGND_Bx 1.9 10 µF COUT_BUCK Output filtering capacitance for buck regulators Effective total capacitance. Maximum includes POL capacitance. 15 22 100 µF COUT_BUCK_POL Point-of-load (POL) capacitance for buck regulators Optional POL capacitance 22 µF COUT_BST Output filtering capacitance for boost regulator Effective capacitance 10 22 40 µF ESRC Input and output capacitor ESR [1-10] MHz 2 10 mΩ LBUCK Inductor for buck regulators Inductance of the inductor 0.47 µH –30% 30% LBST Inductor for boost regulators Inductance of the inductor, 2-MHz switching 1 µHInductance of the inductor, 4-MHz switching 0.47 Inductance of the inductor –30% 30% DCRL Inductor DCR 25 mΩ BUCK REGULATORS V(VIN_Bx), V(VANA) Input voltage range 2.8 3.7 5.5 V VOUT_Bx Output voltage Programmable voltage range 0.7 1 3.36 V Step size, 0.7 V ≤ VOUT < 0.73 V 10 mVStep size, 0.73 V ≤ VOUT < 1.4 V 5 Step size, 1.4 V ≤ VOUT ≤ 3.36 V 20 IOUT_Bx Output current Output current 3.5(3) A Minimum voltage difference between V(VIN_Bx) and VOUT_Bx for electrical characteristics V(VIN_Bx) – VOUT, IOUT_Bx ≤ 2 A 0.8 VV(VIN_Bx) – VOUT, IOUT_Bx > 2 A 1

ADVANCE□INFORMATION LP87702-Q1 www.ti.com SNVSAL1 – DECEMBER 2017 Product Folder Links: LP87702-Q1 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVOUT_Bx, VVOUT_BST, and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.3 V, VOUT_BST = 5 V and VOUT_Bx = 1 V, unless otherwise noted(1) (2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (4) Applies when internal oscillator is used. The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current. (5) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependant on the output voltage, input voltage and the inductor current level. DC output voltage accuracy, includes voltage reference, DC load and line regulations, process and temperature Force PWM mode, VOUT ˂ 1 V –20 20 mV Force PWM mode, VOUT ≥ 1 V –2% 2% PFM mode, VOUT ˂ 1 V, the average output voltage level is increased by maximum 20 mV –20 40 mV PFM mode, VOUT ≥ 1 V, the average output voltage level is increased by maximum 20 mV –2% 2% + 20 mV Ripple voltage PWM mode, L = 0.47 µH 10 mVp-p PFM mode, L = 0.47 µH 25 DCLNR DC line regulation IOUT = IOUT(max) ±0.05 %/V DCLDR DC load regulation in PWM mode VOUT_Bx = 1 V, IOUT from 0 to IOUT(max) 0.3% TLDSR Transient load step response IOUT = 0 A to 3 A, TR = TF = 1 µs, PWM mode, VVIN_Bx = 3.3V, VOUT_Bx = 1 V, COUT = 22 + 22 µF, L = 0.47 µH, fSW = 4 MHz ±60 mV TLNSR Transient line response V(VIN_Bx) stepping 3 V ↔ 3.5 V, TR = TF = 10 µs, IOUT = IOUT(max) ±20 mV ILIM FWD Forward current limit for both bucks (peak for every switching cycle) Programmable range 1.5 4.5 A Step size 0.5 Accuracy, V(VIN_Bx) ≥ 3 V, ILIM = 4 A –5% 7.5% 20% Accuracy, 2.8 V ≤ V(VIN_Bx) < 3 V, ILIM = 4 A –20% 7.5% 20% ILIM NEG Negative current limit 1.6 2 3 A RDS(ON) BUCK HS FET On-resistance, high-side FET Each phase, between VIN_Bx and SW_Bx pins (I = 1 A) 60 110 mΩ RDS(ON) BUCK LS FET On-resistance, low-side FET Each phase, between SW_Bx and PGND_Bx pins (I = 1 A) 55 80 mΩ fSW Switching frequency, PWM mode OTP programmable 2-MHz setting or VOUT_Bx < 0.8 V 1.8 2 2.2 MHz3-MHz setting and VOUT_Bx ≥ 0.8 V 2.7 3 3.3 4-MHz setting and VOUT_Bx ≥ 1.1 V 3.6 4 4.4 Start-up time (soft start) From ENx to VOUT_Bx = 0.35 V (slew-rate control begins) 120 µs Overshoot during start-up 50 mV Output voltage slew-rate(4) SLEW_RATEx[2:0] = 010, VVOUT_Bx ≥ 0.7 V –15% 10 15% mV/µs SLEW_RATEx[2:0] = 011, VVOUT_Bx ≥ 0.7 V –15% 7.5 15% SLEW_RATEx[2:0] = 100, VVOUT_Bx ≥ 0.7 V –15% 3.8 15% SLEW_RATEx[2:0] = 101, VVOUT_Bx ≥ 0.7 V –15% 1.9 15% SLEW_RATEx[2:0] = 110, VVOUT_Bx ≥ 0.7 V –15% 0.94 15% SLEW_RATEx[2:0] = 111, VVOUT_Bx ≥ 0.7 V –15% 0.47 15% IPFM-PWM PFM-to-PWM switch - current threshold(5) 600 mA IPWM-PFM PWM-to-PFM switch - current threshold(5) 240 mA Output pulldown resistance Regulator disabled 80 115 150 Ω

ADVANCE□INFORMATION LP87702-Q1 SNVSAL1 – DECEMBER 2017 www.ti.com Product Folder Links: LP87702-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVOUT_Bx, VVOUT_BST, and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.3 V, VOUT_BST = 5 V and VOUT_Bx = 1 V, unless otherwise noted(1) (2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (6) Minimum boost-power input voltage is 3 V for P87702D. (7) Maximum output current is 0.25 A for P87702D. BOOST REGULATOR VIN_BST Input voltage range for boost power inputs 2.8(6) 3.3 4 V VOUT_BST Output voltage BOOST_VSET = 00 4.9 V BOOST_VSET = 01 5 BOOST_VSET = 10 5.1 BOOST_VSET = 11 5.2 IOUT_BST Output current 0.6(7) A ILIM_BST Output current limit BOOST_ILIM = 00, VIN_BST < 3.6 V 0.8 1 1.2 A BOOST_ILIM = 01, VIN_BST < 3.6 V 1.1 1.4 1.7 BOOST_ILIM = 10, VIN_BST < 3.6 V 1.5 1.9 2.3 BOOST_ILIM = 11, VIN_BST < 3.6 V 2.2 2.8 3.4 VOUT_BST_DC DC output voltage accuracy, includes voltage reference, DC load and line regulations, process and temperature Default output voltage –3% 3% Ripple voltage, forced PWM mode 22 µF effective output capacitance 20 mVp-p Ripple voltage, PFM mode 22 µF effective output capacitance 150 mVp-p DCLDR DC load regulation IOUT = 1 mA to IOUT(max) 0.3% TLDSR Transient load step response IOUT = 1 mA to 250 mA, TR = TF = 1 µs, 22 µF effective output capacitance, VIN_BST > 3 V –220 220 mV ISHORT Short-circuit current limitation During start-up. Applies until VOUT_BST = VIN_BST 625 mA RDS(ON) BST HS FET On-resistance, high-side FET Pin-to-pin, between SW_BST and VOUT_BST pins (I = 250 mA) 145 220 mΩ RDS(ON) BST LS FET On-resistance, low-side FET Pin-to-pin, between SW_BST and PGND_BST pins (I = 250 mA) 90 175 mΩ fSW Switching frequency 2-MHz setting 1.8 2 2.2 MHz 4-MHz setting 3.6 4 4.4 MHz Start-up time From enable to boost VOUT valid; COUT_BST = 22 µF 230 µs Output pulldown resistance Regulator disabled 135 Ω

ADVANCE□INFORMATION LP87702-Q1 SNVSAL1 – DECEMBER 2017 www.ti.com Product Folder Links: LP87702-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVOUT_Bx, VVOUT_BST, and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.3 V, VOUT_BST = 5 V and VOUT_Bx = 1 V, unless otherwise noted(1) (2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PROTECTION FUNCTIONS Thermal warning Temperature rising, TDIE_WARN_LEVEL = 0 115 125 135 °CTemperature rising, TDIE_WARN_LEVEL = 1 130 140 150 Hysteresis 20 Thermal shutdown Temperature rising 140 150 160 Hysteresis 20 VANAOVP VANA overvoltage Voltage rising 5.6 5.8 6.1 V Voltage falling 5.45 5.73 5.96 Hysteresis 40 200 mV VANAUVLO VANA undervoltage lockout Voltage rising 2.51 2.63 2.75 V Voltage falling 2.5 2.6 2.7 BUCKx short-circuit detection Threshold 0.35 V BOOST short-circuit detection Threshold 2.5 V LOAD CURRENT MEASUREMENT FOR BUCK REGULATORS Current measurement range Maximum code 10.22 A Resolution LSB 20 mA Measurement accuracy IOUT > 1 A <10% Measurement time Auto mode (automatically changing to PWM mode for the measurement) 50 µs PWM mode 4 CURRENT CONSUMPTION Shutdown current consumption NRST = 0 1 µA Standby current consumption, regulators disabled NRST = 1 9 µA Active current consumption, one buck regulator enabled in auto mode, internal RC oscillator IOUT_Bx = 0 mA, not switching 60 µA Active current consumption, two buck regulators enabled in auto mode, internal RC oscillator IOUT_Bx = 0 mA, not switching 90 µA Active current consumption during PWM operation, one buck regulator enabled IOUT_Bx = 0 mA 15 mA Active current consumption during PWM operation, two buck regulators enabled IOUT_Bx = 0 mA 30 mA Active current consumption, boost regulator in PFM operation IOUT_BST = 0 mA 200 µA Active current consumption, boost regulator in PWM operation IOUT_BST = 0 mA, fSW = 4 MHz 18 mA PLL and clock detector current consumption Additional current consumption when enabled, 2-MHz external clock 2 mA

0.4 VVANA

Supply voltage for external pullup resistor, configured to open-drain VVANA RPU External pullup resistor, configured to open-drain 10 kΩ ALL DIGITAL INPUTS ILEAK Input current All logic inputs except NRST, over pin voltage range, when PD not enabled −1 1 µA NRST, over pin voltage range. Other logic inputs when PD enabled –1 20 µA (1) Cb refers to the capacitance of one bus line. Cb is expressed in pF units.

6.6 I2C Serial Bus Timing Parameters

See (1). MIN MAX UNIT fSCL Serial clock frequency Standard mode 100 kHz Fast mode 400 Fast mode + 1 MHzHigh-speed mode, Cb = 100 pF 3.4 High-speed mode, Cb = 400 pF 1.7 tLOW SCL low time Standard mode 4.7 µsFast mode 1.3 Fast mode + 0.5 High-speed mode, Cb = 100 pF 160 ns High-speed mode, Cb = 400 pF 320 tHIGH SCL high time Standard mode 4 µsFast mode 0.6 Fast mode + 0.26 High-speed mode, Cb = 100 pF 60 ns High-speed mode, Cb = 400 pF 120

ADVANCE□INFORMATION LP87702-Q1 SNVSAL1 – DECEMBER 2017 www.ti.com Product Folder Links: LP87702-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated I2C Serial Bus Timing Parameters (continued) See (1). MIN MAX UNIT tSU;DAT Data setup time Standard mode 250 ns Fast mode 100 Fast mode + 50 High-speed mode 10 tHD;DAT Data hold time Standard mode 0.01 3.45 µsFast mode 0.01 0.9 Fast mode + 0.01 High-speed mode, Cb = 100 pF 10 70 ns High-speed mode, Cb = 400 pF 10 150 tSU;STA Setup time for a start or a repeated start condition Standard mode 4.7 µsFast mode 0.6 Fast mode + 0.26 High-speed mode 160 ns tHD;STA Hold time for a start or a repeated start condition Standard mode 4 µsFast mode 0.6 Fast mode + 0.26 High-speed mode 160 ns tBUF Bus free time between a stop and start condition Standard Mode 4.7 µsFast Mode 1.3 Fast mode + 0.5 tSU;STO Setup time for a stop condition Standard Mode 4 µsFast Mode 0.6 Fast mode + 0.26 High-speed mode 160 ns trDA Rise time of SDA signal Standard mode 1000 ns Fast mode 20+0.1 Cb 300 Fast mode + 120 High-speed mode, Cb = 100 pF 10 80 High-speed mode, Cb = 400 pF 20 160 tfDA Fall time of SDA signal Standard mode 250 ns Fast mode 20+0.1 Cb 250 Fast mode + 20+0.1 Cb 120 High-speed mode, Cb = 100 pF 10 80 High-speed mode, Cb = 400 pF 20 160 trCL Rise time of SCL signal Standard mode 1000 ns Fast mode 20+0.1 Cb 300 Fast mode + 120 High-speed mode, Cb = 100 pF 10 40 High-speed mode, Cb = 400 pF 20 80 trCL1 Rise time of SCL signal after a repeated start condition and after an acknowledge bit Standard mode 1000 ns Fast mode 20+0.1 Cb 300 Fast mode + 120 High-speed mode, Cb = 100 pF 10 80 High-speed mode, Cb = 400 pF 20 160

Figure 1. I2C Timing

7 Detailed Description

7.1 Overview

Table 1. Supply Specification general-purpose output (GPO2). Alternatively, optional spread spectrum mode can be enabled to reduce EMI.

Soft start
Input undervoltage lockout
Programmable undervoltage or over- and undervoltage monitoring for the input (from VANA pin)
Programmable undervoltage or over- and undervoltage monitoring for the buck and boost regulator outputs
Two inputs (VMONx) with programmable undervoltage or over- and undervoltage thresholds, for monitoring external rails in the system
One dedicated power-good output (PG0) to which selected monitoring signals can be combined
Second programmable power-good output, multiplexed with general purpose output (GPO1)
Power good flag with maskable interrupt
Programmable window watchdog
Buck and boost regulator overload detection
Thermal warning with two selectable levels
Thermal shutdown LP87702-Q1 control interface :
Dedicated EN1, EN2 and E3 inputs with programmable power-up/power-down sequence control
Optional I2C (multiplexed with E2 and EN3 inputs)
Interrupt signal (nINT) to host
Reset input (NRST)
One dedicated general purpose output (GPO0)

ADVANCE□INFORMATION Diagnostics UVLO SW Reset Digital Logic Registers I2C Enable/ Disable, Delay Control Slew-Rate Control InterruptsnINT SDA / EN3 SCL / EN2 EN1 VANA OTP EPROM Thermal Monitor Oscillator Buck0 ILIM Det Pwrgood Det Overload and SC Det Buck1 Boost ILIM Det Pwrgood DetOverload and SC Det ILIM Det Pwrgood Det Overload and SC Det Ref & Bias Iload ADC Iload ADC CLKIN / GPO2 GPO0 Ref & Bias PG0 PG1/ GPO1 VMON1 VMON2 Window Watchdog WD_RESET WDI NRST Copyright © 2017, Texas Instruments Incorporated LP87702-Q1 www.ti.com SNVSAL1 – DECEMBER 2017 Product Folder Links: LP87702-Q1 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

7.2 Functional Block Diagram

7.3 Feature Descriptions

7.3.1 Step-Down DC-DC Converters

7.3.1.1 Overview

The LP87702-Q1 includes two high-efficiency step-down DC-DC converter cores. The buck regulators deliver flexibility; most of the functions are programmable, thus giving a possibility to optimize the regulator operation for each application :

DVS support with programmable slew rate
Automatic mode control based on the loading (PWM or PFM mode)
Forced PWM mode option
Optional external clock input to minimize crosstalk
Optional spread spectrum technique to reduce EMI
Synchronous rectification
Current mode loop with PI compensator
Soft start
Programmable output voltage monitoring with maskable interrupt and selectable connection PG0 and/or PG1
Average output current sensing (for PFM entry and load current measurement) Some of the key parameters that can be programmed via registers (the default values are set by OTP bits):
Output voltage

Forced PWM operation
Switch current limit
Output voltage slew rate
Enable and disable delays with ENx pin control There are two modes of operation for the buck converter, depending on the output current required: pulse width modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load currents of approximately 600 mA or higher. Lighter output current loads will cause the converter to automatically switch into PFM mode for reduced current consumption when forced PWM mode is disabled. The forced PWM mode can be selected to maintain fixed switching frequency at all load currents. When buck is disabled, buck output is isolated from the input voltage rail. Output has an optional pulldown resistor. A block diagram of a single core is shown in Figure 2.

Figure 2. Detailed Block Diagram Showing One Core

7.3.1.2 Transition between PWM and PFM Modes

achieved over a wide output-load current range.

7.3.1.3 Buck Converter Load Current Measurement

7.3.2 Boost Converter

Automatic mode control based on the loading (PFM or PWM mode). PFM mode is not supported in P87702D
Forced PWM option

Optional external clock input to minimize crosstalk
Optional spread spectrum technique to reduce EMI
Synchronous rectification
Current mode loop with PI compensator
Soft start
Programmable output voltage monitoring with maskable interrupt and selectable connection to PG0 and/or PG1 Following parameters can be programmed via registers, the default values are set by OTP bits unless otherwise noted:
Output voltage (BOOST_VSET)
Forced PWM operation (BOOST_FPWM)
Switch current limit (BOOST_ILIM)
Enable and disable delays with ENx pin control (BOOST_DELAY register)
Output discharge resistor enable/disable when boost is disabled (BOOST_RDIS_EN bit, discharge is enabled by default)
Output voltage monitoring enable/disable and monitoring window thresholds There are two modes of operation for the boost converter, depending on the output current required: PWM and PFM. In AUTO mode the boost converter operates in PWM mode at high load currents. Lighter output current loads cause the converter to automatically switch into PFM mode for reduced current consumption when forced PWM mode is disabled. Exact threshold between PWM and PFM depends on conversion ratio. The forced PWM mode can be selected to maintain fixed switching frequency at all load currents. When boost is disabled, boost output is isolated from the input voltage rail. Output has an optional pulldown resistor. Boost block has an alternate operating mode as a bypass/load switch. Input voltage range in this mode is from 4.5 V to 5.5 V. Operating mode is selected in OTP and is fixed, changing the mode on-the-fly is not supported. Bypass mode is not supported in P87702D.

7.3.3 Spread-Spectrum Mode

Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add EMI-filters and shields to the boards. The LP87702-Q1's register selectable spread-spectrum mode minimizes the need for output filters, ferrite beads, or chokes. In spread spectrum mode, the switching frequency varies between 0.85 × fSW and fSW, where fSW is switching frequency selected in the OTP. This reduces the EMI emissions radiated by the converter and associated passive components and PCB traces (see Figure 3). This feature is available only when internal RC oscillator is used (EN_PLL is 0 in PLL_CTRL register) and it is enabled with the EN_SPREAD_SPEC bit in CONFIG register, and it affects both buck cores and the boost regulator.

spectrum architecture of the LP87702-Q1 spreads that energy over a large bandwidth. Figure 3. Spread Spectrum Modulation

7.3.4 Sync Clock Functionality

(–30%/+10%) for valid clock detection. boost regulator is enabled (standby-to-active transition) when EN_PLL = 1. Figure 4. Clock and PLL Module Table 2. PLL Operation

Table 2. PLL Operation (continued)

7.3.5 Power-Up

VANA (and VIN_Bx) reach minimum recommended levels (VVANA > VANAUVLO).
NRST signal is set high. This initiates OTP reading and enables the system I/O interface. The I2C host allows at least 1.2 ms before writing or reading data to the LP87702-Q1.
Device enters STANDBY mode. Watchdog operation starts.
The host can change the default register setting by I2C if needed.
The regulators can be enabled/disabled and the GPO signals can be controlled by EN pin and by I2C interface.

7.3.6 Regulator Control

7.3.6.1 Enabling and Disabling Regulators

Using BUCKx_EN bit in BUCKx_CTRL_1 register (BUCKx_EN_PIN_CTRL bit is 00 in BUCKx_CTRL_1 register)
Using ENx control pin (BUCKx_EN bit is 1 in BUCKx_CTRL_1 register AND BUCKx_EN_PIN_CTRL bit is not 00 in BUCKx_CTRL_1 register) Similarly there are two ways to enable and disable the boost regulator:
Using BOOST_EN bit in BOOST_CTRL register (BOOST_EN_PIN_CTRL bit is 0 in BOOST_CTRL register)
Using ENx control pin (BOOST_EN bit is 1 in BOOST_CTRL register AND BOOST_EN_PIN_CTRL bit is not 00 in BOOST_CTRL register) If the ENx control pin is used for enable and disable then the delay from the control signal rising edge to startup is set by BUCKx_STARTUP_DELAY[3:0] bits in BUCKx_DELAY register and BOOST_STARTUP_DELAY[3:0] bits in BOOST_DELAY register and the delay from falling edge of control signal to shutdown is set by BUCKx_SHUTDOWN_DELAY[3:0] bits in BUCKx_DELAY register and BOOST_SHUTDOWN_DELAY[3:0] bits in BOOST_DELAY register. The delays are valid only for ENx signal transitions and not for control with I2C writings to BUCKx_EN and BOOST_EN bits. The control of the regulators (with 0-ms delays) is shown in Table 3.

Table 3. Regulator Control

0 Don't Care Don't Care Don't Care Don't Care Disabled

Table 3. Regulator Control (continued) BUCKx_PG_INT interrupt flag in INT_BUCK register is set. Figure 5. Buck Regulator Enable and Disable

BOOST_PG_INT interrupt flag in INT_BOOST register is set. always the validity of the output voltage; '1' means valid and '0' means invalid output voltage. can disable those with ENx_PD bits in CONFIG register. Figure 6. Boost Regulator Enable and Disable

7.3.6.2 Changing Buck Output Voltage

current, and the BUCKx_FPWM bit. The voltage change and powergood interrupts are shown in Figure 7.

Figure 7. Regulator Output Voltage Change

7.3.7 Enable and Disable Sequences

BUCKx_CTRL_1(BUCKx_EN) = 1
BUCKx_CTRL_1(BUCKx_EN_PIN_CTRL) = 0x1 or 0x2 or 0x3, for EN1 or EN2 or EN3 control, respectively
BUCKx_VOUT.(BUCKx_VSET[7:0]) = Required voltage when EN pin is high
The delay from rising edge of EN pin to the regulator enable is set by BUCKx_DELAY(BUCKx_STARTUP_DELAY[3:0]) bits and
The delay from falling edge of EN pin to the regulator disable is set by BUCKx_DELAY(BUCKx_SHUTDOWN_DELAY[3:0]) In the same way the boost regulator is selected for delayed control with:
BOOST_CTRL(BOOST_EN) = 1
BOOST_CTRL(BOOST_EN_PIN_CTRL) = 0x1 or 0x2 or 0x3, for EN1 or EN2 or EN3 control, respectively
BOOST_CTRL(BOOST_VSET[2:0]) = Required voltage when EN pin is high
The delay from rising edge of EN pin to the regulator enable is set by BOOST_DELAY(BOOST_STARTUP_DELAY[3:0]) bits and
The delay from falling edge of EN pin to the regulator disable is set by BOOST_DELAY(BOOST_SHUTDOWN_DELAY[3:0]) An example of start-up and shutdown sequences for buck regulators are shown in Figure 8. The start-up and shutdown delays for Buck0 regulator are 1 ms and 4 ms and for Buck1 regulator 3 ms and 1 ms. The delay settings are used only for enable/disable control with EN signal.

Figure 8. Startup and Shutdown Sequencing

7.3.8 Window Watchdog

used for controlling power sequence and ENx pin is active. of these registers initializes the Long Open counter and the Long Open period restarts (except in Stop mode). received during Close window, watchdog enters WD Reset.

When WD_RESET_CNTR_SEL = 00, system restart is disabled and regulators are maintained ON. WD_RESET pin is active for 10 ms. Watchdog returns to Long Open mode.
When WD_RESET_CNTR_SEL = 01 (restart after first reset pulse), LP87702-Q1 performs shutdown sequence followed by startup sequence so the regulators are disabled and re-enabled according to the OTP programmed sequences. During startup, device reloads OTP defaults when WD_EN_OTP_READ = 1. Settings valid before shutdown are maintained when WD_EN_OTP_READ = 0. WD_RESET output pin is active for a period of (10 ms + maximum shutdown delay). Maximum shutdown delay can be selected as 7.5 ms (SHUTDOWN_DELAY_SEL = 0) or 15 ms (SHUTDOWN_DELAY_SEL = 1). After the restart watchdog returns to Long Open mode.

Status bit WD_SYSTEM_RESTART_FLAG is set to indicate that system restart has happened. Status can be cleared by writing "1" to WD_CLR_SYSTEM_RESTART_FLAG. WD_RESET_CNTR_SEL can be set to 10 or 11 to select restart after 2 or 4 WD expirations, respectively. Current status of reset counter is available in WD_RESET_CNTR_STATUS. Reset counter can be cleared by writing WD_CLR_RESET_CNTR to 1.
Watchdog can also be programmed to perform shutdown sequence and enter STOP mode after the second WD expiration. In STOP mode regulators are OFF. WD_RESET output pin is activated for a period of (10 ms + maximum shutdown delay), in STOP mode WD_RESET is inactive. NRST, power cycle, register reset SW_RESET, writing WD_CLR_SYSTEM_RESTART_FLAG = 1 or writing WD_SYSTEM_RESTART_FLAG_MODE = 0 is required to recover. This WD operating mode is selected by setting OTP bit WD_SYS_RESTART_FLAG_MODE = 1. Watchdog settings in WD_CTRL_1 and WD_CTRL_2 registers are locked by setting WD_LOCK bit. WD_SYSTEM_RESTART_FLAG and WD_RESET_CNTR_STATUS can be cleared even if WD_LOCK = 1. Description above is for a case where ENx pin is used for controlling power sequence and ENx pin is active. Depending on OTP settings and ENx pin state watchdog behavior can be slightly different:
When ENx pin is used for controlling power sequence and ENx pin is not active, shutdown sequence can not be performed. WD_RESET pulse length is fixed 31 ms.
When ENx pins are not used for power sequence control and all regulators and GPOs enabled via I2C, there is no OTP defined power sequence. WD expiration does not cause regulator disable/enable sequence even when OTP settings for watchdog are such that restart is enabled. In this case WD_RESET pulse is 11 ms.

Figure 9. Watchdog Operation Table 4. Watchdog Window Periods

Table 4. Watchdog Window Periods (continued) functions. Watchdog disable is not supported by P87702D.

7.3.9 Device Reset Scenarios

Software reset with SW_RESET bit in RESET register
NRST input signal low
Undervoltage lockout (UVLO) reset from VANA supply
Watchdog expiration (depending on watchdog settings) A SW reset occurs when SW_RESET bit is written 1. The bit is automatically cleared after writing. This event disables all the regulators immediately, drives GPO signals low, resets all the register bits to the default values and OTP bits are loaded (see Figure 15). I2C interface is not reset during software reset. The host must wait at least 1.2 ms after writing SW reset until making a new I2C read or write to the device. If VANA supply voltage falls below UVLO threshold level or NRST signal is set low then all the regulators are disabled immediately, GPO signals are driven low and all the register bits are reset to the default values. When the VANA supply voltage rises above UVLO threshold level AND NRST signal rises above threshold level, OTP bits are loaded to the registers and a start-up is initiated according to the register settings. The host must wait at least 1.2 ms before reading or writing to I2C interface. Depending on watchdog settings, watchdog expiration can reset the device to OTP default values.

7.3.10 Diagnostics and Protection Features

Information of input and output voltage which sets interrupt or PGx signal; – Validity of the output voltage of BUCK or BOOST regulators – Validity of VANA, VMON1 and VMON2 input voltages
Warnings for diagnosis which sets interrupt – Peak current limit detection in BUCK or BOOST regulators – Thermal warning
Protection events which are disabling the regulators – Short-circuit and overload protection for BUCK and BOOST regulators – Input overvoltage protection (VANAOVP) – Watchdog expiration – Thermal shutdown
Faults which are causing the device to shutdown – Undervoltage lockout (VANAUVLO)

7.3.10.1 Voltage Monitorings

dedicated reference and bias block, which is independent of the main reference and bias block. level, are selected with BOOST_WINDOW as 2%, ± 4%, ± 6% or ± 8%. For more details on the accuracy of the monitoring windows and deglitch filtering see Specifications.

7.3.10.2 Interrupts

pending interrupts are cleared. Table 5. Summary of Interrupt Signals

Table 5. Summary of Interrupt Signals (continued) (1) PGx_POL bit in PGOOD_CTRL_1 register affects only PGx pin polarity, not PGx interrupt polarity. (2) Interrupt generated during Clock Detector operation and in case Clock is not available when Clock Detector is enabled.

7.3.10.3 Power-Good Information to Interrupt and PG0 and PG1 pins

The output voltage of one or both BUCKx regulators
The output voltage of the BOOST regulator
Input voltage of VANA
Input voltage of VMON1 and/or VMON2
Thermal warning
Thermal shutdown The block diagram for powergood connections to PG0 and PG1 pins and interrupt is shown in Figure 10. Monitored signals are enabled in PGOOD_CTRL register. Regulator output voltage monitoring (not current limit monitoring) can be selected for the indication. Monitoring is enabled by PGOOD_CTRL(EN_PGOOD_BUCKx) and PGOOD_CTRL(EN_PGOOD_BOOST) bits. When a regulator is disabled, the monitoring is automatically masked to prevent it forcing PGx inactive or causing an interrupt. Also monitoring of VANA, VMON1 and VMON2 inputs can be independently enabled via PGOOD_CTRL register. The type of voltage monitoring for PGx signals and nINT is selected by PGOOD_CTRL_1(PGOOD_WINDOW_x) bit. If the bit is 0, only undervoltage is monitored and if the bit is 1 both undervoltage and overvoltage are monitored. For voltage monitoring thresholds see Voltage Monitorings. Monitoring of thermal warning and thermal shutdown monitoring is always enabled.

summary of powergood interrups, mask bits and interrupt clearing. or open-drain) of PG0 and PG1 are selected by PG_CTRL(PGx_POL) and PG_CTRL(PGx_OD) bits. each requested/programmed output voltage. each requested/programmed output voltage. Figure 10. Block Diagram of Power-Good Connections and in PGx pin Operation in Continuous Mode.

7.3.10.3.1 PGx Pin Gated (Unusual) Mode

bit to 0 in PG_CTRL register.

PGx is set to active or asserted state upon exiting OTP configuration as an initial default state.
For each enabled rail PGx status is suspended or unchanged during an 800-μs gated time period from the enable activation, thereby gating-off the status indication.
During normal power-up sequencing and requested voltage changes, PGx state typically remains active or asserted for normal conditions.
During an abnormal power-up sequencing and requested voltage changes, PGx status could change to inactive or de-asserted after an 800-μs gated time period if any output voltage is outside of regulation range.
Using the gated mode of operation could allow the PGx signal to initiate an immediate power shutdown sequence if the PGx signal is wired-OR with signal connected to EN input. This type of circuit configuration provides a smart PORz function for processor that eliminates the need for additional components to generate PORz upon start-up and to monitor voltage levels of key voltage domains. PGx signal is set inactive if the output voltage of a monitored Buck or Boost regulator is invalid or the output voltage is not valid at 800 µs from the enable of the regulator. This should be considered when selecting the BUCKx_SLEW_RATE setting. To avoid PGx triggering at start-up keep the sum of soft start time and slew rate controlled part of voltage ramp below 800 µs. In addition when invalid input voltage at VANA, VMON1 or VMON2 pin is detected PGx is inactive. Mode 0 is selected by setting PG_CTRL(PGx_MODE) bit to 0. Detected fault sets the corresponding fault bit in PG0_FAULT or in PG0_FAULT register. The detected fault must be cleared to continue the PGx monitoring. The over-voltage and thermal shutdown are cleared by writing 1 to the OVP_INT and TDIE_SD_INT interrupt bits in INT_TOP_1 register. The regulator fault is cleared by writing 1 to the corresponding register bit in PGx_FAULT register. An example of PGx pin operation in Mode 0 is shown in and the different use cases for PGx signal operation are summarized in Table 6.

Figure 11. PGx Pin Operation in Gated Mode.

7.3.10.3.2 PGx pin Operation in Continuous Mode

setting PGx_MODE bit to 1 in PG_CTRL register.

PGx is set to active or asserted state upon exiting OTP configuration as an initial default state.
PGx is set to inactive or de-asserted as soon as regulator is enabled.
PGx status begins indicating output voltage regulation status immediately and continuously.
During power-up sequencing and requested voltage changes, PGx will toggle between inactive or deasserted while output voltages are outside of regulation ranges and active or asserted when inside of regulation ranges. When invalid output voltage of monitored regulator is detected, corresponding PG0_FAULT_x or PG1_FAULT_x bit is set to 1 and PGx signal becomes inactive. The PG0_FAULT and PG1_FAULT register bits are latched and maintain the fault information until host clears the fault bit by writing 1 to the bit. The PGx signal indicates also interrupts from VANA, VMON1 and VMON2 inputs and thermal warning and shutdown. All are cleared by clearing the interrupt bits. When regulator voltage is transitioning from one target voltage to another, the PGx signal is set inactive. When PGx signal becomes inactive, the source for the fault can be read from PG_FAULT register. If the invalid output voltage becomes valid again the PGx signal becomes active. Thus the PGx signal shows all the time if the monitored output voltages are valid. The block diagram for this operation is shown in Figure 12. The PGx signal can be also configured so that it maintains inactive state even when the monitored outputs are valid but there are PG_FAULT_x bits pending clearance. This type of operation is selected by setting PGFAULT_GATES_PGOOD bit to 1.

Figure 12. PGx Pin Operation in Continuous Mode

7.3.10.3.3 Summary of PG0, PG1 Gated and Continuous Operating Modes

(1) NOK (Not OK) means faulty situation. PGx pin is inactive if at least one NOK situation is detected. INT_TOP_2(RESET_REG_INT) bit. Table 6. PGx Operation

7.3.10.4 Warnings for Diagnosis (Interrupt)

7.3.10.4.1 Output Power Limit

to see if the regulator is still in peak current regulation mode.

Figure 14. Boost Regulator Overload Situation

7.3.10.4.2 Thermal Warning

processor. The threshold level of the thermal warning is selected with TDIE_WARN_LEVEL bit.

7.3.10.5 Protection (Regulator Disable)

pulldown resistor. The pulldown resistors are active as long as VANA voltage is above approximately 1.2-V level.

7.3.10.5.1 Short-Circuit and Overload Protection

voltage is below the threshold level 1 ms after the boost regulator is enabled.

ADVANCE□INFORMATION LP87702-Q1 www.ti.com SNVSAL1 – DECEMBER 2017 Product Folder Links: LP87702-Q1 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated In a similar way the overload situation is protected during normal operation. If the feedback-pin voltage of the buck regulator falls below 0.35 V and remains below the threshold level for 1 ms the buck regulator is disabled. If the output voltage of the boost regulator falls below 2.5 V and remains below the threshold level for 1 ms the boost regulator is disabled. In the Buck regulator short-circuit and overload situations the BUCKx_SC_INT and the INT_BUCKx bits are set to 1, the BUCKx_STAT bit is set to 0 and the nINT signal is pulled low. In the boost regulator short-circuit and overload situations the BOOST_SC_INT and the BOOST_INT bits are set to 1, the BOOST_STAT bit is set to 0 and the nINT signal is pulled low. The host processor clears the interrupt by writing 1 to the BUCKx_SC_INT or BOOST_SC_INT bit. Upon clearing the interrupt the regulator makes a new start-up attempt if the regulator is in enabled state.

7.3.10.5.2 Overvoltage Protection

The LP87702-Q1 device monitors the input voltage from VANA pin in standby and active operation modes. If the input voltage rises above VANAOVP voltage level, all the regulators are disabled immediately (without switching ramp, no shutdown delays) pulldown resistors discharge the output voltages (BUCKx_RDIS_EN = 1 and BOOST_RDIS_EN = 1), GPOs are set to logic low level, nINT signal is pulled low, OVP_INT bit is set to 1 and BUCKx_STAT and BOOST_STAT bits are set to 0. The host processor clears the interrupt by writing 1 to the OVP_INT bit. If the input voltage is above over-voltage detection level the interrupt is not cleared. The host can read the status of the overvoltage from the OVP_STAT bit. Regulators cannot be enabled as long as the input voltage is above over-voltage detection level or the overvoltage interrupt is pending.

7.3.10.5.3 Thermal Shutdown

The LP87702-Q1 has an overtemperature protection function that operates to protect itself from short-term misuse and overload conditions. When the junction temperature exceeds around 150°C, the regulators are disabled immediately (without switching ramp, no shutdown delays), the TDIE_SD_INT bit is set to 1, the nINT signal is pulled low, and the device enters STANDBY. nINT is cleared by writing 1 to the TDIE_SD_INT bit. If the temperature is above thermal shutdown level the interrupt is not cleared. The host can read the status of the thermal shutdown from the TDIE_SD_STAT bit. Regulators cannot be enabled as long as the junction temperature is above thermal shutdown level or the thermal shutdown interrupt is pending.

7.3.10.6 Fault (Power Down)

7.3.10.6.1 Undervoltage Lockout

When the input voltage falls below VANAUVLO at the VANA pin, the buck and boost regulators are disabled immediately (without switching ramp, no shutdown delays), and the output capacitor is discharged using the pulldown resistor, and the LP87702-Q1 device enters SHUTDOWN. When V(VANA) voltage is above VANAUVLO threshold level, the device powers up to STANDBY state. If the reset interrupt is unmasked by default (TOP_MASK_2(RESET_REG_MASK) = 0) the INT_TOP_2(RESET_REG_INT) interrupt indicates that the device has been in SHUTDOWN. The host processor must clear the interrupt by writing 1 to the INT_TOP_2(RESET_REG_INT) bit. If the host processor reads the INT_TOP_2(RESET_REG_INT) flag after detecting an nINT low signal, it knows that the input supply voltage has been below VANAUVLO level (or the host has requested reset with RESET(SW_RESET) bit), and the registers are reset to default values.

7.3.11 OTP Error Correction

LP87702-Q1 supports OTP bit error detection and 1-bit error correction per five registers. ECC_STATUS register bit SED is set if a single bit error was detected and corrected. In case two bit errors have been detected in any bank of five registers, DED bit is set.

7.3.12 GPO Signals' Operation

The LP87702-Q1 device supports up to 3 General Purpose Output (GPO) signals. The GPO1 signal is multiplexed with PG1 signal and the GPO2 signal is multiplexed with CLKIN signal. The selection between signal use are set with GPO1_SEL and GPO2_SEL bits in GPO_CONTROL_2 register. The type of the output, either push-pull with V(VANA) level or open drain, are set with GPO0_OD and GPO1_PG1_OD bits in GPO_CONTROL_1 register and GPO2_OD bit in GPO_CONTROL_2 register

(1) No glitch filtering, only synchronization. and GPO2_OUT bit in GPO_CONTROL_2 register.

7.3.13 Digital Signal Filtering

The digital signals have a debounce filtering. The signal/supply is sampled with a clock signal and a counter. This results as an accuracy of one clock period for the debounce window. Table 7. Digital Signal Filtering

7.4 Device Functional Modes

7.4.1 Modes of Operation

reference, control and bias circuitry of the LP87702-Q1 device are turned off. interface. Watchdog is active and WDI input is expected to toggle to avoid watchdog expiration. detailed operation see Window Watchdog.

Figure 15. Device Operation Modes.

7.5 Programming

7.5.1 I2C-Compatible Interface

(100 kHz), fast mode (400 kHz), fast mode plus (1 MHz), and high-speed mode (3.4 MHz).

7.5.1.1 Data Validity

state of the data line can only be changed when clock signal is LOW.

Figure 16. Data Validity Diagram

7.5.1.2 Start and Stop Conditions

master always generates the START and STOP conditions. Figure 17. Start and Stop Sequences SDA and SCL signal timing for the I2C-Compatible Bus. See the Figure 1 for timing values. Figure 18. I2C-Compatible Timing

7.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. acknowledge after each byte has been received.

but the SDA line is not pulled down. master is disabled at that time. data to write to the selected register. Figure 19. Write Cycle (w = write; SDA = 0), id = Device Address = 60Hex for LP87702-Q1 When READ function is to be accomplished, a WRITE function must precede the READ function as shown above. Figure 20. Read Cycle ( r = read; SDA = 1), id = Device Address = 60Hex for LP87702-Q1

7.5.1.4 I2C-Compatible Chip Address

written. The third byte contains the data for the selected register.

A. Here device address is 1100000Bin = 60Hex. Figure 21. Device Address

7.5.1.5 Auto Increment Feature

increment feature does not work for read. Table 8. Auto-Increment Example

7.6 Register Maps

7.6.1 Register Descriptions

number are described in a separate Technical Reference Manual.

7.6.1.1 LP8770_MAP Registers

Table 9 should be considered as reserved locations and the register contents should not be modified. Table 9. LP8770_MAP Registers

Table 9. LP8770_MAP Registers (continued)

access types in this section. Table 10. LP8770_MAP Access Type Codes

Table 10. LP8770_MAP Access Type

7.6.1.1.1 DEV_REV Register (Offset = 0h)

DEV_REV is shown in Figure 22 and described in Table 11. Figure 22. DEV_REV Register Table 11. DEV_REV Register Field Descriptions 5-3 DEVICE_ID R/W * Device specific ID code.

7.6.1.1.2 OTP_CODE Register (Offset = 1h)

OTP_CODE is shown in Figure 23 and described in Table 12. Figure 23. OTP_CODE Register Table 12. OTP_CODE Register Field Descriptions 7-2 OTP_ID R/W * Identification Code of the OTP EPROM. 1-0 OTP_REV R/W * Version number of the OTP ID.

7.6.1.1.3 BUCK0_CTRL_1 Register (Offset = 2h)

BUCK0_CTRL_1 is shown in Figure 24 and described in Table 13. Figure 24. BUCK0_CTRL_1 Register

Table 13. BUCK0_CTRL_1 Register Field Descriptions

5 BUCK0_FPWM_MP R/W * Forces the BUCK0 regulator to operate always in multi-phase and

0 - Automatic phase adding and shedding.

4 BUCK0_FPWM R/W * Forces the BUCK0 regulator to operate in PWM mode:

1 - Forced to PWM operation.

3 BUCK0_RDIS_EN R/W 1h Enable output discharge resistor when BUCK0 is disabled:

1 - Discharge resistor enabled.

0 BUCK0_EN R/W * Enable BUCK0 regulator:

1 - BUCK0 regulator is enabled.

7.6.1.1.4 BUCK0_CTRL_2 Register (Offset = 3h)

BUCK0_CTRL_2 is shown in Figure 25 and described in Table 14. Figure 25. BUCK0_CTRL_2 Register Table 14. BUCK0_CTRL_2 Register Field Descriptions

Table 14. BUCK0_CTRL_2 Register Field Descriptions (continued)

7.6.1.1.5 BUCK1_CTRL_1 Register (Offset = 4h)

BUCK1_CTRL_1 is shown in Figure 26 and described in Table 15. Figure 26. BUCK1_CTRL_1 Register Table 15. BUCK1_CTRL_1 Register Field Descriptions

4 BUCK1_FPWM R/W * Forces the BUCK1 regulator to operate in PWM mode:

1 - Forced to PWM operation.

3 BUCK1_RDIS_EN R/W 1h Enable output discharge resistor when BUCK1 is disabled:

1 - Discharge resistor enabled.

0 BUCK1_EN R/W * Enable BUCK1 regulator:

1 - BUCK1 regulator is enabled.

7.6.1.1.6 BUCK1_CTRL_2 Register (Offset = 5h)

BUCK1_CTRL_2 is shown in Figure 27 and described in Table 16. Figure 27. BUCK1_CTRL_2 Register

Table 16. BUCK1_CTRL_2 Register Field Descriptions

7.6.1.1.7 BUCK0_VOUT Register (Offset = 6h)

BUCK0_VOUT is shown in Figure 28 and described in Table 17. Figure 28. BUCK0_VOUT Register Table 17. BUCK0_VOUT Register Field Descriptions

7.6.1.1.8 BUCK1_VOUT Register (Offset = 7h)

BUCK1_VOUT is shown in Figure 29 and described in Table 18. Figure 29. BUCK1_VOUT Register Table 18. BUCK1_VOUT Register Field Descriptions

7.6.1.1.9 BOOST_CTRL Register (Offset = 8h)

BOOST_CTRL is shown in Figure 30 and described in Table 19. Figure 30. BOOST_CTRL Register Table 19. BOOST_CTRL Register Field Descriptions

5 RESERVED R/W 0h

4 BOOST_FPWM R/W * Forces the Boost regulator to operate in PWM mode:

1 - Forced to PWM operation.

3 BOOST_RDIS_EN R/W 1h Enable output discharge resistor when BOOST is disabled:

1 - Discharge resistor enabled.

Table 19. BOOST_CTRL Register Field Descriptions (continued)

0 BOOST_EN R/W * Enable Boost regulator:

1 - Boost regulator is enabled.

7.6.1.1.10 BUCK0_DELAY Register (Offset = 9h)

BUCK0_DELAY is shown in Figure 31 and described in Table 20. Figure 31. BUCK0_DELAY Register Table 20. BUCK0_DELAY Register Field Descriptions

7.6.1.1.11 BUCK1_DELAY Register (Offset = Ah)

BUCK1_DELAY is shown in Figure 32 and described in Table 21. Figure 32. BUCK1_DELAY Register

Table 21. BUCK1_DELAY Register Field Descriptions

7.6.1.1.12 BOOST_DELAY Register (Offset = Bh)

BOOST_DELAY is shown in Figure 33 and described in Table 22. Figure 33. BOOST_DELAY Register Table 22. BOOST_DELAY Register Field Descriptions

7.6.1.1.13 GPO0_DELAY Register (Offset = Ch)

GPO0_DELAY is shown in Figure 34 and described in Table 23. Figure 34. GPO0_DELAY Register

Table 23. GPO0_DELAY Register Field Descriptions

7.6.1.1.14 GPO1_DELAY Register (Offset = Dh)

GPO1_DELAY is shown in Figure 35 and described in Table 24. Figure 35. GPO1_DELAY Register Table 24. GPO1_DELAY Register Field Descriptions

7.6.1.1.15 GPO2_DELAY Register (Offset = Eh)

GPO2_DELAY is shown in Figure 36 and described in Table 25. Figure 36. GPO2_DELAY Register

Table 25. GPO2_DELAY Register Field Descriptions

7.6.1.1.16 GPO_CONTROL_1 Register (Offset = Fh)

GPO_CONTROL_1 is shown in Figure 37 and described in Table 26. Figure 37. GPO_CONTROL_1 Register Table 26. GPO_CONTROL_1 Register Field Descriptions

7 GPO1_PG1_OD R/W * GPO1 / PG1 signal type:

4 GPO1_OUT R/W * Control for GPO1 signal (when configured to GPO1):

3 GPO0_OD R/W * GPO0 signal type:

Table 26. GPO_CONTROL_1 Register Field Descriptions (continued)

0 GPO0_OUT R/W * Control for GPO0 signal:

7.6.1.1.17 GPO_CONTROL_2 Register (Offset = 10h)

GPO_CONTROL_2 is shown in Figure 38 and described in Table 27. Figure 38. GPO_CONTROL_2 Register Table 27. GPO_CONTROL_2 Register Field Descriptions

5 GPO2_SEL R/W * CLKIN/GPO2 pin function:

4 GPO1_SEL R/W * PG1/GPO1 pin function:

3 GPO2_OD R/W * GPO2 signal type (when configured to GPO2):

0 GPO2_OUT R/W * Control for GPO2 signal (when configured to GPO2):

7.6.1.1.18 CONFIG Register (Offset = 11h)

CONFIG is shown in Figure 39 and described in Table 28. Figure 39. CONFIG Register

Table 28. CONFIG Register Field Descriptions

7 STARTUP_DELAY_SEL R/W * Startup delays from control signal:

6 SHUTDOWN_DELAY_SE

5 CLKIN_PD R/W * Selects the pull down resistor on the CLKIN input pin. 0 - Pull-down resistor is disabled. 1 - Pull-down resistor is enabled.

4 EN3_PD R/W * Selects the pull down resistor on the EN3 pin:

3 EN2_PD R/W * Selects the pull down resistor on the EN2 pin:

2 EN1_PD R/W * Selects the pull down resistor on the EN1 pin:

1 TDIE_WARN_LEVEL R/W * Thermal warning threshold level. 0 EN_SPREAD_SPEC R/W * Enable spread spectrum feature for Buck and Boost regulators.

7.6.1.1.19 PLL_CTRL Register (Offset = 12h)

PLL_CTRL is shown in Figure 40 and described in Table 29. Figure 40. PLL_CTRL Register Table 29. PLL_CTRL Register Field Descriptions

7 RESERVED R/W 0h

6 EN_PLL R/W * Selection of external clock and PLL operation:

0 - Forced to internal RC oscillator. PLL disabled. clock appears or disappears.

Table 29. PLL_CTRL Register Field Descriptions (continued) 5 RESERVED R/W 0h This bit must be set to '0'. See electrical specification for input clock frequency tolerance.

7.6.1.1.20 PGOOD_CTRL Register (Offset = 13h)

PGOOD_CTRL is shown in Figure 41 and described in Table 30. Figure 41. PGOOD_CTRL Register Table 30. PGOOD_CTRL Register Field Descriptions

6 PGOOD_WINDOW R/W * Voltage monitoring method for PG0 and PG1 signals:

0 - Only undervoltage monitoring. 1 - Overvoltage and undervoltage monitoring.

5 EN_PGOOD_VANA R/W * Enable powergood diagnostics for VANA

4 EN_PGOOD_VMON2 R/W * Enable powergood diagnostics for VMON2

3 EN_PGOOD_VMON1 R/W * Enable powergood diagnostics for VMON1

2 EN_PGOOD_BOOST R/W * Enable powergood diagnostics for Boost

1 EN_PGOOD_BUCK1 R/W * Enable powergood diagnostics for Buck1

Table 30. PGOOD_CTRL Register Field Descriptions (continued)

0 EN_PGOOD_BUCK0 R/W * Enable powergood diagnostics for Buck0

7.6.1.1.21 PGOOD_LEVEL_1 Register (Offset = 14h)

PGOOD_LEVEL_1 is shown in Figure 42 and described in Table 31. Figure 42. PGOOD_LEVEL_1 Register Table 31. PGOOD_LEVEL_1 Register Field Descriptions

7.6.1.1.22 PGOOD_LEVEL_2 Register (Offset = 15h)

PGOOD_LEVEL_2 is shown in Figure 43 and described in Table 32. Figure 43. PGOOD_LEVEL_2 Register

Table 32. PGOOD_LEVEL_2 Register Field Descriptions

7.6.1.1.23 PGOOD_LEVEL_3 Register (Offset = 16h)

PGOOD_LEVEL_3 is shown in Figure 44 and described in Table 33. Figure 44. PGOOD_LEVEL_3 Register Table 33. PGOOD_LEVEL_3 Register Field Descriptions

1 VANA_WINDOW R/W * Overvoltage and undervoltage threshold levels for VANA:

Table 33. PGOOD_LEVEL_3 Register Field Descriptions (continued)

0 VANA_THRESHOLD R/W * Threshold voltage for VANA input:

7.6.1.1.24 PG_CTRL Register (Offset = 17h)

PG_CTRL is shown in Figure 45 and described in Table 34. Figure 45. PG_CTRL Register Table 34. PG_CTRL Register Field Descriptions

7 PG1_MODE R/W * Operating mode for PG1 signal:

1 - Showing when requested outputs are not valid.

6 PGOOD_FAULT_GATES

0 - Indicates live status of monitored voltage outputs. 4 PG1_POL R/W * PG1 signal polarity.

3 PG0_MODE R/W * Operating mode for PG0 signal:

1 - Showing when requested outputs are not valid.

2 PGOOD_FAULT_GATES

0 - Indicates live status of monitored voltage outputs.

1 PG0_OD R/W * PG0 signal type:

0 PG0_POL R/W * PG0 signal polarity.

7.6.1.1.25 PG0_CTRL Register (Offset = 18h)

PG0_CTRL is shown in Figure 46 and described in Table 35. Figure 46. PG0_CTRL Register Table 35. PG0_CTRL Register Field Descriptions

7 PG0_RISE_DELAY R/W 0h 0 - PG0 rise is not delayed 1 - PG0 rise is delayed 11ms

6 SEL_PG0_TWARN R/W * PG0 control from thermal warning:

5 SEL_PG0_VANA R/W * PG0 signal source control from VANA

4 SEL_PG0_VMON2 R/W * PG0 signal source control from VMON2

3 SEL_PG0_VMON1 R/W * PG0 signal source control from VMON1

2 SEL_PG0_BOOST R/W * PG0 signal source control from Boost

1 SEL_PG0_BUCK1 R/W * PG0 signal source control from Buck1

0 SEL_PG0_BUCK0 R/W * PG0 signal source control from Buck0

7.6.1.1.26 PG0_FAULT Register (Offset = 19h)

PG0_FAULT is shown in Figure 47 and described in Table 36. Figure 47. PG0_FAULT Register

Table 36. PG0_FAULT Register Field Descriptions

7 RESERVED R 0h

6 PG0_FAULT_TWARN R 0h Source for PG0 inactive signal:

0 - TWARN has not set PG0 signal inactive.

5 PG0_FAULT_VANA R 0h Source for PG0 inactive signal:

0 - VANA has not set PG0 signal inactive.

4 PG0_FAULT_VMON2 R 0h Source for PG0 inactive signal:

0 - VMON2 has not set PG0 signal inactive.

3 PG0_FAULT_VMON1 R 0h Source for PG0 inactive signal:

0 - VMON1 has not set PG0 signal inactive.

2 PG0_FAULT_BOOST R 0h Source for PG0 inactive signal:

0 - Boost has not set PG0 signal inactive.

1 PG0_FAULT_BUCK1 R 0h Source for PG0 inactive signal:

0 - Buck1 has not set PG0 signal inactive.

0 PG0_FAULT_BUCK0 R 0h Source for PG0 inactive signal:

0 - Buck0 has not set PG0 signal inactive.

7.6.1.1.27 PG1_CTRL Register (Offset = 1Ah)

PG1_CTRL is shown in Figure 48 and described in Table 37. Figure 48. PG1_CTRL Register

Table 37. PG1_CTRL Register Field Descriptions

7 PG1_RISE_DELAY R/W 0h 0 - PG1 rise is not delayed 1 - PG1 rise is delayed 11ms

6 SEL_PG1_TWARN R/W * PG1 control from thermal warning:

5 SEL_PG1_VANA R/W * PG1 signal source control from VANA

4 SEL_PG1_VMON2 R/W * PG1 signal source control from VMON2

3 SEL_PG1_VMON1 R/W * PG1 signal source control from VMON1

2 SEL_PG1_BOOST R/W * PG1 signal source control from Boost

1 SEL_PG1_BUCK1 R/W * PG1 signal source control from Buck1

0 SEL_PG1_BUCK0 R/W * PG1 signal source control from Buck0

7.6.1.1.28 PG1_FAULT Register (Offset = 1Bh)

PG1_FAULT is shown in Figure 49 and described in Table 38. Figure 49. PG1_FAULT Register Table 38. PG1_FAULT Register Field Descriptions

6 PG1_FAULT_TWARN R 0h Source for PG1 inactive signal:

0 - TWARN has not set PG1 signal inactive.

Table 38. PG1_FAULT Register Field Descriptions (continued)

5 PG1_FAULT_VANA R 0h Source for PG1 inactive signal:

0 - VANA has not set PG1 signal inactive.

4 PG1_FAULT_VMON2 R 0h Source for PG1 inactive signal:

0 - VMON2 has not set PG1 signal inactive.

3 PG1_FAULT_VMON1 R 0h Source for PG1 inactive signal:

0 - VMON1 has not set PG1 signal inactive.

2 PG1_FAULT_BOOST R 0h Source for PG1 inactive signal:

0 - Boost has not set PG1 signal inactive.

1 PG1_FAULT_BUCK1 R 0h Source for PG1 inactive signal:

0 - Buck1 has not set PG1 signal inactive.

0 PG1_FAULT_BUCK0 R 0h Source for PG1 inactive signal:

0 - Buck0 has not set PG1 signal inactive.

7.6.1.1.29 WD_CTRL_1 Register (Offset = 1Ch)

WD_CTRL_1 is shown in Figure 50 and described in Table 39. Figure 50. WD_CTRL_1 Register Table 39. WD_CTRL_1 Register Field Descriptions

7.6.1.1.30 WD_CTRL_2 Register (Offset = 1Dh)

WD_CTRL_2 is shown in Figure 51 and described in Table 40. Figure 51. WD_CTRL_2 Register Table 40. WD_CTRL_2 Register Field Descriptions WD_RESET_CNTR_STATUS can be cleared even if WD_LOCK=1.

4 WD_SYS_RESTART_FLA

3 WD_EN_OTP_READ R/W * Read OTP during system restart sequence 0 - OTP read not

2 WDI_PD R/W * Selects the pull down resistor on the WDI pin:

1 WDR_POL R/W * Watchdog reset output (WDR) polarity select 0 - Active high 1 -

0 WDR_OD R/W * Watchdog reset output (WDR) signal type 0 - Push-pull output

7.6.1.1.31 WD_STATUS Register (Offset = 1Eh)

WD_STATUS is shown in Figure 52 and described in Table 41. Figure 52. WD_STATUS Register Table 41. WD_STATUS Register Field Descriptions

4 WD_CLR_SYSTEM_RES

clear pulse. Reg bit value returns to 0 after clearing is finished.

3 WD_SYSTEM_RESTART

writing WD_CLR_SYSTEM_RESTART_FLAG bit 1.

Table 41. WD_STATUS Register Field Descriptions (continued) 2 WD_CLR_RESET_CNTR R 0h Watchdog reset counter clear. Write 1 to generate a clear pulse. R 0h Current status of watchdog reset counter.

7.6.1.1.32 RESET Register (Offset = 1Fh)

RESET is shown in Figure 53 and described in Table 42. Figure 53. RESET Register Table 42. RESET Register Field Descriptions The bit is automatically cleared.

7.6.1.1.33 INT_TOP_1 Register (Offset = 20h)

INT_TOP_1 is shown in Figure 54 and described in Table 43. Figure 54. INT_TOP_1 Register Table 43. INT_TOP_1 Register Field Descriptions

7 I_MEAS_INT R 0h Latched status bit indicating that the load current measurement

result is available in I_LOAD_1 and I_LOAD_2 registers. 6 DIAG_INT R 0h Interrupt indicating that INT_DIAG register has a pending interrupt. The reason for the interrupt is indicated in INT_DIAG register. reason for the interrupt is indicated in INT_BOOST register.

4 BUCK_INT R 0h Interrupt indicating that BUCK0 and/or BUCK1 have a pending

Table 43. INT_TOP_1 Register Field Descriptions (continued)

3 SYNC_CLK_INT R 0h Latched status bit indicating that the external clock frequency

2 TDIE_SD_INT R 0h Latched status bit indicating that the die junction temperature has

by TDIE_SD_INT_STAT bit in TOP_STAT register.

1 TDIE_WARN_INT R 0h Latched status bit indicating that the die junction temperature has

0 OVP_INT R 0h Latched status bit indicating that the input voltage has exceeded the

indicated by OVP bit in TOP_STAT register.

7.6.1.1.34 INT_TOP_2 Register (Offset = 21h)

INT_TOP_2 is shown in Figure 55 and described in Table 44. Figure 55. INT_TOP_2 Register Table 44. INT_TOP_2 Register Field Descriptions

0 RESET_REG_INT R 0h Latched status bit indicating that either VBAT supply voltage has

7.6.1.1.35 INT_BUCK Register (Offset = 22h)

INT_BUCK is shown in Figure 56 and described in Table 45. Figure 56. INT_BUCK Register

Table 45. INT_BUCK Register Field Descriptions

6 BUCK1_PG_INT R 0h Latched status bit indicating that BUCK1 powergood event has been

5 BUCK1_SC_INT R 0h Latched status bit indicating that the BUCK1 output voltage has

reach 0.35 V level in 1 ms from enable.

4 BUCK1_ILIM_INT R 0h Latched status bit indicating that BUCK1 output current limit has

3 RESERVED R/W 0h

2 BUCK0_PG_INT R 0h Latched status bit indicating that BUCK0 powergood event has been

1 BUCK0_SC_INT R 0h Latched status bit indicating that the BUCK0 output voltage has

reach 0.35 V level in 1 ms from enable.

0 BUCK0_ILIM_INT R 0h Latched status bit indicating that BUCK0 output current limit has

7.6.1.1.36 INT_BOOST Register (Offset = 23h)

INT_BOOST is shown in Figure 57 and described in Table 46. Figure 57. INT_BOOST Register Table 46. INT_BOOST Register Field Descriptions

2 BOOST_PG_INT R 0h Latched status bit indicating that Boost powergood event has been

1 BOOST_SC_INT R 0h Latched status bit indicating that the Boost output voltage has fallen

V level in 1 ms from enable.

0 BOOST_ILIM_INT R 0h Latched status bit indicating that Boost output current limit has been

7.6.1.1.37 INT_DIAG Register (Offset = 24h)

INT_DIAG is shown in Figure 58 and described in Table 47.

Figure 58. INT_DIAG Register Table 47. INT_DIAG Register Field Descriptions

4 VMON2_PG_INT R 0h Latched status bit indicating that VMON2 powergood event has been

2 VMON1_PG_INT R 0h Latched status bit indicating that VMON1 powergood event has been

1 RESERVED R/W 0h

0 VANA_PG_INT R 0h Latched status bit indicating that VANA powergood event has been

7.6.1.1.38 TOP_STATUS Register (Offset = 25h)

TOP_STATUS is shown in Figure 59 and described in Table 48. Figure 59. TOP_STATUS Register Table 48. TOP_STATUS Register Field Descriptions

3 SYNC_CLK_STAT R 0h Status bit indicating the status of external clock (CLKIN):

1 - External clock frequency is not valid.

2 TDIE_SD_STAT R 0h Status bit indicating the status of thermal shutdown:

1 - Die temperature above thermal shutdown level.

1 TDIE_WARN_STAT R 0h Status bit indicating the status of thermal warning:

1 - Die temperature above thermal warning level.

0 OVP_STAT R 0h Status bit indicating the status of input overvoltage monitoring:

1 - Input voltage above overvoltage threshold level.

7.6.1.1.39 BUCK_STATUS Register (Offset = 26h)

BUCK_STATUS is shown in Figure 60 and described in Table 49.

Figure 60. BUCK_STATUS Register Table 49. BUCK_STATUS Register Field Descriptions

7 BUCK1_STAT R 0h Status bit indicating the enable/disable status of BUCK1:

1 - BUCK1 regulator is enabled.

6 BUCK1_PG_STAT R 0h Status bit indicating BUCK1 output voltage validity (raw status)

5 RESERVED R 0h Reserved

4 BUCK1_ILIM_STAT R 0h Status bit indicating BUCK1 current limit status (raw status)

1 - BUCK1 output current is at current limit threshold level.

3 BUCK0_STAT R 0h Status bit indicating the enable/disable status of BUCK0:

1 - BUCK0 regulator is enabled.

2 BUCK0_PG_STAT R 0h Status bit indicating BUCK0 output voltage validity (raw status)

1 RESERVED R 0h Reserved

0 BUCK0_ILIM_STAT R 0h Status bit indicating BUCK0 current limit status (raw status)

1 - BUCK0 output current is at current limit threshold level.

7.6.1.1.40 BOOST_STATUS Register (Offset = 27h)

BOOST_STATUS is shown in Figure 61 and described in Table 50. Figure 61. BOOST_STATUS Register Table 50. BOOST_STATUS Register Field Descriptions

3 BOOST_STAT R 0h Status bit indicating the enable/disable status of Boost:

1 - Boost regulator is enabled.

2 BOOST_PG_STAT R 0h Status bit indicating Boost output voltage validity (raw status)

0 BOOST_ILIM_STAT R 0h Status bit indicating Boost current limit status (raw status)

1 - Boost output current is at current limit threshold level.

7.6.1.1.41 DIAG_STATUS Register (Offset = 28h)

DIAG_STATUS is shown in Figure 62 and described in Table 51. Figure 62. DIAG_STATUS Register Table 51. DIAG_STATUS Register Field Descriptions

4 VMON2_PG_STAT R 0h Status bit indicating VMON2 input voltage validity (raw status)

3 RESERVED R 0h

2 VMON1_PG_STAT R 0h Status bit indicating VMON1 input voltage validity (raw status)

1 RESERVED R 0h

0 VANA_PG_STAT R 0h Status bit indicating VANA input voltage validity (raw status)

7.6.1.1.42 TOP_MASK_1 Register (Offset = 29h)

TOP_MASK_1 is shown in Figure 63 and described in Table 52. Figure 63. TOP_MASK_1 Register Table 52. TOP_MASK_1 Register Field Descriptions

7 I_MEAS_MASK R/W * Masking for load current measurement ready interrupt MEAS_INT in

1 - Interrupt not generated.

3 SYNC_CLK_MASK R/W * Masking for external clock detection interrupt SYNC_CLK_INT in

1 - Interrupt not generated.

2 RESERVED R/W 0h

Table 52. TOP_MASK_1 Register Field Descriptions (continued)

1 TDIE_WARN_MASK R/W * Masking for thermal warning interrupt TDIE_WARN_INT in

1 - Interrupt not generated.

0 RESERVED R/W 0h

7.6.1.1.43 TOP_MASK_2 Register (Offset = 2Ah)

TOP_MASK_2 is shown in Figure 64 and described in Table 53. Figure 64. TOP_MASK_2 Register Table 53. TOP_MASK_2 Register Field Descriptions

0 RESET_REG_MASK R/W * Masking for register reset interrupt RESET_REG_INT in INT_TOP_2

1 - Interrupt not generated.

7.6.1.1.44 BUCK_MASK Register (Offset = 2Bh)

BUCK_MASK is shown in Figure 65 and described in Table 54. Figure 65. BUCK_MASK Register Table 54. BUCK_MASK Register Field Descriptions

7 BUCK1_PGF_MASK R/W * Masking of powergood invalid detection for BUCK1 power good

1 - Interrupt not generated.

Table 54. BUCK_MASK Register Field Descriptions (continued)

6 BUCK1_PGR_MASK R/W * Masking of powergood valid detection for BUCK1 power good

1 - Interrupt not generated.

4 BUCK1_ILIM_MASK R/W * Masking for BUCK1 current monitoring interrupt BUCK1_IMON_INT

1 - Interrupt not generated.

3 BUCK0_PGF_MASK R/W * Masking of powergood invalid detection for BUCK0 power good

1 - Interrupt not generated.

2 BUCK0_PGR_MASK R/W * Masking of powergood valid detection for BUCK0 power good

1 - Interrupt not generated.

0 BUCK0_ILIM_MASK R/W * Masking for BUCK0 current monitoring interrupt BUCK0_IMON_INT

1 - Interrupt not generated.

7.6.1.1.45 BOOST_MASK Register (Offset = 2Ch)

BOOST_MASK is shown in Figure 66 and described in Table 55. Figure 66. BOOST_MASK Register

Table 55. BOOST_MASK Register Field Descriptions

3 BOOST_PGF_MASK R/W * Masking of powergood invalid detection for Boost power good

1 - Interrupt not generated.

2 BOOST_PGR_MASK R/W * Masking of powergood valid detection for Boost power good interrupt

1 - Interrupt not generated.

0 BOOST_ILIM_MASK R/W * Masking for Boost current monitoring interrupt BOOST_IMON_INT in

1 - Interrupt not generated.

7.6.1.1.46 DIAG_MASK Register (Offset = 2Dh)

DIAG_MASK is shown in Figure 67 and described in Table 56. Figure 67. DIAG_MASK Register Table 56. DIAG_MASK Register Field Descriptions

5 VMON2_PGF_MASK R/W * Masking of VMON2 invalid detection for powergood interrupt

1 - Interrupt not generated.

4 VMON2_PGR_MASK R/W * Masking of VMON2 valid detection for powergood interrupt

1 - Interrupt not generated.

Table 56. DIAG_MASK Register Field Descriptions (continued)

3 VMON1_PGF_MASK R/W * Masking of VMON1 invalid detection for powergood interrupt

1 - Interrupt not generated.

2 VMON1_PGR_MASK R/W * Masking of VMON1 valid detection for powergood interrupt

1 - Interrupt not generated.

1 VANA_PGF_MASK R/W * Masking of VANA invalid detection for powergood interrupt

1 - Interrupt not generated.

0 VANA_PGR_MASK R/W * Masking of VANA valid detection for powergood interrupt

1 - Interrupt not generated.

7.6.1.1.47 SEL_I_LOAD Register (Offset = 2Eh)

SEL_I_LOAD is shown in Figure 68 and described in Table 57. Figure 68. SEL_I_LOAD Register Table 57. SEL_I_LOAD Register Field Descriptions The measurement is started when register is written.

7.6.1.1.48 I_LOAD_2 Register (Offset = 2Fh)

I_LOAD_2 is shown in Figure 69 and described in Table 58.

Figure 69. I_LOAD_2 Register Table 58. I_LOAD_2 Register Field Descriptions

0 BUCK_LOAD_CURRENT

7.6.1.1.49 I_LOAD_1 Register (Offset = 30h)

I_LOAD_1 is shown in Figure 70 and described in Table 59. Figure 70. I_LOAD_1 Register Table 59. I_LOAD_1 Register Field Descriptions

7.6.1.1.50 FREQ_SEL Register (Offset = 31h)

FREQ_SEL is shown in Figure 71 and described in Table 60. Figure 71. FREQ_SEL Register Table 60. FREQ_SEL Register Field Descriptions

2 BOOST_FREQ_SEL R/W * Boost switching frequency:

7.6.1.1.51 BOOST_ILIM_CTRL Register (Offset = 32h)

BOOST_ILIM_CTRL is shown in Figure 72 and described in Table 61. Figure 72. BOOST_ILIM_CTRL Register Table 61. BOOST_ILIM_CTRL Register Field Descriptions

7.6.1.1.52 ECC_STATUS Register (Offset = 33h)

ECC_STATUS is shown in Figure 73 and described in Table 62. Figure 73. ECC_STATUS Register Table 62. ECC_STATUS Register Field Descriptions

1 DED R 0h OTP error correction status: 0 - No dual errors detected 1 - Dual

0 SED R 0h OTP error correction status: 0 - No single errors detected 1 - Single

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

general-purpose digital output signals.

8.2 Typical Application

Figure 74. LP87702-Q1 Typical Application

8.2.1 Design Requirements

Table 63. Design Parameters

(1) Operating temperature range is up to 125°C including self temperature rise.

8.2.2 Detailed Design Procedure

8.2.2.1 Application Components

8.2.2.1.1 Inductor Selection

Table 64. Recommended Inductors

8.2.2.1.2 Buck Input Capacitor Selection

capacitance common for all the power input pins on the system power rail. See Table 65. ripple current rating. In addition ferrite can be used in front of the input capacitor to reduce the EMI. Table 65. Recommended Buck Input Capacitors (X7R Dielectric)

8.2.2.1.3 Buck Output Capacitor Selection

including the DC voltage roll-off, tolerances, aging and temperature effects. selection process is at the switching frequency of the part. See Table 66. capacitor more time is required to settle VOUT down as a consequence of the increased time constant. Table 66. Recommended Buck Output Capacitors (X7R or X7T Dielectric)

8.2.2.1.4 Boost Input Capacitor Selection

SW_BST pin of the device. Use X7R types, do not use Y5V or F. See Table 67. Table 67. Recommended Boost Input Capacitors (X7R Dielectric)

8.2.2.1.5 Boost Output Capacitor Selection

sufficient capacitance and sufficiently low ESR and ESL to support load transients. See Table 68. Table 68. Recommended Boost Output Capacitors (X7R or X7T Dielectric)

8.2.2.1.6 Supply Filtering Components

components from for VANA input supply filtering. Table 69. Recommended Supply Filtering Components

9 Power Supply Recommendations

capacitance may be required in addition to the ceramic bypass capacitors.

10 Layout

10.1 Layout Guidelines

The high frequency and large switching currents of the LP87702-Q1 make the choice of layout important. Good power supply results will only occur when care is given to proper design and layout. Layout will affect noise pickup and generation and can cause a good design to perform with less-than-expected results. With a range of output currents from milliamps to several amps, good power supply layout is much more difficult than most general PCB design. The following steps should be used as a reference to ensure the device is stable and maintains proper voltage and current regulation across its intended operating voltage and current range. 1. Place CIN as close as possible to the VIN_Bx pin and the PGND_Bx pin. Route the VIN trace wide and thick to avoid IR drops. The trace between the positive node of the input capacitor and device VIN_Bx pin(s) as well as the trace between the negative node of the input capacitor and power PGND_Bx pin(s) must be kept as short as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The inductance of the connection is the most important parameter of a local decoupling capacitor - parasitic inductance on these traces must be kept as tiny as possible for proper device operation. 2. The output filter, consisting of L and COUT, converts the switching signal at SW_Bx to the noiseless output voltage. It should be placed as close as possible to the device keeping the switch node small, for best EMI behavior. Route the traces between the LP87702-Q1's output capacitors and the load's input capacitors direct and wide to avoid losses due to the IR drop. 3. Input for analog blocks (VANA and AGND) should be isolated from noisy signals. Connect VANA directly to a quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling capacitor as close as possible to the VANA pin. 4. If remote voltage sensing can be used for the load, connect the device feedback pins FB_Bx to the respective sense pins on the load capacitor. The sense lines are susceptible to noise. They must be kept away from noisy signals such as PGND_Bx, VIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I2C. Avoid both capacitive as well as inductive coupling by keeping the sense lines short and direct. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. 5. PGND_Bx, VIN_Bx and SW_Bx should be routed on thick layers. They must not surround inner signal layers which are not able to withstand interference from noisy PGND_Bx, VIN_Bx and SW_Bx. Due to the small package of this converter and the overall small solution size, the thermal performance of the PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures. Wide power traces come with the ability to sink dissipated heat. This can be improved further on multi-layer PCB designs with vias to different planes. This results in reduced junction-to-ambient (RθJA) and junction-to-board (RθJB) thermal resistances and thereby reduces the device junction temperature, TJ. It's strongly recommended to perform a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design process, by using a thermal modeling analysis software.

2 FB_B0

3 FB_B1

7 WDI

4 AGND

5 VANA

6 WD_RESET

25 SW_B0

26 SW_B0

27 VIN_B0

31 VMON2

28 VIN_B0

29 PG0

30 VMON1

32 PG1 (GPO1)

10.2 Layout Example

Figure 75. LP87702-Q1 Board Layout Example

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 19-Dec-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples P87702DRHBRQ1 ACTIVE VQFN RHB 32 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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Product Information

P87702DRHBRQ1 specifications and overview.

Summary

Dual Buck Converter and 5-V Boost With Diagnostic Functions

Description

Dual Buck Converter and 5-V Boost With Diagnostic Functions

Source title P87702DRHBRQ1 Datasheet(PDF) - Texas Instruments

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