Power Management

P87562TRNFRQ1

Texas Instruments

LP8756x-Q1 16-A Buck Converter With Integrated Switches MARCH 2018

Manufacturer: Texas Instruments

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LP87561-Q1_V08 TI | Alldatasheet

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PDF pages: 98

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Output Current (A) Efficiency (%) 0.001 0.01 0.1 1 10 20 20 100 D530 4PH, Vout=1.8V, Vin=3.7V 3PH, Vout=1.8V, Vin=3.7V 2PH, Vout=1.8V, Vin=3.7V 1PH, Vout=1.8V, Vin=3.7V SW_B0 SW_B1 SW_B2 SW_B3 FB_B0 FB_B1 Configurable multi-phase 1 - 4 Outputs FB_B2 FB_B3 VIN_B0 VIN_B1 VIN_B2 VIN_B3 VANA VIN NRST SDA SCL nINT CLKIN EN1 (GPIO1) EN2 (GPIO2) EN3 (GPIO3) GNDs PGOOD Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP87561-Q1 LP87562-Q1, LP87563-Q1, LP87564-Q1, LP87565-Q1 SNVSB22 –MARCH 2018 LP8756x-Q116-ABuckConverterWithIntegratedSwitches

1 Features

1• Qualified for Automotive Applications

AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature – Device HBM ESD Classification Level 2 – Device CDM ESD Classification Level C4B
Input Voltage: 2.8 V to 5.5 V
Output Voltage: 0.6 V to 3.36 V
Four High-Efficiency Step-Down DC/DC Converter Cores: – Maximum Output Current: 16 A (4 A per Phase) – Programmable Output Voltage Slew-Rate: 0.5 mV/µs to 10 mV/µs
Switching Frequency: 2 MHz
Spread-Spectrum Mode and Phase Interleaving
Configurable General Purpose I/O (GPIOs)
I2C-Compatible Interface That Supports Standard (100 kHz), Fast (400 kHz), Fast+ (1 MHz), and High-Speed (3.4 MHz) Modes
Interrupt Function With Programmable Masking
Programmable Power-Good Signal (PGOOD)
Output Short-Circuit and Overload Protection
Overtemperature Warning and Protection
Overvoltage Protection (OVP) and Undervoltage Lockout (UVLO)

2 Applications

Automotive Infotainment, Cluster, Radar, and Camera Power Applications space Simplified Schematic

3 Description

The LP8756x-Q1 device is designed to meet the power-management requirements of the latest processors and platforms in various automotive power applications. The device contains four step- down DC/DC converter cores, which are configured as a 4-phase output, 3-phase and 1-phase outputs, 2-phase and 2-phase outputs, one 2-phase and two 1-phase outputs, or four 1-phase outputs. The device is controlled by an I2C-compatible serial interface and by enable signals. The automatic pulse-width-modulation (PWM) to pulsed-frequency-modulation (PFM) operation (AUTO mode), together with the automatic phase adding and phase shedding, maximizes efficiency over a wide output-current range. The LP8756x-Q1 supports remote differential-voltage sensing for multiphase outputs to compensate IR drop between the regulator output and the point-of-load (POL) improving the accuracy of the output voltage. The switching clock can be forced to PWM mode and also synchronized to an external clock to minimize the disturbances. The LP8756x-Q1 device supports load-current measurement without the addition of external current- sense resistors. The device also supports programmable start-up and shutdown delays and sequences synchronized to enable signals. The sequences can include GPIO signals to control external regulators, load switches, and processor reset. During start-up and voltage change, the device controls the output slew rate to minimize output- voltage overshoot and in-rush current. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LP87561-Q1 VQFN-HR (26) 4.50 mm × 4.00 mm LP87562-Q1 LP87563-Q1 LP87564-Q1 LP87565-Q1 (1) For all available packages, see the orderable addendum at the end of the data sheet. Efficiency vs Output Current

12.4 Receiving Notification of Documentation Updates 86

13 Mechanical, Packaging, and Orderable

4 Revision History

March 2018 * Initial Release

VIN_B3 VIN_B2VIN_B0 VIN_B1 SW_B0 SW_B1 SW_B2 SW_B3 PGND_B01 PGND_B23 9 10 11 12 13 2223242526 FB_B3 FB_B0 FB_B1 FB_B2 LP87561-Q1 LP87562-Q1, LP87563-Q1, LP87564-Q1, LP87565-Q1 www.ti.com SNVSB22 –MARCH 2018 Product Folder Links: LP87561-Q1 LP87562-Q1 LP87563-Q1 LP87564-Q1 LP87565-Q1 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

5 Device Comparison Table

PART NUMBER DC/DC CONFIGURATIONS LP87561-Q1 One 4-phase output LP87562-Q1 One 3-phase and one 1-phase outputs LP87563-Q1 One 2-phase and two 1-phase outputs LP87564-Q1 Four 1-phase outputs LP87565-Q1 Two 2-phase outputs

6 Pin Configuration and Functions

26-Pin VQFN-HR With Thermal Pad Top View

LP87562-Q1, LP87563-Q1, LP87564-Q1, LP87565-Q1 SNVSB22 –MARCH 2018 www.ti.com Product Folder Links: LP87561-Q1 LP87562-Q1 LP87563-Q1 LP87564-Q1 LP87565-Q1 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME 1 FB_B2 A Output voltage feedback (positive) for the BUCK2 converter. 2 EN3 D/I/O Programmable enable signal for the buck regulators (can be also configured to select between two buck output-voltage levels). This pin functions alternatively as GPIO3. 3 CLKIN D/I External clock input. Connect this pin to ground if the external clock is not used. 4, 17, Thermal Pad AGND G Ground 5 SCL D/I Serial interface clock input for I2C access. Connect this pin to a pullup resistor. 6 SDA D/I/O Serial interface data input and output for I2C access. Connect this pin to a pullup resistor. 7 EN1 D/I/O Programmable enable signal for the buck regulators (can be also configured to select between two buck output voltage levels). This pin functions alternatively as GPIO1. 8 FB_B0 A Output voltage feedback (positive) for the BUCK0 converter.

9 VIN_B0 P

Input for the BUCK0 converter. The separate power pins, VIN_Bx, are not connected together internally. The VIN_Bx pins must be connected together in the application and be locally bypassed.

10 SW_B0 A BUCK0 switch node

11 PGND_B01 G Power ground for the BUCK0 and BUCK1 converters

12 SW_B1 A BUCK1 switch node

13 VIN_B1 P

Input for the BUCK1 converter. The separate power pins, VIN_Bx, are not connected together internally. The VIN_Bx pins must be connected together in the application and be locally bypassed. 14 FB_B1 A Output voltage feedback (positive) for the BUCK1 converter. This pin functions alternatively as the output ground feedback (negative) for the BUCK0 converter. 15 EN2 D/I/O Programmable enable signal for the buck regulators (can be also configured to select between two buck output voltage levels). This pin functions alternatively as GPIO2.

16 PGOOD D/O Power-good indication signal

18 VANA P Supply voltage for the analog and digital blocks. This pin must be connected to the same node as VIN_Bx. 19 nINT D/O Open-drain interrupt output. This pin is active low.

20 NRST D/I Reset signal for the device

21 FB_B3 A Output voltage feedback (positive) for the BUCK3 converter. This pin functions alternatively as the output ground feedback (negative) for the BUCK2 converter.

22 VIN_B3 P

Input for the BUCK3 converter. The separate power pins, VIN_Bx, are not connected together internally. The VIN_Bx pins must be connected together in the application and be locally bypassed.

23 SW_B3 A BUCK3 switch node

24 PGND_B23 G Power ground for the BUCK2 and BUCK3 converters

25 SW_B2 A BUCK2 switch node

26 VIN_B2 P

Input for the BUCK2 converter. The separate power pins, VIN_Bx, are not connected together internally. The VIN_Bx pins must be connected together in the application and be locally bypassed.

LP87562-Q1, LP87563-Q1, LP87564-Q1, LP87565-Q1 www.ti.com SNVSB22 –MARCH 2018 Product Folder Links: LP87561-Q1 LP87562-Q1 LP87563-Q1 LP87564-Q1 LP87565-Q1 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground.

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)(2) MIN MAX UNIT Voltage on power connections VIN_Bx, VANA –0.3 6 V Voltage on buck switch nodes SW_Bx –0.3 (VIN_Bx + 0.3 with 6 V maximum V Voltage on buck voltage sense nodes FB_Bx –0.3 (VANA + 0.3 V) with 6 V maximum V Voltage on NRST input NRST –0.3 6 V Voltage on logic pins (input or output pins) SDA, SCL, nINT, CLKIN –0.3 6 V EN1 (GPIO1), EN2 (GPIO2), EN3 (GPIO3), PGOOD –0.3 (VANA + 0.3 V) with 6 V maximum V Maximum lead temperature (soldering, 10 sec.) 260 °C Junction temperature, TJ-MAX –40 150 °C Storage temperature, Tstg –65 150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V Charged-device model (CDM), per AEC Q100-011 All pins ±500 Corner pins (1, 8, 14, and 21) ±750

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT INPUT VOLTAGE Voltage on power connections VIN_Bx, VANA 2.8 5.5 V Voltage on NRST NRST 1.65 VANA with

5.5 V maximum V

Voltage on logic pins (input or output pins) nINT, CLKIN 1.65 5.5 V Voltage on logic pins (input or output pins) ENx, PGOOD 0 VANA with Voltage on I2C interface, standard (100 kHz), fast (400 khz), fast+ (1 MHz), and high-speed (3.4 MHz) modes SCL, SDA 1.65 1.95 V Voltage on I2C interface, standard (100 kHz), fast (400 kHz), and fast+ (1 MHz) modes SCL, SDA 3.1 VANA with

3.6 V maximum V

Junction temperature, TJ –40 140 °C Ambient temperature, TA –40 125 °C

LP87562-Q1, LP87563-Q1, LP87564-Q1, LP87565-Q1 SNVSB22 –MARCH 2018 www.ti.com Product Folder Links: LP87561-Q1 LP87562-Q1 LP87563-Q1 LP87564-Q1 LP87565-Q1 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.4 Thermal Information

THERMAL METRIC(1) LP8756x-Q1 UNITRNF (VQFN-HR)

26 PINS

RθJA Junction-to-ambient thermal resistance 34.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 16.5 °C/W RθJB Junction-to-board thermal resistance 4.7 °C/W ψJT Junction-to-top characterization parameter 0.6 °C/W ψJB Junction-to-board characterization parameter 4.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.4 °C/W (1) All voltage values are with respect to network ground. (2) Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but do represent the most likely norm. (3) The output voltage slew-rate setting may limit the maximum output capacitance.

7.5 Electrical Characteristics

–40°C ≤ TJ ≤ +140°C, CPOL = 22 µF/phase, specified VVANA, VVIN_Bx , VNRST, VVOUT_Bx, and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V, unless otherwise noted(1) (2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EXTERNAL COMPONENTS CIN Input filtering capacitance Connected from VIN_Bx to PGND_Bx 1.9 10 µF COUT Output filtering capacitance per phase, local 10 22 µF CPOL Optional point-of-load (POL) capacitance per phase 22 µF COUT-TOTAL Total output capacitance(3) (local and POL) 4-phase output Output voltage slew-rate ≤ 1.9 mV/µs 2000 µF 3-phase output Output voltage slew-rate ≤ 1.9 mV/µs 1500 2-phase output Output voltage slew-rate ≤ 1.9 mV/µs 1000 1-phase output Output voltage slew-rate ≤ 1.9 mV/µs 500 ESRC ESR of the input and output capacitor 1 MHz ≤ f ≤ 10 MHz 2 10 mΩ L Inductance of the inductor 0.47 µH –30% 30% DCRL Inductor DCR 25 mΩ BUCK REGULATOR VVIN_Bx Input voltage range 2.8 3.7 5.5 V VVOUT_Bx Programmable output voltage range 0.6 3.36 V Output voltage step size 0.6 V ≤ VVOUT < 0.73 V 10 mV0.73 V ≤ VVOUT < 1.4 V 5 1.4 V ≤ VVOUT ≤ 3.36 V 20

2.8 V ≤ VIN < 3 V 12

VIN ≥ 3 V 12

2.8 V ≤ VIN < 3 V 9

VIN ≥ 3 V 8

2.8 V ≤ VIN < 3 V 6

VIN ≥ 3 V 4

2.8 V ≤ VIN < 3 V 3

Input and output voltage difference Minimum voltage between VIN_x and VOUT to fulfill the electrical characteristics 0.5 V VVOUT_DC DC output voltage accuracy, includes voltage reference, DC load and line regulations, process, and temperature VOUT < 1 V, PWM mode –20 20 mV VOUT ≥ 1 V, PWM mode –2% 2% VOUT < 1 V, PFM mode –20 40 mV VOUT ≥ 1 V, PFM mode –2% 2% + 20 mV Ripple voltage 4-phase output PWM mode, ESRC < 2 mΩ, L = 0.47 µH 3 mVp-p PFM mode, L = 0.47 µH 4 3-phase output PWM mode, ESRC < 2 mΩ, L = 0.47 µH 4 PFM mode, L = 0.47 µH 5 2-phase output PWM mode, ESRC < 2 mΩ, L = 0.47 µH 6 PFM mode, L = 0.47 µH 7 1-phase output, PWM mode, ESRC < 2 mΩ, L = 0.47 µH 8 PFM mode, L = 0.47 µH 14 DCLNR DC line regulation IOUT = IOUT(max) 0.1 %/V DCLDR DC load regulation in PWM mode VOUT = 1 V, 0 A ≤ IOUT ≤ IOUT(max) 0.8%

0 A ≤ IOUT ≤ 8 A, tr = tf = 10

µs, PWM mode, COUT = 22 µF/phase, L = 0.47 µH, CPOL = 22 µF/phase –3% 3% mV

0.1 A ≤ IOUT ≤ 8 A, tr = tf = 1

µs, PWM mode, COUT = 22 µF/phase, L = 0.47 µH, CPOL = 22 µF/phase ±40 3-phase output

0 A ≤ IOUT ≤ 6 A, tr = tf = 10

µs, PWM mode, COUT = 22 µF/phase, L = 0.47 µH, CPOL = 22 µF/phase –3% 3%

0.1 A ≤ IOUT ≤ 6 A, tr = tf = 1

µs, PWM mode, COUT = 22 µF/phase, L = 0.47 µH, CPOL = 22 µF/phase ±40 2-phase output

0 A ≤ IOUT ≤ 4 A, tr = tf = 10

µs, PWM mode, COUT = 22 µF/phase, L = 0.47 µH, CPOL = 22 µF/phase –3% 3%

0.1 A ≤ IOUT ≤ 4 A, tr = tf = 1

µs, PWM mode, COUT = 22 µF/phase, L = 0.47 µH, CPOL = 22 µF/phase ±40 1-phase output

0 A ≤ IOUT ≤ 2 A, tr = tf = 10

µs, PWM mode, COUT = 22 µF, L = 0.47 µH, CPOL = 22 µF –3% 3%

0.1 A ≤ IOUT ≤ 2 A, tr = tf = 1

µs, PWM mode, COUT = 22 µF, L = 0.47 µH, CPOL = 22 µF ±40 TLNSR Transient line response VVIN_Bx stepping 3 V ↔ 3.5 V, tr = tf = 10 µs, IOUT = IOUT(max) ±5 mV ILIM FWD Forward current limit for each phase (peak for each switching cycle) Programmable range 1.5 5 A Step size 0.5 Accuracy, VVIN_Bx ≥ 3 V, ILIM ≥ 3 A –5% 7.5% 20% Accuracy, 2.8 V ≤ VVIN_Bx < 3 ILIM NEG Negative current limit per phase (peak for each switching cycle) 1.6 2 2.4 A RDS(ON) HS FET On-resistance, high-side FET Each phase, between VIN_Bx and SW_Bx pins, I = 1 A 29 65 mΩ RDS(ON) LS FET On-resistance, low-side FET Each phase, between SW_Bx and PGND_Bx pins, I = 1 A 17 35 mΩ fSW Switching frequency, PWM mode 1.8 2 2.2 MHz Current balancing for multiphase outputs Current mismatch between phases, IOUT > 1 A/phase 10% Start-up time (soft start) From ENx to VOUT = 0.35 V (slew-rate control begins), COUT_TOTAL = 44 µF/phase 200 µs

LP87562-Q1, LP87563-Q1, LP87564-Q1, LP87565-Q1 www.ti.com SNVSB22 –MARCH 2018 Product Folder Links: LP87561-Q1 LP87562-Q1 LP87563-Q1 LP87564-Q1 LP87565-Q1 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) –40°C ≤ TJ ≤ +140°C, CPOL = 22 µF/phase, specified VVANA, VVIN_Bx , VNRST, VVOUT_Bx, and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V, unless otherwise noted(1) (2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (5) Output capacitance, forward and negative current limits and load current may limit the maximum and minimum slew rates. The actual set fixed slew rate value for specific part number is listed in corresponding TRM document. (6) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage, and the inductor current level. Output voltage slew-rate(5) SLEW_RATEx[2:0] = 2h, COUT-TOTAL ≤ 80 µF/phase –15% 10 15% mV/µs SLEW_RATEx[2:0] = 3h, COUT-TOTAL ≤ 130 µF/phase –15% 7.5 15% SLEW_RATEx[2:0] = 4h, COUT-TOTAL ≤ 250 µF/phase –15% 3.8 15% SLEW_RATEx[2:0] = 5h, COUT-TOTAL ≤ 500 µF/phase –15% 1.9 15% SLEW_RATEx[2:0] = 6h, COUT-TOTAL ≤ 500 µF/phase –15% 0.94 15% SLEW_RATEx[2:0] = 7h, COUT-TOTAL ≤ 500 µF/phase –15% 0.47 15% IPFM-PWM PFM-to-PWM current threshold(6) 600 mA IPWM-PFM PWM-to-PFM current threshold(6) 200 mA IADD Phase adding level (multiphase rails) From 1-phase to 2-phase 1 AFrom 2-phase to 3-phase 2 From 3-phase to 4-phase 3 ISHED Phase shedding level (multiphase rails) From 2-phase to 1-phase 0.7 AFrom 3-phase to 2-phase 1.5 From 4-phase to 3-phase 2.4 Output pulldown resistance Regulator disabled 160 230 300 Ω Output voltage monitoring for PGOOD pin Overvoltage monitoring (compared to DC output- voltage level, VVOUT_DC) 39 50 64 mV Undervoltage monitoring (compared to DC output- voltage level, VVOUT_DC) –53 –40 –29 Debounce time during regulator enable PGOOD_SET_DELAY = 0h 4 10 µs Debounce time during regulator enable PGOOD_SET_DELAY = 1h 10 11 13 ms Deglitch time during operation and after voltage change 4 10 µs Power-good threshold for interrupt BUCKx_PG_INT, difference from final voltage Rising ramp voltage, enable or voltage change –20 –14 –8 mV Falling ramp voltage, voltage change 8 14 20 Power-good threshold for status bit BUCKx_PG_STAT During operation, status signal is forced to 0h during voltage change –20 –14 –8 mV

LP87562-Q1, LP87563-Q1, LP87564-Q1, LP87565-Q1 SNVSB22 –MARCH 2018 www.ti.com Product Folder Links: LP87561-Q1 LP87562-Q1 LP87563-Q1 LP87564-Q1 LP87565-Q1 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) –40°C ≤ TJ ≤ +140°C, CPOL = 22 µF/phase, specified VVANA, VVIN_Bx , VNRST, VVOUT_Bx, and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V, unless otherwise noted(1) (2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EXTERNAL CLOCK AND PLL Nominal frequency of the external input clock 1 24 MHz Nominal frequency step size of the external input clock 1 MHz Required accuracy from nominal frequency of the external input clock –30% 10% Delay time for missing external clock detection 1.8 µs Delay and debounce time for external clock detection 20 µs Clock change delay (internal to external) delay from valid clock detection to use of external clock 600 µs Cycle-to-cycle PLL output clock jitter 300 ps, p- p PROTECTION FUNCTIONS Thermal warning Temperature rising, TDIE_WARN_LEVEL = 0h 115 125 135 Temperature rising, TDIE_WARN_LEVEL = 1h 127 137 147 Thermal warning hysteresis 20 °C Thermal shutdown Temperature rising 140 150 160 °C Thermal shutdown hysteresis 20 °C VANAOVP VANA overvoltage Voltage rising 5.6 5.8 6.1 V Voltage falling 5.45 5.73 5.96 VANA overvoltage hysteresis 40 mV VANAUVLO VANA undervoltage lockout Voltage rising 2.51 2.63 2.75 V Voltage falling 2.5 2.6 2.7 LOAD CURRENT MEASUREMENT Current measurement range Output current for maximum code 20.47 A Resolution LSB 20 mA Measurement accuracy IOUT > 1 A < 10% Measurement time PFM mode (automatically changing to PWM mode for the measurement) µs PWM mode 4 CURRENT CONSUMPTION Shutdown current consumption From VANA and VIN_Bx pins, NRST = 0 V, VANA = VIN_Bx = 3.7 V 1.4 µA Standby current consumption From VANA and VIN_Bx pins, NRST = 1.8 V, VANA = VIN_Bx = 3.7 V, regulators disabled 6.7 µA

LP87562-Q1, LP87563-Q1, LP87564-Q1, LP87565-Q1 www.ti.com SNVSB22 –MARCH 2018 Product Folder Links: LP87561-Q1 LP87562-Q1 LP87563-Q1 LP87564-Q1 LP87565-Q1 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) –40°C ≤ TJ ≤ +140°C, CPOL = 22 µF/phase, specified VVANA, VVIN_Bx , VNRST, VVOUT_Bx, and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V, unless otherwise noted(1) (2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Active current consumption in PFM mode 4-phase enabled: From VANA and VIN_Bx pins, NRST = 1.8 V, VANA = VIN_Bx = 3.7 V, IOUT = 0 mA, not switching, one regulator enabled, internal RC oscillator, PGOOD monitoring enabled µA 3-phase enabled: From VANA and VIN_Bx pins, NRST = 1.8 V, VANA = VIN_Bx = 3.7 V, IOUT = 0 mA, not switching, one regulator enabled, internal RC oscillator, PGOOD monitoring enabled 2-phase enabled: From VANA and VIN_Bx pins, NRST = 1.8 V, VANA = VIN_Bx = 3.7 V, IOUT = 0 mA, not switching, one regulator enabled, internal RC oscillator, PGOOD monitoring enabled 1-phase enabled: From VANA and VIN_Bx pins, NRST = 1.8 V, VANA = VIN_Bx = 3.7 V, IOUT = 0 mA, not switching, one regulator enabled, internal RC oscillator, PGOOD monitoring enabled Active current consumption during PWM operation Each phase 17 mA PLL and clock detector current consumption Additional current consumption when internal RC oscillator, clock detector and PLL are enabled 2 mA DIGITAL INPUT SIGNALS: NRST, EN1, EN2, EN3, EN4, SCL, SDA, GPIO1, GPIO2, GPIO3, CLKIN VIL Input low level 0.4 V VIH Input high level 1.2 V VHYS Hysteresis of Schmitt trigger inputs 10 77 200 mV ENx pulldown resistance ENx_PD = 1h 500 kΩ NRST pulldown resistance Always present 650 1150 1700 kΩ DIGITAL OUTPUT SIGNALS: nINT VOL Output low level ISOURCE = 2 mA 0.4 V RP External pullup resistor To VIO supply 10 kΩ DIGITAL OUTPUT SIGNALS: SDA VOL Output low level ISOURCE = 10 mA 0.4 V DIGITAL OUTPUT SIGNALS: PGOOD, GPIO1, GPIO2, GPIO3 VOL Output low level ISOURCE = 2 mA 0.4 V VOH Output high level, configured to push-pull ISINK = 2 mA VVANA –

0.4 VVANA V

Supply voltage for external pull-up resistor, configured to open-drain VVANA V RPU External pullup resistor, configured to open-drain 10 kΩ ALL DIGITAL INPUTS ILEAK Input current All logic inputs over pin voltage range (except NRST) −1 1 µA

7.6 I2C Serial Bus Timing Requirements

These specifications are ensured by design. VIN_Bx = 3.7 V, unless otherwise noted. MIN MAX UNIT ƒSCL Serial clock frequency Standard mode 100 kHz Fast mode 400 Fast mode+ 1 MHzHigh-speed mode, Cb = 100 pF 3.4 High-speed mode, Cb = 400 pF 1.7 tLOW SCL low time Standard mode 4.7 µsFast mode 1.3 Fast mode+ 0.5 High-speed mode, Cb = 100 pF 160 ns High-speed mode, Cb = 400 pF 320 tHIGH SCL high time Standard mode 4 µsFast mode 0.6 Fast mode+ 0.26 High-speed mode, Cb = 100 pF 60 ns High-speed mode, Cb = 400 pF 120 tSU;DAT Data setup time Standard mode 250 ns Fast mode 100 Fast mode+ 50 High-speed mode 10 tHD;DAT Data hold time Standard mode 10 3450 nsFast mode 10 900 Fast mode+ 10 High-speed mode, Cb = 100 pF 10 70 ns High-speed mode, Cb = 400 pF 10 150 tSU;STA Setup time for a start or a repeated start condition Standard mode 4.7 µsFast mode 0.6 Fast mode+ 0.26 High-speed mode 160 ns tHD;STA Hold time for a start or a repeated start condition Standard mode 4 µsFast mode 0.6 Fast mode+ 0.26 High-speed mode 160 ns tBUF Bus free time between a stop and start condition Standard mode 4.7 µsFast mode 1.3 Fast mode+ 0.5 tSU;STO Setup time for a stop condition Standard mode 4 µsFast mode 0.6 Fast mode+ 0.26 High-speed mode 160 ns trDA Rise time of SDA signal Standard mode 1000 ns Fast mode 20 300 Fast mode+ 120 High-speed mode, Cb = 100 pF 10 80 High-speed mode, Cb = 400 pF 20 160

These specifications are ensured by design. VIN_Bx = 3.7 V, unless otherwise noted.

5.5 V) 300

5.5 V) 120

Figure 1. I2C Timing

7.7 Typical Characteristics

DFE252012PD-R47M), COUT = 22 µF / phase, CPOL = 22 µF / phase. Figure 2. Shutdown Current Consumption vs Input Voltage Figure 3. Standby Current Consumption vs Input Voltage Figure 4. PFM Mode Current Consumption vs Input Voltage Figure 5. PFM Mode Current Consumption vs Input Voltage, Figure 6. PFM Mode Current Consumption vs Input Voltage, Figure 7. PFM Mode Current Consumption vs Input Voltage,

DFE252012PD-R47M), COUT = 22 µF / phase, CPOL = 22 µF / phase. Figure 8. PFM Mode Current Consumption vs Input Voltage, One Regulator Enabled (2+2-Phase Output)

8 Detailed Description

8.1 Overview

converter cores for automotive applications. Table 1 lists the output characteristics of the regulators. Table 1. Supply Specification the external clock can be from 1 MHz to 24 MHz with 1-MHz steps.

Soft start
Input voltage protection: – Undervoltage lockout – Overvoltage protection
Output voltage monitoring and protection: – Overvoltage monitoring – Undervoltage monitoring – Overload protection
Thermal warning
Thermal shutdown Three enable signals can be multiplexed to general purpose I/O (GPIO) signals. The direction and output type (open-drain or push-pull) are programmable for the GPIOs.

Enable, Roof/Floor, Slew-Rate Control Interrupts nINT SDA SCL EN1 (GPIO1) EN2 (GPIO2) VANA OTP EPROM Thermal Monitor Oscillator Buck0 ILIM Det Overload and SC Det Buck1 Buck2 Buck3 ILIM Det Pwrgood Det Overload and SC Det ILIM Det Pwrgood Det Overload and SC Det ILIM Det Pwrgood Det Overload and SC Det Ref & Bias Iload ADC Iload ADC Iload ADC Iload ADC CLKIN EN3 (GPIO3) PGOOD Copyright © 2017, Texas Instruments Incorporated Pwrgood Det LP87561-Q1 LP87562-Q1, LP87563-Q1, LP87564-Q1, LP87565-Q1 www.ti.com SNVSB22 –MARCH 2018 Product Folder Links: LP87561-Q1 LP87562-Q1 LP87563-Q1 LP87564-Q1 LP87565-Q1 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

8.2 Functional Block Diagram

8.3 Feature Descriptions

8.3.1 Multi-Phase DC/DC Converters

8.3.1.1 Overview

The LP8756x-Q1 includes four step-down DC/DC converter cores which can be configured for:

4-phase single output
3-phase and single-phase outputs
dual-phase and two single-phase outputs
four single-phase outputs
two dual-phase outputs The cores are designed for flexibility; most of the functions are programmable, thus allowing optimization of the regulator operation for each application. The LP8756x-Q1 has the following features:
DVS support with programmable slew-rate
Automatic mode control based on the loading (PFM or PWM mode)
Forced-PWM mode operation
Optional external clock input to minimize crosstalk
Optional spread spectrum technique to decrease EMI
Phase control for optimized EMI
Synchronous rectification
Current mode loop with PI compensator
Soft start
Power-Good flag with maskable interrupt

Power-Good signal (PGOOD) with selectable sources
Average output current sensing (for PFM entry, phase shedding/adding, and load current measurement)
Current balancing between the phases of the converter
Differential voltage sensing from point of the load for multiphase output
Dynamic phase shedding/adding, each output being phase shifted The following parameters can be programmed via registers:
Output voltage
Forced-PWM operation
Forced multiphase operation for multiphase outputs (forces also the PWM operation)
Peak current limit for high-side FET
Output voltage slew rate
Enable and disable delays for regulators and GPIOs controlled by ENx pins There are two modes of operation for the converter, depending on the output current required: pulse-width modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load currents of approximately 600 mA or higher. When operating in PWM mode the phases of a multiphase regulator are automatically added/shedded based on the load current level. Lighter output current loads cause the converter to automatically switch into PFM mode for decreased current consumption when forced-PWM mode is disabled. The forced multiphase mode can be enabled for highest transient performance. A multiphase synchronous buck converter offers several advantages over one power stage converter. For application processor power delivery, lower ripple on the input and output currents and faster transient response to load steps are the most significant advantages. Also, because the load current is evenly shared among multiple channels in multiphase output configuration, the heat generated is greatly decreased for each channel due to the fact that power loss is proportional to square of current. The physical size of the output inductor shrinks significantly due to this heat reduction. Figure 9 shows a block diagram of a single core. Interleaving switching action of the multiphase converters is shown in Figure 10.

Figure 9. Detailed Block Diagram Showing One Core

(1) Graph is not in scale and is for illustrative purposes only. Figure 10. Example of PWM Timings, Inductor Current Waveforms, and Total Output Current in 4-Phase

8.3.1.2 Multiphase Operation, Phase Adding, and Phase-Shedding

the load. This is called phase adding/shedding. The concept is shown in Figure 11. automatically to follow the required output current.

(1) Graph is not in scale and is for illustrative purposes only. Figure 11. Multiphase Buck Converter Efficiency vs Number of Phases (Converters in PWM Mode)

8.3.1.3 Transition Between PWM and PFM Modes

modes a high efficiency is achieved over a wide output-load-current range.

8.3.1.4 Multiphase Switcher Configurations

BUCK2 is master for BUCK2, BUCK3 output.

BUCKx_CTRL1 register, except EN_RDISx bit
BUCKx_CTRL2 register, except ILIMx[2:0] bits
BUCKx_VOUT register
BUCKx_FLOOR_VOUT register
BUCKx_DELAY register
interrupt bits related to the slave buck, except BUCKx_ILIM_INT

8.3.1.5 Buck Converter Load-Current Measurement

interrupt (I_LOAD_READY bit in INT_TOP1 register) after the load current measurement sequence is finished. Load current measurement interrupt can be masked with I_LOAD_READY_MASK bit (TOP_MASK1 register). measured current is the output current of the selected phase.

8.3.1.6 Spread-Spectrum Mode

bit (PIN_FUNCTION register), and it affects all the buck cores. spectrum architecture of the LP8756x-Q1 spreads that energy over a large bandwidth. Figure 12. Spread-Spectrum Modulation

8.3.2 Sync Clock Functionality

accuracy limits (–30%/+10%) for valid clock detection.

PLL_MODE[1:0] = 01 and regulator enable (STANDBY-to-ACTIVE transition) when PLL_MODE[1:0] = 10. Figure 13. Clock and PLL Module Table 2. PLL Operation

8.3.3 Power-Up

VANA (and VIN_Bx) reach minimum recommended level (VVANA > VANAUVLO).
NRST is set to high level (or shorted to VANA). This initiates power-on-reset (POR), OTP reading and enables the system I/O interface. The I2C host must wait at least 1.2 ms before writing or reading data to the LP8756x-Q1.
Device goes to the STANDBY mode.
The host can change the default register setting by I2C if needed.
The regulator(s) can be enabled/disabled by ENx pin(s) and by I2C interface.

8.3.4 Regulator Control

8.3.4.1 Enabling and Disabling Regulators

Using EN_BUCKx bit in BUCKx_CTRL1 register (EN_PIN_CTRLx register bit is 0h)
Using EN1, EN2, EN3 control pins (EN_BUCKx bit is 1h AND EN_PIN_CTRLx register bit is 1 in BUCKx_CTRL1 register) If the EN1, EN2, EN3 control pins are used for enable and disable then the control pin is selected with BUCKx_EN_PIN_SELECT[1:0] bits (in BUCKx_CTRL1 register). The delay from the control signal rising edge to enabling of the regulator is set by BUCKx_STARTUP_DELAY[3:0] bits, and the delay from control signal falling edge to disabling of the regulator is set by BUCKx_SHUTDOWN_DELAY[3:0] bits in BUCKx_DELAY register. The delays are valid only for EN1, EN2, EN3 signal control. The control with EN_BUCKx bit is immediate without the delays. The control of the regulator (with 0-ms delays) is shown in Table 3. Multiphase regulators are controlled with registers of the master phase. NOTE The control of the regulator cannot be changed from one ENx pin to a different ENx pin because the control is ENx signal-edge sensitive. The control from ENx pin to register bit and back to the original ENx pin can be done during operation.

Table 3. Regulator Control using BUCKx_PG_MASK bit (in BUCKx_MASK register). host can disable those with ENx_PD bits (in CONFIG register).

Figure 14. Regulator Enable and Disable

8.3.4.2 Changing Output Voltage

and BUCKx_FLOOR_VOUT registers) or by writing to the BUCKx_VOUT and BUCKx_FLOOR_VOUT registers.

Figure 15. Regulator Output Voltage Change With ENx pin

8.3.5 Enable and Disable Sequences

EN_BUCKx = 1 (in BUCKx_CTRL1 register)
EN_PIN_CTRLx = 1 (in BUCKx_CTRL1 register)
EN_ROOF_FLOORx = 0 (in BUCKx_CTRL1 register)
BUCKx_VSET[7:0] = Required voltage when ENx is high (in BUCKx_VOUT register)
The ENABLE pin for control is selected with BUCKx_EN_PIN_SELECT[1:0] (in BUCKx_CTRL1 register)
The delay from rising edge of ENx signal to the regulator enable is set by BUCKx_STARTUP_DELAY[3:0] bits (in BUCKx_DELAY register) and
The delay from falling edge of ENx signal to the regulator disable is set by BUCKx_SHUTDOWN_DELAY[3:0] bits (in BUCKx_DELAY register) There are four time steps available for start-up and shutdown sequences. The delay times are selected with DOUBLE_DELAY bit in CONFIG register and HALF_DELAY bit in PGOOD_CTRL2 register as shown in Table 4.

(1) Interrupt is generated during clock detector operation, and in cases where clock is not available when clock detector is enabled.

8.3.6 Device Reset Scenarios

Software reset with SW_RESET register bit (in RESET register)
POR from rising edge of NRST signal
Undervoltage lockout (UVLO) reset from VANA supply An SW reset occurs when SW_RESET bit is written 1. The bit is automatically cleared after writing. This event disables all the regulators immediately, resets all the register bits to the default values, and OTP bits are loaded (see Figure 21). I2C interface is not reset during software reset. The host must wait at least 1.2 ms after writing an SW reset until making a new I2C read or write to the device. If VANA supply voltage falls below UVLO threshold level or NRST signal is set low then all the regulators are disabled immediately, and all the register bits are reset to the default values. When the VANA supply voltage rises above UVLO threshold level AND NRST signal rises above threshold level an internal POR occurs. OTP bits are loaded to the registers and a start-up is initiated according to the register settings. The host must wait at least 1.2 ms after POR until reading or writing to I2C interface.

8.3.7 Diagnosis and Protection Features

Information of valid regulator output voltage, which sets interrupt or PGOOD signal;
Warnings for diagnosis, which set interrupt;
Protection events that are disabling the regulators affected; and
Faults that are causing the device to shut down. The LP8756x-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the nINT pin is pulled low. nINT is released again after a clear of flags is complete. The nINT signal stays low until all the pending interrupts are cleared. When a fault is detected, it is indicated by a RESET_REG interrupt flag (in INT2_TOP register) after next start- up.

Table 5. Summary of Interrupt Signals

0.35 V at 1 ms after

Table 5. Summary of Interrupt Signals (continued)

8.3.7.1 Power-Good Information (PGOOD Pin)

all the sources shows active status. The status from all the voltage rails are summarized in Table 6. PGOOD_FLT register. During reading all the PGx_FLT bits are cleared that are not driving the PGOOD inactive. signal follows the status of all the monitored outputs. selected by setting EN_PGFLT_STAT bit to 1 (in PGOOD_CTRL2 register).

Figure 18. PGOOD Block Diagram Table 6. PGOOD Operation

Table 6. PGOOD Operation (continued) Figure 19. PGOOD Waveforms (PGOOD_POL = 0)

8.3.7.2 Warnings for Diagnosis (Interrupt)

8.3.7.2.1 Output Power Limit

BUCKx_STAT register) to see if the regulator is still in peak-current-regulation mode.

bit. The overload situation is shown in Figure 20. Figure 20. Overload Situation

8.3.7.2.2 Thermal Warning

TDIE_WARN_STAT bit (in TOP_STAT register), and the interrupt is cleared by writing 1 to TDIE_WARN bit.

8.3.7.3 Protection (Regulator Disable)

8.3.7.3.1 Short-Circuit and Overload Protection

A short-circuit protection feature protects the LP8756x-Q1 device itself and its external components against short circuit at the output or against overload during start-up. The fault threshold is 350 mV, the protection is triggered, and the regulator is disabled if the output voltage is below the threshold level of 1 ms after the regulator is enabled. In a similar way the overload situation is protected during normal operation. If the voltage on the feedback pin of the regulator falls to less than 0.35 V and stays lower the threshold level for 1 ms, the regulator is disabled. In short-circuit and overload situations the BUCKx_SC_INT (in INT_BUCKx register) and the INT_BUCKx bits (in INT_TOP1 register) are set to 1, the BUCKx_STAT bit (in BUCKx_STAT register) is set to 0, and the nINT signal is pulled low. The host processor clears the interrupt by writing 1 to the BUCKx_SC_INT bit. After clearing the interrupt the regulator makes a new start-up attempt if the regulator is in enabled state.

8.3.7.3.2 Overvoltage Protection

The LP8756x-Q1 device monitors the input voltage from the VANA pin in standby and active operation modes. If the input voltage rises above VANAOVP voltage level, all the regulators are disabled, pulldown resistors discharge the output voltages (if EN_RDISx = 1 in BUCKx_CTRL1 register), GPIOs that are configured to outputs are set to logic low level, nINT signal is pulled low, INT_OVP bit (in INT_TOP1 register) is set to 1, and BUCKx_STAT bits (in BUCK_x_STAT register) are set to 0. The host processor clears the interrupt by writing 1 to the INT_OVP bit. If the input voltage is above the overvoltage detection level the interrupt is not cleared. The host can read the status of the overvoltage from the OVP_STAT bit (in TOP_STAT register). Regulators cannot be enabled as long as the input voltage is above overvoltage detection level or the overvoltage interrupt is pending.

8.3.7.3.3 Thermal Shutdown

The LP8756x-Q1 has an overtemperature protection function that operates to protect the device from short-term misuse and overload conditions. When the junction temperature exceeds around 150°C, the regulators are disabled, the TDIE_SD bit (in INT_TOP1 register) is set to 1, the nINT signal is pulled low, and the device goes to the STANDBY state. The nINT pin is cleared by writing 1h to the TDIE_SD bit. If the temperature is above thermal shutdown level the interrupt is not cleared. The host can read the status of the thermal shutdown from the TDIE_SD_STAT bit (in TOP_STAT register). Regulators cannot be enabled as long as the junction temperature is above thermal shutdown level or the thermal shutdown interrupt is pending.

8.3.7.4 Fault (Power Down)

8.3.7.4.1 Undervoltage Lockout

When the input voltage falls below VANAUVLO at the VANA pin, the buck converters are disabled immediately, and the output capacitors are discharged using the pulldown resistor, and the LP8756x-Q1 device goes to the SHUTDOWN state. When the VANA voltage is greater than the UVLO threshold level and NRST signal is high, the device powers up to STANDBY state. If the reset interrupt is unmasked by default (RESET_REG_MASK = 0 in TOP_MASK2 register) the RESET_REG interrupt (in INT_TOP2 register) indicates that the device has been in SHUTDOWN. The host processor must clear the interrupt by writing 1 to the RESET_REG bit. If the host processor reads the RESET_REG flag after detecting an nINT low signal, it knows that the input supply voltage has been below UVLO level (or the host has requested reset), and the registers are reset to default values.

8.3.8 GPIO Signal Operation

The LP8756x-Q1 device supports up to 3 GPIO signals. The GPIO signals are multiplexed with enable signals. The selection between enable and GPIO function is set with GPIOx_SEL bits in PIN_FUNCTION register. The GPIOs are mapped to EN signals so that:

EN1 is multiplexed with GPIO1
EN2 is multiplexed with GPIO2
EN3 is multiplexed with GPIO3 When the pin is selected for GPIO function, additional bits defines how the GPIO operates:
GPIOx_DIR defines the direction of the GPIO, input or output (GPIO_CONFIG register)
GPIOx_OD defines the type of the output when the GPIO is set to output, either push-pull with VANA level or open-drain (GPIO_CONFIG register) When the GPIOx is defined as output, the logic level of the pin is set by GPIOx_OUT bit (in GPIO_OUT register). When the GPIOx is defined as input, the logic level of the pin can be read from GPIOx_IN bit (in GPIO_IN register). The control of the GPIOs configured to outputs can be included to start-up and shutdown sequences. The GPIO control for a sequence with ENx signal is selected by EN_PIN_CTRL_GPIOx and EN_PIN_SELECT_GPIOx bits (in PIN_FUNCTION register). The delays during start-up and shutdown are set by GPIOx_STARTUP_DELAY[3:0] and GPIOx_SHUTDOWN_DELAY[3:0] bits (in GPIOx_DELAY register) in the same way as control of the regulators. The GPIOx signals have a selectable pulldown resistor. The pulldown resistors are selected by ENx_PD bits (in CONFIG register). NOTE The control of the GPIOx pin cannot be changed from one ENx pin to a different ENx pin because the control is ENx signal edge sensitive. The control from ENx pin to register bit and back to the original ENx pin can be done during operation.

8.3.9 Digital Signal Filtering

The digital signals have a debounce filtering. The signal/supply is sampled with a clock signal and a counter. This results as an accuracy of one clock period for the debounce window.

(1) No glitch filtering, only synchronization. Table 7. Digital Signal Filtering

8.4 Device Functional Modes

8.4.1 Modes of Operation

LP8756x-Q1 device are turned off. enabled. The OTP bits are loaded to registers. interface. The regulators can be enabled if needed. host processor via the system serial interface. The operating modes and transitions between the modes are shown in Figure 21.

Figure 21. Device Operation Modes

8.5 Programming

8.5.1 I2C-Compatible Interface

8.5.1.1 Data Validity

state of the data line can only be changed when clock signal is LOW. Figure 22. Data Validity Diagram

8.5.1.2 Start and Stop Conditions

master always generates the START and STOP conditions. Figure 23. Start and Stop Sequences SDA and SCL signal timing for the I2C-compatible bus.

Figure 24. I2C-Compatible Timing

8.5.1.3 Transferring Data

Each byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. acknowledge after each byte has been received. SDA line is not pulled down. SDA line. The ACK signal and data transfer to the master is disabled at that time. data to write to the selected register. Figure 25. Write Cycle (w = write; SDA = 0), Using Example id = Device Address = 0x60 for LP8756x-Q1

When READ function is to be accomplished, a WRITE function must precede the READ function as shown above. Figure 26. Read Cycle ( r = read; SDA = 1), Using Example id = Device Address = 0x60 for LP8756x-Q1

8.5.1.4 I2C-Compatible Chip Address

After the START condition, the I2C master sends the 7-bit address followed by an eighth bit, read or write (R/W). A. Here device address is 1100000Bin = 60Hex. Figure 27. Example Device Address

8.5.1.5 Auto-Increment Feature

Table 8. Auto-Increment Example

8.6 Register Maps

8.6.1 Register Descriptions

The LP8756x-Q1 is controlled by a set of registers through the I2C-compatible interface. The device registers, their addresses, and their abbreviations are listed in Table 9. A more detailed description is given in the OTP_REV to GPIO_OUT sections. NOTE This register map describes the default values for bits that are not read from OTP memory. The orderable code and the default register bit values are defined in part-number specific Technical Reference Manuals.

Table 9. Summary of LP8756x-Q1 Control Registers

Table 9. Summary of LP8756x-Q1 Control Registers (continued)

8.6.1.1 OTP_REV

Address: 0x01 D7 D6 D5 D4 D3 D2 D1 D0 OTP_ID[7:0] Bits Field Type Default Description 7:0 OTP_ID[7:0] R X Identification code of the OTP EPROM version

8.6.1.2 BUCK0_CTRL1

Address: 0x02 D7 D6 D5 D4 D3 D2 D1 D0 EN_BUCK0 EN_PIN_CTRL BUCK0_EN_PIN_SELECT[1:0] EN_ROOF_FL OOR0 EN_RDIS0 BUCK0_FPWM BUCK0_FPWM _MP Bits Field Type Default Description

7 EN_BUCK0 R/W X This bit enables the BUCK0 regulator

0h = BUCK0 regulator is disabled 1h = BUCK0 regulator is enabled

6 EN_PIN_CTRL0 R/W X This bit enables the EN1, EN2, EN3 pin control for the BUCK0 regulator

0h = Only the EN_BUCK0 bit controls the BUCK0 regulator 1h = EN_BUCK0 bit AND ENx pin control the BUCK0 regulator 5:4 BUCK0_EN_PIN_S ELECT[1:0] R/W X This bit enables the EN1, EN2, EN3 pin control for the BUCK0 regulator 0h = EN_BUCK0 bit AND EN1 pin control BUCK0 1h = EN_BUCK0 bit AND EN2 pin control BUCK0 2h = EN_BUCK0 bit AND EN3 pin control BUCK0 3h = Reserved

3 EN_ROOF_FLOO

R/W 0h This bit enables the roof and floor control of the EN1, EN2, and EN3 pins if the EN_PIN_CTRL0 bit is set to 1h. 0h = Enable and disable (1/0) control 1h = Roof and floor (1/0) control

2 EN_RDIS0 R/W 1h This bit enables the output of the discharge resistor when the BUCK0 regulator is

0h = Discharge resistor disabled 1h = Discharge resistor enabled

1 BUCK0_FPWM R/W X This bit forces the BUCK0 regulator to operate in PWM mode

0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation

0 BUCK0_FPWM_M

P R/W X This bit forces the BUCK0 regulator to operate always in multiphase and forced-PWM operation mode 0h = Automatic phase adding and shedding 1h = Forced to multiphase operation; two phases in the 2-phase configuration, three phases in the 3-phase configuration, and four phases in the 4-phase configuration.

8.6.1.3 BUCK0_CTRL2

Address: 0x03 D7 D6 D5 D4 D3 D2 D1 D0 Reserved ILIM0[2:0] SLEW_RATE0[2:0] Bits Field Type Default Description 7:6 Reserved R/W 0h 5:3 ILIM0[2:0] R/W X This bit sets the switch current limit of the BUCK0 regulator. Can be programmed at any time during operation. 0h = 1.5 A 1h = 2 A 2h = 2.5 A 3h = 3 A 4h = 3.5 A 5h = 4 A 6h = 4.5 A 7h = 5 A 2:0 SLEW_RATE0[2:0] R/W X This bit sets the output voltage slew rate for the BUCK0 regulator (rising and falling edges) 0h = Reserved 1h = Reserved 2h = 10 mV/µs 3h = 7.5 mV/µs 4h = 3.8 mV/µs 5h = 1.9 mV/µs 6h = 0.94 mV/µs 7h = 0.47 mV/µs

8.6.1.4 BUCK1_CTRL1

Address: 0x04 D7 D6 D5 D4 D3 D2 D1 D0 EN_BUCK1 EN_PIN_CTRL BUCK1_EN_PIN_SELECT[1:0] EN_ROOF_FL OOR1 EN_RDIS1 BUCK1_FPWM Reserved Bits Field Type Default Description

7 EN_BUCK1 R/W X This bit enables the BUCK1 regulator

0h = BUCK1 regulator is disabled 1h = BUCK1 regulator is enabled

6 EN_PIN_CTRL1 R/W X This bit enables the EN1, EN2, EN3 pin control for the BUCK1 regulator

0h = Only the EN_BUCK1 bit controls the BUCK1 regulator 1h = EN_BUCK1 bit AND ENx pin control the BUCK1 regulator 5:4 BUCK1_EN_PIN_S ELECT[1:0] R/W X This bit enables the EN1, EN2, EN3 pin control for BUCK1 regulator 0h = EN_BUCK1 bit AND EN1 pin control the BUCK1 regulator 1h = EN_BUCK1 bit AND EN2 pin control the BUCK1 regulator 2h = EN_BUCK1 bit AND EN3 pin control the BUCK1 regulator 3h = Reserved R/W 0h This bit enables the roof and floor control of EN1, EN2, EN3 pin if the EN_PIN_CTRL1 bit is set to 1h. 0h = Enable and disable (1/0) control 1h = Roof and floor (1/0) control 2 EN_RDIS1 R/W 1h This bit enables the output discharge resistor when the BUCK1 regulator is disabled. 0h = Discharge resistor disabled 1h = Discharge resistor enabled 1 BUCK1_FPWM R/W X This bit forces the BUCK1 regulator to operate in PWM mode. 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation

0 Reserved R/W 0h

8.6.1.5 BUCK1_CTRL2

Address: 0x05 D7 D6 D5 D4 D3 D2 D1 D0 Reserved ILIM1[2:0] SLEW_RATE1[2:0] Bits Field Type Default Description 7:6 Reserved R/W 0h 5:3 ILIM1[2:0] R/W X This bit sets the switch current limit of the BUCK1 regulator. Can be programmed at any time during operation. 0h = 1.5 A 1h = 2 A 2h = 2.5 A 3h = 3 A 4h = 3.5 A 5h = 4 A 6h = 4.5 A 7h = 5 A 2:0 SLEW_RATE1[2:0] R/W X This bit sets the output voltage slew rate for the BUCK1 regulator (rising and falling edges) 0h = Reserved 1h = Reserved 2h = 10 mV/µs 3h = 7.5 mV/µs 4h = 3.8 mV/µs 5h = 1.9 mV/µs 6h = 0.94 mV/µs 7h = 0.47 mV/µs

8.6.1.6 BUCK2_CTRL1

Address: 0x06 D7 D6 D5 D4 D3 D2 D1 D0 EN_BUCK2 EN_PIN_CTRL BUCK2_EN_PIN_SELECT[1:0] EN_ROOF_FL OOR2 EN_RDIS2 BUCK2_FPWM BUCK2_FPWM _MP Bits Field Type Default Description 7 EN_BUCK2 R/W X This bit enables the BUCK2 regulator. 0h = BUCK2 regulator is disabled 1h = BUCK2 regulator is enabled 6 EN_PIN_CTRL2 R/W X This bit enables the EN1, EN2, EN3 pin control for the BUCK2 regulator. 0h = Only the EN_BUCK2 bit controls BUCK2 1h = EN_BUCK2 bit AND ENx pin control BUCK2 5:4 BUCK2_EN_PIN_S ELECT[1:0] R/W X This bit enables the EN1, EN2, EN3 pin control for the BUCK2 regulator. 0h = EN_BUCK2 bit AND EN1 pin control the BUCK2 regulator 1h = EN_BUCK2 bit AND EN2 pin control the BUCK2 regulator 2h = EN_BUCK2 bit AND EN3 pin control the BUCK2 regulator 3h = Reserved R/W 0h This bit enables the roof and floor control of EN1, EN2, EN3 pin if the EN_PIN_CTRL2 bit is set to 1h. 0h = Enable and disable (1/0) control 1h = Roof and floor (1/0) control 2 EN_RDIS2 R/W 1h Enable output discharge resistor when BUCK2 is disabled. 0h = Discharge resistor disabled 1h = Discharge resistor enabled 1 BUCK2_FPWM R/W X This bit forces the BUCK2 regulator to operate in PWM mode. 0h = Automatic transitions between PFM and PWM modes (AUTO mode) 1h = Forced to PWM operation

0 BUCK2_FPWM_M

P R/W X This bit forces the BUCK2 regulator to operate always in multiphase and forced-PWM operation mode. 0h = Automatic phase adding and phase shedding 1h = Forced to multiphase operation; two phases in the 2-phase configuration

8.6.1.7 BUCK2_CTRL2

Address: 0x07 D7 D6 D5 D4 D3 D2 D1 D0 Reserved ILIM2[2:0] SLEW_RATE2[2:0] Bits Field Type Default Description 7:6 Reserved R/W 0h 5:3 ILIM2[2:0] R/W X This bit sets the switch current limit of the BUCK2 regulator. Can be programmed at any time during operation. 0h = 1.5 A 1h = 2 A 2h = 2.5 A 3h = 3 A 4h = 3.5 A 5h = 4 A 6h = 4.5 A 7h = 5 A 2:0 SLEW_RATE2[2:0] R/W X This bit sets the output voltage slew rate for the BUCK2 regulator (rising and falling edges). 0h = Reserved 1h = Reserved 2h = 10 mV/µs 3h = 7.5 mV/µs 4h = 3.8 mV/µs 5h = 1.9 mV/µs 6h = 0.94 mV/µs 7h = 0.47 mV/µs

8.6.1.8 BUCK3_CTRL1

Address: 0x08 D7 D6 D5 D4 D3 D2 D1 D0 EN_BUCK3 EN_PIN_CTRL BUCK3_EN_PIN_SELECT[1:0] EN_ROOF_FL OOR3 EN_RDIS3 BUCK3_FPWM Reserved Bits Field Type Default Description 7 EN_BUCK3 R/W X This bit enables the BUCK3 regulator. 0h = BUCK3 regulator is disabled 1h = BUCK3 regulator is enabled 6 EN_PIN_CTRL3 R/W X This bit enables the EN1, EN2, EN3 pin control for the BUCK3 regulator. 0h = Only the EN_BUCK3 bit controls the BUCK3 regulator 1h = EN_BUCK3 bit AND ENx pin control the BUCK3 regulator 5:4 BUCK3_EN_PIN_S ELECT[1:0] R/W X This bit enables the EN1, EN2, EN3 pin control for the BUCK3 regulator. 0h = EN_BUCK3 bit AND EN1 pin control the BUCK3 regulator 1h = EN_BUCK3 bit AND EN2 pin control the BUCK3 regulator 2h = EN_BUCK3 bit AND EN3 pin control the BUCK3 regulator 3h = Reserved R/W 0h This bit enables the roof and floor control of EN1, EN2, EN3 pin if the EN_PIN_CTRL3 bit is set to 1h. 0h = Enable and disable (1/0) control 1h = Roof and floor (1/0) control 2 EN_RDIS3 R/W 1h This bit enables the output discharge resistor when the BUCK3 regulator is disabled. 0h = Discharge resistor disabled 1h = Discharge resistor enabled 1 BUCK3_FPWM R/W X This bit forces the BUCK3 regulator to operate in PWM mode. 0h = Automatic transitions between PFM and PWM modes (AUTO mode) 1h = Forced to PWM operation

8.6.1.9 BUCK3_CTRL2

Address: 0x09 D7 D6 D5 D4 D3 D2 D1 D0 Reserved ILIM3[2:0] SLEW_RATE3[2:0] Bits Field Type Default Description 7:6 Reserved R/W 0h 5:3 ILIM3[2:0] R/W X This bit sets the switch current limit of the BUCK3 regulator. Can be programmed at any time during operation. 0h = 1.5 A 1h = 2 A 2h = 2.5 A 3h = 3 A 4h = 3.5 A 5h = 4 A 6h = 4.5 A 7h = 5 A 2:0 SLEW_RATE3[2:0] R/W X This bit sets the output voltage slew rate for the BUCK3 regulator (rising and falling edges). 0h = Reserved 1h = Reserved 2h = 10 mV/µs 3h = 7.5 mV/µs 4h = 3.8 mV/µs 5h = 1.9 mV/µs 6h = 0.94 mV/µs 7h = 0.47 mV/µs

8.6.1.10 BUCK0_VOUT

Address: 0x0A D7 D6 D5 D4 D3 D2 D1 D0 BUCK0_VSET[7:0] Bits Field Type Default Description 7:0 BUCK0_VSET[7:0] R/W X This bit sets the output voltage of the BUCK0 regulator. Reserved, do not use 0h to 9h 0.6 V to 0.73 V, 10-mV steps Ah = 0.6 V ... 17h = 0.73 V 0.73 V to 1.4 V, 5-mV steps 18h = 0.735 V ... 9Dh = 1.4 V 1.4 V to 3.36 V, 20-mV steps 9Eh = 1.42 V ... FFh = 3.36 V

8.6.1.11 BUCK0_FLOOR_VOUT

Address: 0x0B D7 D6 D5 D4 D3 D2 D1 D0 BUCK0_FLOOR_VSET[7:0] Bits Field Type Default Description 7:0 BUCK0_FLOOR_V SET[7:0] R/W 0h This bit sets the output voltage of the BUCK0 regulator when the floor state is used. Reserved, do not use 0h to 9h 0.6 V to 0.73 V, 10-mV steps Ah = 0.6 V ... 17h = 0.73 V 0.73 V to 1.4 V, 5-mV steps 18h = 0.735 V ... 9Dh = 1.4 V 1.4 V to 3.36 V, 20-mV steps 9Eh = 1.42 V ... FFh = 3.36 V

8.6.1.12 BUCK1_VOUT

Address: 0x0C D7 D6 D5 D4 D3 D2 D1 D0 BUCK1_VSET[7:0]

LP87562-Q1, LP87563-Q1, LP87564-Q1, LP87565-Q1 SNVSB22 –MARCH 2018 www.ti.com Product Folder Links: LP87561-Q1 LP87562-Q1 LP87563-Q1 LP87564-Q1 LP87565-Q1 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Bits Field Type Default Description 7:0 BUCK1_VSET[7:0] R/W X This bit sets the output voltage of the BUCK1 regulator. Reserved, do not use 0h to 9h 0.6 V - 0.73 V, 10-mV steps Ah = 0.6 V ... 17h = 0.73 V 0.73 V - 1.4 V, 5-mV steps 18h = 0.735 V ... 9Dh = 1.4 V 1.4 V - 3.36 V, 20-mV steps 9Eh = 1.42 V ... FFh = 3.36 V

8.6.1.13 BUCK1_FLOOR_VOUT

Address: 0x0D D7 D6 D5 D4 D3 D2 D1 D0 BUCK1_FLOOR_VSET[7:0] Bits Field Type Default Description 7:0 BUCK1_FLOOR_V SET[7:0] R/W 0h This bit sets the output voltage of the BUCK1 regulator when the floor state is used. Reserved, do not use 0h to 9h 0.6 V to 0.73 V, 10-mV steps Ah = 0.6 V ... 17h = 0.73 V 0.73 V to 1.4 V, 5-mV steps 18h = 0.735 V ... 9Dh = 1.4 V 1.4 V to 3.36 V, 20-mV steps 9Eh = 1.42 V ... FFh = 3.36 V

8.6.1.14 BUCK2_VOUT

Address: 0x0E D7 D6 D5 D4 D3 D2 D1 D0 BUCK2_VSET[7:0] Bits Field Type Default Description 7:0 BUCK2_VSET[7:0] R/W X This bit sets the output voltage of the BUCK2 regulator. Reserved, do not use 0h to 9h 0.6 V to 0.73 V, 10-mV steps Ah = 0.6V ... 17h = 0.73 V 0.73 V to 1.4 V, 5-mV steps 18h = 0.735 V ... 9Dh = 1.4 V 1.4 V to 3.36 V, 20-mV steps 9Eh = 1.42 V ... FFh = 3.36 V

8.6.1.15 BUCK2_FLOOR_VOUT

Address: 0x0F D7 D6 D5 D4 D3 D2 D1 D0 BUCK2_FLOOR_VSET[7:0] Bits Field Type Default Description 7:0 BUCK2_FLOOR_V SET[7:0] R/W 0h This bit sets the output voltage of the BUCK2 regulator when the floor state is used. Reserved, do not use 0h to 9h 0.6 V to 0.73 V, 10-mV steps Ah = 0.6 V ... 17h = 0.73 V 0.73 V to 1.4 V, 5-mV steps 18h = 0.735 V ... 9Dh = 1.4 V 1.4 V to 3.36 V, 20-mV steps 9Eh = 1.42 V ... FFh = 3.36 V

8.6.1.16 BUCK3_VOUT

Address: 0x10 D7 D6 D5 D4 D3 D2 D1 D0 BUCK3_VSET[7:0] Bits Field Type Default Description 7:0 BUCK3_VSET[7:0] R/W X This bit sets the output voltage of the BUCK3 regulator. Reserved, do not use 0h to 9h 0.6 V to 0.73 V, 10-mV steps Ah = 0.6 V ... 17h = 0.73 V 0.73 V to 1.4 V, 5-mV steps 18h = 0.735 V ... 9Dh = 1.4 V 1.4 V to 3.36 V, 20-mV steps 9Eh = 1.42 V ... FFh = 3.36 V

8.6.1.17 BUCK3_FLOOR_VOUT

Address: 0x11 D7 D6 D5 D4 D3 D2 D1 D0 BUCK3_FLOOR_VSET[7:0]

LP87562-Q1, LP87563-Q1, LP87564-Q1, LP87565-Q1 SNVSB22 –MARCH 2018 www.ti.com Product Folder Links: LP87561-Q1 LP87562-Q1 LP87563-Q1 LP87564-Q1 LP87565-Q1 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Bits Field Type Default Description 7:0 BUCK3_FLOOR_V SET[7:0] R/W 0h This bit sets the output voltage of the BUCK3 regulator when the floor state is used. Reserved, do not use 0h to 9h 0.6 V to 0.73 V, 10-mV steps Ah = 0.6 V ... 17h = 0.73 V 0.73 V to 1.4 V, 5-mV steps 18h = 0.735 V ... 9Dh = 1.4 V 1.4 V to 3.36 V, 20-mV steps 9Eh = 1.42 V ... FFh = 3.36 V

8.6.1.18 BUCK0_DELAY

Address: 0x12 D7 D6 D5 D4 D3 D2 D1 D0 BUCK0_SHUTDOWN_DELAY[3:0] BUCK0_STARTUP_DELAY[3:0] Bits Field Type Default Description 7:4 BUCK0_SHUTDO WN_DELAY[3:0] R/W X Shutdown delay of the BUCK0 regulator from the falling edge of the ENx signal (the DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown Delays table. 0h = 0 ms 1h = 1 ms Fh = 15 ms 3:0 BUCK0_STARTUP _DELAY[3:0] R/W X Start-up delay the of the BUCK0 regulator from the rising edge of the ENx signal (the DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown Delays table. 0h = 0 ms 1h = 1 ms Fh = 15 ms

8.6.1.19 BUCK1_DELAY

Address: 0x13 D7 D6 D5 D4 D3 D2 D1 D0 BUCK1_SHUTDOWN_DELAY[3:0] BUCK1_STARTUP_DELAY[3:0] Bits Field Type Default Description 7:4 BUCK1_SHUTDO WN_DELAY[3:0] R/W X Shutdown delay of the BUCK1 regulator from the falling edge of the ENx signal (the DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown Delays table. 0h = 0 ms 1h = 1 ms Fh = 15 ms 3:0 BUCK1_STARTUP _DELAY[3:0] R/W X start-up delay of the BUCK1 regulator from the rising edge of the ENx signal (the DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown Delays table. 0h = 0 ms 1h = 1 ms Fh = 15 ms

8.6.1.20 BUCK2_DELAY

Address: 0x14 D7 D6 D5 D4 D3 D2 D1 D0 BUCK2_SHUTDOWN_DELAY[3:0] BUCK2_STARTUP_DELAY[3:0] Bits Field Type Default Description 7:4 BUCK2_SHUTDO WN_DELAY[3:0] R/W X Shutdown delay of the BUCK2 regulator from the falling edge of the ENx signal (the DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown Delays table. 0h = 0 ms 1h = 1 ms ... Fh = 15 ms (Default from OTP memory) 3:0 BUCK2_STARTUP _DELAY[3:0] R/W X start-up delay of the BUCK2 regulator from the rising edge of the ENx signal (the DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown Delays table. 0h = 0 ms 1h = 1 ms Fh = 15 ms

8.6.1.21 BUCK3_DELAY

Address: 0x15 D7 D6 D5 D4 D3 D2 D1 D0 BUCK3_SHUTDOWN_DELAY[3:0] BUCK3_STARTUP_DELAY[3:0] Bits Field Type Default Description 7:4 BUCK3_SHUTDO WN_DELAY[3:0] R/W X Shutdown delay of the BUCK3 regulator from the falling edge of the ENx signal (the DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown Delays table. 0h = 0 ms 1h = 1 ms Fh = 15 ms 3:0 BUCK3_STARTUP _DELAY[3:0] R/W X Startup delay of the BUCK3 regulator from the rising edge of the ENx signal (the DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown Delays table. 0h = 0 ms 1h = 1 ms Fh = 15 ms

8.6.1.22 GPIO2_DELAY

Address: 0x16 D7 D6 D5 D4 D3 D2 D1 D0 GPIO2_SHUTDOWN_DELAY[3:0] GPIO2_STARTUP_DELAY[3:0] Bits Field Type Default Description 7:4 GPIO2_SHUTDOW N_DELAY[3:0] R/W X Delay for the GPIO2 falling edge from the falling edge of the ENx signal (the DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown Delays table. 0h = 0 ms 1h = 1 ms Fh = 15 ms 3:0 GPIO2_STARTUP _DELAY[3:0] R/W X Delay for the GPIO2 rising edge from the rising edge of the ENx signal (the DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown Delays table. 0h = 0 ms 1h = 1 ms Fh = 15 ms

8.6.1.23 GPIO3_DELAY

Address: 0x17 D7 D6 D5 D4 D3 D2 D1 D0 GPIO3_SHUTDOWN_DELAY[3:0] GPIO3_STARTUP_DELAY[3:0] Bits Field Type Default Description 7:4 GPIO3_SHUTDOW N_DELAY[3:0] R/W X Delay for the GPIO3 falling edge from the falling edge of the ENx signal (the DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown Delays table. 0h = 0 ms 1h = 1 ms Fh = 15 ms

LP87562-Q1, LP87563-Q1, LP87564-Q1, LP87565-Q1 www.ti.com SNVSB22 –MARCH 2018 Product Folder Links: LP87561-Q1 LP87562-Q1 LP87563-Q1 LP87564-Q1 LP87565-Q1 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Bits Field Type Default Description 3:0 GPIO3_STARTUP _DELAY[3:0] R/W X Delay for GPIO3 rising edge from rising edge of ENx signal (the DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown Delays table. 0h = 0 ms 1h = 1 ms . Fh = 15 ms

8.6.1.24 RESET

Address: 0x18 D7 D6 D5 D4 D3 D2 D1 D0 Reserved SW_RESET Bits Field Type Default Description 7:1 Reserved R/W 0h 0 SW_RESET R/W 0h Software commanded reset. When this bit is written to 1h, the registers are reset to the default values, OTP memory is read, and the I2C interface is reset. The bit is automatically cleared.

8.6.1.25 CONFIG

Address: 0x19 D7 D6 D5 D4 D3 D2 D1 D0 DOUBLE_DEL AY CLKIN_PD Reserved EN3_PD TDIE_WARN_ LEVEL EN2_PD EN1_PD Reserved Bits Field Type Default Description

7 DOUBLE_DELAY R/W X Start-up and shutdown delays from the ENx signals

0h = 0 ms to 15 ms with 1-ms steps 1h = 0 ms to 30 ms with 2-ms steps 6 CLKIN_PD R/W X This bit selects the pulldown resistor on the CLKIN input pin. 0h = Pulldown resistor is disabled 1h = Pulldown resistor is enabled

5 Reserved R/W 0h

4 EN3_PD R/W X This bit selects the pulldown resistor on the EN3 (GPIO3) input pin. 0h = Pulldown resistor is disabled 1h = Pulldown resistor is enabled

3 TDIE_WARN_LEV

R/W X Thermal warning threshold level 0h = 125°C 1h = 137°C 2 EN2_PD R/W X This bit selects the pulldown resistor on the EN2 (GPIO2) input pin. 0h = Pulldown resistor is disabled 1h = Pulldown resistor is enabled 1 EN1_PD R/W X This bit selects the pulldown resistor on the EN1 (GPIO1) input pin. 0h = Pulldown resistor is disabled 1h = Pulldown resistor is enabled

8.6.1.26 INT_TOP1

Address: 0x1A D7 D6 D5 D4 D3 D2 D1 D0 Reserved INT_BUCK23 INT_BUCK01 NO_SYNC_CL K TDIE_SD TDIE_WARN INT_OVP I_LOAD_ READY

7 Reserved R/W 0h

6 INT_BUCK23 R 0h Interrupt indicating that the output of the BUCK3 regulator,BUCK2 regulator, or both

regulators has a pending interrupt. The reason for the interrupt is indicated in the INT_BUCK_2_3 register. This bit is cleared automatically when the INT_BUCK_2_3 register is cleared to 0x00.

5 INT_BUCK01 R 0h Interrupt indicating that the output of the BUCK1 regulator, BUCK0 regulator, or both

regulators has a pending interrupt. The reason for the interrupt is indicated in the INT_BUCK_0_1 register. This bit is cleared automatically when the INT_BUCK_0_1 register is cleared to 0x00. 4 NO_SYNC_CLK R/W1C 0h Latched status bit indicating that the external clock is not valid. Write this bit to 1h to clear the interrupt.

3 TDIE_SD R/W1C 0h Latched status bit indicating that the die junction temperature is greater than the

thermal shutdown level. The regulators are disabled if previously enabled. The regulators cannot be enabled if this bit is active. The actual status of the thermal warning condition is indicated by the TDIE_SD_STAT bit in the TOP_STAT register. Write this bit to 1h to clear the interrupt. 2 TDIE_WARN R/W1C 0h Latched status bit indicating that the die junction temperature is greater than the thermal warning level. The actual status of the thermal warning condition is indicated by the TDIE_WARN_STAT bit in the TOP_STAT register. Write this bit to 1h to clear the interrupt. 1 INT_OVP R/W1C 0h Latched status bit indicating that the input voltage is greater than the overvoltage- detection level. The actual status of the overvoltage condition is indicated by the OVP_STAT bit in the OP_STAT register. Write this bit to 1h to clear the interrupt. 0 I_LOAD_READY R/W1C 0h Latched status bit indicating that the load-current measurement result is available in the I_LOAD_1 and I_LOAD_2 registers. Write this bit to 1h to clear the interrupt.

8.6.1.27 INT_TOP2

Address: 0x1B D7 D6 D5 D4 D3 D2 D1 D0 Reserved RESET_REG Bits Field Type Default Description 7:1 Reserved R/W 0h 0 RESET_REG R/W1C 0h Latched status bit indicating that either start-up (NRST rising edge) is done, VANA supply voltage is less than the undervoltage threshold level, or the host has requested a reset (the SW_RESET bit in the RESET register). The regulators are disabled, the registers are reset to default values, and the normal start-up procedure is done. Write this bit to 1h to clear the interrupt.

8.6.1.28 INT_BUCK_0_1

Address: 0x1C D7 D6 D5 D4 D3 D2 D1 D0 Reserved BUCK1_PG _INT BUCK1_SC _INT BUCK1_ILIM _INT Reserved BUCK0_PG _INT BUCK0_SC _INT BUCK0_ILIM _INT Bits Field Type Default Description 6 BUCK1_PG_INT R/W1C 0h Latched status bit indicating that the BUCK1 output voltage reached the power-good- threshold level. Write this bit to 1h to clear. 5 BUCK1_SC_INT R/W1C 0h Latched status bit indicating that the BUCK1 output voltage has fallen to less than the 0.35-V level during operation or the BUCK1 output did not reach the 0.35-V level in 1 ms from enable. Write this bit to 1h to clear.

LP87562-Q1, LP87563-Q1, LP87564-Q1, LP87565-Q1 www.ti.com SNVSB22 –MARCH 2018 Product Folder Links: LP87561-Q1 LP87562-Q1 LP87563-Q1 LP87564-Q1 LP87565-Q1 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Bits Field Type Default Description 4 BUCK1_ILIM_INT R/W1C 0h Latched status bit indicating that output current limit is active. Write this bit to 1h to clear.

3 Reserved R/W 0h

2 BUCK0_PG_INT R/W1C 0h Latched status bit indicating that the BUCK0 output voltage reached power-good-

threshold level. Write this bit to 1h to clear. 1 BUCK0_SC_INT R/W1C 0h Latched status bit indicating that the BUCK0 output voltage has fallen to less than the 0.35-V level during operation or the BUCK0 output did not reach the 0.35-V level in 1 ms from enable. Write this bit to 1h to clear. 0 BUCK0_ILIM_INT R/W1C 0h Latched status bit indicating that output current limit is active. Write this bit to 1h to clear.

8.6.1.29 INT_BUCK_2_3

Address: 0x1D D7 D6 D5 D4 D3 D2 D1 D0 Reserved BUCK3_PG _INT BUCK3_SC _INT BUCK3_ILIM _INT Reserved BUCK2_PG _INT BUCK2_SC _INT BUCK2_ILIM _INT Bits Field Type Default Description 6 BUCK3_PG_INT R/W1C 0h Latched status bit indicating that the BUCK3 output voltage reached the power-good- threshold level. Write this bit to 1h to clear. 5 BUCK3_SC_INT R/W1C 0h Latched status bit indicating that the BUCK3 output voltage has fallen to less than the 0.35-V level during operation or the BUCK3 output did not reach the 0.35-V level in 1 ms from enable. Write this bit to 1h to clear. 4 BUCK3_ILIM_INT R/W1C 0h Latched status bit indicating that the output current limit is active. Write this bit to 1h to clear. 2 BUCK2_PG_INT R/W1C 0h Latched status bit indicating that the BUCK2 output voltage reached the power-good- threshold level. Write this bit to 1h to clear. 1 BUCK2_SC_INT R/W1C 0h Latched status bit indicating that the BUCK2 output voltage has fallen to less than the 0.35-V level during operation or the BUCK2 output did not reach the 0.35-V level in 1 ms from enable. Write this bit to 1h to clear. 0 BUCK2_ILIM_INT R/W1C 0h Latched status bit indicating that the output current limit is active. Write this bit to 1h to clear.

8.6.1.30 TOP_STAT

Address: 0x1E D7 D6 D5 D4 D3 D2 D1 D0 Reserved SYNC_CLK _STAT TDIE_SD _STAT TDIE_WARN _STAT OVP_STAT Reserved Bits Field Type Default Description 7:5 Reserved R 0h 4 SYNC_CLK_STAT R 0h Status bit indicating the status of the external clock (CLKIN). 0h = External clock frequency is valid 1h = External clock frequency is not valid 3 TDIE_SD_STAT R 0h Status bit indicating the status of the thermal shutdown condition. 0h = Die temperature is less than the thermal shutdown level 1h = Die temperature is greater than the thermal shutdown level

2 TDIE_WARN_STA

T R 0h Status bit indicating the status of thermal warning condition. 0h = Die temperature is less than the thermal warning level 1h = Die temperature is greater than the thermal warning level 1 OVP_STAT R 0h Status bit indicating the status of input overvoltage monitoring. 0h = Input voltage is less than the overvoltage threshold level 1h = Input voltage is greater than the overvoltage threshold level

0 Reserved R 0h

8.6.1.31 BUCK_0_1_STAT

Address: 0x1F D7 D6 D5 D4 D3 D2 D1 D0 BUCK1_STAT BUCK1_PG _STAT Reserved BUCK1_ILIM _STAT BUCK0_STAT BUCK0_PG _STAT Reserved BUCK0_ILIM _STAT Bits Field Type Default Description 7 BUCK1_STAT R 0 Status bit indicating the enable or disable status of the BUCK1 regulator. 0h = BUCK1 regulator is disabled 1h = BUCK1 regulator is enabled 6 BUCK1_PG_STAT R 0 Status bit indicating the validity of the BUCK1 output voltage (raw status). 0h = BUCK1 output is less than the power-good-threshold level 1h = BUCK1 output is greater than the power-good-threshold level

5 Reserved R 0

4 BUCK1_ILIM_STA

T R 0 Status bit indicating the BUCK1 current limit status (raw status). 0h = BUCK1 output current is less than the current limit level 1h = BUCK1 output current limit is active 3 BUCK0_STAT R 0 Status bit indicating the enable or disable status of the BUCK0 regulator. 0h = BUCK0 regulator is disabled 1h = BUCK0 regulator is enabled 2 BUCK0_PG_STAT R 0 Status bit indicating the validity of the BUCK0 output voltage (raw status). 0h = BUCK0 output is less than the power-good-threshold level 1h = BUCK0 output is greater than the power-good-threshold level

1 Reserved R 0

0 BUCK0_ILIM_STA

T R 0 Status bit indicating the BUCK0 current limit status (raw status). 0h = BUCK0 output current is less than the current limit level 1h = BUCK0 output current limit is active

8.6.1.32 BUCK_2_3_STAT

Address: 0x20 D7 D6 D5 D4 D3 D2 D1 D0 BUCK3_STAT BUCK3_PG _STAT Reserved BUCK3_ILIM _STAT BUCK2_STAT BUCK2_PG _STAT Reserved BUCK2_ILIM _STAT Bits Field Type Default Description 7 BUCK3_STAT R 0 Status bit indicating the enable or disable status of the BUCK3 regulator. 0h = BUCK3 regulator is disabled 1h = BUCK3 regulator is enabled 6 BUCK3_PG_STAT R 0 Status bit indicating the validity of the BUCK3 output voltage (raw status). 0h = BUCK3 output is less than the power-good-threshold level 1h = BUCK3 output is greater than the power-good-threshold level

4 BUCK3_ILIM_STA

T R 0 Status bit indicating the BUCK3 current limit status (raw status). 0h = BUCK3 output current is less than the current limit level 1h = BUCK3 output current limit is active 3 BUCK2_STAT R 0 Status bit indicating the enable or disable status of the BUCK2 regulator. 0h = BUCK2 regulator is disabled 1h = BUCK2 regulator is enabled

2 BUCK2_PG_STAT R 0 Status bit indicating the validity of the BUCK2 output voltage (raw status)

0h = BUCK2 output is less than the power-good-threshold level 1h = BUCK2 output is greater than the power-good-threshold level

0 BUCK2_ILIM_STA

T R 0 Status bit indicating the BUCK2 current limit status (raw status). 0h = BUCK2 output current is less than the current limit level 1h = BUCK2 output current limit is active

8.6.1.33 TOP_MASK1

Address: 0x21 D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved SYNC_CLK _MASK Reserved TDIE_WARN _MASK Reserved I_LOAD_ READY_MASK Bits Field Type Default Description

7 Reserved R/W 1h

6:5 Reserved R/W 0h

4 SYNC_CLK_MASK R/W X Masking for the external clock detection interrupt (the NO_SYNC_CLK bit in the

INT_TOP1 register) 0h = Interrupt generated 1h = Interrupt not generated

2 TDIE_WARN_MAS

K R/W X Masking for the thermal warning interrupt (the TDIE_WARN bit in the INT_TOP1 register) This bit does not affect TDIE_WARN_STAT status bit in the TOP_STAT register. 0h = Interrupt generated 1h = Interrupt not generated

1 Reserved R/W 0

0 I_LOAD_READY_

R/W X Masking for the load-current measurement-ready interrupt (the I_LOAD_READY bit in the INT_TOP register). 0h = Interrupt generated 1h = Interrupt not generated

8.6.1.34 TOP_MASK2

Address: 0x22 D7 D6 D5 D4 D3 D2 D1 D0 Reserved RESET_REG _MASK Bits Field Type Default Description 7:1 Reserved R/W 0h

0 RESET_REG_MAS

K R/W X Masking for the register reset interrupt (the RESET_REG bit in the INT_TOP2 register) 0h = Interrupt generated 1h = Interrupt not generated

8.6.1.35 BUCK_0_1_MASK

Address: 0x23 D7 D6 D5 D4 D3 D2 D1 D0 Reserved BUCK1_PG _MASK Reserved BUCK1_ILIM _MASK Reserved BUCK0_PG _MASK Reserved BUCK0_ILIM _MASK

6 BUCK1_PG_MASK R/W X Masking for the BUCK1 power-good interrupt (the BUCK1_PG_INT bit in the

INT_BUCK_0_1 register) This bit does not affect BUCK1_PG_STAT status bit in BUCK_0_1_STAT register. 0h = Interrupt generated 1h = Interrupt not generated

5 Reserved R 0h

4 BUCK1_ILIM_MAS

K R/W X Masking for the BUCK1 current-limit-detection interrupt (the BUCK1_ILIM_INT bit in the INT_BUCK_0_1 register) This bit does not affect the BUCK1_ILIM_STAT status bit in the BUCK_0_1_STAT register. 0h = Interrupt generated 1h = Interrupt not generated

2 BUCK0_PG_MASK R/W X Masking for the BUCK0 power-good interrupt (the BUCK0_PG_INT bit in the

INT_BUCK_0_1 register) This bit does not affect the BUCK0_PG_STAT status bit in the BUCK_0_1_STAT register. 0h = Interrupt generated 1h = Interrupt not generated

1 Reserved R 0h

0 BUCK0_ILIM_MAS

K R/W X Masking for the BUCK0 current-limit-detection interrupt (the BUCK0_ILIM_INT bit in the INT_BUCK_0_1 register) This bit does not affect the BUCK0_ILIM_STAT status bit in the BUCK_0_1_STAT register. 0h = Interrupt generated 1h = Interrupt not generated

8.6.1.36 BUCK_2_3_MASK

Address: 0x24 D7 D6 D5 D4 D3 D2 D1 D0 Reserved BUCK3_PG _MASK Reserved BUCK3_ILIM _MASK Reserved BUCK2_PG _MASK Reserved BUCK2_ILIM _MASK Bits Field Type Default Description

6 BUCK3_PG_MASK R/W X Masking for the BUCK3 power-good interrupt (the BUCK3_PG_INT bit in the

INT_BUCK_2_3 register) This bit does not affect the BUCK3_PG_STAT status bit in the BUCK_2_3_STAT register. 0h = Interrupt generated 1h = Interrupt not generated

4 BUCK3_ILIM_MAS

K R/W X Masking for the BUCK3 current-limit-detection interrupt (the BUCK3_ILIM_INT bit in the INT_BUCK_2_3 register) This bit does not affect the BUCK3_ILIM_STAT status bit in the BUCK_2_3_STAT register. 0h = Interrupt generated 1h = Interrupt not generated

2 BUCK2_PG_MASK R/W X Masking for the BUCK2 power-good interrupt (the BUCK2_PG_INT bit in the

INT_BUCK_2_3 register) This bit does not affect the BUCK2_PG_STAT status bit in the BUCK_2_3_STAT register. 0h = Interrupt generated 1h = Interrupt not generated

0 BUCK2_ILIM_MAS

K R/W X Masking for the BUCK2 current limit-detection interrupt (the BUCK2_ILIM_INT bit in the INT_BUCK_2_3 register) This bit does not affect the BUCK2_ILIM_STAT status bit in the BUCK_2_3_STAT register. 0h = Interrupt generated 1h = Interrupt not generated

8.6.1.37 SEL_I_LOAD

Address: 0x25 D7 D6 D5 D4 D3 D2 D1 D0 Reserved LOAD_CURRENT_BUCK _SELECT[1:0] Bits Field Type Default Description 7:2 Reserved R/W 0h 1:0 LOAD_CURRENT_ BUCK_SELECT[1: R/W 0h This bit starts the current measurement on the selected regulator. One measurement is started when the register is written. If the selected buck is a master, the measurement result is the sum of the current of both the master and slave bucks. If the selected buck is a slave, the measurement result is the current of the selected slave bucks. 0h = BUCK0 1h = BUCK1 2h = BUCK2 3h = BUCK3

8.6.1.38 I_LOAD_2

Address: 0x26 D7 D6 D5 D4 D3 D2 D1 D0 Reserved BUCK_LOAD_CURRENT[9:8] Bits Field Type Default Description 7:2 Reserved R 0h 1:0 BUCK_LOAD_CUR RENT[9:8] R 0h This register describes the three MSB bits of the average load current on the selected regulator with a resolution of 20 mA per LSB and maximum code corresponding to a 20.47-A current.

8.6.1.39 I_LOAD_1

Address: 0x27 D7 D6 D5 D4 D3 D2 D1 D0 BUCK_LOAD_CURRENT[7:0] Bits Field Type Default Description 7:0 BUCK_LOAD_CUR RENT[7:0] R 0x00 This register describes the eight LSB bits of the average load current on the selected regulator with a resolution of 20 mA per LSB and maximum code corresponding to a 20.47-A current.

8.6.1.40 PGOOD_CTRL1

Address: 0x28 D7 D6 D5 D4 D3 D2 D1 D0 PG3_SEL[1:0] PG2_SEL[1:0] PG1_SEL[1:0] PG0_SEL[1:0] Bits Field Type Default Description 7:6 PG3_SEL[1:0] R/W X PGOOD signal source control from the BUCK3 regulator 0h = Masked 1h = Power-good-threshold voltage 2h = Reserved, do not use 3h = Power-good-threshold voltage AND current limit 5:4 PG2_SEL[1:0] R/W X PGOOD signal source control from the BUCK2 regulator 0h = Masked 1h = Power-good-threshold voltage 2h = Reserved, do not use 3h = Power-good threshold voltage AND current limit 3:2 PG1_SEL[1:0] R/W X PGOOD signal source control from the BUCK1 regulator 0h = Masked 1h = Power-good-threshold voltage 2h = Reserved, do not use 3h = Power-good-threshold voltage AND current limit 1:0 PG0_SEL[1:0] R/W X PGOOD signal source control from the BUCK0 regulator 0h = Masked 1h = Power-good-threshold voltage 2h = Reserved, do not use 3h = Power-good-threshold voltage AND current limit

8.6.1.41 PGOOD_CTRL2

Address: 0x29 D7 D6 D5 D4 D3 D2 D1 D0 HALF_DELAY EN_PG0 _NINT PGOOD_SET _DELAY EN_PGFLT _STAT Reserved PGOOD_ WINDOW PGOOD_OD PGOOD_POL

LP87562-Q1, LP87563-Q1, LP87564-Q1, LP87565-Q1 www.ti.com SNVSB22 –MARCH 2018 Product Folder Links: LP87561-Q1 LP87562-Q1 LP87563-Q1 LP87564-Q1 LP87565-Q1 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Bits Field Type Default Description 7 HALF_DELAY R/W X This bit elects the time step for the start-up and shutdown delays. 0h = Start-up and shutdown delays have 0.5-ms or 1-ms time steps, based on the DOUBLE_DELAY bit in the CONFIG register. 1h = Start-up and shutdown delays have 0.32-ms or 0.64-ms time steps, based on the DOUBLE_DELAY bit in the CONFIG register.

6 EN_PG0_NINT R/W X This bit combines theBUCK0 PGOOD signal with the nINT signal

0h = BUCK0 PGOOD signal not included with the nINT signal 1h = BUCK0 PGOOD signal included with the nINT signal. If the nINT OR the BUCK0 PGOOD signal is low then the nINT signal is low.

5 PGOOD_SET_DEL

R/W X Debounce time of the output voltage monitoring for the PGOOD signal (only when the PGOOD signal goes valid) 0h = 4-10 µs 1h = 11 ms

4 EN_PGFLT_STAT R/W X Operation mode for PGOOD signal

0h = Indicates live status of monitored voltage outputs 1h = Indicates status of the PGOOD_FLT register, inactive if at least one of the PGx_FLT bit is inactive

2 PGOOD_WINDOW R/W X Voltage monitoring method for the PGOOD signal

0h = Only undervoltage monitoring 1h = Overvoltage and undervoltage monitoring

1 PGOOD_OD R/W X PGOOD signal type

0h = Push-pull output (VANA level) 1h = Open-drain output

0 PGOOD_POL R/W X PGOOD signal polarity

0h = PGOOD signal high when monitored outputs are valid 1h = PGOOD signal low when monitored outputs are valid

8.6.1.42 PGOOD_FLT

Address: 0x2A D7 D6 D5 D4 D3 D2 D1 D0 Reserved PG3_FLT PG2_FLT PG1_FLT PG0_FLT Bits Field Type Default Description 7:4 Reserved R/W 0x0

3 PG3_FLT R 0 Source for the PGOOD inactive signal

0h = BUCK3 has not set the PGOOD signal inactive. 1h = BUCK3 has set the PGOOD signal inactive. This bit can be cleared by reading this register when the BUCK3 output is valid.

2 PG2_FLT R 0 Source for the PGOOD inactive signal

0h = BUCK2 has not set the PGOOD signal inactive. 1h = BUCK2 has set the PGOOD signal inactive. This bit can be cleared by reading this register when the BUCK2 output is valid.

1 PG1_FLT R 0 Source for the PGOOD inactive signal

0h = BUCK1 has not set the PGOOD signal inactive. 1h = BUCK1 has set the PGOOD signal inactive. This bit can be cleared by reading this register when the BUCK1 output is valid.

0 PG0_FLT R 0 Source for the PGOOD inactive signal

0h = BUCK0 has not set the PGOOD signal inactive. 1h = BUCK0 has set the PGOOD signal inactive. This bit can be cleared by reading this register when the BUCK0 output is valid.

8.6.1.43 PLL_CTRL

Address: 0x2B D7 D6 D5 D4 D3 D2 D1 D0 PLL_MODE[1:0] Reserved EXT_CLK_FREQ[4:0]

LP87562-Q1, LP87563-Q1, LP87564-Q1, LP87565-Q1 SNVSB22 –MARCH 2018 www.ti.com Product Folder Links: LP87561-Q1 LP87562-Q1 LP87563-Q1 LP87564-Q1 LP87565-Q1 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Bits Field Type Default Description 7:6 PLL_MODE[1:0] R/W X This bit selects the external clock and PLL operation. 0h = Forced to internal RC oscillator (PLL is disabled). 1h = PLL is enabled in the STANDBY and ACTIVE states. Automatic external clock use when available, interrupt generated if external clock appears or disappears. 2h = PLL is enabled only in the ACTIVE state. Automatic external clock use when available, interrupt generated if external clock appears or disappears. 3h = Reserved

5 Reserved R/W 0

4:0 EXT_CLK_FREQ[4 :0] R/W X Frequency of the external clock (CLKIN). For the input clock frequency tolerance see the Electrical Characteristics table. Settings 18h through 1Fh are reserved and must not be used. 0x00h = 1 MHz 0x01h = 2 MHz 2h = 3 MHz 16h = 23 MHz 17h = 24 MHz .

8.6.1.44 PIN_FUNCTION

Address: 0x2C D7 D6 D5 D4 D3 D2 D1 D0 EN_SPREAD_ SPEC EN_PIN_CTRL _GPIO3 EN_PIN_SELE CT_GPIO3 EN_PIN_CTRL _GPIO2 EN_PIN_SELE CT_GPIO2 GPIO3_SEL GPIO2_SEL GPIO1_SEL Bits Field Type Default Description

7 EN_SPREAD_SPE

C R/W X This bit enables the spread-spectrum feature. 0h = Disabled 1h = Enabled

6 EN_PIN_CTRL_GP

R/W X This bit enables EN1 and EN2 pin control for GPIO3 (the GPIO3_SEL bit is set to 1h AND the GPIO3_DIR bit is set to 1h). 0h = Only GPIO3_OUT bit controls GPIO3 1h = GPIO3_OUT bit AND ENx pin control GPIO3

5 EN_PIN_SELECT_

R/W X This bit enables EN1 and EN2 pin control for GPIO3. 0h = GPIO3_SEL bit AND EN1 pin control GPIO3 1h = GPIO3_SEL bit AND EN2 pin control GPIO3

4 EN_PIN_CTRL_GP

R/W X This bit enables EN1 and EN3 pin control for GPIO2 (the GPIO2_SEL bit is set to 1h AND the GPIO2_DIR bit is set to 1h). 0h = Only GPIO2_OUT bit controls GPIO2 1h = GPIO2_OUT bit AND ENx pin control GPIO2

3 EN_PIN_SELECT_

R/W X This bit enables EN1 and EN3 pin control for GPIO2 0h = GPIO2_SEL bit AND EN1 pin control GPIO2 1h = GPIO2_SEL bit AND EN3 pin control GPIO2

2 GPIO3_SEL R/W X This bit selects the EN3 pin function

0h = EN3 1h = GPIO3

1 GPIO2_SEL R/W X This bit selects the EN2 pin function

0h = EN2 1h = GPIO2

0 GPIO1_SEL R/W X This bit selects the EN1 pin function

0h = EN1 1h = GPIO1

8.6.1.45 GPIO_CONFIG

Address: 0x2D D7 D6 D5 D4 D3 D2 D1 D0 Reserved GPIO3_OD GPIO2_OD GPIO1_OD Reserved GPIO3_DIR GPIO2_DIR GPIO1_DIR

7 Reserved R 0h

6 GPIO3_OD R/W X GPIO3 signal type when configured as an output

0h = Push-pull output (VANA level) 1h = Open-drain output

5 GPIO2_OD R/W X GPIO2 signal type when configured as an output

0h = Push-pull output (VANA level) 1h = Open-drain output

4 GPIO1_OD R/W X GPIO1 signal type when configured as an output

0h = Push-pull output (VANA level) 1h = Open-drain output

3 Reserved R 0h

2 GPIO3_DIR R/W X GPIO3 signal direction

0h = Input 1h = Output

1 GPIO2_DIR R/W X GPIO2 signal direction

0h = Input 1h = Output

0 GPIO1_DIR R/W X GPIO1 signal direction

0h = Input 1h = Output

8.6.1.46 GPIO_IN

Address: 0x2E D7 D6 D5 D4 D3 D2 D1 D0 Reserved GPIO3_IN GPIO2_IN GPIO1_IN Bits Field Type Default Description 7:3 Reserved R 0h