P82C435

82A436 ETC1 | Alldatasheet

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• 14 Aemress | Be000n-BEFFFH-used in of the corresponding bit in each of the four

i 82C435 ENHANCED GRAPHICS CONTROLLER 82A436 BUS INTERFACE = 100% hardware and software compatible m= Improved CPU access to display memory, to IBM Enhanced Graphics Adapter™ card allowing up to two times faster per- = Backward compatible to IBM Color formance over IBM EGA without software Graphics”, IBM Monochrome™ and ng Hercules™ adapters = Supports 640 480 resolution. 38 MHz = Reduces the chip-count for an EGA im- options supports 800 x 600 resolution plementation to 13 standard components, = BIOS and software drivers for 640 x 480 including 256 Kbytes of display memory resolution and 800 = 600 resolution = Hardware support for context switching in available windowing and multi-tasking environments @ Smart Auto-Emulation adjusts automati- cally to display mode required by applica- tion software The 82C435 Graphics Controller and 82A436 82A436 Bus Interface Bus Interface offer a complete, highly inte- The 82A436 Bus Interface provides bus inter- grated solution for implementing an IBM face, memory select and I/O select logic Enhanced Graphics Adapter compatible con- functions. The 82A436 is a bipolar device and troller, with backward compatibility to CGA, is packaged in a 68 pin PLCC. IBM Monochrome, and Hercules modes. A . complete EGA, with backward compatibility Backward Compatibility/Smart Auto-Emulation can be implemented using a total of 13 The 82C435 supports backward compatibility off-the-shelf components, including 256K on-chip to CGA, IBM Monochrome and bytes of display memory. Hercules modes. It also supports Smart Auto- Emulation which automatically adjusts to the

820435 Graphics Controller graphics mode required by the application

The 82C435 single-chip graphics controller software. The 82C435 provides enhanced integrates the functions of the four-chip performance to CGA modes by displaying

88240 CHIPSet (82C431 Graphics Control- CGA text in EGA resolution

ler, 82C432A Sequencer, 82C433 Attributes Controller, and 82C434A CRT Controller) with Hardware Support for Context Switching additional support logic and registers for For support of multitasking and windowing backward compatibility to CGA, Hercules and environments, the entire state of the 82C435/ IBM Monochrome modes. 82A436 (most registers and latches in the 8204: 24: id itable The 83C435 is packaged in an 84-pin PLCC. (0435/82A436) is readable and writable, system Ee T =] L rary fw cOntroucen =E} Gy exrose 82C435/82A436 EGA System Diagram Publication No, 3-435-8 ! 8/88 REV 3

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Pin No. a a cs i 29 | ADDRO 28 19 i] ADDR2 26 ' ADDR1 27 ' ADDR3 55 ! ADDR4 56 ' ADDRS 57 ' ADDR6 58 | ADDR7 SYSTEM ADDRESS bits 0-15. These bits are used for ad- 59 1 ADDR8 dressing the display memory. 30 | ADDRO 3 | AODDR10 4 ' ADDR11 44 ! ADDR12 53 ! ADDR13 13 ! ADDR14 Mot ADDR NG 80 fe) DATAO 81 vO DATA1 82 fe} DATA2 SYSTEM DATA BUS bits 0-7. These bits are used to transfer 83 vo DATA3 data to and from the CPU data bus. These are open drain 2 ie} DATA4 outputs and must have external pull up resistors. 3 vo DATAS 4 vo DATA6 BS WO DATA 10 ! MA16 Buffered MA16 input from the 82A436; derived from the CPU address. 63 ! CLKIN DOT CLOCK INPUT. CLKIN is the clock input from an external multiplexer (LS153). CLKSELO and CLKSEL1 (bits 2 and 3 of the Miscellaneous Output Register) determine which frequency is used: 14.317 MHz, 16.25 MHz (up to 25MHz) external crystal or external oscillator (up to 25MHz). 9 | ADDMO Active Low Decoded input (from the 82A436) for the three upper system address bus bits to address the display memory at locations AXXXX and BXXXX. Low when A19-A17 = 101. 79 i MIORD MEMORY I/O READ. MIORD is an active low input from 82A436 for memory or I/O read operations. 78 ' MIOWR MEMORY I/O WRITE. MIOWR is an active low input from 82A436 for all memory or I/O write ‘operations. 72 1 MEMIO MEMORY 1/O. MEMIO is a control signal from 82A436: 0 = memory; 1 = I/O. 3 82C435

Cru ———— eS 82C435 Pin Description (Continued) Pin No. PLCC Type Symbol Description pa Naki 75 1 RESET RESET is an active high input from the system bus used to reset the CRT Controller Registers as follows: a. It initializes the horizontal and vertical polarity control to logical 0. b. Mode Register bits 4 and 7 are reset. c. All counters in the CRT Controller Registers are reset. d. Address Register bits 3 and 4 are reset. e. Hercules configuration switch (I/O address 3BF) bits 0 and 1 are reset. All other control registers remain unchanged. RESET must be active for at least 64 dot clocks. 73 I LPENSTB LIGHT PEN STROBE. LPENSTB is an input from the 82A436. It latches the current address being displayed into the light pen register on a low to high transition. 14 1 1OADS /O ADDRESS. IOADS selects the I/O address to the CRT Controller. 0 = 2XX, 1 = 3XX. 68 1 CIN LINEAR ADDRESSING INPUT. When LIN = 1, the 82C435 works in the normal mode (index addressing) for normal EGA operation. When LIN = 0, the address bus points to the register location and I/O writes and reads (MIOWR and MIORD) can be performed in one operation. 76 i TEST TEST = 0 sets the vertical retrace counter to the complement of the contents of the Vertical Retrace Start Register (CR10) at the end of the current scan line. TEST = 1 allows normal operation. 62 fe) R 61 3 G R, G, B, RS, GS/I, BS/V are the 6 outputs that drive the 60 3 B monochrome or color monitor. R, G, and B are the Red, 67 3 RS Green and Blue signals, respectively. The RS, GS/!, and BS/V 66 ° Gs/| are the Secondary Red, Secondary Green/intensity Secondary 65 ° BS/V Blue/Monochrome Video (display) signals. 71 fe} HIN HORIZONTAL SYNC OUTPUT. HIN is active high if horizontal polarity bit (bit 6 of the Miscellaneous Output Register (I/O address 3C2)) is low. It is active low if the horizontal polarity bit is high. 7 fe) VIN VERTICAL SYNC OUTPUT. VIN is active high if the vertical polarity bit (bit 7 of the Miscellaneous Output Register (I/O address 3C2)) is low. It is active low if the vertical polarity bit is high.

70 O° BLANK BLANK is an active high output for blanking the screen

during retrace periods. 820435 4

82C435 Pin Description (Continued) Pin No. PLCC Type Symbol Description 15 ° SLOUT ATTRIBUTE SHIFT LOAD. SLOUT is an active low output on the features connector (pin 9). It is used internally by the Attributes Controller in text mode to load parallel data coming in from the display memory. 6 ° CRTINT CRT INTERRUPT. CRTINT is an active high output signal to the system bus pin IRQ2 (IRQ9), used to signal the CPU that the CRT needs attention. CRTINT is enabled by bit 5 of the Vertical Retrace End Register. It can be cleared by program- ming bit 4 of the Vertical Retrace End Register to 0. When ___ inet active, the GRTINT output is in a tri-state condition. __ 8 fe} RDY READY. RDY is an active low output used by the 82C435 to indicate to the CPU that a data transfer will be completed. RDY becomes inactive as soon as a memory read or a memory write operation is completed. When a read or write operation is completed, the RDY output goes high for one dot clock period, and then goes tri-state. RDY can directly drive the VOCHRDY on the VO bus 7 VO TRAP. TRAP can be programmed as an output or as an input. As an output this is active low and is used to inform an external processor that some assistance is needed in the Hercules or CGA emulation modes. This pin can directly drive the IOCHCHK line on the PC-AT bus. As an input, this pin when ___ 10 forces all writes to go to plane 2 only (fonts).

34 VO AAO

36 VO AAI

38 VO AA2

40 vO AASB Multiplexed data/address bus AAO-7 for memory planes 0 46 VO AA and 1.

48 VO AAS

50 VO AAS

52 VO AAT

25 ° RAS ROW ADDRESS STROBE. RAS is an active low signal to the display memory. At the falling edge of RAS, the row address is present on the AA and BA busses. 24 ° CAS COLUMN ADDRESS STROBE. CAS is an active low signal to the display memory. At the falling edge of CAS, the column address is present on the AA and BA busses. 23 oO E02 OUTPUT ENABLE PLANES 0 AND 2. OE02 is an active low signal which causes plane 0 and plane 2 data to be read by the 820435. Plane 0 data is read over the AA bus and plane 2 data is read over the BA bus. Pa) ° OEI3 OUTPUT ENABLE PLANES 1 AND 3. 0E13 is an active low signal which causes plane 1 and plane 3 data to be read by the 82C436. Plane 1 data is read over the AA bus and plane 3 data is read over the BA bus. 5 82C435

82C435 Pin Description (Continued) Pin No. PLCC Type Symbol Description 20 ° WEO WRITE ENABLE PLANE 0. WEO is an active low write enable to display memory plane 0 for memory write operations. 19 fe) WE1 WRITE ENABLE PLANE 1. WE1 is an active low write enable to display memory plane 1 for memory write operations. 18 ° WE2 WRITE ENABLE PLANE 2. WE? is an active low write enable to display memory plane 2 for memory write operations. 7 ° WE3 WRITE ENABLE PLANE 3. WES is an active low write enable to display memory plane 3 for memory write operations. 33 vo BAO 35 vo BAI 37 vo BA2 39 vo BAS Multiplexed data/address bus BAO-7 for memory planes 2 45 vo BA4 and 3. 47 vo BAS 49 vo BA6 51 vo BA7 16 fe) ERMEN EARLY MEMORY ENABLE. ERMEN goes low one dot clock before the time slot for a CPU-to-memory read or write access. 69 ° VALRAD VALID READ ADDRESS. VALRAD is active high when bit 1 (enable RAM) of the Miscellaneous Output Register (I/O address 3C2) is high and one of the following conditions is true: Bits 3 2 Valid Address Ranges © 0 A0000 for 128K bytes EGA mode 0 1 A0000 for 64K bytes EGA mode 1 0 B0000 for 32K bytes EGA mode, Hercules or Mono emulation for 4K bytes (small memory), or 64K bytes Hercules (large memory) 1 1 B8000 for 32K bytes EGA mode or CGA emulation for 32K bytes (large memory) 820435 6

Figure 1. Enchanced Graphics Controller

82C435 FUNCTIONAL DESCRIPTION c) Attributes Controller — The Attributes The 82C435/82A436 is a complete implemen- Controller generates the video data tation of the IBM Enhanced Graphics Adapter stream from the font pattern and attri- with improved features. All EGA functions are bute code in the text mode. Additionally, supported by the 82C435 Single Chip En- the Attributes Controller provides a 16/64 hanced Graphics Controller directly in hard- color palette (in both the text and gra- ware at the register level. The entire EGA phics modes), display memory of 256 Kbytes is supported using 8 64kx4 DRAM chips. Additionally, the d) CRT Controller — The CRT Controller 82C435 allows the CPU more frequent access generates all the sync and timing signals, into the display buffer (memory), which for the monitor and also generates the speeds up graphics intensive applications pro- multiplexed display memory row and grams by up to two times. This high band- column addresses for display refresh and width feature is transparent to all applications CPU access to display memory programs that use the EGA in the standard resolutions of 640+200 or 640350. No special GRAPHICS CONTROLLER software drivers are required to enable this The Graphics Controller is responsible for feature. directing data from the display memory to the Attributes Controller and the CPU. The For support of multitasking environments and aden Tex talgnanunere) and Graphic ta context switching, the entire state of the the Text Mode, the Graphics Controller 82C-435/82A436 (most registers and latches fetches the character code snd attribute byte in the 82C435/82A436) is readable and from memory, it then fetches the appropriate writable. byte of the character font from the memory based character font table. The font pattern The 82A436 Bus Interface Chip integrates ail ne the ainibute byte are then sent to the the external logic required around the 82C435 the Graph aerate ine Graphics Mode. to implement a EGA/CGA/MDA/ Hercules . compatible graphics subsystem. The 824436 pixels (4 bits/pixel) from display memory and. internally decodes all memory and I/O (nor- then serially sends each pixel data to the mal and alternate) addresses used by each of Attributes Controller the graphics subsystems The Graphics Controller formats the data for use in various compatible modes. The Gra- The 82C435 is an integration of four different phics Controller also provides color compa- modules. These modules are essentially the rators which can be used in color painting four chips in the CS8240 EGA CHIPSet and filling operations. Data can be written to 82C431, 82C432, 82C433 and 82C434 with the display memory planes in 32 bit words to extended functionality. Each of the four mo- expedite fast color presetting of the display dules retains its identity within the 82C435. areas on the monitor. Logical functions on The four modules are: the chip allow for manipulation of the data . efore being written to the display memory, a) Graphics Controller — The Graphics allowing the user to implement features pa Controller interfaces the 8 bit CPU data as transparency and overlaying bus to four planes of display memory. It supports different types of pixel/data The Graphics Controller has two major sec- mappings for read and write operations tions, Graphics A and Graphics B, The Gra- b) Sequencer — The Sequencer generates phics A section normally writes to the display all the timing signals for the 82C435 and memory planes 0 and 1, and the Graphics B the memory control signals for the dis- section normally writes to the memory planes play memory. 82C435 8

2 and 3. The following description will refer pointer to the actual data register into the to these two sections as Graphics A and Graphics Address Register and then acces- Graphics B sing the Graphics Data Register. The Graphics Address Register is located at 1/O address GRAPHICS CONTROLLER REGISTERS 3CEh, and the Graphics Data Registers are Most Graphics Controller registers are located all located at I/O address 3CFh. The following at two byte addresses in the CPU I/O space table describes the Graphics Registers: The registers are accessed by first writing a Register Number —_ Register Name Address Pointer Address = Graphics A Position = 3CCh _ Graphics B Position - 3CAh - Graphics Address - 3CEh GRO Set/Reset 00 3CFh GRI Enable Set/Reset 01 3CFh GR2 Color Compare 02 3CFh GR3 Data Rotate 03 3CFh GR4 Read Map Select 04 3CFh GR5 Graphics Mode 05 3CFh GR6 Miscellaneous 06 3CFh GR7 Color Don't Care 07 3CFh GRE Bit Mask 08 3CFh GRF8 Processor Latch 0 Fen 3CFh GRF9 Processor Latch 1 F9h 3CFh GRFA Processor Latch 2 FAh 3CFh GRFB Processor Latch 3 FBh 3CFh 9 82C435

REGISTER DESCRIPTION GRAPHICS ADDRESS REGISTER Read-Write Register GRAPHICS A POSITION REGISTER VO Address: 3CEh Read-Write Register W/O Address: 3CCh (brToe]os]oeTo3]o2]o: Ion] (orJoe[osToJosoz[o:[oo) | wen euanes 0 ano » | Gnapwics ADDRESS POINTER | or useo The Graphics Address Register is used to point to other registers in the Graphics Con- The Graphics A Position Register selects the troller. The four least significant bits deter- CPU data bus signals and directs them to/from mine the register which will be pointed to in display memory planes 0 and 1. This register the next register write operation. When this should normally be programmed to 00h to register is read, D5, D6 and D7 are always 1’ select DO and D1 for display memory planes D4 is ‘1’ if D5, D6 and D7 were written as 1 0 and 1 respectively. D4 is ‘0’ if D5, D6 or D7 were written as ‘0' GRAPHICS B POSITION REGISTER SETRESET REGISTER (GRO) Read-Write Register Read-Write Register V/O Address. 3CAh W/O Address: 3CFh Address Pointer: 00 (br [os]oeJoe[os]oa]ox]o0 or[oe[osJo[ox]ox]or oe] | JY wemony panes 2 an0 9 SeTRESEY air © — SEPRESEY ait 4 sevmeser evr 2 L___ sevmeser errs Nor useo The Graphics B Position Register selects the CPU data bus signals and directs them to/from. When the Graphics Mode Register selects display memory planes 2 and 3. This register write mode 0, and the Set/Reset mode is en- should normally be programmed to Oth to abled through the Enable Set/Reset Register, select D2 and D3 for display memory planes bit 0 of this register is written to the entire 2 and 3 respectively. addressed byte in display memory plane 0. Similarly bits 1, 2 and 3 determine the data to be written into display memory planes 1, 2 and 3 respectively LL 820435 10 82C435

ENABLE SET/RESET REGISTER (GR1) example to illustrate the mechanism: Read-Write Register If Color Compare Register = 0011, Color Don't VO Address: 3CFh Care = 1111, and: Address Pointer: 01 Plane 0 has data = 11111111 EES EE ENEIEN ES Plane 1 has data = 00000001 enance sermeser ere Plane 2 has data = 11111110 enanue sevaeser i Plane 3 has data = 00000000 wane Sermeser 02 then the data bus D7-D0 will have 00000001, LL enaace serneser a> indicating that a match occurred on the bit DO only. — |~ sto DATA ROTATE REGISTER (GR3) Read-Write Register _ VO Address: 30Fh The Enable Set/Reset Register works in con- Adress Pointer: 03 junction with the Set/Reset Register. If the ICSC oo Graphics Mode Register is programmed to novare count ® write mode 0, and Set/Reset is enabled (=1), then the contents of the Set/Reset Register movare counT determine the data to be written to the respec- ——— ovare counr 2 tive display memory planes. If write mode 0 is | selected and Set/Reset is not enabled (= 0) _ Jroncron stuecr on a plane, the plane is written with the data from the CPU data bus nor vee COLOR COMPARE REGISTER (GR2) } Read-Write Register W/O Address: 3CFh The Data Rotate Register is used to perform Address Pointer: 02 a rotate function on the data written by the pops | CPU. If the Graphics Mode Register is pro- T T co.on coupane (ruant 0 grammed for write mode 0, then the value in j COLOR COMPARE (PLANE 1) the Rotate Count Field represents the number of bits the CPU data will be rotated (right) coLon cowpane (uaNe 2 during the GPU write cycles, The CPU data |_____ corm comune rane 2) bits are first rotated and then subject to the | logical operation as specified in the Function | Select Field. | wor usee The Function Select bits allow the contents i of the processor latches to operate logically upon the CPU data being written into the If the Graphics Mode Register is set to Read EGA memory. The bits operate as follows: Mode 1, each bit of data read from the display > bs memory planes 0-3 is compared to bits D0 see through D3 programmed in the Color Com- © 0 No change to the Data pare Register and the Color Don't Care Regis- 0 1 Logical ‘AND’ between Data ter. A match between the memory data and and latched data. the Color Compare Register (for the bits as 1 0 Logical ‘OR’ between Data and specified in the Color Don't Care Register) latched data results in a logical 1 being output on the 11 Logical ‘XOR’ between Data corresponding data bus bit. Following is an and latched data. 1" 820435,

READ MAP SELECT REGISTER (GR4) pipe Read-Write Register ee VO Address: 3CFh 0 0 Each of the four display memory Address Pointer: 04 planes is written with the CPU data rotated by the number of counts in Glee Teele) ar seutcro the Rotate Register, except when the Set/Reset Register is enabled war sececr for any of the four planes. When the Lae sextet 2 Set/Reset Register is enabled, the corresponding plane is written with the data stored in the Set/Reset Register. Nor usto a 0 1 Each of the four display memory _ __ planes is written with the data pre- viously loaded in the processor The contents of the Read Map Select Register latches. These latches are loaded represent the memory plane trom which the during all read operations. CPU reads the data in read mode 0. This 1 0 All planes (0-3) in the addressed register does not effect the read operation byte are set to the value of data bus performed through the Color Compare Regis- (D0-D3). The data bits are treated ter (read mode 1). The four memory maps are as the color value to be written into selected as follows: the eight pixels in the addressed byte. For example, memory plane 0 ll '"'"™'""'—” is set to the value of data bit DO, D2 D1 DO memory plane 1 is set to the value 7.0 0 Mapo of data bus bit D1, etc. Individual o 0 4 Map 1 pixels (all planes) in the addressed 0 1 0 Map 2 byte can be prevented from being o 1 4 Map 3 updated by appropriately program- ming the Bit Mask Register.

11 Illegal

GRAPHICS MODE REGISTER (GR5) Read-Write Register The operations specified above will also work VO Address: 3CFh in conjunction with the Function Select op- ‘Address Pointer: 05 tions available through Data Rotate Register. (br[os]os]ox[osToaTor] 0} Read Mode (D3)—Figure 3 Joni woo D3 mesenveo - Must eo 0 When D3 = 0, the CPU reads the nao woot data from one of the display memo- 1 ry planes. The exact plane is se- L__ ovoeven lected through the Read Map Select SHIFT REGISTER MODE Register.

1 When D3 = 1, the CPU reads the

Jror useo result of the logical comparison between the four display memory The function of the bits is as follows planes data and the contents of the Color Compare and Color Don't Write Mode (D0,D1)—Figure 2 Care Registers, 82C435 12

TO PLANES 0.1.2.3 Fig. 2 Odd/Even (D4) The data bits in the memory planes 0-3 are D4 = 1 will put the Graphics Controller in the represented as MODO-MOD7, M1D0-M1D7, Odd/Even addressing mode. In this mode, M2D0-M2D7, and M3D0-M307, respectively. even CPU addresses access planes 0 and 2 When D5 = 1, the data in the 4 serial shift while odd CPU addresses access planes 1 registers will be formatted as follows: and 3. This option is useful for IBM Color Graphics Adapter compatible memory organi- Lad LSB Output te: zation. The value of this bit should be the D0 MID2 MrDs M16 MOD MoO? MODS MODS. BO complement of the value programrhed in D2 wb) M103 MIDS M107 MODY Moos MODS MOOT Bit of the Sequencer Memory Mode Register. \\wsb0 WaD2 MSDs M308 M2D0-M2O2 M2D_MZ05 Bit? Shift Register (D5) yop1 MaD3 M308 M307 M2D" M203 M25 MZO7 Bid 13 82C435

FROM PLANES 0.1.2.3 LATCH BITSO-3 READ MAP ‘COMPARATOR RESo Mabe ‘SELECTOR BITS 0-3, SELECT TO CPU DATA BUS Fig. 3 The Least Significant Bit (LSB) is shifted out MISCELLANEOUS REGISTER (GR6) first. The first two registers correspond to the —-Read-Write Register Graphics A shift registers, while the following VO Address: 3CFh two correspond to the Graphics B shift re- Address Pointer: 06 gisters. This is normally used for CGA com- patible 320%200, 4 color graphics mode. (exee]oeToe[osToaTos]o5] ‘onapnics:Texr Moot When D5 = 0, then MOD7-M0DO, M1D7-M1D0, | main 000-E¥EN PLANES M2D7-M2D0 and M3D7-M300 are shifted out - nemonv war 0 with the bit D7 going out first in all cases. emony Map 9 ‘SB LSB Output to: { MoD MIOY MrO2 M103 MOD4 MODS MODE MOD? BHO i nor useo M00 MOY MIDZ MIO9 MDE MATOS MNO MDT BHI M200 M201 M2D2 M203 M2DE MZO5 M206 M207 Bi

300 M301 M302 M3D3 MSDS M3D5_MBDB M3DT Bia Graphics/Text Mode

0 = 1 selects the graphics mode. DO = 0 selects the text mode. Chain Odd-Even Planes When D1 = 1, the CPU address bit AO is replaced by a higher order address bit. The $$$ 820435 14

Figure 4. Memory Cycle Division for High CPU Bandwidth Mode (SR1-D5=0), 8 Dots/Character

2 CAS ADDRESS

Figure 5. Memory Cycle Division for High CPU Bandwidth Mode (SR1-D5=0), 9 Dots/Character allows the CPU to access memory during planes. memory cycle selection allows different screen two byte addresses in the CPU 1/O space.

# ONLY ACTIVE FOR VALI CPU MEMORY READ WRITE CYCLES.

2 Gas ADDRESS = BATA

Figure 6. Memory Cycle Division for Low CPU Bandwidth Mode (SR1-D5=0), 8 Dots/Character

"TA YW = ATALANTA SY | WEO nT Wei wot ed “" i Cocoa _ = tV\\t | @.NOE, ACTIVE DURING CRT READ CYCLE A AND 0 ONLY FOR HIGH CRT BANDWIDTH MODE (SRO-01-0) Figure 7, Memory Cycle Division for Low CRT Bandwidth Mode (SR1-D5=0), 9 Dots/Character 19 82C435

SEQUENCER Reset). Asynchronous Reset can cause data REGISTER DESCRIPTION loss in the dynamic display RAMs. ADDRESS REGISTER Synchronous Reset Read-Write Register D1=0 causes the Sequencer to clear synchro- 1/0 Address: 3C4h nously and halt. D1=1 causes the Sequencer to run unless DO (Asynchronous Reset) is [prJes{osTo«]os oz] osJoo] cleared to zero. Srovencen agonesgerre Before changing the Clocking Mode Register, ‘SEQUENCER ADDRESS BIT the Sequencer should be reset with this bit. SEQUENCER ADDRESS BIT 7 This will preserve the memory contents. _ ror seo Both the Reset bits must be a logical 1 to allow the Sequencer to operate. Ne abonenzaenecs SEQUENCER CLOCKING MODE REGISTER 7) eng oneneren (sR1) ——— J worren Read-Write Register W/O Address: 3C5h The Address Register is a three bit write-only Address Pointer: 01 register. When loaded with a binary value (pointer), it points to the data register where [pr JosTos]osJos]o2] Joo) data is to be accessed. 8/9 DOT CLOCKS D5 is a secondary read location for the I/O CRT BANOWIDTH address select bit of the EGA Miscellaneous —— sHiFTLOAD Output Register (I/O address 3C2h). cuoce D6 and D7 are the read locations for the CPU BANDWIDTH Hercules Configuration Register (bits DO and | nor use 1 at 1/O address 3BFh) | per veso RESET REGISTER (SRO) or useo Read-Write Register VO Address: Sesh The description for the individual bit fields is Address Pointer: 00 as follows: DO 8/9 Dot Clocks: DO=0 causes the Se- (erJoe[os[ox]os]o2]ox]o0 quencer to generate character clocks ASYNCHRONOUS BESET which are 9 dots wide. DO=1 causes the — srncnnonous reser Sequencer to generate character clocks | _ which are 8 dots wide. The only mode | that uses 9 dots wide character clocks is the monochrome text mode. The resolu- a or useo tion for this mode is 720 x 350. All other ee modes use 8 dots wide character clocks. [! ——— D1 CRT Bandwidth: D1=1 makes CRT a memory accesses for the low resolution Asynchronous Reset modes (horizontal resolution of 320 4 pixels). D1=0 must be programmed for pore causes Ne ek taco “aces all ihe all higher resolution modes (horizontal chronously al resolution of 640 or 720 pixels! outputs (except R, G, 8, RS, GS/I, BS/V) ina Pixels), high impedance state. DO=1 causes the Se- D2 Shift/Load: D2=0 causes the display quencer to run unless D1-0 (Synchronous serializers in the Graphics Controller to 820435, 20

be reloaded every character clock. D2=1 some cases as Map Mask Register. A logical causes the display serializers to be re-_—_‘1 in any of the bits 0 through 3 enables the loaded every other character clock. This CPU to write to the corresponding memory mode is useful when 16 bits are fetched planes 0 through 3. A logical 0 in any of the every memory cycle and chained toge- bits disables the CPU to write to the corres- ther in the shift registers. This bit is only ponding memory planes by suppressing the set for APA (all-points-addressable) WE signal to that memory plane. When this graphics modes. register is loaded with OFH, the CPU can 7 perform a 32-bit write operation in one D3 Dot Clock: D3°0 selects the Sequencer memory cycle. This substantially reduces the master clock input to be output on the CPU overhead in the CPU in graphics drawing Dot Clock output pin. D3=1 causes the Sha thing operations master clock to be divided by 2 to gener- : ate the dot clock. As tne pot Clone When odd/even modes are selected (by clear- 'e primary clock used by the : ing bit 2 of the Sequencer Memory Mode all other timings will be stretched as Register) planes 0, 1 and planes 2, 3 should they are derived from the Dot Clock. Dot have the same plane mask value Clock divided by 2 is used for 320 x 200 modes In Graphics modes, each pixel consists of D4 CPU Bandwidth: D4=0 allows two CPU four bits, Planes 0-3 contain one bit each accesses into display memory for every from the four bit pixel information. In the four CRTC accesses. This effectively Text mode, plane 0 contains the character doubles the memory bandwidth available codes, plane 1 contains the corresponding to the CPU. This high speed mode can attribute byte, plane 2 contains the character be used for video clocks up to 20 MHz font (up to four fonts can be stored in plane 2) Therefore at normal EGA operation (16 and plane 3 is not used. Figure 8 represents MHz video clock), the CPU can update the memory organization in the two modes. the screen at up to twice the normal speed, At higher video rates, D4 must be CHARACTER MAP SELECT REGISTER set to one, resulting in the normal EGA (SR3) mode of one CPU memory access for Read-Write Register every four CRTC memory accesses. CPU VO Address: 3C5h Bandwidth is independent of the CRT Address Pointer: 03 Bandwidth (bit D1) of this register {o> ]oe]os[o<[os [o2]01Joo) PLANE MASK REGISTER (MAP MASK REGISTER SR2) [ ) cuancre near eer Read-Write Register | | — W/O Address: 3C5h | cnanacten cenenaron seuecr« Address Pointer: 02 | | L__ (leslie Lalas) [= HABE MEMORY PLANE € wor uses LL ewaste weworr eLane 1 —— | ENABLE MEMORY PLANE 2 es | ENABLE MEMORY PLANE 3 Character Generator Select B UL D1-D0 select the character generator used to generate alphanumeric characters when attri- OT Use bute bit 3’ is 0 (display memory bit M1D3) according to the following table: The Plane Mask Register is also referred to in 21 820435

Figure 8. Enhanced Graphics Display Memory Organization

. OO In text modes, bit 3 of the attribute bit D3 Odd/Even (D2) normally turns the foreground intensity on or D2 - 0 puts the Sequencer in the Odd/Even off. This bit may be redefined to be a switch addressing mode. In this mode, even CPU between character sets. This function is en- addresses access planes 0 and 2, while odd abled when there is a difference in the values CPU addresses access planes 1 and 3. This of Character Map Select A and Character option is useful for IBM Color Graphics Map Select B bits. Whenever the two values. Adapter (text and graphics mode) compatible are the same, the character select function is memory organization. The value of this bit disabled and attribute bit D3 turns the fore- should be the complement of the value pro- ground intensity on or off. 256K bytes of grammed in D4 of the Graphics Controller memory support 4 character sets. Mode Register (GR5) Asynchronous Reset (Reset Register bit 0) clears the Character Map Select Register to 0. This should only be done during a system ATTRIBUTES CONTROLLER reset. The Attributes Controller provides a palette of, SEQUENCER MEMORY MODE REGISTER 16 colors selectable trom a possible 64, (SR4) each one of which may be specified sepa- Read-Write Register rately. Six color outputs, Red (R), Green (G), V/O Address: 3C5h Blue (B), Secondary Red (RS), Secondary Address Pointer: 04 Green/Intensity (GS/1) and Secondary Blue/ Monochrome (BS/V) are available as outputs. (beTes]ex]seJ03]oa]orJoe

7 TY T serrcnsnmcs tou The Attributes Controller also controls blink

" ing and underline operations | | | Le exrewoeo enone i Ps | | | KH & ovoeven The Attributes Controller formats data from Po the display memory for display on the screen. t _ it also provides the horizontal pixel panning { capability in both text and graphics modes. 1} wor useo in the text mode, the attribute bits are de- - coded to select one of the 16 color palette Dt cl a hich consists of Graph registers. The color palette, wi Text/Graphics (D0) 16 registers, each 6-bit wide, can be loaded D0-0 indicates that a graphics mode is active with any color combination. Thus it is possible This forces the same address on the multi- to display the characters in any one of the 16 plexed memory address bus AAx and BAx colors out of a possible of 64 (6-bit wide DO=1 indicates that the text mode is active registers) and forces the display buffer address on memory address bus AAx and the character In the graphics mode, the color information is generator address on memory address bus stored in the display memory as 1, 2 or 4 bits. BAx. per pixel, The pixel bit pattern is used to Extended Memory (D1) select one of the 2, 4 or 16 color registers. In EGA modes this bit must be programmed The six bit contents of the respective color to 1. The 82C435 does not support 16k"4 register determines the color on the screen DRAMSs. Only 64k"4 DRAMs are supported. for each individual pixel, for 256 Kbytes of display memory. In CGA/ Hercules modes this bit must be programmed ATTRIBUTES CONTROLLER REGISTERS to 0. In CGA mode, the memory is restricted The Attributes Controller registers are all to 16 Kbytes while in the Monochrome (Her- located at a single byte address in the CPU cules) Text mode the memory is restricted to (0 space. The registers are accessed by first 4 Kbytes. writing @ pointer to the actual data register -'7)))——SS A 23 820435

into the Attributes Address Register and then the palette registers (ARO-ARF). After the accessing the Attributes Data Register. Both palette registers have been loaded, this bit the Attributes Address and Data Registers are must be set to 1 to enable the video data located at I/O address 3COh. Both registers can also be accessed at I/O address 3C1h. D7 indicates the current state of the Attributes An internal flip-flop controls the selection of flip-flop that toggles between the Attributes the Attributes Address and Data Registers Address and Data Registers. D7 = 0 when the To select the Address Register, an 1O Read Attributes Address Register is read and D7 is executed to address 3BAh/3DAh to clear 1 when any of the Attributes Data Registers is this flip-flop. After the Address Register has read, This bit is a read-only bit. To set this bit been loaded by an IO Write to address 3C0h to a desired value, you need to reset the flip- this flip-flop toggles, and the 82C435 is ready flop as described earlier and then it can be to have Data Register (pointed to by the toggled to the right state Address Register) loaded. Every 10 Write to address 3COh toggles this flip-flop. The PALETTE REGISTERS (ARO-ARF) following table describes the Attributes Read-Write Registers Registers: V/O Address: 3C0h Address Pointer. 00-OFh Register Register Address malale alee Number Name _____ Pointer Address. TT] © ewe nee - ‘Address Register — 3Con ARO-ARF Palette Registers 00n-OFh 3COh Gacen WiogS ARIO Attributes Mode RED VIDEO ARIt — Overscan Color = 11h 3COW ARI2 Color Plane SECONDARY GREEN INTENSITY. ARIZ. Horizontal Pixel SECONDARY REC ATTRIBUTES ADDRESS REGISTER ArmmiauTe Fae FLOP Reaa-write Register These six bit registers allow a dynamic map- /O Address: 3COh ping between the text attribute or graphic color input and the display color on the CRT Jos [os]ee|o[oa[ox]o8] screen. The six bits, D0-D5 are output as aecisten AooRESS 817 0 B.G.R,BS,GS/I, and RS/V respectively. A snccisten AD0AESS 817 + logical 1 in a bit selects the corresponding | color for that bit while a 0 de-selects it. The nearsren aopwess oie maximum number of possible displayable | \\——— stoisten anpness rT > colors is 64 for monitors with six color inputs. L______— neeisten sooness or « Monitors with three color inputs allow a [| ener co onane maximum of eight displayable colors, while wor useo monitors which also have an intensity input allow a maximum of sixteen displayable Larne rar or colors D0-D4 are used to point to the internal data registers in the Attributes Controller D5=0 disables the color palette and video to allow access to the color registers. D5=1 enables the video and normal palette function of color translation. This bit must be 0 to load OE 82C435 24

-. SS ATTRIBUTES MODE CONTROL REGISTER It divides the VRTC period by 32. For text and {AR10) graphics modes, the blink is ON for 16 VRTC Read-Write Register Periods and OFF for 16 VRTC periods. In the VO Address: 3Con text mode, blink is usually used only in Mono- Address Pointer: 10h chrome display modes. In this case , the blink ee affect displays the character for 16 frames 0? Jos os]os]oslor]orJoo) and blanks the screen for 16 frames. In the T] [TC cmarmes reer woot graphics mode, when blink is activated, the | Lb orspuar reve Most significant color bit (bit 3) for each pixel | ENABLE LINE GRAPHICS CHARACTER is inverted alternately, thus allowing two dif- | comes ferent colors to be displayed for 16 CRT Fi Satststexcnoumo uensrveunx trames each. When the CURSOR is displayed | (—____ in the text mode, the ‘characters’ are blinked L ~~ | voruseo at the rate of 16 frames ON and 16 frames - a OFF, The CURSOR, however, is blinked at a rate of ON for 8 frames and OFF for 8 frames. arrmiauve FUP FLOP Graphics/Text Mode (D0) OVERSCAN COLOR REGISTER (AR11) DO-0 selects text mode. DO=1 selects graphics To nae oaister mode Address Pointer: 11h Monochrome/Color Display (D1) FICCI CINE] D1=0 selects color display attributes. D1=1 xe wonoea selects IBM Monochrome display attributes. } | | —— Gneen sonven Enable Line Graphics Character Codes (D2) | L BEE BonvER 2-0 makes the ninth dot the same as the SECONDARY BLUE BORDER background, This enables compatibility with ——— stconpany cneen nonorn the IBM Monochrome display adapter, which ———— stconoany neo sonoen uses 9 dots per character. D2=1 enables the _ wor seo special line graphics character codes for the { IBM Monochrome Display Adapter. When this ATTRIBUTE FIP FLOP bit is set, it forces the ninth dot of a line Overscan Color graphics character to be identical to the This six-bit register defines the overscan or eighth dot of the character. The line graphics border color displayed on the CAT sereen character codes for the Monochrome Display For monochrome displays, this register should Adapter are COH through DFH. When a Line be cleared to logical 0. A logical 1 selects the Graphics character is to be displayed, the corresponding color. The border color is dis- Attributes Controller will force the ninth dot played in the interval after Display Enable bit of a line graphics character to be identical End and before Blank Start and between to the eighth dot of the character. Blank End and Display Enable Start (the Enable Blink/Select Background Intensity beginning) (D3) 03-0 selects the background intensity for the attribute input. This is required for Mono- chrome and Color Graphics Adapter compa- tibility. D3=1 enables the blink attribute in text and graphics modes. The blinking counter operates off the Vertical Syne signal —_—_. 25 82C435

a COLOR PLANE ENABLE REGISTER (AR12) HORIZONTAL PIXEL PANNING REGISTER Read-Write Register (AR13) 1/0 Address: 3COh Read-Write Register Address Pointer: 12h W/O Address: 3COh Address Pointer: 13h (or]oeJos[o«[os]o2] osJoe) ENABLE COLOR PLANE 0 or[oe[osJou]os]o2]o1] ENABLE COLOR FLAME 9 | PiREL POSITION BIT 2 wor use | of moruseo ATTRIBUTE FLIP FLOP | — Larimer rLor Enable Color Plane (D0-D3): A logical 1 in any of the bits DO-D3 enables Horizontal Pixel (Pel) Panning the respective color bits for each pixel. If any Bits DO-D3 select the number of pixels to bit is set to zero, the corresponding bit of the shift the display data horizontally to the left pixel data from memory is forced to zero Pixel panning is available in both text and before accessing the palette. graphics modes. In monochrome text mode the output can be shifted a maximum of 9 Display Status MUX (D4-D5): pixels, whereas in all other modes a maximum Bits D4 and D5 select two of the six color shift of 8 pixels is possible. The Start Address outputs to the CRT screen, which are 2 out- Register specifies the byte of the upper left puts of the 4 status bits. The output color corner of the screen display, and pixel pan- combinations available on the status bits are ning gives pixel resolution to the left end of listed in the following table: the display. oe COLOR PLANE ENABLE EGA STATUS REGISTER REGISTER | OUTPUTS DS D4 Bits Bita oO oO Red Blue 0 1 Secondary Secondary Red Green 1 0 Secondary Green Blue 1 1 Not Used Not Used This capability can be used to run diagnostics on the color sub-system card. D4 = 1 will also — Tristate the color monitor outputs, R, G B, RS, GS/I and BS/V and, Clear the cursor blink counter. D4 must be cleared to logical 0 for the cursor blink counter to function. 82C435 26

CRT CONTROLLER related characteristics. The CRT Controller The CRT Controller provides the synchroni- also provides split screen capability, soft zation signals for the display monitor. The Scrolling and a light pen interface, CRT Controller contains various CPU acces- VO address bits A1 and A2 are ignored sible 1/0 registers, that allow flexible configu- when the CRTC registers are accessed. The ration options. These options include user CRTC registers can therefore be accessed configurable horizontal and vertical timings at I/O addresses 3X0/th, 3X2/3h, 3X4/Sh and and polarity, cursor type and position, hori- 3X6/7h (X=B in monochrome mode and X=D zontal scan lines, and several other display in color mode). CRT CONTROLLER REGISTERS Register Register Name Address Address Number Pointer = Address Register — 3B4h/3D4h CRO Horizontal Total 00 3B85h/3D5h cri Horizontal Display Enable End 01 3B5h/3D5h cre Start Horizontal Blanking 02 3B5h/3D5h cR3 End Horizontal Blanking 03 3BSh/3D5h cra Start Horizontal Retrace Pulse 04 3B5h/3D5h CRS End Horizontal Retrace Pulse 05 3B5h/3D5h CRE Vertical Total 06 3B5h/305h CR7 CRT Controller Overflow 07 3B5h/3D5h CRB Preset Row Scan 08 3B5h/3D5h cro Maximum Scan Line 09 3B5h/3D5h CRA Cursor Start Scan Line OAn 3B5h/3D5h CRB Cursor End Scan Line 08h 385h/305h CRC Start Address High 0Ch 3B5h/3D5h CRD Start Address Low oon 3B5h/3D5h CRE Cursor Location High Eh 3B5h/3D5h CRF Cursor Location Low OFh 3B5h/3D5h CRI0 Vertical Retrace Start 10h 3B5h/3D5h cRI0 Light Pen High 10h 3B5h/3D5h crit Vertical Retrace End 11h 3B5h/3D5h cRit Light Pen Low 11h 3B5h/3D5h cRI2 Vertical Display Enable End 12h 385h/3D5h CRI3 Offset 13h 385n/305h CRI4 Underline Location 14h 3B5h/3D5h CRIS Start Vertical Blanking 15h 3B5h/3D5h cRi6 End Vertical Blanking 16h 3BSh/3D5h cRI7 CRT Mode Control 17h 3B5h/3D5h CRIB Line Compare 18h 3B5n/3D5h CRF7 Tag Register 0 F7h 3B5h/3D5h CRF8 Tag Register 12 F8h 3B5h/3D5h CRF9 400 Line Register? F9h 3B5h/3D5h CRFA Temporary Storage 0°? FAh 3B5h/3D5h CRFB Temporary Storage 11? FBh 3B5h/3D5h CRFC Temporary Storage 2'? FCh 3B5h/3D5h CRFD Temporary Storage 3°? FDh 3B5h/3D5h CRFE Temporary Storage 4'2 FEh 3B5h/3D5h CRFF Emulation Mode Register? FFh 3B5h/3D5h (1—in 824436, 2—used in CRTC Extended Mode only) 27 82C435

——— ADDRESS REGISTER number of characters in a horizontal scan Read-Write Register {ine, including the retrace time. This defines V/O Address: 3B4h/3D4h the horizontal sweep rate. The character clock is derived from the dot clock as defined by [G7JosJos]osJos]oz]ox]oo) the Sequencer Clocking Mode Register. The actual number of character clocks per hori- zontal scan is two more than the value pro- grammed in this register. | nour ro ome necisren HORIZONTAL DISPLAY ENABLE — $ END REGISTER (CR1) | Read-Write Register __ V/O Address: 385h/3DSh Address Pointer: 01h The CRT Controller Registers are all located (erfecfosToeToo oaTorToe at two byte addresses in the CPU I/O space. | | The registers are accessed by first writing a pointer to the actual data register into the | | CRT Controller Address Register and then accessing the CRT Controller Data Register. | Te eeaNncrencroces) The Address Register is located at I/O address 3B4h/3D4h. The data registers are all located at I/O address 3B5h/3D5h. The exact address 3Bx/3Dx is selected thorough bit DO of the _ EGA Misc, Output Register. The Horizontal Display Enable End Register The Address Register is normally a 5 bit defines the number of characters to be dis- register with the upper 3 bits being ignored. played per horizontal line. The actual charac- When the CRTC Extended Mode Registers ters displayed per horizontal line is one more are enabled through register CR17, all 8 bits than the contents of this register. of the Address Register are used to point to the appropriate data register. When this START HORIZONTAL BLANKING register is read, D6 and D7 are always ‘1. DS. REGISTER (CR2) is 1" if D6 and D7 were written as 1. D5 is ‘0’ if Read-Write Register D6 or D7 were written as 0. \\/O Address: 3B5h/3D5h HORIZONTAL TOTAL REGISTER (CRO) Address Pointer: 02h Read-Write Register V/O Address: 385h/3D5h eel ete Address Pointer: 00h | ar ores foe] Joa]or]oo | | SR CsieTeR oes} [= — The contents of the Start Horizontal Blanking oe Register define the time when the horizontal The Horizontal Total Register defines the total 82C435 28

blanking will start. The register is defined in display enable signal to be skewed terms of the number of horizontal character by one character clock to allow for clocks. The period between horizontal display synchronization with the horizontal enable end and horizontal blanking start is and vertical retrace pulses. The the right side border on the screen display enable skew bits in this register allow for this skew. The END HORIZONTAL BLANKING skew can be programmed from 0-3 REGISTER (CR3) character clocks as follows: Read-Write Register W/O Address: 3B5h/3DSh —— Address Pointer: 03h D6 D5 Skew in character clocks (erfor[osJosJosfor] oO r) o 4 1 - 1 0 2 — }ewo womzowrar acannines +4 3 _—a [E _ START HORIZONTAL RETRACE PULSE REGISTER (CR4) } orseuar ENABLE SKEW Read-Write Register VO Address: 3B5h/3D5h NOT USED Address Pointer: 04h The contents of the End Horizontal Blanking - Register define the time when the horizontal (elses lols T blanking will terminate. The register is defined in terms of the number of character clocks. | cu D0-D4_—_ End Horizontal Blanking: The hori- zontal blanking signal width, W, is PEFR ocesy Ace HSE determined as follows Value in Start Blanking Register + uu W = 5-bit value to be programmed i in End Horizontal Blanking Register. The Start Horizontal Retrace Pulse Register The five least significant bits of the horizontal defines the character position at which the character counter are compared with the con- Horizontal Retrace Pulse becomes active. It is tents of this register. When a match occurs, used to center the monitor screen horizon- the horizontal blanking pulse becomes inac- tally. The value in the register is the character tive. Note that the five bits of this register count at which the Horizontal Retrace Pulse limit the length of the blanking pulse to 31 becomes active. character clocks. D5-D6 Display Enable Skew Control: Prior to displaying data on the screen, the 820435 has to fetch the charac- ter and attribute code, then access the character generator font and finally read the Pixel Panning Regis- ter in the Attributes Controller. Each one of these accesses require the 29 82C435

END HORIZONTAL RETRACE that the signals are latched properly, PULSE REGISTER (CR5) the retrace signal is started before Read-Write Register the end of the display enable signal VO Address: 3B5h/3D5h It is then skewed several character Address Pointer: 05h clocks to provide the proper screen centering. [prfoe[os]o«Josfoz]ox]oo} D6 DS Skew in character clocks END HORLZONTAL RETRACE PULSE —— o 0 0 tt) 1 1 10 2 J wonzontanerrace oevar 11 3 stan 00 memony avoness 07 Start Odd/Even Memory Address This bit determines the CRT The contents of the End Horizontal Retrace memory address after a horizontal Register define the character count at which the retrace. D7 = 0 selects an even ad- Horizontal Retrace Pulse becomes inactive. dress, and D7 = 1 selects an odd address. In most cases this bit D0-D4 End Horizontal Retrace: The hori- should be set to ‘0’. The bit is useful zontal retrace signal becomes inac- in applications where horizontal tive after the character count be- pixel panning is required comes equal to the count in these bits. The width, W, of the retrace VERTICAL TOTAL REGISTER (CR6) signal (in character clocks) is deter- Read-Write Register mined as follows: V/O Address: 3B5h/3DSh Address Pointer: 06h Value in Horizontal Retrace Start Register + W = 5-bit result to be 7] be]os]o«]o3]ox] ox[0e] programmed in End Horizontal Re- ] trace Register. L_ The five least significant bits of the horizontal character counter are compared to the con- | VERTICAL TOTAL (SCAN LINES) tents of this register. When a match occurs, L____ [Hewmnenray the horizontal retrace pulse becomes inactive. Note that the 5 bit register limits the length of the retrace signal to 31 character clocks maximum The Vertical Total Register contains the 8 DS5-D6 Horizontal Retrace Delay: The skew low-order bits of a 9 bit register. The ninth bit of the horizontal retrace signal is is located in the CRT Controller Overflow controlled by these bits. For some Register. The Vertical Total Register defines monitors, it is necessary to provide the total number of scan lines (horizontal a horizontal retrace signal that takes retrace periods) per frame up the entire blanking period. The horizontal retrace signal also trig- gers some internal timings on the falling edge of the signal. To ensure 820435 30

—...—— A CRT CONTROLLER OVERFLOW REGISTER MAXIMUM SCAN LINE REGISTER (CR9) (CR7) Read-Write Register Read-Write Register VO Address: 385h/3D5h VO Address: 3B5h/3D5h Address Pointer: 09h Address Pointer: 07h [70s JosToe]osTo2]osTos] (07Jos[os[osJos [oz] oJoo| | VERTICAL DISPLAY ENABLE END OrT 8 | LI annum scan une | | vemcas nermace sven ara _ ~ The contents of the Maximum Scan Line The CRT Controller Overflow Register con- Register specifies the number of scan lines tains the ninth bit (D8) of Vertical Total, per character row. This actual number of Vertical Retrace Start, Start Vertical Blanking scan lines per row is the contents of this and Line Compare Registers. register plus one. PRESET ROW SCAN REGISTER (CR8) CURSOR START SCAN LINE REGISTER Read-Write Register (CRA) VO Address: 3B5h/3D8h Read-Write Register Address Pointer: 08h V/O Address: 3B5h/3D5h Address Pointer: OAH (bies[os]o«[esToa]orfos | | = (o*[osJosTosTosToa]o Joo] i} ~ | ! | (| seem som can coon Hida - | | Renee Ae ety | a | { —— CURSOR START SCAN LINE tL — ee a D0-D4 of the Preset Row Scan Register speci- fy the starting row scan count after a vertical The Cursor Start Register defines the scan retrace. Each horizontal retrace increments line within a character row where the cursor the character row scan line counter. The hori- block is to begin. The first scan line for the zontal row scan counter is cleared at maxi- cursor is the contents of this register. mum row scan count, which is programmed through register CR9. This register is used for soft scrolling in text modes and in the Hercules Graphics or CGA graphics modes. =... 3 82C435

CURSOR END SCAN LINE REGISTER (CRB) The Start Address is a 16-bit value which Read-Write Register specifies the first word address in the display V/O Address: 3B5h/3D5h buffer for the screen refresh process. This Address Pointer: OBh display buffer address is mapped to the upper left corner of the screen. The Start Address [07 Jos TosTo«Joo Joa] os]oo} High Register contains 8 high order bits of the address, while the Start Address Low Register specifies the other 8 low order bits. Byte resolution on this address can be scURsom ENO SAN CME achieved through the Extended Mode Register (CRF9 - bit D1) START ADDRESS LOW REGISTER (CRD) } cunson skew contnoL Read-Write Register VO Address: 3B5h/3D5h rr se Address Pointer: ODh The Cursor End Register defines the scan orfon)osToifos Tool :[oe! line within a character row where the cursor r block is to end. It also controls the cursor | skew as described below i | . D0-D4 the last scan line for the block cursor is the contents of this field | [___f tow onven stant aooness minus one. L D5-D6 The cursor skew is controlled by a these two bits. The bits control the - skew as follows: The Start Address Low Register contains the 8 low order bits of the Start Address (word D6 D5 Skew address) 0 © One character skew CURSOR LOCATION HIGH REGISTER 0 1 One character skew (CRE)

10 Two character skew Read-Write Register

1 1 Three character skew VO Address: 3B5h/3DSh Address Pointer: 0Eh START ADDRESS HIGH REGISTER (CRC) Read-Write Register [2*Tee[osJoa]oa]oa]ox]s) VO Address: 385h/3DSh Address Pointer: 0Ch | | [pr[ee]os]oeJosfox[or Tor] —— ‘aw onoER CURSOR LocaTioN | Wait ORDER stant ADOHESS TO — The Cursor Location address is a 16-bit value. | The 8 high order bits are programmed in the Cursor Location High Register. The other 8 82C435 32

low order bits are programmed in the Cursor LIGHT PEN HIGH REGISTER (CR10) Location Low Register. The 16-bit word ad- Read only Register dress defines the memory adddress for the VO Address: 3B6h/3DSh character which should have the cursor Address Pointer: 10h superimposed on it [o*Jo«[os]o«]o3fo2}or]oo) CURSOR LOCATION LOW REGISTER (CRF) Read-Write Register — VO Address: 3B5n/3D5h — Address Pointer: OFh L__ {o7]os[os[o<JosToa[o: oo] | TO | LL | a I oy onoee cunson cocarion The Light Pen High Register contains the 8 j;——— high order bits of the memory address that | was displayed when the light pen strobe Lo signal was triggered. The low order 8 bits are stored in the Light Pen Low Register (CR11) In conjunction with the Cursor Location High Normally all write operations to Data Register Register, the Cursor Location Low Register CR10 access the Vertical Retrace Start Regis- defines the low order 8 bits of the cursor ter and read operations access the Light Pen location High Register. Using the Extended Mode Registers of the 82C435, it is also possible to VERTICAL RETRACE START REGISTER read the Vertical Retrace Start Register (CR10) Read-Write Register VERTICAL RETRACE VO Address: 3B5h/3DSh END REGISTER (CR11) Address Pointer. 10h Read-Write Register V/O Address: 3B5h/3D5h [a7 [oe] 0s [oe Jos] 02] 07 Joo} Address Pointer; 11h | (oloeTes]eeterora) | | | - Varc PULSE START SCAN LE | | freee seace | | 0 cueanvenricas wreanver a 0 enaote veericar renner i rr est The Vertical Retrace Start Register is a 9-bit vor useo address which defines the scan line position 1 Of the VATC pulse. The tow order 8 bite are he Vertical Retrace End Register performs programmed through this register, while the multiple functions, as described below: high order ninth bit is programmed through the Overliow Register, CRP D3-D0 Vertical Retrace End: These four bits specify the scan line count at which —— ee 33 82C435

the vertical retrace output pulse CR11 access the Vertical Retrace End Register becomes inactive. The four bits are and read operations access the Light Pen compared with the four least signi- Low Register. Using the Extended Mode ficant bits of the scan line counter, Registers of the 82C435, it is also possible to When the four counter bits are equal read the Vertical Retrace End Register. to the contents in this register, the vertical retrace is terminated. The VERTICAL DISPLAY ENABLE maximum retrace pulse width can END REGISTER (CR12) only be 15 scan lines. The width, W. Read-Write Register of the vertical retrace pulse can be VO Address: 3B5h/3D5h determined as follows Address Pointer: 12h Value of Start Vertical Retrace (erfeo]os[oeJooTes]o:]e9] Register + W = four bit value to be programmed into the End Vertical Retrace Register. Da Clear Vertical interrupt: This bit is venricat ousptay ENABLE ENO used to clear the vertical interrupt | generated on the CRTINT output. A LW logical 0 will clear the interrupt Ds Enable Vertical Interrupt: A logical 0 will enable the vertical interrupt of The Vertical Display Enable End Register de- the CRT Controlier. fines 8 bits of the 9-bits address which speci- fies the scan line position where the display 06 Test: For normal operation this bit ‘on the screen ends. The ninth bit is located in must be set to logical 0. the Overflow Register CR7. LIGHT PEN LOW REGISTER (CR11) OFFSET REGISTER (CR13) Read only Register Read-Write Register VO Address: 3BSh/3D5h VO Address: 385h/3D5h Address Pointer: 011h ‘Address Pointer: 13h [or ]o¢]osJo«]os Jo] or [00 {o7]o8]os]o*]o3 ]Joz[0i]00) The Light Pen Low Register contains the 8 The Offset Register contents define the width low order bits of the memory address Gis- of the Display Buffer currently used. This played when the light pen strobe signal was register is used to compute the memory start triggered. The high order 8 bits are stored in ing address for the next display row (or scan the Light Pen High Register (CR10) line in graphics modes). The byte starting address of the next display row is computed Normally all write operations to Data Register as follows 82C435 34

Byte Start Address for next row = Byte Start the low order 8 bits of the scan line count at Address for current row + K«Contents of which vertical blanking becomes effective. Offset Register (where K = 2 in Byte Mode The ninth bit is located in the Overflow Regis- and K = 4 in Word Mode). ter CR7. END VERTICAL The byte or word mode for the memory ad- BLANKING REGISTER (CR16) dress counter is selected by the CRT Mode Ri 'ead-Write Register Control Register CR17, bit 6. In the CRTC (/O Address: 3B5h/3D5h Extended Mode, the 400 Line Register (CRF9) Address Pointer: 16h bit D2 allows byte/word resolution to the Display Buffer Width. s]o¢]os]o«]o3]oa] [00 UNDERLINE LOCATION REGISTER (CR14) | Read-Write Register | | no vear W/O Address: 385h/3D5h | ERO MERTICAS okaanins Address Pointer: 14h (erleeTesIoe]osTex[oTe0) | | | - The End Vertical Blanking Register specifies the scan line count at which vertical blanking | becomes inactive. The vertical blanking width, W, is determined as follows: }~ seo Value of Start Vertical Register + W = 5-bit value to be programmed into the End Vertical Blanking Register. The Underline Location Register specifies the scan line within a character row at which the The five least significant bits of the result are underline will appear for underlined charac- Programmed into this register. When the five ters. The value in the register should be one least significant bits of the horizontal scan less than the desired scan line number. line counter are equal to the value in this register, Vertical Blanking is terminated. Note START VERTICAL that the maximum width of the vertical blank- BLANKING REGISTER (CR15) ing is limited to 31 scan lines. Read-Write Register CRT MODE CONTROL REGISTER (CR17, V/O Address; 3B5h/3D5h Read-Write Register A ) Address Pointer: 15h W/O Address: 3B5h/3D5h PUCSEI COCCI EIES Address Pointer: 17h | i or[os[osTo<]os]=x]o°]oo] T Companiaiuity Move supPoRT oT | COUNT By Two a i] voness weae The Start Vertical Blanking Register contains RESERVED. sss 35 820435

The CRT Mode Control Register is a multi- Da Extended Register Enable: D4 = 0 is function register, with each bit defining a the default on reset. In this case the different option. Following is a description of 82C435 behaves exactly as an EGA. these bits When D4= 1, then all the Extended Mode Registers in the 82 - Do Compatibility Mode Support: This Mode Berg These eqitcrs be bit allows compatibility with the IBM used for compatibility with CGA/ Color Graphics Adapter. When MDA/Hercules graphics card and DO-0, the character row scan line to save/restore the context of the counter bit 0 is substituted for 82C435. All extended register func- memory address bit 13 during active tionality is gated with this bit. The Gisplay time. When D0=1, no such extended registers can always be Substitution takes place. read or written regardless of this bit D1 Select Row Scan Counter: This bit Ds Address Wrap: Since the 820435 allows compatibility with the Hercu- does not support 64 Kbytes of dis- les graphics card and with any other play memory (it requires 256 4-bank graphics system. When Kbytes), this bit must always be one D1=0, the row scan line counter bit for all EGA modes. In the CGA 1 is substituted for memory address mode, this bit must be set to 0 bit 14 during active display time. When D1=1, no such substitution 06 Word Mode or Byte Mode: When takes place. D6=0, Word Mode is selected. This mode causes the display memory

2 Horizontal Retrace Select: This bit address counter bits to shift down

controls the vertical resolution capa- one bit, and the most significant bit bility of the CAT Controller. The of the counter appears on the least vertical counter has a maximum re- significant bit of the memory ad- solution of §12 scan lines as defined dress output. D6 =1 selects the Byte by the Vertical Total Register. If the Mode. vertical retrace counter is clocked LINE COMPARE REGISTER (CR18) with the horizontal retrace clock Read-Write Register divided by 2, then the vertical reso- V/O Address: 3B5H/3D5h lution is doubled to 1024 horizontal Address Pointer: 18h scan lines. D2=0 selects the horizon- PO EICOCSES ECOG tal retrace clock, and D2=1 selects the horizontal retrace clock divided | by 2 | i bs Count By Two: This bit selects the Le character clock as the clock input or Ne COMPARE TARGET character clock divided by 2 as the | character clock. This bit defines | whether the contents of the Offset —_—— Register are a word or a double word value. When D3-0, the memory The Line Compare Register is used to im- address counter is clocked by the plement a split screen function. When the character clock input. When 03-1, scan line counter value is equal to the con- the memory address is clocked by tents of this register, the memory address the character clock input divided by generator is cleared to 0. The display buffer 2. This bit is also used to create address generator then sequentially addres- either a byte or word refresh address ses the display butter starting at address 0. for the display memory. Each subsequent row address is generated by the addition of Offset Register contents. 82C435 36

This feature allows a given area on the screen ing signal. The screen blanking signal BLANK to be immune to scrolling. The scrolling is a logical ‘OR’ of HBLANK and VBLANK as. operation utilizes the Start Address High and programmed in the respective registers. The Low Registers, and the split screen screen horizontal retrace start location and width are capability will allow scrolling through some controlled by the contents of the CR4 and CRS areas of the screen while the remaining screen registers, while the vertical retrace start loca- remains immune to it. The CRT Controller tion and width are controlled by the CR10 provides all the timing and control signals for and CR11 registers. CRO controls the total the display monitor. Figure 9 shows a graphic number of characters in the horizontal scan illustration of how the contents of these interval, including the retrace time. The total registers control the display screen. The number of scan lines on one raster are deter- horizontal blanking signal is controlled by the mined by the vertical total register CR6. CR1 contents of CR2 and CR3 registers. Similarly, and CR12 define the effective display area on the contents of CR15 and CR16 determine the screen by specifying the horizontal and the location and length of the vertical blank- vertical display enable positions, respectively. START LOCATION REGISTERS, zfegee £ o¢ (RC + RD) is z SCREEN? H+ os FOR SPLIT SCREEN SCREEN 2 ‘| _ CoP 8 Corre ee a Cee ee Coe a — Fig. 9 eee 37 820435

CRTC EXTENDED REGISTERS tion is in progress, then the emulation soft- The CRTC Extended Registers are located in ware can read these registers to determine the CRT Controller address space (Address which register access caused the trap result- Pointer at 3B4h/3D4h and Data Register at ing in the emulation software being invoked 3B5h/3D5h). These registers are functional Reading these registers clears the registers, only after bit D4 of the CRTC Register is set serving as a trap acknowledge.

400 LINE REGISTER (CRF9)

TAG REGISTER 0 (CRF7) Read-Write Register Read-Clear Register VO Address: 3B5h/3D5h W/O Address: 385h/3D5h Address Pointer: F9h Address Pointer: F7h EET CICUEICIENES ive now counter or] oe ]osToo [ea) yo — CRTC REGISTER 00 DIVIDE VERTICAL COUNTER cenre necisren ot | Usa -oispLay eurrER wiom —— care nearsren 02 | ENABLE COA OVERSCAN | = care mtoisren oo SELECT OVERSCAN REGISTER | “care aecisren nonizonTaL 0OURLE - care mecisven os O\\SABLE COAIMDA BLANKING ——— emre necisten er The 400 Line Register is located at offset OF9h in the CRT Controller. This register can TAG REGISTER 1 (CRF8) be accessed by first writing OF9h in the CRTC Read-Clear Register Address Register (I/O address 3B4h/3D4h) VO Address: 3B5h/3D5h and then accessing the CRTC Data Register Address Pointer: F8h (VO address 3B5h/3D5h) (br [oa] 5s] eos ox] or]o0] The description for the individual bit fields is conre necisren 0¢ as follows: | CATE REGISTER 08 “ Do Divide Row Counter: D0=0 causes CRTC REGISTER 0% the scan line (in a row) counter to ‘CATE REGISTER 0B be incremented every scan line. MODE CONTROL REGISTER (288 208) 00-1 causes this counter to be HERCULES CONFIG. REGISTER (28F) incremented every two scan lines. This bit should be set to 1 when it is FOR REGISTERS GC) desired to double each scan line ——— cos coron serecr necisren (209) (running 200 scan line software on Tag Registers 0 and 1 are located at offset a 400 scar ‘ne moniton Power-on OF7h (Tag Register 0) and OF8h (Tag Regis- Clears this Di ter 1) in the CRT Controller. They can be D1 Divide Vertical Counter: D1=0 accessed by first writing OF7h/OF8h in the causes the vertical counters to be CRTC Address Register (I/O address 3B4h/ incremented every scan line. D1=1 3D4h) and then accessing the CRTC Data causes the vertical counters to be Register (I/O address 3B5h/3D5h) incremented every two scan lines. This bit should be set to 1 when it is A bit in these registers is set whenever the desired to double each scan line corresponding register is written into. When (running 200 scan line software on. traps are enabled, then any bit set in the two a 400 scan line monitor). Power-on Tag Registers will cause a trap. When emula- reset clears this bit. 820435 38

—_—.1.

02 LSB - Display Buffer Width: This is trace Start and End Registers when

the complement of the least signifi- reading CRTC Registers CRE, CRF, cant bit for the Display Buffer Width CR10 and CR11 respectively. D7=1 (CRTC Offset Register CR13). This returns the contents of the Cursor allows byte resolution on the Dis- Location High and Low Registers, play Buffer Width. and Light Pen High and Low Regis- D3 Enable CGA Overscan: 03-0 dis- Re Car, cing CRTC Registers CRF, and CR11 respec- ables the CGA overscan (border) tively. On reset, this bit is set to 1 feature. This is useful when running " CGA software on a 21,8 KHz moni- TEMPORARY STORAGE REGISTERS tor, when it may be desirable to There are five byte wide temporary storage disable the borders. D3=1 enables read-write registers in the 82A436. These this feature, This bit is effective registers are located at offset OFAh-OFEh in only in 80 column text mode. the CRT Controller data register space. These ba Select Overscan Register: D4=0 se- registers can be accessed by first writing lects the CGA Color Select Register OFAh/OFBH/OFCh/OFDH/OFE in the CRTC. (hardware palette) as the source for Address Register (I/O address 384h/3D4h) the border color. D4=1 selects the and then accessing the CRTC Data Register Attribute Controller Overscan Color (VO address 3B5h/3D5h). These registers can Register as the source for the border be used as working registers color. This bit is ignored in the EGA EMULATION MODE REGISTER (CRFF) mode. Read-Write Register Ds Horizontal Double: D5-0 causes the —_—‘1/O Address: 385h/3D5h CRTC to generate a 640*200 display Address Pointer: FFh when programmed for a 320*200 display. D5=0 generates a 320*200 (poe [osTo<]os oa]: Joo} display. When emulating the 640*200 CMBLE con EMULATION CGA mode, it is easiest to algo- | ENABLE MONO/HERCULES EMULATION * rithmically translate the 6845 para- ewuLsrion in proaness#® meters to EGA CRTC parameters | in the 320*200 mode. Setting this | SIABLE Ca wamowane PALETTE bit to 0 results in a 640*200 display. || EMULATION TYPE DESIRED This bit is used only when emulating | = enaare rears 640*200*1 CGA graphics mode. For ———— emance care necisten accesses all other modes, this bit must be Laue seesneciaren wnrve Programmed high * (20425 AND 820436)

06 Disable CGA/MDA Blanking: D6 = 1,

disables the functionality of the The Emulation Mode Register is located at Display Blanking feature of the CGA offset OFFh in the CRT Controller. This regis- and MDA Mode Control Register— ter can be accessed by first writing OFFh in bit 03 of MDA CRT Control Register the CRTC Address Register (I/O address (VO address 3B8h) and bit D3 of 3B4h/3D4h) and then accessing the CRTC CGA Mode Control Register (1/0 Data Register (I/O address 3B5h/3D5h) address 3D8h). D6 = 0 enables this functionality The description for the individual bit fields is as follows: v7 Alternate Read Select: D7=0 returns the contents of the EGA Miscelia- Do Enable CGA Emulation: This bit neous Output Register, EGA Feature determines if CGA Emulation is to Control Register, and Vertical Re- be enabled (=1) or disabled (=0) —_—_ 39 82C435

01 Enable Mono/Hercules Emulation cating that CGA emulation is de-

This bit determines if Monochrome/ sired. If Mono/Hercules emulation Hercules Emulation is to be enabled is enabled (D1 of this register) then (1) or disabled (=0) any access to 1/O address 3B8h To automatically allow switching causes this bit to be set to one between EGA. CGA and Hercules indicating that Monochrome/ emulation modes, CRFF bits D0 and Hercules emulation is desired. D1 must be set as follows: Ds Enable Traps: A one in this bit generates a trap indicating proces- sor support required for emulation D1 DO Switching between whenever emulation is enabled and oe software desires a change in mode 0 0 Lock into EGA mode only. A zero in this bit disables the traps. i?) 1 Allow auto-emulation between EGA and CGA A trap is generated under any one mode only of the following conditions 10 slow auto emulauen a) Write to /O address 38Fh when modes only Emulation Mode Register bit D1=1 + 1. Anow suto-emulation (Hercules emulation enabled and between EGA OGA and access to Hercules Configuration Hercules modes. Register) b) Write to 1/0 address 388h when D2 Emulation in Progress: This bit de- Emulation Mode Register bit termines if the 82C436 is currently D1=1 and bit D2= 0 (Currently in in the CGA or Hercules emulation EGA mode, Hercules emulation mode (<1) or in the normal EGA enabled and access to Hercules mode (=0). This bit must be set Mode Control Register). while CGA/MDA/Hercules emula- ¢) Write to 1/0 address 388h when tion is in progress Emulation Mode Register bit D1=1, bit D2=1 and bit D4-0 Ds Enable CGA Hardware Palette: A (Currently emulating CGA and one in this bit selects the CGA Color access to Hercules Mode Con- Select Register (at I/O address trol Register) h) to generate the colors to be displayed A zero in this bit causes 4) Write to 1/0 address 3B8h when colors to be selected from the EGA Emulation Mode Register bit Attribute Controller Palette. When O1=1, bit D2=1, bit D4=1, Her- this bit is set to 1, then TAG Regis- cules Mode Control Register bit ter 1 bit 7 (CGA Color Select Regis- 08-1 and bit D1 toggles (cur- ter is disabled) rently emulating Hercules, video enabled and switch between text Da Emulation Type: This is a read only and graphics modes). bit that indicates what type of emu- €) Write to 1/0 address 308h when lation is desired by the application Emulation Mode Register bit software. If CGA emulation is en- DO=1 and bit D2= 0 (Currently in abled (D0 of this register) then any EGA mode, CGA emulation access to /O address 3D8h will enabled and access to CGA cause this bit to be set to zero indi- Mode Control Register). 82C435 40

a f) Write to 1/0 address 3D8h when registers and D6=0 reads the 6845 Emulation Mode Register bit registers. DO-1, bit D2=1 and bit D4=1 (Currently emulating Hercules br Enable 6845 Registers: A one in this, and access to CGA Mode Con- bit causes data writes to I/O address trol Register) 3B5h/3D5h to be directed to the 6845 registers. Simultaneously set- 9 fre to VO address 308h when ting D6 and D7=1 causes both the mulation Mode Register bit CATO ond peas DO=1, bit D2=1, bit D4=0, CGA an registers to be Mode Control Register bit D3=1 written and any one of bits D0,01,02 or D4 change state (currently emu- lating CGA, video enabled and OTHER EGA REGISTERS mode switch). ee h) Write to 1/0 address 309 when Register Name Address Emulation Mode Register bit tT DO=1 and bit 03-0 (CGA emul. EGA Miscellaneous Output 3C2h tion enabled. CGA hardware Feature Control Register 3BAN/3DAh palette disabled and access to Input Status Register 0 3C2h CGA Color Select Register) Input Status Register | SBAh/3DAh )) Write to any one of /O ad- EGA MISCELLANEOUS OUTPUT REGISTER dresses 3C0h, 3C2h, 3C4h, 3C5h, Read/Write Register 3CAh, 3CCh, 3CEh or 3CFh VO Address. 362h when Emulation Mode Register bit D2=1 (currently emulating or Jox[os]oe]os]o[or[55) Hercules or CGA and access to TL veavoness seuccr« any EGA only register) | cwance nam i) Write to /O address 3B5h when | toc sececr o# Emulation Mode Register bit | cuoce seuecr ve D7 = 1, EGA Misc. Output | | Register bit DO 0 and Okra | L____ assaace mreona voto Address Register = 00 through i aceset OBh (emulating Hercules/CGA | — Have povaarTy and access to the Hercules 6845 —_ mvc povanres Data Register) act ano ean) k) Write to 1/0 address 35h when Emulation Mode Register bit The EGA Miscellaneous Output Register is D7 = 1, EGA Misc. Output normally a write only register. It can be read Register bit DO = 1 and CRTC by setting the alternate read select bit in the Address Register = 00 through 400 Line Register (CRF9 bit D7 = 0) and then OBh (emulating Hercules/CGA reading CRTC Data Register at offset OFh and access to the CGA 6845 The 1/0 Address Select bit (DO) can aiso be Data Register) read at bit DS of the Sequencer Address Register (I/O address 3C4n). This register

06 Enable CRTC Registers: A one in performs the following functions:

this bit causes data writes to /O address 3B5h/3D5h to be directed Do This bit maps the CRT Controller to the CRT Controller Registers. For adress and data registers into the data read operation at 1/O address SBxh/3Dxh address space. This bit 3B5h/3D5h, D6-1 reads the CRTC defauits to 0 on reset and is present ee 4 82C435

in both the 82C435 and 82A436. FEATURE CONTROL REGISTER Setting this bit to 0 or 1 maps the Read/Write Register registers as follows. W/O Address: 3BAh/3DAh a IOS NO IoIGT VO Address ] FEATURE CONTROL ort o* for Register Name 6 Do-1 yy fs FEATURE CONTROL Orr 1 CRTC Address Register 1) seseneoo (82C435/82A436) 3B4h = 3D4h | '—— FESERVED 6 CRTC Data Register a (820435/82A436) 3B5h 305 Feature Control Register {| (82C435/82A436) 3BAn 3DAn | (ap nr use Input Status Register 1 (82C435/82A436) 3BAh 3DAh a

01 D1 = 0 prevents the CPU from neon

accessing the EGA display memory. The Feature Control Register exists in both D1 = 1 allows such accesses the 82C435 and the 82A436, This is normally a write only register in the 824436. It can be. D2-D3 D2-D3 bits are output on the read (in the 82C435) by setting the alternate CLKSELO and CLKSEL! pins on the read select bit in the 400 Line Register (CRF9 82A436, Typically these are used to bit D7= 0) and then reading the CRTC Data externally select the clock source Register at offset OE. Feature Control Bits 0 for the 82C435. These bits are pres- and 1 from this register are also output on ent in the 82C435 so that this register 82A436 output pins FCOUTO and FCOUT1 can be read correctly respectively. These pins are typically used to drive the EGA Features Connecter. Da Disable Internal Video: This bit is used in the 824436. It is also present INPUT STATUS REGISTER 0 in the 82C435 so that this register Read Only Register can be read correctly. VO Address: 3C2h DS Since the 82C435 does not support erJoeJos]os]es]oxJo: oe]

64 Kbytes of display memory (it |

requires 256 Kbytes) this bit must - always be 1 | | | LL prer uss 06 6 selects the polarity for the Horiz- | | ontal Sync pulse | L__ gwaret sense an e2aase

0 Positive horizontal sync pulse ——-— renvume coe oun a2asay

1 Negative horizontal sync pulse Lo pearune co + zac

o7 D7 selects the polarity for the Verti- as or mreney cal Sync pulse. Parts of the Input Status Register 0 exist in 0 Positive vertical sync pulse both the 82C435 and the 82A436. The data

1 Negative vertical sync pulse path to the CPU from the 82C435 always

goes through the 82A436. When the CPU. reads this register, the 824436 reformats the status data put out by the 82C435 and passes the final status to the CPU. ese 820435 42

Switch Sense (D4 - in 824436) the horizontal and vertical retrace interval. In This bit returns the current status of the Hercules emulation mode this bit is driven by 82A436 input pin SWITCH to the CPU. Typi- the 82A436 and it indicates the current level cally, the CPU scans the state of the DIP of the 82C435 Horizontal Syne signal, HIN. switches on the EGA board through this bit, Light Pen Strobe (D1 - 824436) Feature Code 0 and 1 (D5-D6 - in 82A436) D1 is driven by the 824436 and indicates the These two bits return the current status of the state of the Light Pen Latch. This latch is set 82A436 input pins FEATINO and FEATIN1 whenever a valid Light Pen pulse is generated. respectively. These bits are typically used to read the status information from the EGA Light Pen Switch (D2 - 824436) Board Feature Connecter D2 is driven by the 824436 and indicates the state of the Light Pen Switch (on the Light CRT Interrupt (D7) Pen Connecter.) 07 is a reflection of the CRTINT output from the 82C435. This bit is 1 if the CRTINT pin is Vertical Retrace/Video (D3) high. CRTINT is enabled through bit D5 of In EGA mode, D3 is an active high vertical CR11. Once CRTINT goes active, it can only retrace signal, which is functionally the same be reset through bit D4 of CR11 as the active high Vertical Sync output (VIN) from the 82C435 (the polarity of this bit is INPUT STATUS REGISTER | always positive). In CGA emulation mode, D3 (CGA/HERCULES STATUS REGISTER) is driven by the 82A436 and is same as the Read Only Register Vertical Sync output from the 82C435. In 1/0 Address: 3BAh/3DAh Hercules emulation mode D3 is driven by the 82A436 and it indicates the current status of [e7JosTosTo«Jos [ox]or Joo) the Video (Secondary Blue) signal from the OISPLAY ENARLE:MSYNC OUTPUT # 820435, | Lec season Color Palette Output (D4, D5) venricas nevaace vioeo # D4 and DS are two bits of the six bit video | output from the color palette. Two of these 6 | coroners ourura bits can be selectively read by the CPU colon paverre outeur + through bits 04 and D5 of Input Status Regis- (nor useo ter |. The two output signals to be multiplexed eric oureur oan are determined by the contents of the Attri- ezcess ana ezaase, butes Color Plane Enable Register (AR12). These bits are valid only in the EGA mode. In Parts of the Input Status Register | exist in the CGA and Hercules modes, the 82A436 both the 82C435 and the 82A436. The data always drives these bits high. path to the CPU from the 82C436 always goes through the 82A436. When the CPU reads Vertical Sync Output (D7) this register, depending on the current emula- This bit is valid only in the Hercules emulation tion mode, the 82A436 reformats the status mode. In this mode, D7 indicates the current data output by the 82C435 and passes the level of the 82C435 Vertical Sync signal (to final status to the CPU. the monitor). In the EGA and CGA modes. this bit is always high Display Enable/HSYNC Output (D0) In EGA and CGA modes, D0 is an active low Display Enable signal generated by the 82C435. A logical 0 indicates the active dis- play interval. This bit is returned high during 43 82C435

BACKWARD COMPATIBILITY Do CGA 80/40 Column Mode: This bit REGISTERS is effective only when CGA emula- tion is in progress. DO = 0 selects 40 To complete the register description, there column CGA text mode. DO = 1 are some additional registers in the 82C435/ selects 80 column CGA text mode 82A436. These registers are D1 Hercules/CGA Graphics/Text Mode a D1 = 0 selects the text mode and 1/0 Address Register D1 = 1 selects the graphics mode This is effective for both CGA and 388h/3D8h —_Hercules/CGA Mode Control Hercules emulation modes Register (in 82C435) 3D8h CGA Color Select Register D2 CGA Black & White/Color Mode (in 820435) This bit is effective only when CGA 389h/3DCh _ Set Light Pen Latch (in emulation is in progress, D2 - 1 820436) selects CGA Black & White mode, 3BBh/3DBh —_Clear Light Pen Latch (in D2 = 0 selects CGA color mode. 82A436) 3BFh Hercules Configuration D3 Hercules/CGA Video Enable: 03 Register (in 820435) 1 enables the video signals. D3 = 0 blanks the screen. This is effective for both CGA and Hercules emula- HERCULES/CGA MODE CONTROL REGIS- tion modes. TER Read/Write Register Da CGA High Resolution Mode: This VO Address: 388h/3D8h bit is effective only when CGA emu- lation is in progress. D4 = 0 selects Wee [eeToTosTos Toe) the 320 * 200 CGA graphics mode, ] COA #0 49 COLUMN MODE D4 = 1 selects 640 * 200 CGA HERCULES CoA GRAPH TEXT MODE graphics mode. on A TE COON MOE DS Hercules/CGA Text Blink Enable: MEREULES CGR VIDE ENABLE DS = 1 enables the character blink GA WiGH RESOLUTION MODE attribute. D5 = 0 disables the cha- | HERCULES CGA TEXT BUNK ENABLE racter blink feature and the blink wor useo attribute bit is used to control back- ground intensity. This is effective HERCULES PAGE SELECT for both CGA and Hercules emula- All the bits in the Hercules/CGA Mode Con- tion modes trol Register are effective only when emula- 7 Hercul This bit i tion is in progress (CRFF bit D2 = 1), When Thoctue opie hes taveulbe emule. CGA emulation is in progress (EGA Misc. tion is in progress. D7 ~ 0 selects Output Register bit DO = 1), then this register the lower part of memory (address functions as the CGA Mode Register and is B0000h onwards) in the Hercules located at I/O address 3D8h. When Hercules Graphics Mode. D7 = 1 selects the emulation is in progress (EGA Misc. Output upper part of the memory (address Register bit DO = 0), then this register func- B8000n onwards) tions as the Hercules Mode Register and is located at 1/O address 3B8h. 82C435 44

a CGA COLOR SELECT REGISTER D4 Alternate/Background: Selects alter Read/Write Register nate intensified colors in CGA V/O Address: 3D9h graphics mode. Selects background colors in CGA text modes. T] | [S BLUE BORDER BACKGROUND Ds Select Color Set: Selects colors in | | ncen sono 84cKoROUND CGA 320+200 graphics mode. The | aco sonotn eacrcnouno colors are generated as follows | -— nrernare eacxcnouno Pixel Pixel ——~ setecr covon ser D5 Bit 1 Bit 0 Color Lo nor useo a) 0 Background ae ~ Nor useo (=D0-D3) 0 0 1 Green This registers serves as the CGA hardware 04 0 Red palette register. This register is effective only o 1 1 Brown when emulation is in progress (CRFF bit 2 = 1 0 0 Background 1). This register can be disabled through the (-D0-D3) Emulation Mode Register (CRFF bit D3 = 0) 1 0 1 Cyan 144 0 Magenta Do Blue Border/Background: Selects 14 1 White blue border in 40*25 CGA text mode. Selects blue background in CGA SET LIGHT PEN LATCH (in 824436) 320%200 graphics mode. Selects Write Only Register blue foreground in CGA 640+200 VO Address: 30Ch/389h graphics mode. The Set Light Pen Register is used to trigger DI Green Border/Background: Selects the Light Pen from software. In the EGA green border in 40+25 CGA text mode, this is done by an I/O Write to address mode. Selects green background 3DCh. In CGA mode, the Light Pen is trig- in CGA 320%200 graphics mode. gered by an I/O Read or I/O Write to address Selects green foreground in CGA 3DCh. In Hercules mode, this is done by an 640200 graphics mode. W/O Write to address 3B9h

02 Red Border/Background: Selects red CLEAR LIGHT PEN LATCH (in 824436)

border in 4025 CGA text mode Write Only Register Selects red background in CGA VO Address: 3DBh/3BBh 320%200 graphics mode. Selects red foreground in CGA 640*200 graph- The Clear Light Pen Register is used to clear ies mode the Light Pen Latch. In the EGA mode, this is done by an I/O Write to address 3DBh. In D3 Intensified Border/Background: Se- CGA mode, the Light Pen is triggered by an lects Intensified border in 40*25 '/O Read or \\/O Write to address 3DBh. In CGA text mode. Selects intensified Hercules mode, this is done by an I/O Write background in CGA 320+200 graph- to address 3BBh ics mode. Selects Intensified fore- ground in CGA 640+200 graphics mode. a 45 82C435

—$ $s HERCULES CONFIGURATION REGISTER addresses are generated as required by an Read/Write Register internal 16-bit memory address counter W/O Address: 3BFh (MAO-MA15). All DRAM refreshes are done. during the horizontal blanking period. The is ox[oi]o fos]: o0) refresh is done by reading the display | ] T euaace omapwics wove memory. The refresh addresses are generated — enance wemony pace + by an internal refresh counter. For CPU ac- bp Lo cesses to display memory, the 82C435 gener- yy de ates the DRAM row and column addresses as | — required by the CPU (A0-A16). } Lt - — freee The DRAM row/column addresses are gener- | ated as follows: The Hercules Configuration Register is effec- AAT ARG AAS AAS AAS AAZ AAT AAO tive only when Hercules emulation is in pro- BAT BAS BAS BA4 BAS BA2 BAI BAD gress (CRFF bit D2 = 1) and EGA Misc Output AT Ab AB Ak OAS AZ At AO No Chaining Register bit DO = 0. Bits DO and D1 are read AT AB AS Ad AS AZ AT ANB Chained & at bits D6 and 07 respectively in the Se- CDSELO.1=00 quencer Address Register (1/O Address 3C4h). AT AB AS AS AB AZ AT PAGESEL Chained & CDSELO.1-01. bo Enable Graphics Mode: D0 = 0 locks ton the 82C435 in the Hercules/MDA COLUMN ADDRESSES FOR CPU ACCESS text mode. In this mode, the CPU AAT ARG ARS ARS AAS AA AAT AAO has access to memory only in the BAT BAS BAS BAS BAS BAZ BAI BAO address range 80000h-BOFFFh AIS AB AIS AI AIT AIO AQ ANE

1 Enable Memory Page 1: DO = 0 pre- ROW ADDRESSES FOR CRT ACCESSES

vents the setting of Page Select bit GRAPHICS MODE) (07 in Hercules Mode Control AAT AAS ARS AMA AAS ARQ AAT AsO Register). This also restricts memory GA? GAS BAS BAS BAS BA2 BA) BAO usage to address 80000h-B7FFFh DO = 1 allows setting of the Page MAT MAB MAS MAd MAS MA2 MAI MAO Select bit and enables the use of COLUMN ADDRESSES FOR CRY ACCESSES cout the upper part of the display Saatnce aces. memory (address B8000h-BFFFFH) AAT ARG ARS AAS AAS AA2 AAI AAO MEMORY ADDRESS GENERATION BAT BAS BAS GAS BAI BAZ BAT BAD The 82C435 serves as a DRAM controller for MAIS MAB_MAI3 MAI2 MATS MA10. MAS. MAt4 the 256 Kbytes. of display memory required by the EGA. The 82C435 is responsible for ROW ADDRESSES FOR CRT ACCESSES (TEXT MODE) DRAM refresh, fetching of display data (text AAT AAG ARS AAS AAS AA2 AAI AAO and graphics mode) from the display memory, and controlling CPU accesses to the display MAT MAG MAS MA4 MA3 MAZ MAT MAO memory. All the DRAM control signals are SA7 BAS BAS BAA BAI BA2 BAI BAO generated by the 82C435. The 82C435 inter- faces to the DRAMs using a multiplexed row cc2 CCI CCO AS’ ASS AS2 AST RSO address/column address/data bus. When the 82C435 accesses the display memory to fetch data to transfer to the screen, the DRAM ss 82C435 46

| $A Aa ‘COLUMN ADDRESSES FOR CRT ACCESSES Offset Register contents as described earlier (TEXT MODE) under register description. ART AAS AAS AA AAS AA2 AAI AAO SOFT SCROLL MAIS MAB MATS MAIZ MA11 MAIO MAS MA14 The CRT Controller offers soft scrolling capa- BAT BAS BAS BAd BAS BA2 BAI BAO bility by pre-setting a value in the Preset Scan Register, CR8. Figure 10 shows a typical Fs1 ccs 0 ce? CoB CCS CCA FSO example of how this can be achieved. As described in the CRT Controller section, the Oo Mnipieees Meer, agiemme Gus fon E2049 Start Address Registers CRC and CRD define FSx—Font Select Codes as programmed in the Sequencer ‘on the screen. MAx—Memory Address/Refresn Counter Outputs ©Cx—Character Code In the text mode, the start address is the address of the first character which will be DISPLAY MEMORY REFRESH displayed in the first row. The Preset Scan The 82C435 automatically generates contro! Row Register defines the top scan line for the signals to refresh the display memory. The first character row on the screen. By incre- refresh is performed using the horizontal menting CR8, the screen will appear to scroll blanking period. There is an internal eight bit upwards one scan line at a time. When CRB refresh row address counter in the 82C435. becomes equal to CR9 (maximum scan line), Every horizontal blankng period, this counter then CR8 should be reset to 0 and the Start is used to generate six read cycles with incre- Address Registers (CRC and CRD) should be mentng row addresses. The user should al- updated to start with the next character row. ways program the horizontal parameters in the CRT Controller, so that six refresh cycles The Preset Scan Register should be set to per horizontal blanking period is sufficient to zero for graphics modes. In this mode the meet the refresh specs for the DRAMs being vertical scrolling can be controlled by up- used. dating the Start Address Registers only SPLIT SCREEN CURSOR CONTROL The CRT Controller is capable of displaying The height of the CURSOR is programmable split screens. Figure 9 shows a split screen through registers CRA and CRB. The memory display. The two screens, Screen 1 and Screen address of the CURSOR 1s programmable 2, are created by properly setting the Memory through registers CRE and CAF. Figure 11 Address Registers (CRC and CRD) and the shows how the CURSOR height is controlied Line Compare Register (CR18). The CRC and by setting the horizontal scan line equal to CRD register contents specify the memory the contents of CRA and CRB registers, address for the first pixel to be displayed on the active screen. The start address for Screen VERTICAL INTERRUPT 1 in figure 9 is determined by the contents of The 82C435 generates an interrupt at the end the registers CRC and CRD. Split screens are ota vertical display The Vertical Display End created with the use of Line Compare Register Register CR12 controls the lime vines the CRI8. The internal display memory address interrupt becomes active, if the interrupt en- Counter is cleared when the absolute scan bie bit was cleared in the Vertical Retrace line counter reaches the value equal to the. End Register CR11. The interrupt can be used contents of CRIB. Thus Screen 2 in figure 9 5 ne GPL to update the BoC eds during the Starts at display memory address 0000. The 2utical blanking intorvel linear address generator addresses the display : buffer sequentially starting at OOOOH. Each subsequent row address is determined by the es 47 82C435

$$$ CGA/MDA/HERCULES b) software access to certain hardware regis- COMPATIBILITY ters, these include the CGA Color Select Register (at I/O address 3D9h), the Status Compatibility with the CGA, MDA and Her- Register, the 6845 Cursor Position Regis- cules display subsystems is required to be ters (Registers OEh and OFh) and the 6845 compatible with older software that does not Start Address Registers (Registers OCh support an EGA. There are two levels of and 0Dh) compatibility. ¢) software access to the other hardware registers, including the mode registers and a) Compatibility at memory interface and the video timing (6845 internal) registers. higher level mode selections, The 82C435/82A436 provide a direct hardware >) Compatibility at direct register level interface to the software at levels a) and b) described above. Software accesses to the The 82C435/82A436 allow compatibility at registers at level c) described above are very both levels described above. infrequent. Typically most accesses to these registers is done through the BIOS and the The memory interfaces required are BIOS on the display board should program the EGA registers properly to correspond to cone Column Text ees oon the CGA/MDA/Hercules display modes. In CGA 80 Column Text 8 Kbytes at the event of some software that directly ac- Mode aadrece 88000 cesses these registers, the 82C435/82A436 CGA 160+100 Graphics 16 Kbytes at require some assistance from the CPU. Mode address B8000h CGA 320+200 Graphics 16 Kbytes at Any software that is configured to run with a Mode address B8000h CGA/MDA/Hercules board that programs 2 scan bank format registers on the video boards directly, acces- CGA 640+200 Graphics 16 Kbytes at ses the registers at I/O addresses 3B8/3D8h Mode address B8000h Mode Register, 3BFh Hercules Configuration 2 scan bank format Register, 3B4/3D4h - 6845 Index Register and MDA/Hercules Text 4 Kytes at 3B5/3D5h - 6845 Data Register. Mode address BOO00h Hercules Graphics 32 Kbytes at The 6845 Index Register is present in hard- Mogesal a sen benk format ware on the 82C435. The EGA CRT Controller registers are mapped to the same address Hercules Graphics 64 Kbytes at Mode-Full address 80000h space as the 6845 registers. Of the 18 regis- 4 scan bank format ters in the 6845, 7 have a direct one-to-one correspondence with the registers on the EGA The 82C435 supports text mode memory CRT Controller (Registers OCh-11h). The organizations required by the CGA and the other registers on the 6845 however do not Monochrome/Hercules boards. have a one to one correspondence with the EGA CRT Controller registers. From a software point of view, the accesses that the software makes to the hardware can The CPU has to in this case transform the be categorized as follows (in order of fre- register contents of the 6845 registers and quency of occurrences) write them into the EGA CRT Controller. To assist in the transform process, the 82C435 a) software access to display memory - this has an alternate bank of 11 registers corres- is done to update the character codes and ponding to 6845 Data Registers 0-08h, OAh attributes in the text mode and to set the and OBh. These registers are called 6845 pixel pattern in the graphics modes. Registers. In the emulation mode all CPU a 49 82C435

——. accesses to I/O address 3B5h/3DSh (6845/ 6845 REGISTERS CRTC Data Register) are directed to the CRT Controller Register or the 6845 registers (or INDEX REGISTER both) depending on the contents of the Emu- 0 bits 6-0 of Horizontal Total Register lation Mode Register in the 826435. Whenever 1 bits 6-0 of Horizontal Displayed a 6845 register is written into, a trap to the Register CPU is generated in the form of a Non- 2 bits 4-0 of Horizontal Sync Position Maskable Interrupt. The Emulation Mode Register Register also enables or disables such traps. 3 bits 7-0 of Horizontal Sync Width On a write to a 6845 register, a bit is also set Register in one of two Tag Register in the 82C435. 4 bits 6-0 of Vertical Total Register There is one bit in the Tag Registers for each 5 bits 4-0 of Vertical Total Adjust of the 6845 registers, Mode Control Registers Register and the unique EGA-only Registers 6 bits 6-0 of Vertical Displayed On receipt of an NMI, the CPU should first Register read the TAG Registers which will indicate 7 bits 6-0 of Vertical Sync Position which register access generated the trap and Register requires emulation help. This can also be. 8 bits 5, 4, 1 and 0 of interlace used to automatically switch from one emula- Mode Register tion mode to another emulation mode or to Ah bits 6-0 of Cursor Start Register the normal EGA mode. if none of the bits in Bh bits 4-0 of Cursor End Register the Tag Registers are set, it means that the NMI was not generated by the video board but by some other source (eg parity error) The CPU should then be directed to the old NMI handling routine. The emulation software when loaded, redirects the PC NMI vector to point to the emulation software. The old NMI vector can be stored in temporary storage registers in the 82A436 allowing for a safe way to store the old NMI vector Traps to the CPU can also be selectively enabled on accesses to the CGA/MDA/ Hercules Mode Registers, the CGA Color Palette and the unique EGA-only Registers. Thus it is possible to let the board automa- tically detect if software wants to use an EGA/CGA/MDA/Hercules modes on the board. It is also possible to disable all the emulation and lock the board in the 100% EGA mode. One advantage of using the NMI to trap CPU accesses to the 6845 is to allow CGA text mode emulation on the enhanced 350 scan line monitor. In this case although the software selects a 200 scan line display, the emulation software can still cause higher quality character to appear on the screen. Sa 82C435 50

iS | aA Absolute Maximum Ratings ee Parameter Symbol Min. Max. Units ——SSd OOO Supply Voltage Voo = 70 Vv ——— Input Voltage vi -0.5 Vp 0.5 V eee eee SM 05 OV Output Voltage Vo -0.5 Vpn +0.5 en eee OSV Operating Temperature Top -25 85 c eovmn”z”:v_ OI Storage Temperature Tst6 -40 125 c 82C435 Operating Conditions Parameter Symbol Min. Max. Units ——S.o $a eet Supply Voltage Voo 4.75 5.25 v —SSsSeSeseses SAS Ambient Temperature Ts 0 70 °C ——OE—eEO A 82C435 DC Characteristics Parameter Symbol Min. Max. Units —— sq EEO TEE Input Low Voltage Vi 08 v Input High Voltage Vie 2.0 v I Output Low Voltage lous = 2mat Vou 0.45 v lova = 4mA? lov3 = 8MAS loug = 4m At th eee Output High Voltage Ioy,; = 2mAt Vou 3.5 v lone = AMA? lon = BMAE ~One a Se Input Leakage Current he -100 +100 uA ron OA Power Supply Current loc 100 mA @ 25MHz CLKIN, OC — eee Output High Impedence Leakage loz -100 +100 uA 0.45 < Vain < Voo IN NOTES: 1. 2 mA source and sink drive on pins ERMEN, CDSELO-1, CCLK, DOTCLK. VALRAD. BS/V. GS/I 4. 4 mA sink drive only (open grain) on pins DATAg ; —_.] 51 82C435

(Tq = 0°C-70°C, Vpp = 5V 15%) CLKIN Timings Parameter Symbol Min.(ns) CLKIN Period te 40 CLKIN High time toy 1,/2-5% CLKIN Low time toy 1,/2-5% Video Timings Parameter Symbol Max.(ns) VIN, BLANK delay from CLKIN ban 150 HIN delay from CLKIN bin 100 VIDEO delay from CLKIN bag 66 Other Timings Parameter Symbol Min.(ns) LPENSTB Pulse Width 119 100 RESET Pulse Width 120 64 In CLKIN/2 mode, 120 must be 128 t, minimum 1/0 Bus Timings Parameter Symbol Min.(ns) Max.(ns) MIORD, MIOWR Pulse Width "1 200 MIORD, MIOWR to RDY Low delay 12 50 Address setup to MIOWR (I/O Write) 13 80 Address hoid from MIOWR (I/O Write) 4 80 Address setup to MIORD (I/O Read) 13 20 Address hold from MIORD (I/O Read) 14 20 Address setup to MIORD/MIOWR (Memory) t3 20 Address hold from RDY (Memory Read/Write) t4a i Trap delay from MIOWR 1s 150 MEMIO setup to MIORD/MIOWR 6 20 820435 52

1/0 Bus Timings (Continued) Parameter Symbol Min.(ns) Max.(ns) MEMIO hold from MIORD/MIOWR 7 5 1/0 Write Data setup to MIOWR ‘8 45 V/O Write Data hold from MIOWR 9 60 \\/O Read Data delay from MIORD. 110 150 1/0 Write Data hold from MIORD ut 5 90 ROY high time 12 05t, Memory Read Data setup to RDY U3 1.5t, Memory Read Data hold from MIORD. 14 20 Memory Write Data setup to ROY 115 6te Memory Write Data hold from RDY 16 1.5te VALRAD delay trom Address u7 60 CDSELO,1 delay from MIOWR 18 200 RDY width t21 6t, 42, DRAM Timings High CPU Bandwidth Mode Parameter Symbol Min.(ns) Max.(ns) Read/Write Cycle time (read) tre Ste RAS Pulse Width (read) tras 3t,-8 Read/Write Cycle time (write) be 6t. RAS Pulse Width (write) tas 4t, -8 Column Address Hold from RAS. tar 1.5t, +10 RAS precharge tip 2t. -B CAS to RAS precharge erp te +3 CAS hold trom RAS tosh at, -3 RAS to CAS delay trea 0.5t, +4 RAS hold from CAS. tish 2.5t, -28 CAS Precharge toon 15t, +7 CAS Pulse Width teas 3.5t, -23 Row Address Setup to RAS tase 0.5, -5 Column Address setup to CAS, tase 1 Row Address hold from RAS tran 0.5, Column Address hold from CAS tean te 53 82C435

a DRAM Timings High CPU Bandwidth Mode (Continuec) Parameter Symbol Min.(ns) Max.(ns) Data Access time from CAS. teac 24, -26 Data Access time from RAS trac 2.5t, -3 WE Pulse Width twp te -7 Write Data Setup to WE tas 0 Write Data Hold from WE ton tS Write Data Hold from RAS tone 2.51, -10 WE hold from CAS twon 2t, -7 WE hold from RAS twee 2.5t, +2 WE lead to RAS tow! te-14 WE lead to CAS tow! te 6 DRAM Timings Low CPU Bandwidth Mode Parameter Symbol Min.(ns) Max.(ns) Read/Write Cycle time (read) tic bt RAS Pulse Width (read) tras 3.5t. +1 Read/Write Cycle time (write) be 8, RAS Pulse Width (write) as 5.5to-1 Column Address Hold from RAS tar 2.51. +8 RAS precharge tp 25t, -2 CAS to RAS precharge tor 1.43 CAS hold from RAS tesh St, -3 RAS to CAS delay trea 0.5t. +5 RAS hold from CAS tes 3t, -8 CAS Precharge topa 1.5t. +6 CAS Pulse Width teas 4.51, -13 Row Address Setup to RAS tase 0.5t, -5 Column Address setup to CAS tase 1 Row Address hold from RAS tran O5t. Column Address hold from CAS tean 2te Data Access time from OE loca te-10 SSS 820435 54

$$ eee DRAM Timings Low CPU Bandwidth Mode (Continued) Parameter Symbol Min.(ns) Max.(ns) xs) Data Access time from CAS teac 2t, -16 =r ewe eG Data Access time from RAS trac 3.5t, -6 WE Pulse Width two 1.5t, -23 I Write Data Setup to WE tas 0 nO Write Data Hold from WE ton t.-5 —— ees te Write Data Hold from RAS. tone 2.5t, -10 pa Rha WE hold from CAS ton 3.5t, -14 WE hold from RAS ter 41, -4 ST WE lead to RAS tra 1.5t,-3 ee WE lead to CAS tow 2.5t, -8 eae ows eB Compatibility with DRAMs Maximum CLKIN frequency for RAS access time High ew CPU Bandwidth Mode CPU Bandwidth Mode 150ns 16.5MHz 20MHz 120ns 20MHz 25MHz 100ns 20MHz 25MHz ae II MH CLKIN TIMINGS VIDEO TIMINGS To RESET TIMINGS te nG.8. HOUT ptvio Twn HIN Le Tn VIN, BLANK LiGHTPEN TIMINGS: poe a 55 820435

CHiPs. V/O BUS TIMINGS an Eid mown

2 Cee

emo Cp) ADDRESS —— —Saa ee Taap es —4 TOCrcLES ony TH See patch 77727LELLL ALLL LLL LLL 2) TTT Ts. hee oaTA TO a D Ta — | Ta BOY wm -_ THEORY CvcLes onty hs aa REND DATA o> YD eee Ths waite DATA >?) Ta —| coseLes a TW cc SSSSSsSsSSSSSSSSsSsSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS 82C435 56

J READ CYCLE DRAM TIMINGS Tre ‘Tras: Trp ~ Tan Tore a Tom — [| CAS /aiiad nia SB O00 IND CUM SLINED O00: now couuwn ASdness Robness Teac __ a | oes - __ Toes oe WRITE CYCLE eee Tras Tap: TAR RAS CAS Er ne ADORESS/DATA 2s SC CUT ROW — COLUMN ~/ AbonEss —KooRESS | Twer- WEO, WE? Tos Ton WET. WES Tow 57 820435

eas —a a ADDRESS’ Row ABORKCOLUMN ADDRESS KDATAD2K7/KOATA 13X77 )K ROW ADDRESS. O02 (OE13 — WRITE CYCLE reef —__] Teas nal Tcan——>| eTASC Tour Tash ADDRESS, [COLUWN ADDRESS _XONTADE DATALS RESS/ TX COLUMN ADDRESS = Twou Tawi. —> ‘WEO, WE2 1 Tos WE’, WES. a 82C435 58

82C435—38MHz AC Timing Characteristics (Ta = 0°C-70°C, Vpp = 5V +5%) CLKIN Timings Se Parameter Symbol Min.(ns) Oe CLKIN Period tc 26 CLKINHightime CLKIN High time ton t,/2-5% CLKINLowtime CLKIN Low time ter t,/2-5% Video Timings Parameter Symbol Min.(ns) Max.(ns) Se) x(n) VIN, BLANK delay from CLKIN bin 150 ig 5 HIN delay from CLKIN thin 150 tin SO R,G,B,RS,GS,BS delay from CLKIN tia 5 30 gs SLOUT delay from CLKIN tui 5 66 eee Other Timings a Parameter Symbol Min.(ns) Max.(ns) LPENSTBPulseWidih gg LPENSTB Pulse Width t19 100 i > RESET Pulse Width 120 64t, * In CLKIN/2 mode, 120 must be 128 minimum In CLKIN/2 mode, 20 must be 128 t, minimum. 1/0 Bus Timings en apne Parameter Symbol Min.(ns) Max.(ns) ——_ SS ins) MIORD, MIOWR Pulse Width t 200 EI MIORD, MIOWR to RDY Low delay t2 50 NE Address setup to MIOWR (I/O Write) 13 80 Address hold fre NR Address hold from MIOWR (I/O Write) t4 80 SF Address setup to MIORD (I/O Read) t3 20 NS Address hold from MIORD (1/O Read) t4 20 Memon Addons an aS SS SO Memory Address setup to MIORD, MIOWR 13 20 TORD DIGITS ald te MIORD,MIOWR hold from ROY (Memory) t4a 0 ON Trap delay from MIORD,MIOWR ts 150 ss 59 820435

1/0 Bus Timings (Continued) Parameter Symbol Min.(ns) Max.(ns) MEMIO setup to MIORD,MIOWR t6 20 MEMIO hold from MIORD,MIOWR 7 5 1/O Write Data setup to MIOWR 8 45 1/O Write Data hold from MIOWR ‘9 60 \\/O Read Data delay from MIORD t10 150 V/O Write Data hold from MIORD tt 5 100 RDY high time 12 0.5t, Memory Read Data setup to RDY GE 1.5t, Memory Read Data hold from RDY tl4 20 Memory Write Data setup to RDY tts 6te Memory Write Data hold from RDY ti6 -1.5te VALRAD delay from Address ti7 60 RDY width t21 6t, 42t, DRAM Timings High CPU Bandwidth Mode Parameter Symbol Min.(ns) Max.(ns) Min.(ns) Max.(ns) Bdotmode 9dotmode Read/Write Cycle time (read) tre Bte Bt, RAS Pulse Width (read) tras 3t, -8 3te Read/Write Cycle time (write) te Bt, Bt, - RAS Pulse Width (write) tras 4t, -8 4te Column Address Hold from RAS tar 1.5t, +10 1.5t, +10 RAS precharge tp te -2 ate -2 CAS to RAS precharge top to+1 to +1 CAS hold from RAS tosh 4t, -5 4t,-5 RAS to CAS delay trod O.5t, +4 O.5t, +4 RAS hold from GAS trsh 2.5t, -28 2.5, -28 CAS Precharge tepn 1.5t, +7 1.5t, +7 CAS Pulse Width teas 3.5t, -23 3.5t, -23 Row Address Setup to RAS. tasr 0.5t, -11 O.5t, -11 Column Address setup to CAS tase 1 1 Row Address hold from RAS tran 0.5t, 0.5t, 82C435 60

DRAM Timings High CPU Bandwidth Mode (Continued) Parameter Symbol Min.(ns) Max.(ns) Min.(ns) Max.(ns) Bdotmode 9dotmode Column Address hold from CAS tean te te Data Access time from OE toea t,-10 te -10 Data Access time from CAS teac 2t, -26 2t, -26 Data Access time from RAS trac 2.5t,-3 2.5t,-3 WE Pulse Width twp t,-7 to-7 Write Data Setup to WE tas oO 0 Write Data Hold from WE ton te -5 to -5 Write Data Hold from RAS tone 2.5, -10 2.5t, -10 WE hold from CAS twch to -7 2to-7 WE hold from RAS twer 2.5t, +2 2.5t, +2 DRAM Timings Low CPU Bandwidth Mode Parameter Symbol Min.(ns) Max.(ns) Min.(ns) Max.(ns) 8 dot mode 9 dot mode Read/Write Cycle time (read) tre bt, Tt RAS Pulse Width (read) tras 3.5t, -1 4.5t,-1 Read/Write Cycle time (write) tre 8te Bt, RAS Pulse Width (write) tras 5.5t,-1 5.5to-1 Column Address Hold from RAS tar 2.5, +8 2.51, +8 RAS precharge tp 2.5t, -2 2.5t, -2 CAS to RAS precharge top toH1 to#1 CAS hold from RAS tosh 5 -5 5, 5 RAS to CAS delay trea 0.5t, +7 0.5t, +7 RAS hold from CAS tren 3-8 3t, -8 CAS Precharge toon 1.5t, +6 1.5t, +6 CAS Pulse Width teas 4.5t, -13 4.5t,-13 Row Address Setup to RAS tasr 0.5t, -11 0.5t, -11 Column Address setup to CAS tase 1 1 Row Address hold from RAS tran 0.5t, 0.5te Column Address hold from CAS tah 2te 2te Data Access time from OE toca te -6 t.-6 eS 61 82C435

DRAM Timings Low CPU Bandwidth Mode (Continued) Sdotmode Odotmode Data Access time from CAS teac 2te -10 te -10 Data Access time from RAS trac 3.5t,-6 3.5, -6 WE Pulse Width tap 1.5t, -15 1.5t,-15 Write Data Setup to WE tas 0 0 Write Data Hold from WE tan te -2 t.-2 Write Data Hold from RAS tone 2.5t, +3 2.5t, +3 WE hold from CAS twch 3.5, -14 3.5t,-14 WE hold from RAS. twor 4te -4 Ato -4 Compatibility with DRAMs Maximum CLKIN frequency for RAS access time High Low CPU Bandwidth Mode CPU Bandwidth Mode 150ns 16.5MHz 20MHz 120ns 20MHz 27MHz 100ns 21.5MHz 30MHz DRAM Refresh Interval (ms) = 43000/(V,*V,) V, = Vertical Refresh Rate V, = Total Number of lines/frame (including retrace) SS 820435 62

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a 82A436 Pin Description Pin Pin No. Type Symbol Description 55 1 ADDRO SYSTEM ADDRESS bits 0-9 and 14-19. These bits are 56 1 ADDR1 used for addressing the display memory and 1/O 87 1 ADDR2 operations. ADDRO-ADORG are I/O and memory ad- 58 1 ADDR3 dresses. ADDR14-ADDR19 are memory addresses 59 l ADDR4 only 60 1 ADDRS

61 I ADDR6

62 1 ADDR? 63 1 ADDRB 64 1 ADDR 24 1 ADDR14 23 1 ADDR15 22 1 ADDR16 21 1 ADDR17 20 1 ADDR18 19 1 ADDR19 65 ie) DATAO SYSTEM DATA BUS bits 0-7. These bits are used to 66 ie) DATAt transter data to and from the CPU data bus. 67 ie) DATA 68 ie) DATA3 2 ie) DATA4 3 vo DATAS 4 ie) DATA6 5 vo DATA7 47 1 MEMR MEMORY READ. MEMR is an active low input from the system bus. It is used by the CPU to read display memory and the EGA BIOS ROM in conjunction with the 82C435, 46 ! MEMW MEMORY WRITE. MEMW is an active low input from the system bus. It isused to write into the display memory and the EGA BIOS ROM in conjunction with the 82C435 54 ' lor 1/0 READ. IOR is an active low signal from the system bus. It is used to read the 82C435 and 824436 registers. 50 l low /O WRITE. |OW is an active low signal from the system bus. It is used to write to the 82C435 and 82A436 registers. 48 ' DACKO DMA ACKNOWLEDGE. DACKO is an active iow input from the system bus used to acknowledge DMA re- quests. It disables all memory read and memory write operations (MEMR and MEMW) to the 82C435 and 824436. aS 820435 64

Xv | A$$ 82A436 Pin Description (Continued) eeSSSSSSSSSSSSSSSSO Pin Pin No. Type Symbol Description oo 49 \\ AEN ADDRESS ENABLE. AEN is an input from the system bus used to disable devices from the I/O channel to allow DMA transfers to take place. 7 1 RESET RESET is an active high input. from the system bus used to reset the Miscellaneous Output Register (I/O address 3C2h), the Feature Control Register (I/O address 3BAh/3DAh) and the Emulation Mode Regis- ter (I/O address 3B5h/3D5h) 51 1 SYSCLK SYSTEM CLOCK. SYSCLK is the I/O bus clock and is used to synchronize IOW. 53 I LPENIN LIGHT PEN INPUT. LPENIN is a negative edge trig- gered input which sets bit 1 (LIGHT PEN STROBE) in the Input Status Register 1 (1/O address 3BAh/3DAh). 0 = light pen trigger has not been set 1 = light pen trigger has been set A low level on LPENIN also generates a high level on output pin LPENSTB to inform the 82C435 of a valid light pen trigger, 12 ' LPENSW LIGHT PEN SWITCH. LPENSW goes to bit 2 of the Input Status Register 1 0 = light pen switch closed 1 = light pen switch open 44 ° LPENSTB LIGHT PEN STROBE. LPENSTB goes active high on the falling edge of LPENIN. It is used by the 82C435 to load the Light Pen High (CR10) and Light Pen Low (CR11) registers in the CRT Controller. IIE I SE Gorton 13 1 FEATINO FEATURE CODE 0 and FEATURE CODE 1 are inputs 14 1 FEATIN1 from the feature connector (pins 19 and 17, respec- tively) and can be read in the EGA mode as bits 5 and 6 in the Input Status Register 0 (I/O address 3C2h) 43 ° FCOUTO FEATURE CONTROL 0, FEATURE CONTROL 1 42 ° FCOUT1 FCOUTO and FCOUT1 are bits 0 and 1 of the Feature Control Register (I/O address 3BAh/3DAh). FCOUTO and FCOUT? go to pins 20 and 21 of the Feature Connector. —..q 65 820435

CHIPS. 82A436 Pin Description (Continued) Pin Pin No. Type Symbol Description " 1 SWITCH SWITCH is a multiplexed input from a 4-position external configuration DIP-switch. In the EGA mode. the state of this input can be read as the switch sense bit (bit 4 of the Input Status Register 0 - I/O address 3C2h). CLKSELO and CLKSEL1 pins (bits 2 and 3 of the Miscellaneous Output Register - 1/O address 3C2h) determines which switch is read. 7 1 HIN HORIZONTAL RETRACE INPUT. HIN is a an input from the 82C435. This input is used in Hercules mode to generate bit 0 of the Hercules Status Register (I/O address 3BAh) 8 1 VIN VERTICAL RETRACE INPUT. VIN is an input from the 82C435, This input is used in CGA mode to generate bit 3 of the CGA Status Register (I/O address 3DAn). In Hercules mode, this input generates bit 7 of the Hercules Status Register (I/O address 3BAh) 10 1 BS/V SECONDARY BLUE/MONOCHROME VIDEO. BS/V input on the 824436 is normally the BS/V output from the 82C435. This input is used to generate bit 3 of the CRT Status Register in Hercules mode (I/O address 3BAn). 39 vo DADDO Local data bus for memory or I/O data between the 38 vo DADD1 82C435, 824436 and the BIOS ROM 37 vo DADD2 36 vo DADD3 34 vo DADDA 33 vo DADDS 32 vo DADDS 31 vo DADD7 29 ° ROMWE BIOS ROM WRITE ENABLE. ROMWE is active low for memory writes at address CO000h-C3FFFh. This out- put can be used to select the active page in Page Select ROMs (27513) 30 ° ROMOE BIOS ROM OUTPUT ENABLE. ROMOE is active low for memory reads at address CO000h-C3FFFh 27 ° MAI6 Buffered system address bus bit A16. 28 ° ADDMO Address Decode. Decoded output for three upper system address bus bits to address the display memory at locations AXXXX and BXXXX. This output is low when A19-A17 =101 82C435 66

82A436 Pin Description (Continued) eee Pin Pin No. Type Symbol Description ee 40 ° MIORD MEMORY-I/O READ. MIORD is active low for memory or /O read operations. MIORD is active whenever MEMR or IOR is active en 41 ° MiOWR MEMORY-I/O WRITE. MIOWR is active low for all memory or 1/O write operations. MIOWR is active whenever MEMW or IOW is active 45 ° MEMIO MEMORY-/O. MEMIO is a contro! signal, low for memory (MEMR or MEMW), high for 1/O (IOR or 1ow) 25 ° CLKSELO CLOCK SELECT 0 AND 1. CLKSELO and CLKSEL1 26 ° CLKSEL1 are bits 2 and 3 of the Miscellaneous Output Register (V/O address 3C2h). These bits are used as select inputs into an external multiplexer to select the con- figuration switch bits and the clock source. TN ete A NC Sart 15 1 IOADS. /O ADDRESS. IOADS selects the I/O address to the CRT Controller. 0 = 2xXh, 1 = 3XXh ET SRR 16 fl VALRAD VALID READ ADDRESS. VALRAD, generated by the 820435, allows the 82A436 to drive the system data bus during a memory read cycle (MEMA) en a 6 ° INTERNL INTERNAL SELECT. INTERNL is bit 4 of the Miscel- laneous Output Register (I/O address 3C2h). It is an active low signal which enables the 820435 outputs (R. G. B, RS. GS/I, BS/V, HIN, VIN) through an ex- ternal buffer to the monitor. It is also an output to the feature connector (pin 27) er pine Oo 67 82C435

82A436 Functional Description The 824436 integrates the bus drivers, decode a) If the data is to come froma register (or logic and other external logic that is required register bit) that exists in the 82A436, to implement a complete EGA/CGA/Hercules the 824436 drives those specific bits onto compatible display subsystem around the the /O bus data bus. 820435. ) For all other read cycles (memory, other register and register bits), the 82A436 The functionality of the 82A436 can be classi- transfers the data from the local data fied as follows bus through to the I/O bus. In this case, the local data bus is driven by the BIOS. a) Decodes memory addresses and contro! ROM or the 820436. signals. b) Serves as a data transceiver between the Temporary Storage Registers V/O bus and the 82C435, display memory and EGA BIOS. There are five byte wide temporary storage c) Provides temporary storage locations. read-write registers in the 82A436, These. @) Light Pen logic registers are located at offset OFAh-OFEh in e) Feature Connector interface logic the CRT Controller data register space. These f) Includes parts of some registers on the registers can be accessed by first writing EGA/CGA/Hercules display subsystems. OFAn/OFBh/OFCh/OFDH/OFEH in the CRTC Address Register (I/O address 3B4h/3D4h) Memory Address and Control Decode and then accessing the CRTC Data Register (VO address 3B5h/3D5h). These registers can. The 82A436 generates a memory address be used as working registers. select signal (ADDMO) for the 82C435. This signal is active low for all memory accesses Light Pen Logic in the address space AOQOOh-BFFFFh. The. 82A436 also generates Output Enable and The Light Pen logic consists of the Light Pen Write Enable signals for the BIOS ROM in the Latch and Light Pen Switch. The Light Pen address range CO000h-C3FFFh. The ROMOE Latch is set by software through an internal signal is low for all read accesses to this register or by hardware when there is a valid address space. The ROMWE signal is low for negative pulse on the LPENIN input. The. all write accesses to this address space. The latch can only be cleared by software. The ROMWE signal aliows the use of page select, Light Pen Latch and Switch status can be. ROMs like 27513 on the EGA board read by software through the Input Status Register | at 1/0 address 3C2h (described The 82C435_uses the same control pins later) (MIORD & MIOWR) for memory and \\/O accesses. The 824436 generates MIORD. SET LIGHT PEN LATCH MIOWR and MEMIO signals from the 1/O bus Write Only Register control signals. W/O Address: 3DCh/3B9h Data Transceiver Function The Set Light Pen Register is used to trigger the Light Pen from software. In the EGA The 82A436 also serves as a bidirectional mode, this is done by an I/O Write to address transceiver for data transfer between the CPU, 3DCh. In CGA mode, the Light Pen is trig- (/O bus) and the display memory, BIOS ROM. gered by an I/O Read or I/O Write to address and 82C435. When the CPU needs to write to 3DCh. In Hercules mode, this is done by an the display subsystem, the 82A436 passes the VO Write to address 389h, data through to the local data bus in the display subsystem. When the CPU reads from CLEAR LIGHT PEN LATCH the display subsystem, the 82A436 handles Write Only Register the data transfer in two ways V/O Address: 3D8h/3B8h 820435 68

The Clear Light Pen Register is used to clear used to enable a tri-state buffer that isolates. the Light Pen Latch. In the EGA mode, this is the monitor from the 82C435. If the feature done by an /O Write to address 3DBh. In connector is to drive the monitor, then the CGA mode, the Light Pen is triggered by an Disable Internal Video bit must be program- W/O Read or 1/0 Write to address 3DBh. In med to 1 Hercules mode, this is done by an I/O Write to address 3BBh 82A436 Registers Feature Connector Interface Logic There are several registers (or parts of regis- The EGA has the facility to interface to an ters) in the 82A436. These are: external video system. This interface is through the Feature Connector. The external 5.500 video system, can take the Sync signals and Register Address video data stream from the 82C435. It can el also accept a composite signal through an Bits DO, D1 of EGA Feature external port. This external video system, can Control Register 3BAh/3DAh then either drive a composite video signal or Bits DO, D1, 02 of Emulation also drive a standard RGB monitor through Mode Register 3BSh/3D5h the EGA. The Feature Connector interface (Pointer = FFh) logic consists of the Feature Control outputs, Bits DO, 02, D3, D4 of EGA Feature Code inputs and a control signal to Miscellaneous Output Register 3C2h select between internal and external video Bits D4, D5, D6 of EGA Input Source Status Register 0 3C2h The CPU can pass control and status infor- Bits D1. D2 of EGA input mation to the external video system through Status Register | 3BAh/3DAh the Feature Control Register. Feature Control Bits D1, D2, D3 of CGA Bits 0 and 1 from this register are output on Status Register 3DAh 82A436 output pins FCOUTO and FCOUT1 Bits D0, D3, D7 of Hercules respectively. These pins are usually connected Status Register 3BAh to the Feature Connector. EGA/CGA Set Light Pen The Feature Ci tor can also pass inf Register 30Ch ‘eature Connector can also pass infor- mation to the CPU. This is done though two Roost Set Light Pen 389h pins FEATINO and FEATIN1 on the 82A436. The CPU can read the state of these two pins. EGA/CGA Clear Light Pen through Input Status Register 0 at I/O address Register 3DBh 3C2h. Hercules Clear Light Pen Register 3BBh Select Video Source Temporary Storage The Video and Sync outputs to the monitor Registers 0-4 385h/3D5h can come from two sources. The 82C435 (Pointer = FAh-FEh) could drive the monitor or the Feature a Connector could drive the monitor. The in- ternal video stream or the Feature Connector video stream is selected through the Disable Internal Video bit in the EGA Miscellaneous Register at 1/O address 3C2h. This bit controls. the state of the INTERNL output pin on the 82A436. The INTERNL output is typically —_.] 69 82C435

FEATURE CONTROL REGISTER The Emulation Mode Register exists in both Write Only Register the 82C435 and the 82A436. This register is VO Address: 3BAh/3DAh located at offset OFFh in the CRT Controller register space. In the 82A436 this is a write [0+ ]osJos]o«]osJoa]or]oo] only register and only bits 0, 1 and 2 are Fearune CONTRO ot @ implemented. These bits are also present in — Feavune conrmot art + the 82C435. When this register is read, the Meseaves, oscees) 82C435 drives the local data bus and the 82A436 transfers the contents of the local nesenveo oaces) data bus to the CPU. Do Enable CGA Emulation: This bit mor useo determines if CGA Emulation is to be enabled (=1) or disabled (=0) On reset, this bit defaults to 0. The Feature Control Register exists in both the 82C435 and the 82A436. In the 82A436 o1 Enable Mono/Hercules Emulation. this is a write only register and only bits 0 This bit determines if Monochrome/ and 1 are implemented. These bits are also Hercules Emulation is to be enabled present in the 820435. When this register is (=1) or disabled (=0). On reset, this read, the 82C435 drives the local data bus bit defaults to 0. and the 824436 transfers the contents of the locai data bus to the CPU. Feature Control be Emulation in Progress: This bit Bits 0 and 1 from this register are output on determines if the 82C435/82A436 is output pins FCOUTO and FCOUT! respec- currently in the CGA or Hercules tively. These bits can be used to transfer emulation mode (=1) or in the status information to the Feature Connector. normal EGA mode (=0). This bit On reset, bits DO and D1 of this register must be set while CGA/MDA/ default to 0 Hercules emulation is in progress. On reset, this bit defaults to 0. EMULATION MODE REGISTER (CRFF) Write Only Register D4 Emulation Type: This bit is set when WO Address: 3B5h/3D5h software desires an automatic emu- Address Pointer: FFh lation mode switch. D4 = 0 and CGA emulation enabled means that the (rToeTos]oe]os]oe]e:]o9) software desires CGA emulation. D4 txeess Sve wae = 1 and Hercules emulation enabled ager womoaanciass eMuLsTion means that the software desires EMULATION Ws PROGRESS Hercules emulation. On reset, this fees) excess AnD Women) The 824436 determines the address for the eae TRAPS (2c438) Light Pen Set and Clear registers depending fugue nC mEGIEN AccEBEES on the contents of these bits. The format for tne es neste wares the Input Status Register 1 (CGA/Hercules (acess) Status Register) is also determined according to these bits. eee 82C435 70

EGA 02-03 02-D3 bits are output on the MISCELLANEOUS OUTPUT REGISTER CLKSELO and CLKSEL1 pins on the Write Only Register 824436. Typically these are used to VO Address: 3C2h externally select the clock source for the 82C435. On reset, these bits (erTeeTorJosJos]o2]or]oe) default to 0 isicets ano vost ENABLE RAM (20498) Da Disable Internal Video. This bit is CLOCK SELECT 8 (826495 AND HAA) output on the INTERNL pin on the 82A436. The INTERNL output is onane mewn" used to select the 82C435 video data (aces ano wanes) stream or an external video data RESERVED 1 420435) stream to the monitor. On reset | ware povanire (ces) this bit defaults to 0. are sovaniry aces “me INPUT STATUS REGISTER 0 The EGA Miscellaneous Register exists in Read Only Register both the 82C435 and the 82A436. This register V/O Address: 3C2h is located at I/O address 3C2h. In the 82A436, this is a write only register and only bits 0, 2. (er]oe]oa]oeTos [oa] o%]o9] 3, and 4 are implemented. These bits are also present in the 82C435. When this register is read, the 82C435 drives the local data bus nor useo and the 82A436 transfers the contents of the local data bus to the CPU smiron sense bo VO Address Select. This bit maps FEATURE CODE 0 the CRT Controller address and data Feaune covey registers into the 3Bxh/3Dxh ad- car wrenmupr ow a2caiy dress space. This bit defaults to 0 ‘on reset and is present in both the The EGA Input Status Register 0 exists in 82C435 and 82A436. Setting this bit both the 82C435 and the 82A436. This register to 0 or 1 maps the registers as Js located at I/O address 3C2h. In the 82A436, follows this is a read-only register and only bits 4, 5, Se and 7 are implemented. When this register is VO Address for read in the EGA mode, the 82C435 drives the Register Name D0 = 0 DO=1 local data bus bit 7 and the 824436 drives the “alone other bits. In the CGA and Hercules modes, Fagaee 34h aban this register returns undefined values when CRTC Data Register 3BAh 3DAn This bit returns the current status of the Input Status 82A436 input pin ‘SWITCH’ to the CPU. The Register | 3BAh 3DAh CPU scans the state of the DIP switches on hii Ronenvtnealanemcaeialay the EGA board through this bit a n 820435

CHIPS. $$$ Feature Code 0 and 1 (D5-D6) Display Enable/HSYNC Output (D0) These two bits return the current status of the. In EGA and CGA modes, DO is an active low 824436 input pins FEATINO and FEATIN1 Display Enable signal generated by the respectively. These bits are used to read the 82C435. A logical 0 indicates the active dis status information from the EGA Board Fea- play interval. This bit is returned high during ture Connector the horizontal and vertical retrace interval. In Hercules emulation mode this bit is driven by INPUT STATUS REGISTER | the 82A436 and it indicates the current level (CGA/HERCULES STATUS REGISTER) of the 824436 HIN input Read Only Register 1/0 Address: 3BA/3DAh Light Pen Strobe (D1) D1 is driven by the 82A436 and indicates the [rlos]osToeJoa]o2]0s]o9} state of the Light Pen Latch, This latch is set DISPLAY ENABLE NEYNG OUTPUT whenever a valid Light Pen pulse is generated. Lai Pen srnose ‘uonr pen mires Light Pen Switch (D2) venrical nerRaceviogo 02 is driven by the 82A436 and indicates the coton paterre ourrur 0 #2¢85) state of the Light Pen Switch (on the Light Pen Connector) COLOR PALETTE OUTPUT 1 (#26435) mer useo seas Vertical Retrace/Video (D3) ——— ene ourrur In EGA mode, D3 is an active high vertical The Input Status Register | exists in both the retrace signal, which is functionally the same 82C435 and the 82A436. This register changes as the active high Vertical Sync output from address and format in the EGA, CGA and the 82C435 (the polarity of this bit is always. Hercules modes. In EGA mode this register is Positive). In CGA emulation mode, D3 is located at 1/O address 3BAh/3DAh. In CGA Griven by the 824436 and is the complement mode this register is located at 1/O address of the VIN input on the 82A436. In Hercules 3DAh. In Hercules mode this register is 1o- emulation mode D3 is driven by the 82A436 cated at I/O address 38Ah, When this register and it indicates the current state of the BS/V is read, the 820435 and 824436 drive different input on the 82A436. bits in the three modes as follows: Vertical Sync Output (D7) EGA mode — 82C435 drives bits 0, 3, 4, 5 D7 is high during the Vertical Sync interval 82A436 drives bits 1 and 2 bits 6 and 7 are high CGA mode —82C435 drives bit 0 824436 drives bits 1, 2 and 3 bits 4, 5, 6 and 7 are high Hercules 82436 drives bits 0, 3 and 7 mode bits 1, 2, 4, 5 and 6 are high 82C435, 72

X — Se Parameter Symbol! Min. Max. Units Supply Voltage Voo _ 70 v ee Input Voltage vi -0.5 5.5 v a Output Voltage Vo -0.5 55 Vv a Operating Temperature Tor -25 85 Cc + rE ee Storage Temperature Tst6 -40 125 Cc 82A436 Operating Conditions ee Parameter Symbol Min. Max. Units Supply Voltage Veo 4.75 5.25 v rr Ambient Temperature Ta 0 70 °c a 82A436 DC Characteristics ee Parameter Symbol Min. Max. Units —_ gs EOE Input Low Voltage Vc 0.8 v BN Input High Voltage Vi 2.0 Vv ——$—es Output Low Voltage lous = 10mAt Vou 05 v love = 24mAz we Output High Voltage low = 3.3MA Vou 24 v oe ek ce ce Input Leakage Current he -200 +200 uA Power Supply Current loc 250 mA Oe mA Output High Impedence Leakage loz -300 +120 uA 0.45 < Vein < Voc PIN NOTES: 1. Io, = 10mA onall pins except DATAAO-7 2. lou = 24mA on DATAO-7 Ss 73 820435

(Ty = 0°C-70°C, Voc = 5V +5%) Timings Parameter Symbol Min.(ns) Max.(ns) System Clock Period To 80 IOR Pulse Width Ty To Address Setup (82A436 Register Access) To 20 Address Hold (82A436 Register Access) Ts 0 Control Active Delay Ts 25 Control Inactive Delay Ts 23 V/O Read Data Delay (82A436 Register) Te 45 \\/O Read Data Hold (82A436 Register) Tt, 10 30 Propagation Delay (DATA-DADD, DADD-DATA) —_T, 25 TOW Setup to System Clock To” 10 TOW Pulse Width (Short Write) Tio 2To lOWPulse Width (Long Write) Tro eT. MIOWR Active Delay (1/O Write) Thy" 31 MIOWR Inactive Delay (Short I/O Write) Tie 28 MIOWR Inactive Delay (Long I/O Write) Ty." 34 \\/O Write Data Setup (824436 Register) Tra 10 1/O Write Data Hold (824436 Register) Tis 20 LPENSTB Delay (Software Strobe) Ths 45 Register Output Delay (Long Write) The 45 Register Output Delay (Short Write) Ths 40 VALRAD Setup (Display Memory Access) Too 5 Address Setup (ROM Access) Too 20 VALRAD Hold (Display Memory Access) Tos 0 Address Hold (ROM Access) Tos 0 Control Active Delay (Memory Access) Too 26 Control Inactive Delay (Memory Access) Tog 20 ADDMO Delay Tos 26 MA\\6 Delay Tos 20 LPENSTB Delay (Hardware Strobe) Tos 40 NOTE: a + To, T;; and Tj2 (long write) are specified on both rising and falling edges of SYSCLK. MIOWR stays active for a maximum of 1’» SYSCLKs starting at any of the edges of SYSCLK 820435 74

| $$ CPU—IO READ ACCESS AD waaaao) ———— (READ 824436) Te Ty ion espe MIORD, MEMIO [xX ae ea r Data (READ 82436) oD ano Te DATA (READ 820435) CPU—IO WRITE ACCESS (SHORT WRITE) Te S¥SCLK Ts __ Tra iow K_| Te Ts MEMIO Te 1 CPU ADDR ~ (write #24436) C[ 9 Tie Te wow ie ona psa (WRITE 824436) a aa Te papo (wAITE 626435) |X] Ts LPensTe TH FCO, FCI. CLKSELO, CLKSEL'. INTERNE 75 820435

CPU—IO WRITE ACCESS (LONG WRITE) To. svscix Ts - | —- iow memo a \\~— ts (WRITE 824636) a i, mel Ts mow rey ava (WrITE 628436) a a nl paoo (were 620835) a «| FCO, FC1, CLKSELO, SEL ATEN f a 820435 76

$$ ee CPU—MEMORY ACCESS cpu ADDR Tao Ta MEMR, MEMW _ Tx: Tas: \\MIORD. MIOWR, MEMIO. ROMOE, ROMWE DATA(WR), DADD (RD) —_{—— To DADD(WR), DATA(RD) cpu apn a |< Tas ADDMO, MA16 PENN Tes a, Ce eS 77 820435

Figure 10. Load Circuit and AC Characteristics Measurement Waveform

68-PIN PLASTIC LEADED CHIP CARRIER oesias an kl (5 3F) ¥50(3 30) a ees (md COCROCOOT HH, T ia BE : 3 qd o p = S| 2 2 d b <4 +4 Fos] 3 a ch SCHAAR) 4 ales 0007877 T osounani 84-PIN PLASTIC LEADED CHIP CARRIER CULE: (RRR R BORED ORR OOOO iin COCDCNOCOON0D Afonon : & n q q q ! q P 3 | a: — zg ial qj b fom) C H q i = ey SSeS i} DOO Oooo

CHIPS.

Ordering Information

—— ee tee P82C435 PLCC-84 pins P82A436 PLCC-68 pins Note: 1. PLCC = Plastic Leaded Chip Carrier PFP = Plastic Flat Pack

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Chips and Technologies, Incorporated

3050 Zanker Road, San Jose, CA 95134 408-434-0600 Telex 272929 CHIP UR

IBM, AT, XT, PS/2, Micro Channel, Personal System/2, Enhanced Graphics Adapter, Color Graphics Adapter, Monochrome Adapter, IBM Color Display, IBM Monochrome Display are trademarks of International Business Machines. Intel, iAPX 386 are trademarks of Intel Corporation. MOTOROLA is a trademark of Motorola Hercules Graphics is a trademark of Hercules Computer Technology. Lotus is a trademark of Lotus Corporation Microsoft is a trademark of Microsoft. CHIPSet, CHIPSpak, CHIPSport, SharpScan EGA, ChipsLink, MicroCHIPS are trademarks of Chips and Technologies, Inc. Copyright® 1985, 1986, 1987 Chips and Technologies, Inc Chips and Technologies, Inc. makes no warranty for the use of its products and bears no responsibility for any errors which may appear in this document. Chips and Techonologies, Inc. retains the right to make changes to these specifications at any time without notice. #2 o08579 Lo