P82B96_V01 NXP | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 General description
- 2 Features
- 3 Applications
- 4 Ordering information
- 4.1 Ordering options
- 5 Block diagram
- 6 Pinning information
- 6.1 Pinning
- 6.2 Pin description
- 7 Functional description
- 8 Limiting values
- 9 Characteristics
- 10 Application information
- 10.1 Calculating system delays and bus clock
- 10.2 Negative undershoot below absolute
- 10.2.1 Example with questions and answers
- 11 Package outline
- 12 Soldering of SMD packages
- 12.1 Introduction to soldering
- 12.2 Wave and reflow soldering
- 12.3 Wave soldering
- 12.4 Reflow soldering
- 13 Soldering of through-hole mount
- 13.1 Introduction to soldering through-hole
- 13.2 Soldering by dipping or by solder wave
- 13.3 Manual soldering
- 13.4 Package related soldering information
- 14 Abbreviations
- 15 Revision history
- 16 Legal information
Dual bidirectional bus buffer Rev. 8.1 — 20 December 2021 Product data sheet
1 General description
The P82B96 is a bipolar IC that creates a non-latching, bidirectional, logic interface between the normal I2C-bus and a range of other bus configurations. It can interface I2C- bus logic signals to similar buses having different voltage and current levels. For example, it can interface to the 350 μA SMBus, to 3.3 V logic devices, and to 15 V levels and/or low-impedance lines to improve noise immunity on longer bus lengths. It achieves this interface without any restrictions on the normal I2C-bus protocols or clock speed. The IC adds minimal loading to the I2C-bus node, and loadings of the new bus or remote I2C-bus nodes are not transmitted or transformed to the local node. Restrictions on the number of I2C-bus devices in a system, or the physical separation between them, are virtually eliminated. Transmitting SDA and SCL signals via balanced transmission lines (twisted pairs) or with galvanic isolation (opto-coupling) is simple because separate directional Tx and Rx signals are provided. The Tx and Rx signals may be directly connected, without causing latching, to provide an alternative bidirectional signal line with I2C-bus properties.
2 Features
- Bidirectional data transfer of I2C-bus signals
- Isolates capacitance allowing 400 pF on Sx/Sy side and 4000 pF on Tx/Ty side
- Tx/Ty outputs have 60 mA sink capability for driving low-impedance or high capacitive buses
- 400 kHz operation over at least 20 meters of wire (see AN10148)
- Supply voltage range of 2 V to 15 V with I2C-bus logic levels on Sx/Sy side independent of supply voltage
- Splits I2C-bus signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals for interface with opto-electrical isolators and similar devices that need unidirectional input and output signal paths.
- Low power supply current
- ESD protection exceeds 3500 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
- Latch-up free (bipolar process with no latching structures)
- Packages offered: SO8 and TSSOP8
3 Applications
- Interface between I2C-buses operating at different logic levels (for example, 5 V and
3 V or 15 V)
- Interface between I2C-bus and SMBus (350 µA) standard
- Simple conversion of I2C-bus SDA or SCL signals to multi-drop differential bus hardware, for example, via compatible PCA82C250
- Interfaces with opto-couplers to provide opto-isolation between I2C-bus nodes up to 400 kHz
4 Ordering information
Table 1. Ordering information
4.1 Ordering options
Table 2. Ordering options [1] Standard packing quantities and other packaging data are available at www.nxp.com/packages/. [2] Orderable part number P82B96DPZ is a drop in alternate for P82B96DP,118. [3] This packing method uses a Static Shielding Bag (SSB) solution. Material should be kept in sealed bag between uses.
5 Block diagram
Figure 1. Block diagram of P82B96
6 Pinning information
6.1 Pinning
Figure 2. Pin configuration for SO8 Figure 3. Pin configuration for TSSOP8
6.2 Pin description
Table 3. Pin description
7 Functional description
- sense the voltage state of the I2C-bus pin Sx (or Sy) and transmit this state to the pin Tx (Ty respectively), and
- sense the state of the pin Rx (Ry) and pull the I2C-bus pin LOW whenever Rx (Ry) is LOW. Product data sheet Rev. 8.1 — 20 December 2021
Dual bidirectional bus buffer The rest of this discussion will address only the ‘x’ side of the buffer; the ‘y’ side is identical. The I2C-bus pin (Sx) is designed to interface with a normal I2C-bus. The logic threshold voltage levels on the I2C-bus are independent of the IC supply VCC. The maximum I2C-bus supply voltage is 15 V and the guaranteed static sink current is 3 mA. The logic level of Rx is determined from the power supply voltage VCC of the chip. Logic LOW is below 42 % of VCC, and logic HIGH is above 58 % of VCC (with a typical switching threshold of half VCC). Tx is an open-collector output without ESD protection diodes to VCC. It may be connected via a pull-up resistor to a supply voltage in excess of VCC, as long as the 15 V rating is not exceeded. It has a larger current sinking capability than a normal I2C-bus device, being able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down capability as well. A logic LOW is only transmitted to Tx when the voltage at the I2C-bus pin (Sx) is below 0.6 V. A logic LOW at Rx will cause the I2C-bus (Sx) to be pulled to a logic LOW level in accordance with I2C-bus requirements (maximum 1.5 V in 5 V applications) but not low enough to be looped back to the Tx output and cause the buffer to latch LOW. The minimum LOW level this chip can achieve on the I2C-bus by a LOW at Rx is typically 0.8 V. If the supply voltage VCC fails, then neither the I2C-bus nor the Tx output will be held LOW. Their open-collector configuration allows them to be pulled up to the rated maximum of 15 V even without VCC present. The input configuration on Sx and Rx also present no loading of external signals even when VCC is not present. The effective input capacitance of any signal pin, measured by its effect on bus rise times, is less than 7 pF for all bus voltages and supply voltages including VCC = 0 V. Remark: Two or more Sx or Sy I/Os must not be interconnected. The P82B96 design does not support this configuration. Bidirectional I2C-bus signals do not allow any direction control pin so, instead, slightly different logic low voltage levels are used at Sx/Sy to avoid latching of this buffer. A ‘regular I2C-bus LOW’ applied at the Rx/Ry of a P82B96 will be propagated to Sx/Sy as a ‘buffered LOW’ with a slightly higher voltage level. If this special ‘buffered LOW’ is applied to the Sx/Sy of another P82B96 that second P82B96 will not recognize it as a ‘regular I2C-bus LOW’ and will not propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special logic thresholds for their operation, for example PCA9511, PCA9515, or PCA9518. The Sx/Sy side is only intended for, and compatible with, the normal I2C-bus logic voltage levels of I2C-bus master and slave chips, or even Tx/Rx signals of a second P82B96 if required. The Tx/Rx and Ty/Ry I/O pins use the standard I2C-bus logic voltage levels of all I2C-bus parts. There are no restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or multipoint configuration with the Tx/Rx and Ty/Ry I/O pins on the common bus and the Sx/Sy side connected to the line card slave devices. For more details see Application Note AN255. Product data sheet Rev. 8.1 — 20 December 2021
8 Limiting values
Table 4. Limiting values
9 Characteristics
Tamb = +25 °C; voltages are specified with respect to GND with VCC = 5 V, unless otherwise specified. Table 5. Characteristics
Tamb = +25 °C; voltages are specified with respect to GND with VCC = 5 V, unless otherwise specified. Table 5. Characteristics...continued
Tamb = +25 °C; voltages are specified with respect to GND with VCC = 5 V, unless otherwise specified. [1] Limit data for +125 °C applies to P82B96TD/S900 version. It is guaranteed by design/characterization, but not by 100 % test. and would not support all I2C-bus operating modes. [3] The output logic LOW depends on the sink current. For scaling, see Application Note AN255.
Refer to AN460 and AN255 for more application detail. Figure 9. Interfacing an ‘I2C’ type of bus with different logic levels Figure 10. Galvanic isolation of I2C-bus nodes via opto-couplers
3.3 V to 5 V
Figure 11. Long distance I2C-bus communications
plus the net delay in the slave's response data signal caused by bus and buffer delays. of 600 ns, yields a cycle period of 2535 ns or 394 kHz. than 600 ns and all Fm+ devices must be < 450 ns. Figure 13. Driving ribbon or flat telephone cables
Table 6. Examples of bus capability
10.1 Calculating system delays and bus clock frequency for a Fast mode
Effective delay of SCL at slave: 255 + 17VCCM + (2.5 + 4 × 109 Cb)VCCB + 10VCCS ns. Figure 14. Falling edge of SCL at master is delayed by the buffers and bus fall times Effective delay of SCL at master: 270 + RmCm + 0.7RbCb ns. Figure 15. Rising edge of SCL at master is delayed (clock stretch) by buffer and bus rise times
The master bus has an RmCm product of 100 ns and VCCM = 5 V. giving an RbCb product of 160 ns. The slave bus also has an RsCs product of 100 ns. Its HIGH period may be programmed to the minimum 600 ns. equivalent to a frequency of 442 kHz. Figure 17. I2C-bus multipoint application Figure 18. Propagation Sx to Tx (Sx pull-up to 5 V; Tx pull-up to VCC = 10 V)
Figure 19. Propagation Rx to Sx (Sx pull-up to 5 V; Rx pull-up to VCC = 10 V)
10.2 Negative undershoot below absolute minimum value
-0.55 V with respect to GND at 25 °C ambient. Figure 20 shows the measured characteristic for one of those diodes inside P82B96. to guarantee the published specification. pins were tested to at least -80 mA which, from Figure 20, would be more than -0.8 V. during transients, more than -0.3 V is applied to the bus interface pins of P82B96.
negative transients, in Section 10.2.1 we show they can be managed if required. Figure 20. Diode characteristic curve
10.2.1 Example with questions and answers
with no IC connected at the end of the wiring, the undershoot is about 2 V.
Figure 21. Transients generated by the bus wiring inside the IC to the Sx/Sy side of the IC.
Figure 22. Wiring transients limited by the diodes in P82B96 result of the system wiring, then there will be no problems.
Figure 23. Wiring transients limited by a Schottky diode
- Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
- Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
Figure 24. Package outline SOT96-1 (SO8)
- Plastic or metal protrusions of 0.15 mm maximum per side are not included.
- Plastic or metal protrusions of 0.25 mm maximum per side are not included.
Figure 25. Package outline SOT505-1 (TSSOP8)
Dual bidirectional bus buffer
12 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”.
12.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
12.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
- Through-hole components
- Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
- Board specifications, including the board finish, solder masks and vias
- Package footprints, including solder thieves and orientation
- The moisture sensitivity level of the packages
- Package placement
- Inspection and repair
- Lead-free soldering versus SnPb soldering
12.3 Wave soldering
Key characteristics in wave soldering are:
- Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave
- Solder bath specifications, including temperature and impurities
12.4 Reflow soldering
Key characteristics in reflow soldering are: Product data sheet Rev. 8.1 — 20 December 2021
- Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 26) than a SnPb process, thus reducing the process window
- Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board
- Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 7 and Table 8 Package reflow temperature (°C) Volume (mm³) Package thickness (mm) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220
Table 7. SnPb eutectic process (from J-STD-020D) Table 8. Lead-free process (from J-STD-020D)
Figure 26. Temperature profiles for large and small components “Surface mount reflow soldering description”.
13 Soldering of through-hole mount packages
13.1 Introduction to soldering through-hole mount packages
This text gives a very brief insight into wave, dip and manual soldering.
13.2 Soldering by dipping or by solder wave
The total contact time of successive solder waves must not exceed 5 seconds. after soldering to keep the temperature within the permissible limit.
13.3 Manual soldering
between 300 °C and 400 °C, contact may be up to 5 seconds.
13.4 Package related soldering information
Table 9. Suitability of through-hole mount IC packages for dipping and wave [1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. [2] For PMFP packages hot bar soldering or manual soldering is suitable.
14 Abbreviations
Table 10. Abbreviations
- Removed DIP package
- Added P82B96DPZ orderable part number P82B96_8 20091110 Product data sheet - P82B96_7 P82B96_7 20090212 Product data sheet - P82B96_6 P82B96_6 20080131 Product data sheet - P82B96_5 P82B96_5 20060127 Product data sheet - P82B96_4 P82B96_4 (9397 750 12932)
20040329 Product data - P82B96_3
20030402 Product data 853-2241 29602 of
2003 Feb 28
Table 11. Revision history
20030220 Product data 853-2241 29410 of
2003 Jan 22
20010306 Product data 853-2241 25758 of
2001 Mar 06
Table 11. Revision history...continued
Dual bidirectional bus buffer
16 Legal information
16.1 Data sheet status
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16.2 Definitions
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Dual bidirectional bus buffer Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Suitability for use in non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products.
16.4 Trademarks
Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. Product data sheet Rev. 8.1 — 20 December 2021
Dual bidirectional bus buffer Tables Tab. 9. Suitability of through-hole mount IC Figures Fig. 4. VOL as a function of junction temperature Fig. 5. VOL as a function of junction temperature Fig. 6. VIL(max) as a function of junction Fig. 7. VIH(min) as a function of junction Fig. 8. VCC(max) that guarantees bus release Fig. 9. Interfacing an ‘I2C’ type of bus with Fig. 10. Galvanic isolation of I2C-bus nodes via Fig. 14. Falling edge of SCL at master is delayed Fig. 15. Rising edge of SCL at master is delayed Fig. 16. Rising edge of SDA at slave is delayed by Fig. 18. Propagation Sx to Tx (Sx pull-up to 5 V; Tx Fig. 19. Propagation Rx to Sx (Sx pull-up to 5 V; Rx Fig. 22. Wiring transients limited by the diodes in Fig. 23. Wiring transients limited by a Schottky Fig. 26. Temperature profiles for large and small Product data sheet Rev. 8.1 — 20 December 2021