P82B96PWG4

P82B96_09 TI | Alldatasheet

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(TOP VIEW) GND 4 5 8Sx Rx Tx T y Ry Sy VCC P PACKAGE (TOP VIEW) 4 5 8Sx Rx Tx GND T y Ry Sy VCC DGK PACKAGE (TOP VIEW) 4 5 T y Ry Sy VCCSx Rx Tx GND PW PACKAGE (TOP VIEW) 4 5 8Sx Rx Tx GND T y Ry Sy V CC DESCRIPTION/ORDERING INFORMATION P82B96 DUAL BIDIRECTIONAL BUS BUFFER SCPS144B MAY 2006 REVISED JULY 2007 Operating Power-Supply Voltage Range Forward (Tx/Ty) and Reverse (Rx/Ry) Signals of V to V for Interface With Optoelectrical Isolators and Similar Devices That Need Unidirectional Can Interface Between I C Buses Operating at Input and Output Signal Paths Different Logic Levels V to 400-kHz Fast I C Bus Operation Over at Least Supports Bidirectional Data Transfer of I C Meters of Wire Bus Signals Low Standby Current Consumption Allows Bus Capacitance of 400 pF on the Main I C Bus (Sx/Sy Side) and 4000 pF on the Latch-Up Performance Exceeds 100 mA Per Transmission Side (Tx/Ty) JESD 78, Class II Outputs on the Transmission Side (Tx/Ty) ESD Protection Exceeds JESD Have High Sink Capability for Driving 3500-V Human-Body Model (A114-A) Low-Impedance or High-Capacitive Buses 200-V Machine Model (A115-A) I C Bus Signals Can Be Split Into Pairs of 1000-V Charged-Device Model (C101) The P82B96 is a bipolar device that supports bidirectional data transfer between the normal I C bus and a range of other bus configurations with different voltage and current levels. It can function as the interface without any limitations on the normal I C operation and clock speed. ORDERING INFORMATION T A PACKAGE (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP P Tube of P82B96P P82B96P Reel of 2000 P82B96DR SOIC D PG96 Tube of P82B96D C to C Reel of 2000 P82B96PWR TSSOP PW PG96 Tube of 150 P82B96PW VSSOP DGK Reel of 2500 P82B96DGKR 7DS (1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. PRODUCTION DATA information is current as of publication date. Copyright 2006 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) P82B96 DUAL BIDIRECTIONAL BUS BUFFER SCPS144B MAY 2006 REVISED JULY 2007 One of the advantages of the P82B96 is that it can isolate bus capacitance such that the total loading (devices and trace lengths) of the new bus or remote I C nodes are not apparent to other I C buses (or nodes). This device also adds minimal loading to I C node where it is positioned. Any restrictions on the number of I C devices in a system, or the physical separation between them, are virtually eliminated. The P82B96 easily can transmit SDA/SCL signals via balanced transmission lines (twisted pairs) or with galvanic isolation (optocoupling), because separate directional Tx and Rx signals are provided. The Tx and Rx signals may be connected directly (without causing bus latching), to provide an alternative bidirectional signal line with I C properties. Two or more Sx or Sy I/Os must not be interconnected. The P82B96 design does not support this configuration. Bidirectional I C signals do not allow any direction control pin so, instead, slightly different logic low-voltage levels are used at Sx/Sy to avoid latching of this buffer. A regular I C low applied at the Rx/Ry of a P82B96 is propagated to Sx/Sy as a buffered low with a slightly higher voltage level. If this special buffered low is applied to the Sx/Sy of another P82B96, the second P82B96 does not recognize it as a regular I C bus low and does not propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special logic thresholds for their operation, such as the PCA9515A. The Sx/Sy side is intended only for, and compatible with, the normal I C logic voltage levels of I C master and slave devices or Tx/Rx signals of a second P82B96, if required. The Tx/Rx and Ty/Ry I/O pins use the standard I C logic voltage levels of all I C parts. If Rx and Tx are connected, Sx can function as either the SDA or SCL line. Similarly, if Ry and Ty are connected, Sy can function as either the SDA or SCL line. There are no restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or multi-point configuration with the Tx/Rx and Ty/Ry I/O pins on the common bus, and the Sx/Sy side connected to the line-card slave devices. TERMINAL FUNCTIONS NO. NAME

DESCRIPTION

SDA. Connect to V CC of I C master through a pullup resistor. Rx Receive signal. Connect to V CC of P82B96 through a pullup resistor. Tx Transmit signal. Connect to V CC of P82B96 through a pullup resistor. GND Ground Ty Transmit signal. Connect to V CC of P82B96 through a pullup resistor. Ry Receive signal. Connect to V CC of P82B96 through a pullup resistor. Sy Serial clock bus or SCL. Connect to V CC of I C master through a pullup resistor. V CC Supply voltage Submit Documentation Feedback

www.ti.com P82B96 Sx (SDA) Sy (SCL) Ry (RxD, SCL) Ty (TxD, SCL) Rx (RxD, SDA) Tx (TxD, SDA)1 GND V (2–15□V)CC Functional I C pins, Sx and Sy, are designed to interface with a normal I C bus. The logic threshold-voltage levels on the I C bus are independent of the supply V CC The maximum I C bus supply voltage is and the specified static sink current is mA. Sx and Sy have two identical buffers. Each buffer is made up of two logic signal paths. The first one, named Tx or Ty, is a forward path from the I C interface pin, which drives the buffered bus. The second one, named Rx or Ry, is a reverse signal path from the buffered bus input to drive the I C bus interface. There are two purposes for these paths: to sense the voltage state of the I C pin (Sx or Sy) and transmit this state to Tx or Ty, respectively, and to detect the state of the Rx or Ry and pull the I C pin low when Rx or Ry is low. Tx and Ty are open-collector outputs without ESD protection diodes to V CC Each pin may be connected via a pullup resistor to a supply voltage in excess of V CC as long as the 15-V rating is not exceeded. Tx and Ty have a larger current-sinking capability than a normal I C device and can sink a static current of greater than mA. They also have dynamic pulldown capability of 100-mA, typically. A logic low is transmitted to Tx or Ty only when the voltage at the I C pin (Sx or Sy) is below 0.6 A logic low at Rx or Ry causes the I C bus (Sx or Sy) to be pulled to a logic low level in accordance with I C requirements (maximum 1.5 V in 5-V applications), but not low enough to be looped back to the Tx or Ty output and cause the buffer to latch low. The minimum low level that the P82B96 can achieve on the I C bus by a low at Rx or Ry typically is 0.8 If V CC fails, neither the I C pins nor the Tx or Ty outputs are held low. Their open-collector configuration allows them to be pulled up to the rated maximum of V without V CC present. The input configuration on Sx, Sy, Rx, and Ry also presents no loading of external signals when V CC is not present. The effective input capacitance of any signal pin, measured by its effect on bus rise times, is less than pF for all bus voltages and supply voltages, including V CC Submit Documentation Feedback

www.ti.com Absolute Maximum Ratings (1) Recommended Operating Conditions P82B96 DUAL BIDIRECTIONAL BUS BUFFER SCPS144B MAY 2006 REVISED JULY 2007 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range 0.3 V Sx or Sy (SDA or SCL) 0.3 V I Voltage range on buffered input V Rx or Ry 0.3 Sx or Sy (SDA or SCL) 0.3 V O Voltage range on buffered output V Tx or Ty 0.3 Sx or Sy 250 I O Continuous output current mA Tx or Ty 250 I CC Continuous current through V CC or GND 250 mA D package P package θ JA Package thermal impedance (2) C/W PW package 149 DGK package 172 T stg Storage temperature range 125 C T A Operating free-air temperature range C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The package thermal impedance is calculated in accordance with JESD 51-7. MIN MAX UNIT V CC Supply voltage V Sx, Sy V Sx V Sy V Rx V Ry 0.42 V I OL Low-level output current mA Tx, Ty V Sx V Sy 0.4 V Tx V Ty 0.4 V Sx, Sy V Tx V Ty 0.4 V V IOmax Maximum input/output voltage level V Tx, Ty V Sx V Sy 0.4 V V ILdiff Low-level input voltage difference Sx, Sy 0.4 V T A Operating free-air temperature C Submit Documentation Feedback

www.ti.com Electrical Characteristics P82B96 DUAL BIDIRECTIONAL BUS BUFFER SCPS144B MAY 2006 REVISED JULY 2007 V CC 2.3 V to 2.7 voltages are specified with respect to GND (unless otherwise noted) T A C T A C to C TEST PARAMETER UNIT CONDITIONS MIN TYP (1) MAX MIN MAX Temperature coefficient of Δ Δ T IN Sx, Sy mV/ C input thresholds I Sx I Sy mA 0.8 0.88 V OL Low-level output voltage Sx, Sy (2) V I Sx I Sy 0.2 mA 0.67 0.73 0.79 (2) Temperature coefficient of Δ V Δ T OUT Sx, Sy I Sx I Sy 0.2 mA 1.8 mV/ C output low levels (3) I CC Quiescent supply current Sx Sy V CC 0.9 1.8 mA Additional supply current Δ I CC Tx, Ty 1.7 2.75 mA per pin low Dynamic output sink V Sx V Sy 5.5 mA capability on I C bus V Rx V Ry low I IOS Sx, Sy V Sx V Sy 2.5 Leakage current on I C bus 0.1 μ A V Rx V Ry high V Tx V Ty Dynamic output sink Tx, Ty V Sx V Sy low on 100 mA capability on buffered bus I C bus 0.4 V I IOT V Tx V Ty V CC Leakage current 2.5 0.1 μ A on buffered bus V Sx V Sy high Bus low, V Rx Input current from I C bus Sx, Sy V Ry high Input current Bus low, V Rx I I μ A from buffered bus V Ry 0.4 V Rx, Ry Leakage current V Rx V Ry V CC 1.5 on buffered bus input Input logic level high threshold (4) 0.65 0.7 (2) on normal I C bus Sx, Sy Input logic level low threshold (4) 0.6 0.65 (2) V IT Input threshold V on normal I C bus Input logic level high 0.58 V CC 0.58 V CC Rx, Ry Input threshold 0.5 V CC Input logic level low 0.42 V CC 0.42 V CC Sx output low Input/output logic level at mA) V IOdiff Sx, Sy 100 150 100 mV difference (5) Sx input high max) for I C Sx, Sy are low, V CC V CC voltage at which all Sx, Sy ramping, voltage on V IOrel V buses are released Tx, Ty Tx, Ty lowered until released Temperature coefficient of release Δ Δ T REL mV/ C voltage C in Input capacitance Rx, Ry 2.5 pF (1) Typical value is at V CC 2.5 T A C (2) See the Typical Characteristics section of this data sheet. (3) The output logic low depends on the sink current. (4) The input logic threshold is independent of the supply voltage. (5) The minimum value requirement for pullup current, 200 μ ensures that the minimum value for V SX output low always exceeds the minimum V Sx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device. While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another P82B96, this has no consequences for normal applications. In any design, the Sx pins of different devices should never be linked, because the resulting system would be very susceptible to induced noise and would not support all I C operating modes. Submit Documentation Feedback

www.ti.com Electrical Characteristics P82B96 DUAL BIDIRECTIONAL BUS BUFFER SCPS144B MAY 2006 REVISED JULY 2007 V CC V to 3.6 voltages are specified with respect to GND (unless otherwise noted) T A C T A C to C PARAMETER TEST CONDITIONS UNIT MIN TYP (1) MAX MIN MAX Temperature Δ Δ T IN coefficient of Sx, Sy mV/ C input thresholds I Sx I Sy mA 0.8 0.88 Low-level output V OL Sx, Sy (2) V voltage I Sx I Sy 0.2 mA 0.67 0.73 0.79 (2) Temperature coefficient of Δ V Δ T OUT Sx, Sy I Sx I Sy 0.2 mA 1.8 mV/ C output low levels (3) I CC Quiescent supply current Sx Sy V CC 0.9 1.8 mA Additional supply Δ I CC current per pin Tx, Ty 1.7 2.75 mA low Dynamic output V Sx V Sy sink capability 5.7 mA V Rx V Ry low on I C bus I IOS Sx, Sy Leakage current V Sx V Sy 0.1 μ A on I C bus V Rx V Ry high Dynamic output V Tx V Ty sink capability V Sx V Sy low on I C 100 mA on buffered bus bus 0.4 V I IOT Tx, Ty Leakage current V Tx V Ty V CC 0.1 μ A on buffered bus 3.3 V Sx V Sy high Input current Bus low, V Rx Sx, Sy from I C bus V Ry high Input current Bus low, V Rx I I from buffered bus V Ry 0.4 V μ A Rx, Ry Leakage current on buffered bus V Rx V Ry V CC 1.5 input Input logic-level high threshold (4) 0.65 0.7 (2) on normal I C bus Sx, Sy Input logic-level low threshold (4) 0.6 0.65 (2) V IT Input threshold V on normal I C bus Input logic level high 0.58 V CC 0.58 V CC Rx, Ry Input threshold 0.5 V CC Input logic level low 0.42 V CC 0.42 V CC Sx output low Input/output logic at mA) V IOdiff Sx, Sy 100 150 100 mV level difference (5) Sx input high max) for I C Sx, Sy are low, V CC V CC voltage at Sx, Sy ramping, voltage on V IOrel which all buses V Tx, Ty Tx, Ty lowered until are released released (1) Typical value is at V CC 3.3 T A C (2) See the Typical Characteristics section of this data sheet. (3) The output logic low depends on the sink current. (4) The input logic threshold is independent of the supply voltage. (5) The minimum value requirement for pullup current, 200 μ ensures that the minimum value for V SX output low always exceeds the minimum V Sx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device. While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another P82B96, this has no consequences for normal applications. In any design, the Sx pins of different devices never should be linked, because the resulting system would be very susceptible to induced noise and would not support all I C operating modes. Submit Documentation Feedback

www.ti.com P82B96 DUAL BIDIRECTIONAL BUS BUFFER SCPS144B MAY 2006 REVISED JULY 2007 Electrical Characteristics (continued) V CC V to 3.6 voltages are specified with respect to GND (unless otherwise noted) T A C T A C to C PARAMETER TEST CONDITIONS UNIT MIN TYP (1) MAX MIN MAX Temperature coefficient of Δ Δ T REL mV/ C release voltage C in Input capacitance Rx, Ry 2.5 pF Submit Documentation Feedback

www.ti.com Electrical Characteristics P82B96 DUAL BIDIRECTIONAL BUS BUFFER SCPS144B MAY 2006 REVISED JULY 2007 V CC 4.5 V to 5.5 voltages are specified with respect to GND (unless otherwise noted) T A C T A C to C PARAMETER TEST CONDITIONS UNIT MIN TYP (1) MAX MIN MAX Temperature Δ Δ T IN coefficient of Sx, Sy mV/ C input thresholds I Sx I Sy mA 0.8 0.88 Low-level output V OL Sx, Sy (2) V voltage I Sx I Sy 0.2 mA 0.67 0.73 0.79 (2) Temperature coefficient of Δ V Δ T OUT Sx, Sy I Sx I Sy 0.2 mA 1.8 mV/ C output low levels (3) I CC Quiescent supply current Sx Sy V CC 0.9 1.8 mA Additional supply Δ I CC current Tx, Ty 1.7 2.75 mA per pin low Dynamic output V Sx V Sy sink capability mA V Rx V Ry low on I C bus I IOS Sx, Sy Leakage current V Sx V Sy 0.1 μ A on I C bus V Rx V Ry high Dynamic output V Tx V Ty sink capability V Sx V Sy low on 100 mA on buffered bus I C bus 0.4 V I IOT Tx, Ty Leakage current V Tx V Ty V CC 0.1 μ A on buffered bus V Sx V Sy high Input current Bus low, V Rx Sx, Sy from I C bus V Ry high Input current Bus low, V Rx I I from buffered bus V Ry 0.4 V μ A Rx, Ry Leakage current on buffered bus V Rx V Ry V CC 1.5 input Input logic-level high threshold (4) 0.65 0.7 (2) on normal I C bus Sx, Sy Input logic-level low threshold (4) 0.6 0.65 (2) V IT Input threshold V on normal I C bus Input logic level high 0.58 V CC 0.58 V CC Rx, Ry Input threshold 0.5 V CC Input logic level low 0.42 V CC 0.42 V CC Sx output low at Input/output logic mA) V IOdiff Sx, Sy 100 150 100 mV level difference (5) Sx input high max) for I C Sx, Sy are low, V CC V CC voltage at Sx, Sy ramping, voltage on V IOrel which all buses V Tx, Ty Tx, Ty lowered until are released released (1) Typical value is at V CC T A C (2) See the Typical Characteristics section of this data sheet. (3) The output logic low depends on the sink current. (4) The input logic threshold is independent of the supply voltage. (5) The minimum value requirement for pullup current, 200 μ ensures that the minimum value for V SX output low always exceeds the minimum V Sx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device. While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another P82B96, this has no consequences for normal applications. In any design, the Sx pins of different devices never should be linked, because the resulting system would be very susceptible to induced noise and would not support all I C operating modes. Submit Documentation Feedback

www.ti.com P82B96 DUAL BIDIRECTIONAL BUS BUFFER SCPS144B MAY 2006 REVISED JULY 2007 Electrical Characteristics (continued) V CC 4.5 V to 5.5 voltages are specified with respect to GND (unless otherwise noted) T A C T A C to C PARAMETER TEST CONDITIONS UNIT MIN TYP (1) MAX MIN MAX Temperature coefficient of Δ Δ T REL mV/ C release voltage C in Input capacitance Rx, Ry 2.5 pF Submit Documentation Feedback

www.ti.com Electrical Characteristics P82B96 DUAL BIDIRECTIONAL BUS BUFFER SCPS144B MAY 2006 REVISED JULY 2007 V CC voltages are specified with respect to GND (unless otherwise noted) T A C T A C to C PARAMETER TEST CONDITIONS UNIT MIN TYP (1) MAX MIN MAX Temperature Δ Δ T IN coefficient of Sx, Sy mV/ C input thresholds I Sx I Sy mA 0.8 0.88 Low-level output V OL Sx, Sy (2) V voltage I Sx I Sy 0.2 mA 0.67 0.73 0.79 (2) Temperature coefficient of Δ V Δ T OUT Sx, Sy I Sx I Sy 0.2 mA 1.8 mV/ C output low levels (3) Quiescent supply I CC Sx Sy V CC 0.9 1.8 mA current Additional supply Δ I CC current Tx, Ty 1.7 2.75 mA per pin low Dynamic output V Sx V Sy sink capability 6.5 mA V Rx V Ry low on I C bus I IOS Sx, Sy Leakage current V Sx V Sy 0.1 μ A on I C bus V Rx V Ry high Dynamic output V Tx V Ty sink capability V Sx V Sy low on 100 mA on buffered bus I C bus 0.4 V I IOT Tx, Ty V Tx V Ty V CC Leakage current 0.1 μ A on buffered bus V Sx V Sy high Input current Bus low, V Rx Sx, Sy from I C bus V Ry high Input current Bus low, V Rx I I from buffered bus V Ry 0.4 V μ A Rx, Ry Leakage current on buffered bus V Rx V Ry V CC 1.5 input Input logic-level high threshold (4) 0.65 0.7 (2) on normal I C bus Sx, Sy Input logic-level high threshold (4) 0.6 0.65 (2) V IT Input threshold V on normal I C bus Input logic level high 0.58 V CC 0.58 V CC Rx, Ry Input threshold 0.5 V CC Input logic level low 0.42 V CC 0.42 V CC Sx output low at Input/output logic mA) V IOdiff Sx, Sy 100 150 100 mV level difference (5) Sx input high max) for I C (1) Typical value is at V CC T A C (2) See the Typical Characteristics section of this data sheet. (3) The output logic low depends on the sink current. (4) The input logic threshold is independent of the supply voltage. (5) The minimum value requirement for pullup current, 200 μ ensures that the minimum value for V SX output low always exceeds the minimum V Sx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device. While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another P82B96, this has no consequences for normal applications. In any design, the Sx pins of different devices never should be linked, because the resulting system would be very susceptible to induced noise and would not support all I C operating modes. Submit Documentation Feedback

www.ti.com Switching Characteristics P82B96 DUAL BIDIRECTIONAL BUS BUFFER SCPS144B MAY 2006 REVISED JULY 2007 Electrical Characteristics (continued) V CC voltages are specified with respect to GND (unless otherwise noted) T A C T A C to C PARAMETER TEST CONDITIONS UNIT MIN TYP (1) MAX MIN MAX Sx, Sy are low, V CC V CC voltage at Sx, Sy ramping, voltage on V IOrel which all buses V Tx, Ty Tx, Ty lowered until are released released Temperature coefficient of Δ Δ T REL mV/ C release voltage C in Input capacitance Rx, Ry 2.5 pF V CC T A no capacitive loads, voltages are specified with respect to GND (unless otherwise noted) FROM TO PARAMETER TEST CONDITIONS TYP UNIT (INPUT) (OUTPUT) R Tx pullup 160 Ω Buffer delay time on falling V Sx (or V Sy input switching V Tx (or V Ty output falling t pzl C Tx pF board ns input (1) threshold 50% of V LOAD trace capacitance R Tx pullup 160 Ω Buffer delay time on rising V Sx (or V Sy input switching V Tx (or V Ty output t plz C Tx pF board ns input (2) threshold reaching 50% of V LOAD trace capacitance R Sx pullup 1500 Ω Buffer delay time on falling V Rx (or V Ry input switching V Sx (or V Sy output falling t pzl C Tx pF board 250 ns input (3) threshold 50% of V LOAD trace capacitance R Sx pullup 1500 Ω Buffer delay time on rising V Rx (or V Ry input switching V Sx (or V Sy output t plz C Tx pF board 270 ns input (4) threshold reaching 50% of V LOAD trace capacitance (1) The fall time of V Tx from V to 2.5 V in the test is approximately ns. (2) The fall time of V Sx from V to 2.5 V in the test is approximately ns. (3) The rise time of V Tx from V to 2.5 V in the test is approximately ns. (4) The rise time of V Sx from 0.9 V to 2.5 V in the test is approximately ns. Submit Documentation Feedback

www.ti.com TYPICAL CHARACTERISTICS 1200 400 1000 800 600 -50 100 7550250–25 125 V – mV OL T – °Cj Maximum Typical Minimum 600 800 1000 400 -50 100 7550250–25 125 V – mV OL T – °Cj Maximum Typical Minimum 1000 200 800 600 400 -50 100 7550250–25 125 V – mV IH(min) T – °Cj 1000 200 800 600 400 -50 100 7550250–25 125 V – mV IL(max) T – °Cj 600 1400 400 800 1000 1200 -50 100 7550250–25 125 V – mV CC(max) T – °Cj P82B96 DUAL BIDIRECTIONAL BUS BUFFER SCPS144B MAY 2006 REVISED JULY 2007 V OL AT Sx V OL AT Sx vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE I OL 0.2 mA I OL mA V IL(max) AT Sx V IH(min) AT Sx vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE V CC(max) vs JUNCTION TEMPERATURE Submit Documentation Feedback

www.ti.com PARAMETER MEASUREMENT INFORMATION tPLZ/tPZL VCC TEST S1 C = Probe and jig capacitance (see Note A) L GND R = 160 to 1500L /c87 VCC Tx or Ty PULSE GENERATOR DUT RT VCC VIN VOUT tPLZtPZL VCC 0 V Sx or Sy VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES TEST CIRCUIT FOR OPEN-DRAIN OUTPUT 0.6 V VCC VOL

0.5 V/c180 CC

C L includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR MHz, Z O Ω t r f ns. Figure Test Circuit and Voltage Waveforms Submit Documentation Feedback

www.ti.com APPLICATION INFORMATION Typical 5□V V (2–15V)CC 1/2 PB2B96 Tx (SDA) Rx (SDA) SDA (New□Levels) I C SDA 5□V 1/2 P82B96 I C SDA Tx (SDA) Rx (SDA) VCC VCC1 I C SDA SCL SCL SDA P82B96 Main Enclosure Remote-Control Enclosure 3.3–5 V 3.3–5 V

12 V 12 V

3.3–5 V 3.3–5 V SDA P82B96 P82B96 DUAL BIDIRECTIONAL BUS BUFFER SCPS144B MAY 2006 REVISED JULY 2007 Figure through Figure show typical P82B96. Figure Interfacing I C Bus With Different Logic Levels Figure Galvanic Isolation of I C Nodes Figure Long-Distance I C Communications Submit Documentation Feedback

www.ti.com SCL SCL SDA P82B96 3-m to 20-m Cables P82B96 V +V Cable Drive VCC I C/DDC Master GND Sx Sy Rx Tx Ry T y 470 k/c87 4700 /c87 I C/DDC Rx Tx T y Ry VCC1 VCC2 Sx Sy I C/DDC Slave PC/TV Receiver/Decoder Box Monitor/Flat TV Video Signals R G B 100 k /c87 100 nF 470 k/c87 +V Cable Drive VCC GND BC 847B BC 847B SDA P82B96 DUAL BIDIRECTIONAL BUS BUFFER SCPS144B MAY 2006 REVISED JULY 2007 APPLICATION INFORMATION (continued) Figure shows how a master I C bus can be protected against short circuits or failures in damaged. A simple circuit is added to monitor the SDA bus and, if its low time exceeds the design value, disconnect the master bus. P82B96 frees all of its I/Os if its supply is removed, so one option is to connect its V CC to the output of a logic gate from, for example, the LVC family. The SDA and SCL lines could be timed, and V CC disabled via the gate, if a line exceeds a design value of the low period. If the supply voltage of logic gates restricts the choice of V CC supply, the low-cost discrete circuit in Figure can be used. If the SDA line is held low, the 100-nF capacitor charges, and Ry is pulled toward V CC When it exceeds V CC /2, Ry sets Sy high, which effectively releases it. Figure Extending DCC Bus In this example, the SCL line is made unidirectional by tying Rx to V CC The state of the buffered SCL line cannot affect the master clock line, which is allowed when clock stretching is not required. It is simple to add an additional transistor or diode to control the Rx input in the same way as Ry, when necessary. The cable drive can be any voltage up to and the bus may be run at a lower impedance by selecting pullup resistors for a static sink current up to mA. V CC1 and V CC2 may be chosen to suit the connected devices. Because DDC uses relatively low speeds <100 kHz), the cable length is not restricted to m by the I C signaling, but it may be limited by the video signaling. Figure and Table show that P82B96 can achieve high clock rates over long cables. While calculating with lumped wiring capacitance yields reasonable approximations to actual timing; even m of cable is better treated using transmission line theory. Flat ribbon cables connected as shown, with the bus signals on the outer edge, have a characteristic impedance in the range 100 200 Ω For simplicity, they cannot be terminated in their characteristic impedance, but a practical compromise is to use the minimum pullup allowed for P82B96 and place half this termination at each end of the cable. When each pullup is below 330 Ω the rising-edge waveforms have their first voltage step level above the logic threshold at Rx, and cable timing calculations can be based on the fast rise/fall times of resistive loading, plus simple one-way propagation delays. When the pullup is larger, but below 750 Ω the threshold at Rx is crossed after one signal reflection. So, at the sending Submit Documentation Feedback

www.ti.com SCL SDA P82B96 GND SCL SDA P82B96 R1R1 R2R2 R2 R2 R1R1 Cable +V Cable Drive Propagation Delay = 5 ns/m I C MASTER

2 I C

SLAVE(S) C2 C2 VCC1 VCC Rx Tx Ry Ty Sx Sy VCC Rx Tx Ry Ty Sx Sy VCC2 GND BAT54A BAT54A C2 C2 P82B96 DUAL BIDIRECTIONAL BUS BUFFER SCPS144B MAY 2006 REVISED JULY 2007 APPLICATION INFORMATION (continued) end, it is crossed after two times the one-way propagation delay and, at the receiving end, after three times that propagation delay. For flat cables with partial plastic dielectric insulation (by using outer cores) the one-way propagation delays are about ns/m. The 10% to 90% rise and fall times on the cable are between ns and ns, so their delay contributions are small. There is ringing on falling edges that can be damped, if required, using Schottky diodes, as shown. Figure Driving Ribbon or Flat Telephone Cables Table Bus Capabilities MASTER SCL BUS MAXIMUM PULSE CABLE CABLE V CC1 V CC2 CABLE CLOCK SLAVE DURATION CABLE LENGTH DELAY (V) (V) Ω Ω (pF) CAPACITANCE SPEED RESPONSE (ns) (V) (m) (ns) (kHz) DELAY HIGH LOW 750 2.2 400 250 (1) 1250 600 4000 120 (2) 750 2.2 220 100 (1) 500 600 2600 185 (2) 3.3 3.3 330 220 nF 125 600 1500 390 (2) 3.3 3.3 330 100 120 pF 600 1000 500 600 ns (1) Not applicable; calculations are delay based. (2) Normal 400-kHz bus specification When the master SCL high and low periods can be programmed separately, the timings can allow for bus delays. The low period should be programmed to achieve the minimum 1300 ns plus the net delay in the slave response data signal caused by bus and buffer delays. The longest data delay is the sum of the delay of the falling edge of SCL from master to slave and the delay of the rising edge of SDA from slave data to master. Because the buffer stretches the programmed SCL low period, the actual SCL frequency is lower than calculated from the programmed clock periods. In the example for the 25-m cable in Table the clock is stretched 400 ns, the falling edge of SCL is delayed 490 ns, and the SDA rising edge is delayed 570 ns. The required additional low period is (490 570) 1060 ns and the I C bus specifications already include an allowance for a worst-case bus rise time (0% to 70%) of 425 ns. The bus rise time can be 300 ns (30% to 70%), which means it can be 425 ns (0% to 70%). The 25-m cable delay times include all rise and fall times. Therefore, the device only needs to be programmed with an additional (1060 400 425) 235 ns, making a total programmed low period 1535 ns. The programmed low is stretched by 400 ns to yield an actual bus low time of 1935 ns, which, allowing the minimum high period of 600 ns, yields a cycle period of 2535 ns or 394 kHz. Submit Documentation Feedback

www.ti.com Calculating System Delays and Bus-Clock Frequency for Fast Mode System MASTER I C2 I C2 SLA VE P82B96 P82B96 SCL Rm Rb Rs VCCS SCL Sx Tx/Rx Tx/Rx Sx GND Falling edge of SCL at master is delayed by the buffers and bus fall times. Local Master Bus VCCB Effective□Delay□of□SCL at□Slave□=□255□+□17□V +□(2.5□+□4 10 Cb)□V (ns) CCM CCB× VCCM Cb□=□Buffered□Bus Wiring□Capacitance Cm□=□Master□Bus Capacitance Cs□=□Slave□Bus Capacitance Buffered□Expansion□Bus Remote□Slave□Bus MASTER P82B96 VCCM SCL Rm Rb Sx Tx/Rx Tx/Rx GND VCCB I C Cb□=□Buffered□Bus Wiring□Capacitance Cm□=□Master□Bus Capacitance Rising□edge□of□SCL at□master□is□delayed□(clock□stretch)□by□buffer□and□bus□rise□times. Effective□delay□of□SCL at□master□=□270□+□RmCm□+□0.7RbCb□(ns) C□=□F,□R□= Ω Local□Master□Bus Buffered□Expansion□Bus P82B96 DUAL BIDIRECTIONAL BUS BUFFER SCPS144B MAY 2006 REVISED JULY 2007 Note that, in both the 100-m and 250-m examples, the capacitive loading on the I C buses at each end is within the maximum allowed Standard mode loading of 400 pF, but exceeds the Fast mode limit. This is an example of a hybrid mode, because it relies on the response delays of Fast mode parts, but uses (allowable) Standard mode bus loadings with rise times that contribute significantly to the system delays. The cables cause large propagation delays. Therefore, these systems must operate well below the 400-kHz limit, but illustrate how they still can exceed the 100-kHz limit, provided all parts are capable of Fast mode operation. The fastest example illustrates how the 400-kHz limit can be exceeded, provided master and slave parts have delay specifications smaller than the maximum allowed. Many TI slaves have delays shorter than 600 ns, but none have that specified. Figure through Figure show the P82B96 used to drive extended bus wiring, with relatively large capacitance, linking two Fast mode I C bus nodes. It includes simplified expressions for making the relevant timing calculations for 3.3-/5-V operation. Because the buffers and the wiring introduce timing delays, it may be necessary to decrease the nominal SCL frequency below 400 kHz. In most cases, the actual bus frequency is lower than the nominal master timing, due to bit-wise stretching of the clock periods. Figure Figure Submit Documentation Feedback

www.ti.com MASTER P82B96 P82B96 SDA Rm Rb Rs SDA Sx Tx/Rx Tx/Rx Sx GND I C2 VCCS Local Master Bus VCCM Cb□=□Buffered□Bus Wiring□Capacitance Cm□=□Master□Bus Capacitance Cs□=□Slave□Bus Capacitance Buffered□Expansion□Bus Remote□Slave□Bus I C2 SLAVE VCCB Rising□edge□of□SDA at□slave□is□delayed□by□the□buffers□and□bus□rise□times. Effective□delay□of□SDA at□master□=□270□+□0.2RsCs□+□0.7(RbCb□+□RmCm)□(ns) C□=□F,□R□= Ω P82B96 DUAL BIDIRECTIONAL BUS BUFFER SCPS144B MAY 2006 REVISED JULY 2007 Figure The delay factors involved in calculation of the allowed bus speed are: The propagation delay of the master signal through the buffers and wiring to the slave. The important delay is that of the falling edge of SCL, because this edge requests the data or ACK from a slave. The effective stretching of the nominal low period of SCL at the master, caused by the buffer and bus rise times. The propagation delay of the slave response signal through the buffers and wiring back to the master. The important delay is that of a rising edge in the SDA signal. Rising edges always are slower and, therefore, are delayed by a longer time than falling edges. (The rising edges are limited by the passive pullup, while falling edges actively are driven.) The timing requirement in any I C system is that a slave s data response (which is provided in response to a falling edge of SCL) must be received at the master before the end of the corresponding low period of SCL as it appears on the bus wiring at the master. Because all slaves, as a minimum, satisfy the worst-case timing requirements of a 400-kHz part, they must provide their response within the minimum allowed clock low period of 1300 ns. Therefore, in systems that introduce additional delays, it is necessary only to extend that minimum clock low period by any effective delay of the slave response. The effective delay of the slave's response equals the total delays in SCL falling edge from the master reaching the slave (A) minus the effective delay (stretch) of the SCL rising edge (B) plus total delays in the slave response data, carried on SDA, and reaching the master (C). The master microcontroller should be programmed to produce a nominal SCL low period of (1300 A B ns and should be programmed to produce the nominal minimum SCL high period of 600 ns. Then, a check should be made to ensure the cycle time is not shorter than the minimum 2500 ns. If found to be necessary, increase either clock period. Due to clock stretching, the SCL cycle time always is longer than (600 1300 A ns. Submit Documentation Feedback

www.ti.com Sample Calculations P82B96 DUAL BIDIRECTIONAL BUS BUFFER SCPS144B MAY 2006 REVISED JULY 2007 The master bus has an RmCm product of 100 ns and V CCM The buffered bus has a capacitance of nF and a pullup resistor of 160 Ω to giving an RbCb product of 160 ns. The slave bus also has an RsCs product of 100 ns. The master low period should be programmed to be (1300 372.5 482 472) ns, which calculates to 1662.5 ns. The master high period may be programmed to the minimum 600 ns. The nominal master clock period is (1662.5 600) ns 2262.5 ns, equivalent to a frequency of 442 kHz. The actual bus-clock period, including the 482-ns clock stretch effect, is below (nominal stretch) (2262.5 482) ns or 2745 ns, equivalent to an allowable frequency of 364 kHz. Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) P82B96D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM P82B96DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM P82B96DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM P82B96DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM P82B96DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM P82B96DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM P82B96P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type P82B96PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type P82B96PW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM P82B96PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM P82B96PWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM P82B96PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. PACKAGE OPTION ADDENDUM www.ti.com 25-Jul-2007 Addendum-Page 1

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 25-Jul-2007 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2009 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) P82B96DGKR MSOP DGK 8 2500 358.0 335.0 35.0 P82B96DR SOIC D 8 2500 346.0 346.0 29.0 P82B96PWR TSSOP PW 8 2000 346.0 346.0 29.0 PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2009 Pack Materials-Page 2

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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