P82B96PN

P82B96 PHILIPS | Alldatasheet

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/C0080 /C0115 /C0111/C0110/C0111 /C0115 P82B96 Dual bi-directional bus buffer Product data Supersedes data of 2003 Apr 02

2004 Mar 26

Philips Semiconductors Product data P82B96Dual bi-directional bus buffer

22004 Mar 26

FEATURES

• Bi-directional data transfer of I2C-bus signals
• Isolates capacitance allowing 400 pF on Sx/Sy side and 4000 pF on Tx/Ty side
• Tx/Ty outputs have 60 mA sink capability for driving low impedance or high capacitive buses
• 400 kHz operation over at least 20 meters of wire (see AN10148 )
• Supply voltage range of 2 V to 15 V with I2C logic levels on Sx/Sy side independent of supply voltage
• Splits I2C signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals for interface with opto-electrical isolators and similar devices that need uni-directional input and output signal paths.
• Low power supply current
• ESD protection exceeds 3500 V HBM per JESD22-A114,

250 V DIP package / 400 V SO package MM per JESD22-A115,

and 1000 V CDM per JESD22-C101

• Latch-up free (bipolar process with no latching structures)
• Packages offered: DIP, SO, and TSSOP TYPICAL APPLICATIONS
• Interface between I2C buses operating at different logic levels (e.g., 5 V and 3 V or 15 V)
• Interface between I2C and SMB (350 µA) bus standard.
• Simple conversion of I2C SDA or SCL signals to multi-drop differential bus hardware, e.g., via compatible PCA82C250.
• Interfaces with Opto-couplers to provide Opto isolation between I2C-bus nodes up to 400 kHz.

DESCRIPTION

The P82B96 is a bipolar IC that creates a non-latching, bi-directional, logic interface between the normal I2C-bus and a range of other bus configurations. It can interface I2C-bus logic signals to similar buses having different voltage and current levels. For example it can interface to the 350 µA SMB bus, to 3.3 V logic devices, and to 15 V levels and/or low impedance lines to improve noise immunity on longer bus lengths. It achieves this interface without any restrictions on the normal I2C protocols or clock speed. The IC adds minimal loading to the I2C node, and loadings of the new bus or remote I2C nodes are not transmitted or transformed to the local node. Restrictions on the number of I2C devices in a system, or the physical separation between them, are virtually eliminated. Transmitting SDA/SCL signals via balanced transmission lines (twisted pairs) or with galvanic isolation (opto-coupling) is simple because separate directional Tx and Rx signals are provided. The Tx and Rx signals may be directly connected, without causing latching, to provide an alternative bi-directional signal line with I 2C properties. PIN CONFIGURATIONS 8-pin dual in-line, SO, TSSOP 8Sx Rx Tx GND Ty Ry Sy VCC SU01011 PINNING ÁÁÁÁÁÁ ÁÁÁÁÁÁ SYMBOL ÁÁÁ ÁÁÁ PIN ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Sx ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ I2C-bus (SDA or SCL) ÁÁÁÁÁÁ ÁÁÁÁÁÁ Rx ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Receive signal ÁÁÁÁÁÁ ÁÁÁÁÁÁ Tx ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Transmit signal ÁÁÁÁÁÁ ÁÁÁÁÁÁ GND ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Negative Supply ÁÁÁÁÁÁ ÁÁÁÁÁÁ Ty ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Transmit signal ÁÁÁÁÁÁ ÁÁÁÁÁÁ Ry ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Receive signal ÁÁÁÁÁÁ ÁÁÁÁÁÁ Sy ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ I2C-bus (SDA or SCL) ÁÁÁÁÁÁ ÁÁÁÁÁÁ VCC ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Positive supply SPECIAL NOTE: Two or more Sx or Sy I/Os must not be interconnected. The P82B96 design does not support this configuration. Bi-directional I2C signals do not allow any direction control pin so, instead, slightly different logic low voltage levels are used at Sx/Sy to avoid latching of this buffer. A “regular I2C low” applied at the Rx/Ry of a P82B96 will be propagated to Sx/Sy as a “buffered low” with a slightly higher voltage level. If this special “buffered low” is applied to the Sx/Sy of another P82B96 that second P82B96 will not recognize it as a “regular I 2C-bus low” and will not propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special logic thresholds for their operation, for example PCA9511, PCA9515, or PCA9518. The Sx/Sy side is only intended for, and compatible with, the normal I 2C logic voltage levels of I2C master and slave chips—or even Tx/Rx signals of a second P82B96 if required. The Tx/Rx and Ty/Ry I/O pins use the standard I2C logic voltage levels of all I2C parts. There are NO restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or multi-point configuration with the Tx/Rx and Ty/Ry I/O pins on the common bus and the Sx/Sy side connected to the line card slave devices. For more details see Application Note AN255.

Philips Semiconductors Product data P82B96Dual bi-directional bus buffer

2004 Mar 26 3

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER 8-pin plastic dual In-line package –40 °C to +85 °C P82B96PN P82B96PN SOT97-1 8-pin plastic small outline package –40 °C to +85 °C P82B96TD P82B96T SOT96-1 8-pin plastic thin shrink small outline package–40 °C to +85 °C P82B96DP 82B96 SOT505-1 NOTE: 1. Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging. BLOCK DIAGRAM P82B96 Sx (SDA) Sy (SCL) Ry (RxD, SCL) Ty (TxD, SCL) Rx (RxD, SDA) Tx (TxD, SDA)1 GND +V CC (2–15 V) SU01012 FUNCTIONAL DESCRIPTION The P82B96 has two identical buffers allowing buffering of both of the I2C (SDA and SCL) signals. Each buffer is made up of two logic signal paths, a forward path from the I2C interface pin which drives the buffered bus, and a reverse signal path from the buffered bus input to drive the I 2C-bus interface. Thus these paths are: 1. Sense the voltage state of the I2C pin Sx (or Sy) and transmit this state to the pin Tx (Ty resp.), and 2. Sense the state of the pin Rx (Ry) and pull the I2C pin LOW whenever Rx (Ry) is LOW. The rest of this discussion will address only the “x” side of the buffer: the “y” side is identical. The I2C pin (Sx) is designed to interface with a normal I2C-bus. The logic threshold voltage levels on the I2C-bus are independent of the IC supply VCC The maximum I2C-bus supply voltage is 15 V and the guaranteed static sink current is 3 mA. The logic level of Rx is determined from the power supply voltage VCC of the chip. Logic LOW is below 42 % of VCC , and logic HIGH is above 58 % of VCC : with a typical switching threshold of half VCC. Tx is an open collector output without ESD protection diodes to VCC . It may be connected via a pull-up resistor to a supply voltage in excess of VCC, as long as the 15 V rating is not exceeded. It has a larger current sinking capability than a normal I2C device, being able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down capability as well. A logic LOW is only transmitted to Tx when the voltage at the I2C pin (Sx) is below 0.6 V. A logic LOW at Rx will cause the I2C-bus (Sx) to be pulled to a logic LOW level in accordance with I2C requirements (max. 1.5 V in 5 V applications) but not low enough to be looped back to the Tx output and cause the buffer to latch LOW. The minimum LOW level this chip can achieve on the I2C-bus by a LOW at Rx is typically 0.8 V. If the supply voltage VCC fails, then neither the I2C nor the Tx output will be held LOW. Their open collector configuration allows them to be pulled up to the rated maximum of 15 V even without V CC present. The input configuration on Sx and Rx also present no loading of external signals even when V CC is not present. The effective input capacitance of any signal pin, measured by its effect on bus rise times, is less than 7 pF for all bus voltages and supply voltages including VCC = 0 V.

Philips Semiconductors Product data P82B96Dual bi-directional bus buffer

2004 Mar 26 4

In accordance with the Absolute Maximum Rating System (IEC 134). Voltages with respect to pin GND (pin 4). ÁÁÁÁÁ ÁÁÁÁÁ SYMBOL ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PARAMETER ÁÁÁÁ ÁÁÁÁ MIN. ÁÁÁÁÁ ÁÁÁÁÁ MAX. ÁÁÁÁ ÁÁÁÁ UNIT ÁÁÁÁÁ ÁÁÁÁÁ VCC to GND ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Supply voltage range VCC ÁÁÁÁ ÁÁÁÁ –0.3 ÁÁÁÁÁ ÁÁÁÁÁ +18 ÁÁÁÁ ÁÁÁÁ V ÁÁÁÁÁ Vbus ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Voltage range on I2C Bus, SDA or SCL ÁÁÁÁ –0.3 ÁÁÁÁÁ +18 ÁÁÁÁ V ÁÁÁÁÁ ÁÁÁÁÁ VTx ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Voltage range on buffered output ÁÁÁÁ ÁÁÁÁ –0.3 ÁÁÁÁÁ ÁÁÁÁÁ +18 ÁÁÁÁ ÁÁÁÁ V ÁÁÁÁÁ ÁÁÁÁÁ VRx ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Voltage range on receive input ÁÁÁÁ ÁÁÁÁ –0.3 ÁÁÁÁÁ ÁÁÁÁÁ +18 ÁÁÁÁ ÁÁÁÁ V ÁÁÁÁÁ ÁÁÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DC current (any pin) ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 250 ÁÁÁÁ ÁÁÁÁ mA ÁÁÁÁÁ ÁÁÁÁÁ R tot ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Power dissipation ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 300 ÁÁÁÁ ÁÁÁÁ mW ÁÁÁÁÁ ÁÁÁÁÁ Tstg ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Storage temperature range ÁÁÁÁ ÁÁÁÁ –55 ÁÁÁÁÁ ÁÁÁÁÁ +125 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Tamb ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Operating ambient temperature range ÁÁÁÁ ÁÁÁÁ –40 ÁÁÁÁÁ ÁÁÁÁÁ +85 ÁÁÁÁ ÁÁÁÁ CHARACTERISTICS At Tamb = 25 °C; Voltages are specified with respect to GND with VCC = 5 V unless otherwise stated. ÁÁÁÁÁ ÁÁÁÁÁ SYMBOL ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ PARAMETER ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ CONDITIONS ÁÁÁÁ ÁÁÁÁ MIN. ÁÁÁ ÁÁÁ TYP. ÁÁÁ ÁÁÁ MAX. ÁÁÁÁ ÁÁÁÁ UNIT ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Power Supply ÁÁÁÁÁ ÁÁÁÁÁ VCC ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Supply voltage (operating) ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 2.0 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ V ÁÁÁÁÁ ÁÁÁÁÁ ICC ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Supply current, buses HIGH ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ 0.9 ÁÁÁ ÁÁÁ 1.8 ÁÁÁÁ ÁÁÁÁ mA ÁÁÁÁÁ ICC ÁÁÁÁÁÁÁÁÁÁÁ Supply current at VCC = 15 V, buses HIGH ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ 1.1 ÁÁÁ 2.5 ÁÁÁÁ mA ÁÁÁÁÁ ÁÁÁÁÁ ICC ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Additional supply current per Tx or Ty LOW ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ 1.7 ÁÁÁ ÁÁÁ 3.5 ÁÁÁÁ ÁÁÁÁ mA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Bus pull-up (load) voltages and currents ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ VSx, VSy ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Maximum input/output voltage level ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ Open collector; I2C-bus and VRx, VRy = HIGH ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ V ÁÁÁÁÁ ÁÁÁÁÁ ISx, ISy ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Static output loading on I2C-bus (Note 1) ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ VSx, VSy = 1.0 V; VRx, VRy = LOW ÁÁÁÁ ÁÁÁÁ 0.2 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ mA ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ ISx, ISy ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Dynamic output sink capability on I2C-bus ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ VSx, VSy > 2 V; VRx, VRy = LOW ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ mA ÁÁÁÁÁ ÁÁÁÁÁ ISx, ISy ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Leakage current on I2C-bus ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ VSx, VSy = 5 V; VRx, VRy = HIGH ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ µA ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ ISx, ISy ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Leakage current on I2C-bus ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ VSx, VSy = 15 V; VRx, VRy = HIGH ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ µA ÁÁÁÁÁ ÁÁÁÁÁ VTx, VTy ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Maximum output voltage level ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Open collector ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ V ÁÁÁÁÁ ÁÁÁÁÁ ITx, ITy ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Static output loading on buffered bus ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ VTx, VTy = 0.4 V; VSx, VSy = LOW on I2C-bus = 0.4 V ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ mA ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ ITx, ITy ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Dynamic output sink capability, buffered bus ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ VTx, VTy > 1 V VSx, VSy = LOW on I2C-bus = 0.4 V ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ 100 ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ mA ÁÁÁÁÁ ÁÁÁÁÁ ITx, ITy ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Leakage current on buffered bus ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ VTx, VTy = VCC = 15 V; VSx, VSy = HIGH ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ µA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Currents ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ ISx, ISy ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Input current from I2C-bus ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ bus LOW VRx, VRy = HIGH ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ µA ÁÁÁÁÁ ÁÁÁÁÁ IRx, IRy ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Input current from buffered bus ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ bus LOW VRx, VRy = 0.4 V ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ µA ÁÁÁÁÁ ÁÁÁÁÁ IRx, IRy ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Leakage current on buffered bus input ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ VRx, VRy = VCC ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ µA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Output Logic LOW Levels ÁÁÁÁÁ ÁÁÁÁÁ VSx, VSy ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Output logic level LOW, on normal I2C bus (Note 2) ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ISx, ISy = 3 mA ÁÁÁÁ ÁÁÁÁ 0.8 ÁÁÁ ÁÁÁ 0.88 ÁÁÁ ÁÁÁ 1.0 ÁÁÁÁ ÁÁÁÁ V ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ VSx, VSy ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Output logic level LOW, on normal I2C bus (Note 2) ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ ISx, ISy = 0.2 mA ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ 670 ÁÁÁ Á Á Á ÁÁÁ 730 ÁÁÁ Á Á Á ÁÁÁ 790 ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ mV ÁÁÁÁÁ ÁÁÁÁÁ dVSx/dT, dVSy/dT ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Temperature coefficient of output LOW levels (Note 2) ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ISx, ISy = 0.2 mA ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ –1.8 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ mV/K

Philips Semiconductors Product data P82B96Dual bi-directional bus buffer

2004 Mar 26 5

ÁÁÁÁ ÁÁÁÁ UNIT ÁÁÁ ÁÁÁ MAX. ÁÁÁ ÁÁÁ TYP. ÁÁÁÁ ÁÁÁÁ MIN. ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ CONDITIONS ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ PARAMETER ÁÁÁÁÁ ÁÁÁÁÁ SYMBOL ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input logic switching threshold voltages ÁÁÁÁÁ ÁÁÁÁÁ VSx, VSy ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Input logic voltage LOW (Note 3) ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ On normal I2C-bus ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ 640 ÁÁÁ ÁÁÁ 600 ÁÁÁÁ ÁÁÁÁ mV ÁÁÁÁÁ ÁÁÁÁÁ VSx, VSy ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Input logic level HIGH threshold (Note 3) ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ On normal I2C-bus ÁÁÁÁ ÁÁÁÁ 700 ÁÁÁ ÁÁÁ 650 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ mV ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ dVSx/dT, dVSy/dT ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Temperature coefficient of input thresholds ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ mV/K ÁÁÁÁÁ ÁÁÁÁÁ VRx, VRy ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Input logic HIGH level ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Fraction of applied VCC ÁÁÁÁ ÁÁÁÁ 0.58 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ V ÁÁÁÁÁ VRx, VRy ÁÁÁÁÁÁÁÁÁÁÁ Input threshold ÁÁÁÁÁÁÁÁÁÁ Fraction of applied VCC ÁÁÁÁ ÁÁÁ 0.5 ÁÁÁ ÁÁÁÁ V ÁÁÁÁÁ ÁÁÁÁÁ VRx, VRy ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Input logic LOW level ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Fraction of applied VCC ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 0.42 ÁÁÁÁ ÁÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Logic level threshold difference ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ VSx, VSy ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Input/Output logic level difference (Note 1) ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ VSX output LOW at 0.2 mA – VSX input HIGH max ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ mV NOTES: 1. The minimum value requirement for pull-up current, 200 µA, guarantees that the minimum value for VSX output LOW will always exceed the minimum VSX input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any IC. While the tolerances on absolute levels allow a small probability the LOW from one SX output is recognized by an SX input of another P82B96 this has no consequences for normal applications. In any design the SX pins of different ICs should never be linked because the resulting system would be very susceptible to induced noise and would not support all I2C operating modes. 2. The output logic LOW depends on the sink current. For scaling, see Application Note AN255. 3. The input logic threshold is independent of the supply voltage. CHARACTERISTICS At Tamb = 25 °C; Voltages are specified with respect to GND with VCC = 5 V unless otherwise stated. ÁÁÁÁÁ ÁÁÁÁÁ SYMBOL ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ PARAMETER ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ CONDITIONS ÁÁÁÁ ÁÁÁÁ MIN. ÁÁÁÁ ÁÁÁÁ TYP. ÁÁÁ ÁÁÁ MAX. ÁÁÁÁ ÁÁÁÁ UNIT ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Bus Release on VCC Failure ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ VSx, VSy, VTx, VTy ÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁ VCC voltage at which all buses are guaranteed to be released ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ V ÁÁÁÁÁ ÁÁÁÁÁ dV/dT ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Temperature coefficient of guaranteed release voltage ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ mV/K ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Buffer response time ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ Tfall delay VSx to VTx VSy to VTy ÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁ Buffer time delay on FALLING input between VSx = input switching threshold, and VTx output falling 50%. ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ R Tx pull-up = 160 Ω , no capacitive load, VCC = 5 V ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ns ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ Trise delay VSx to VTx VSy to VTy ÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁ Buffer time delay on RISING input between VSx = input switching threshold, and VTx output reaching 50% VCC ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ R Tx pull-up = 160 Ω , no capacitive load, VCC = 5 V ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ns ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ Tfall delay VRx to VSx VRy to VSy ÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁ Buffer time delay on FALLING input between VRx = input switching threshold, and VSx output falling 50%. ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ R Sx pull-up = 1500 Ω , no capacitive load, VCC = 5 V ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ 250 ÁÁÁ Á Á Á Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ns ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ Trise delay VRx to VSx VRy to VSy ÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁ Buffer time delay on RISING input between VRx = input switching threshold, and VSx output reaching 50% VCC ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ R Sx pull-up = 1500 Ω , no capacitive load, VCC = 5 V ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ 270 ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input capacitance ÁÁÁÁÁ ÁÁÁÁÁ C in ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Effective input capacitance of any signal pin measured by incremental bus rise times ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ pF NOTES ON RESPONSE TIME The fall-time of VTX from 5 V to 2.5 V in the test is approximately 15 ns. The fall-time of VSX from 5 V to 2.5 V in the test is approximately 50 ns. The rise-time of VTX from 0 V to 2.5 V in the test is approximately 20 ns. The rise-time of VSX from 0.9 V to 2.5 V in the test is approximately 70 ns.

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See AN460 and AN255 for more application detail. Figure 1. Interfacing an ‘I2C’ type of bus with different logic levels. Figure 2. Galvanic isolation of I2C nodes via opto-couplers

12 V 12 V

Figure 3. Long distance I2C communications

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Figure 4. Extending a DCC bus practice means simply releasing it. signalling, but it may be limited by the video signalling. delay and at the receiving end after 3 times that propagation delay. cores) the one-way propagation delays will be about 5 ns/meter.

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600 ns, yields a cycle period of 2535 ns or 394 kHz. than 600 ns, but none have that guaranteed. Figure 5. Driving ribbon or flat telephone cables

Philips Semiconductors Product data P82B96Dual bi-directional bus buffer

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CALCULATING SYSTEM DELAYS AND BUS CLOCK FREQUENCY FOR A FAST MODE SYSTEM Cm = MASTER BUS CAPACITANCE Cb = BUFFERED BUS WIRING CAPACITANCE Cs = SLAVE BUS CAPACITANCE MASTER I2C I2C SLAVE P82B96 P82B96 VCCM SCL Rm Rb Rs VCCS SCL Sx Tx/Rx Tx/Rx Sx GND/0 V A) FALLING EDGE OF SCL AT MASTER IS DELAYED BY THE BUFFERS AND BUS FALL TIMES EFFECTIVE DELAY OF SCL AT SLAVE = 255 + 17 VCCM + (2.5 + 4 × 109 Cb) VCCB (ns) C = F, V = VOLTS LOCAL MASTER BUS BUFFERED EXPANSION BUS REMOTE SLAVE BUS su01787 VCCB Figure 6. Cm = MASTER BUS CAPACITANCE Cb = BUFFERED BUS WIRING CAPACITANCE MASTER I2C P82B96 VCCM SCL Rm Rb Sx Tx/Rx Tx/Rx GND/0 V B) RISING EDGE OF SCL AT MASTER IS DELAYED (CLOCK STRETCH) BY BUFFER AND BUS RISE TIMES EFFECTIVE DELAY OF SCL AT MASTER = 270 + RmCm + 0.7RbCb (ns), C = F, R = Ω LOCAL MASTER BUS BUFFERED EXPANSION BUS su01788 VCCB Figure 7.

Philips Semiconductors Product data P82B96Dual bi-directional bus buffer

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Cm = MASTER BUS CAPACITANCE Cb = BUFFERED BUS WIRING CAPACITANCE Cs = SLAVE BUS CAPACITANCE MASTER I2C I2C SLAVE P82B96 P82B96 VCCM SDA Rm Rb Rs VCCS SDA Sx Tx/Rx Tx/Rx Sx GND/0 V C) RISING EDGE OF SDA AT SLAVE IS DELAYED BY THE BUFFERS AND BUS RISE TIMES EFFECTIVE DELAY OF SDA AT MASTER = 270 + 0.2RsCs + 0.7 (RbCb + RmCm) (ns), C = F, R = Ω LOCAL MASTER BUS BUFFERED EXPANSION BUS REMOTE SLAVE BUS su01789 VCCB Figure 8. Figures 6, 7, and 8 show the P82B96 used to drive extended bus wiring, with relatively large capacitance, linking two Fast mode I2C-bus nodes. It includes simplified expressions for making the relevant timing calculations for 3.3/5 V operation. Because the buffers and the wiring introduce timing delays, it may be necessary to decrease the nominal SCL frequency below 400 kHz. In most cases the actual bus frequency will be lower than the nominal Master timing due to bit-wise stretching of the clock periods. The delay factors involved in calculation of the allowed bus speed are: A) The propagation delay of the Master signal through the buffers and wiring to the Slave. The important delay is that of the falling edge of SCL because this edge ‘requests’ the data or Acknowledge from a Slave. B) The effective stretching of the nominal LOW period of SCL at the Master caused by the buffer and bus rise times C) The propagation delay of the Slave’s response signal through the buffers and wiring back to the Master. The important delay is that of a rising edge in the SDA signal. Rising edges are always slower and are therefore delayed by a longer time than falling edges. (The rising edges are limited by the passive pull-up while falling edges are actively driven) The timing requirement in any I 2C system is that a Slave’s data response (which is provided in response to a falling edge of SCL) must be received at the Master before the end of the corresponding low period of SCL as appears on the bus wiring at the Master. Since all Slaves will, as a minimum, satisfy the worst case timing requirements of a 400 kHz part, they must provide their response within the minimum allowed clock LOW period of 1300 ns. Therefore in systems that introduce additional delays it is only necessary to extend that minimum clock low period by any “effective” delay of the Slave’s response. The effective delay of the slaves response = total delays in SCL falling edge from the Master reaching the Slave (A) – the effective delay (stretch) of the SCL rising edge (B) + total delays in the Slave’s response data, carried on SDA, reaching the Master (C). The Master microcontroller should be programmed to produce a nominal SCL LOW period = (1300 + A – B + C) ns, and should be programmed to produce the nominal minimum SCL HIGH period of 600 ns. Then a check should be made to ensure the cycle time is not shorter than the minimum 2500 ns. If found necessary, just increase either clock period. Due to clock stretching, the SCL cycle time will always be longer than (600 + 1300 + A + C) ns. Example: The Master bus has an RmCm product of 100 ns and V CCM = 5 V. The buffered bus has a capacitance of 1 nF and a pull-up resistor of 160 ohms to 5 V giving an RbCb product of 160 ns. The Slave bus also has an RsCs product of 100 ns. The microcontroller LOW period should be programmed to ≥ (1300 + 372.5 – 482 + 472) ns, that is ≥ 1662.5 ns. Its HIGH period may be programmed to the minimum 600 ns. The nominal microcontroller clock period will be ≥ (1662.5 + 600) ns = 2262.5 ns, equivalent to a frequency of 442 kHz. The actual bus clock period, including the 482 ns clock stretch effect, will be below (nominal + stretch) = (2262.5 + 482) ns or ≥ 2745 ns, equivalent to an allowable frequency of 364 kHz.

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NO LIMIT TO THE NUMBER OF CONNECTED BUS DEVICES. Figure 9. I2C multi-point applications Horiz: 200 ns/div. VertL 2 V/div. Figure 10. Propagation Sx to Tx — Sx pull-up to 5V, Horiz: 200 ns/div. VertL 2 V/div. Figure 11. Propagation Rx to Sx — Sx pull-up to 5V,

Philips Semiconductors Product data P82B96Dual bi-directional bus buffer

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SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

Philips Semiconductors Product data P82B96Dual bi-directional bus buffer

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DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1

Philips Semiconductors Product data P82B96Dual bi-directional bus buffer

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TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1

Philips Semiconductors Product data P82B96Dual bi-directional bus buffer

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REVISION HISTORY

_4 20040326 Product data (9397 750 12932). Supersedes data of 2003 Apr 02 (9397 750 11351). Modifications:

• Page 2: – Features section re-written. – Add “TSSOP” to heading for pin configurations
• Page 3, Ordering information table: correct description of TSSOP8 package.
• Page 5, (continued) Characteristics table, Note 1, – third sentence: – fourth sentence: from “In any design the SX pins of different ICs because the resulting ...” to “In any design the SX pins of different ICs should never be linked because the resulting ...”
• Figure 4: Change 2 transistors to bipolar type. Add dashed line between VCC1 and VCC , and between VCC2 and VCC to indicate optional/allowed links.
• Figure 5: Add dashed line between VCC1 and VCC , and between VCC2 and VCC to indicate optional/allowed links.
• Page 8, table “Examples of bus capability”: – cable capacitance 1 nF: change LOW period from “1600 ns” to “1500 ns” change Effective bus clock speed from “380 kHz” to “390 kHz” – change cable capacitance “120 nF” to “120 pF”
• Add title “Calculating system delays and bus clock frequency for a Fast mode system” on page 9.
• Add VCCB label to Figures 6, 7 and 8.
• Page 10, “Example:” paragraphs 3, 5 and 6: values corrected in equations.
• Add signal names to Figure 9.
• Add package outline drawing SOT505-1. _3 20030402 Product data (9397 750 11351); ECN 853-2241 29602 dated 28 February 2003. Supersedes data of 2003 Jan 22 (9397 750 11093) _2 20030226 Product data (9397 750 11093); ECN 853-2241 29410 of 22 January 2003; supersedes data of 2001 Mar 06 (9397 750 08122) _1 20010306 Product data (9397 750 08122); ECN 853-2241 25758 of 2001 Mar 06.

Philips Semiconductors Product data P82B96Dual bi-directional bus buffer

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Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to:  Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Date of release: 03-04 Document order number: 9397 750 12932 Philips Semiconductors Data sheet status[1] Objective data Preliminary data Product data Product status[2] [3] Development Qualification Production Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Level I II III