P82B715D

P82B715 TI | Alldatasheet

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Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. P82B715 SCPS145B –DECEMBER 2007–REVISED FEBRUARY 2016 P82B715I2CBusExtender

1 Features

1• Operating Power-Supply Voltage Range of

3 V to 12 V

• Supports Bidirectional Data Transfer of I2C Bus Signals
• Allows Bus Capacitance of 400 pF on Main I2C Bus (Sx/Sy Side) and 3000 pF on Transmission Side (Lx/Ly Side)
• Dual Bidirectional Unity-Voltage-Gain Buffer With No External Directional Control Required
• Drives 10× Lower-Impedance Bus Wiring for Improved Noise Immunity
• Multi-Drop Distribution of I2C Signals Using Low- Cost Twisted-Pair Cables
• I2C Bus Operation Over 50 Meters of Twisted-Pair Wire
• Latch-up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22 – 2500-V Human-Body Model (A114-A) – 400-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)

2 Applications

• HDMI DDC
• Long I2C Communications
• Industrial Communications

3 Description

The P82B715 is a device for buffering highly- capacitive I2C bus systems, and it supports bidirectional data transfer through the I2C bus. The P82B715 buffers both the serial data (SDA) and serial clock (SCL) signals on the I2C bus and allows for extension of the I2C bus, while retaining all the operating modes and features of the I2C system. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) P82B715 SOIC (8) 4.90 mm × 3.91 mm PDIP (8) 9.81 mm × 6.35 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Block Diagram

SCPS145B –DECEMBER 2007–REVISED FEBRUARY 2016 www.ti.com Product Folder Links: P82B715 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated Table of Contents

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (February 2008) to Revision B Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

NC – No internal connection 1 8NC VCC 2 7Lx Ly 3 6Sx Sy 4 5GND NC P82B715 www.ti.com SCPS145B –DECEMBER 2007–REVISED FEBRUARY 2016 Product Folder Links: P82B715 Submit Documentation FeedbackCopyright © 2007–2016, Texas Instruments Incorporated

5 Pin Configuration and Functions

NO. NAME

1 NC — No connection

2 Lx I/O Buffered serial data bus or LDA

3 Sx I/O Serial data bus or SDA. Connect to VCC of I2C master through a pullup resistor.

4 GND — Ground

5 NC — No connection

6 Sy I/O Serial clock bus or SCL. Connect to VCC of I2C master through a pullup resistor.

7 Ly I/O Buffered serial clock bus or LCL

8 VCC I Supply voltage

SCPS145B –DECEMBER 2007–REVISED FEBRUARY 2016 www.ti.com Product Folder Links: P82B715 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage –0.3 12 V Vb I2C bus voltage Sx or Sy 0 VCC V Buffered bus voltage Lx or Ly 0 VCC IO Continuous output current Sx or Sy 60 mA Lx or Ly 60 ICC Continuous current through VCC or GND 60 mA Tstg Storage temperature –55 125 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±1000 Machine model (MM) ±400 (1) Operation with reduced performance is possible down to 3 V. Typical static sinking performance is not degraded at 3 V, but the dynamic sink currents while the output is being driven through VCC/2 are reduced and can increase fall times. Timing-critical designs should accommodate the specified minimums.

6.3 Recommended Operating Conditions

VCC Supply voltage(1) 4.5 12 V TA Operating free-air temperature –40 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.4 Thermal Information

THERMAL METRIC(1) P82B715 UNITD (SOIC) P (PDIP)

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 105.3 48.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 51.1 38.1 °C/W RθJB Junction-to-board thermal resistance 46.2 26.1 °C/W ψJT Junction-to-top characterization parameter 8.5 15.4 °C/W ψJB Junction-to-board characterization parameter 45.6 26 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

www.ti.com SCPS145B –DECEMBER 2007–REVISED FEBRUARY 2016 Product Folder Links: P82B715 Submit Documentation FeedbackCopyright © 2007–2016, Texas Instruments Incorporated (1) Buffer is passive in this test. The Sx/Sy sink current flows through an internal resistor to the driver connected at the Lx/Ly I/O.

6.5 Electrical Characteristics

VCC = 5 V, TA = 25°C, voltages are specified with respect to GND (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ICC Quiescent supply current Sx = Sy = VCC 14 mAVCC = 12 V 15 Both I2C inputs low, Both buffered outputs sinking 30 mA 22 IIOS Output sink current on I2C bus Sx, Sy VCC > 3 V, VSx, VSy (low) = 0.4 V, VLx, VLy (low) on buffered bus = 0.3 V, ILx, ILy = –3 mA (1) 2.6 mA IIOL Output sink current on buffered bus Lx, Ly VLx, VLy (low) = 0.4 V, VSx, VSy (low) on I2C bus = 0.3 V 30 mA 3 V < VCC < 4.5 V, VLx, VLy (low) = 0.4 V to 1.5 V, ISx, ISy sinking on I2C bus < –4 mA 3 V < VCC < 4.5 V, VLx, VLy (low) = 1.5 V to VCC, ISx, ISy sinking on I2C bus = –7 mA II Input current from I2C bus Sx, Sy ILx, ILy sink on buffered bus = 30 mA –3.2 mA Input current from buffered bus(1) Lx, Ly VCC > 3 V, ISx, ISy sink on I2C bus = 3 mA(1) –3 Leakage current on buffered bus VCC = 3 V to 12 V, VLx, VLy = VCC, VSx, VSy = VCC 200 μA Zin/Zout Input/output impedance VSx < VLx, Buffer is active 8 10 13 (1) A conventional input-output delay is not observed in the Sx/Lx voltage waveforms, because the input and output pins are internally tied with a 30-Ω resistor so they show equal logic voltage levels to within 100 mV. When connected in an I2C system, an Sx/Sy input pin cannot rise/fall until the buffered bus load at the output pin has been driven by the internal amplifier. This test measures the bus propagation delay caused to falling or rising voltages at the Lx/Ly output (as well as the Sx/Sy input) by the amplifier’s response time. The figure given is measured with a drive current as shown in Figure 2. Because this is a dynamic bus test in which a corresponding bus driving IC has an output voltage well above 0.4 V, 6 mA is used instead of the static 3 mA. (2) The signal path Lx to Sx and Ly to Sy is passive through the internal 30-Ω resistor. There is no amplifier involved and essentially no signal propagation delay.

6.6 Switching Characteristics

VCC = 5 V, TA = 25°C, no capacitive loads, voltages are specified with respect to GND (unless otherwise specified) PARAMETER TEST CONDITIONS FROM (INPUT) TO (OUTPUT) MIN TYP MAX UNIT BUFFER DELAY TIMES trise/fall Delay time to VLx voltage crossing VCC/2 for input drive current step ISx at Sx(1) (see Figure 2) RLx pullup = 270 Ω ISx ISy VLx VLy 250 ns Buffer delay time, switching edges between VLx input and VSx output(2) RLx pullup = 4700 Ω VLx VLy VSx VSy 0 ns

6.7 Typical Characteristics

Figure 1. Typical VOL of Lx/Ly (RPU on Sx = 4.7 kΩ, TA = 25 C, VSX = 0 V)

7 Parameter Measurement Information

Figure 2. Test Circuit for Delay Times

www.ti.com SCPS145B –DECEMBER 2007–REVISED FEBRUARY 2016 Product Folder Links: P82B715 Submit Documentation FeedbackCopyright © 2007–2016, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The I2C bus capacitance limit of 400 pF restricts practical communication distances to a few meters. One of the advantages of the P82B715 is that it can isolate bus capacitance such that the total loading (devices, connectors, traces and wires) of the new bus or remote I2C nodes are not apparent to other I2C buses (or nodes). This is achieved by using one P82B715 device at each end of a long cable. The pin Lx of one P82B715 device must be connected to Lx of the second P82B715 (similarly for Ly). This allows the total system capacitance load to be around 3000 pF. The P82B715 uses unidirectional analog current amplification to increase the current sink capability of I2C chips to change the 400-pF I2C bus specification limit into a 3-nF bus wiring capacitance limit. That means longer cables or lower-cost general-purpose wiring may be used to connect two separate I2C-based systems, without worrying about the special voltage levels associated with other I2C bus buffers. Multiple P82B715s can be connected together in a star or multipoint architecture by their Lx/Ly ports, without limit, as long as the total capacitance of the system remains less than about 3000 pF (400 pF or less when referenced to any Sx/Sy connection). In that arrangement, the master and/or slave devices are attached to the Sx/Sy port of each P82B715. In normal use, the power-supply voltages at each end of the low-impedance buffered bus line should be the same. If these differ by a significant amount, noise margin is sacrificed. Two or more Sx or Sy I/Os can be interconnected and are also fully compatible with bus buffers that use voltage- level offsets (such as the TCA9517) because it duplicates and transmits the offset voltage.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Sx and Sy

The I2C pins (Sx and Sy) are designed to interface with a normal I2C bus. The maximum I2C bus supply voltage is 12 V. The Sx and Sy pins contain identical circuitry and can be used interchangeably as SCL or SDA.

8.3.2 Lx and Ly

The Lx and Ly pins are designed to interface with the high capacitance bus. This port of the device features circuitry to assist in sinking large amounts of currents required to operate a large capacitance bus at high speeds. More on this circuitry can be found in Lx/Ly Buffered Bus Circuitry.

8.3.3 Lx/Ly Buffered Bus Circuitry

On the special low-impedance or buffered-line side, the corresponding output becomes the LDA data line or LCL clock line. The P82B715 provides current amplification from its I2C bus to its low impedance or buffered bus. Whenever current is flowing out of Sx into an I2C chip driving the I2C bus low, its amplifier sinks ten times that current into Lx, to drive the buffered bus low (see Figure 3). To minimize interference and ensure stability, the current rise and fall times of the Lx drive amplifier are internally controlled. The P82B715 does not amplify signal

9 I/c180 Sx

clamped at (VCC + 0.7 V) but, otherwise, are independent of the supply voltage, VCC. Figure 3. Equivalent Circuit (One-Half of P82B715)

8.4 Device Functional Modes

The P82B715 has two modes when powered, which depend on the state of the I2C bus.

8.4.1 Idle Bus

8.4.2 Active-Low Bus

through the P82B715, which activates the internal pulldown to assist with the large capacitance.

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

swing if the applied logic levels would have exceeded the supply voltage by more than 0.7 V. In normal applications, external pullup resistors pull the connected buses up to the desired voltage high level. 3.3 V and preferably higher. Note that full performance over temperature is ensured only from 4.5 V. Specification deratings apply when its supply voltage is reduced below 4.5 V. The absolute minimum VCC is 3 V.

9.2 Typical Application

normal I2C device so that the subsystem may be included in, or added to, any I2C or related system. Figure 4. Minimum Subsystem Diagram

9.2.1 Design Requirements

Table 1 lists the design parameters for this example. Table 1. Design Parameters

2 Lx Sx

9.2.2 Detailed Design Procedure

9.2.2.1 I2C Systems

subsystem pullups acting in parallel with the existing I2C bus pullup must be considered.

9.2.2.2 Pullup Resistance Calculation

the total system (product of the net resistance and net capacitance) is set to 1 μs or less. stand-alone operation of individual I2C buses if parts of the extended system are disconnected or reconnected.

• Cdevice = Sum of any connected device capacitances
• Cwiring = Total wiring and stray capacitance on the bus section (1) The 1 μs is an approximation with a safety factor to the theoretical time constant necessary to meet the specified 1-μs bus rise-time specification in a system with variable logic thresholds, where the CMOS limits of 30% and 70% of VCC apply. The calculated value is 1.18 μs. If these capacitances cannot be measured or calculated, an approximation can be made by assuming that each device presents 10 pF of load capacitance and 10 pF of trace capacitance, and that cables range from 50 pF to 100 pF per meter.

Figure 5. Single Pullup Buffered Bus loading on the buffered bus.

www.ti.com SCPS145B –DECEMBER 2007–REVISED FEBRUARY 2016 Product Folder Links: P82B715 Submit Documentation FeedbackCopyright © 2007–2016, Texas Instruments Incorporated This equivalent capacitance is the sum of the capacitance on the buffered bus plus ten times the sum of the capacitances on all the connected I2C nodes. The calculated value should not exceed 4 nF. The single buffered bus pullup resistor is then calculated to achieve the 1-μs rise time, and it provides the pullup for the buffered bus and for all other connected I2C bus nodes included in the calculation.

9.2.2.3 Calculating Bus Drive Currents

Figure 5 shows three P82B715 devices connected to a common buffered bus. The associated bus capacitances are omitted for clarity, but assume the resistors have been selected to give R-C products of less than 1 μs so the bus rise-time requirement is satisfied. An I2C device connected at I2C 1 and holding the SDA bus low must sink the current flowing in its local pullup R1, plus, with assistance from the P82B715, the currents in R2, R3, and R4. Because the resistors R3 and R4 act to pull the bus nodes I2C 2 and I2C 3 and their corresponding Sx pins to a voltage higher than the voltage at the Lx pins, their buffer amplifiers are inactive. The SDA at Sx of I2C 2 and I2C 3 is pulled low by the low at Lx through the internal 30-Ω resistor that links Lx to Sx. So the effective current that must be sunk by the P82B715 buffer on I2C 1 at its Lx pin is the sum of the currents in R2, R3, and R4. The Sx current that must be sunk by an I2C device at I2C 1 due to the buffer gain action is 1/10 of the Lx current. So the effective pullup determining the current to be sunk by an I2C device at I2C 1 is R1 in parallel with resistors ten times the values of R2, R3, and R4. If R1 = R3 = R4 = 10 kΩ, and R2 = 1 kΩ, the effective pullup load at I2C 1 is 10 kΩ||10 kΩ||100 kΩ||100 kΩ = 4.55 kΩ. The same calculation applies for I2C 2 or I2C 3. To calculate the current sunk by the Lx pin of the buffer at I2C 1, note that the current in R1 is sunk directly by the device at I2C 1. The buffer, therefore, sinks only the currents flowing in R2, R3, and R4, so the effective pullup is R2 in parallel with R3 and R4. In this example that is 1 kΩ||10 kΩ||10 kΩ = 833 Ω. For a 5.5-V supply and 0.4-V low, the buffer is sinking 16.3 mA. The P82B715 has a static sink rating of 30 mA at Lx. The requirement is that the pullup on the buffered bus, in parallel with all other pullups that it is indirectly pulling low on Sx pins of other P82B715 devices, does not cause this 30-mA limit to be exceeded. The minimum pullup resistance in a 5-V ± 10% system is 170 Ω. The general requirement is: (VCC(max) – 0.4)/RP < 30 mA where

• Rp = Parallel combination of all pullup resistors driven by the Lx pin of the P82B715 (2) Figure 6 shows calculations for an expanded I2C bus with 3 nF of cable capacitance.

2 I C□Devices×

1 I C□Devices×

Figure 6. Typical Loading Calculations

9.2.3 Application Curve

Figure 7. Voltage On Bus (3000 pF on Lx/Ly With RPU = 330 Ω)

0603 Cap

10 Power Supply Recommendations

P82B715 can operate down to 3 V, but at reduced performance.

11 Layout

11.1 Layout Guidelines

in the form of wide polygon pours, and multiple vias. capacitor (typically 0.1 μF) to filter out high-frequency ripple.

11.2 Layout Example

Figure 8. D Package Example Layout

SCPS145B –DECEMBER 2007–REVISED FEBRUARY 2016 www.ti.com Product Folder Links: P82B715 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated

12 Device and Documentation Support

12.1 Community Resource

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.2 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) P82B715D Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 85 PG715 P82B715DR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PG715 P82B715DR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PG715 P82B715DRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PG715 P82B715P Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 P82B715P P82B715P.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 P82B715P P82B715PE4 Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 P82B715P (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 23-May-2025 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) P82B715DR SOIC D 8 2500 356.0 356.0 35.0 P82B715DR SOIC D 8 2500 353.0 353.0 32.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) P82B715P P PDIP 8 50 506 13.97 11230 4.32 P82B715P.A P PDIP 8 50 506 13.97 11230 4.32 P82B715PE4 P PDIP 8 50 506 13.97 11230 4.32 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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