P80C51SBPN

80C51 PHILIPS | Alldatasheet

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Technical content

/C0080 /C0115 /C0111/C0110/C0111 /C0115 80C51/87C51/80C31 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) Product specification Supersedes data of 1999 Apr 01 IC28 Data Handbook

2000 Jan 20

Philips Semiconductors Product specification 80C51/87C51/80C31 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

22000 Jan 20 853–0169 23001

DESCRIPTION

The Philips 8XC51/31 is a high-performance static 80C51 design fabricated with Philips high-density CMOS technology with operation from 2.7V to 5.5V. The 8XC51/31 contains a 4k × 8 ROM, a 128 × 8 RAM, 32 I/O lines, three 16-bit counter/timers, a six-source, four-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits. In addition, the device is a low power static design which offers a wide range of operating frequencies down to zero. Two software selectable modes of power reduction—idle mode and power-down mode are available. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. Since the design is static, the clock can be stopped without loss of user data and then the execution resumed from the point the clock was stopped. SELECTION TABLE For applications requiring more ROM and RAM, see the 8XC52/54/58/80C32, 8XC51FA/FB/FC/80C51FA, and 8XC51RA+/RB+/RC+/80C51RA+ data sheet. ROM/EPROM Memory Size (X by 8) RAM Size (X by 8) Programmable Timer Counter (PCA) Hardware Watch Dog Timer 80C31/8XC51 0K/4K 128 No No 80C32/8XC52/54/58 0K/8K/16K/32K 256 No No 80C51FA/8XC51FA/FB/FC 0K/8K/16K/32K 256 Yes No 80C51RA+/8XC51RA+/RB+/RC+ 0K/8K/16K/32K 512 Yes Yes 8XC51RD+ 64K 1024 Yes Yes

FEATURES

• 8051 Central Processing Unit – 4k × 8 ROM (80C51) – 128 × 8 RAM – Three 16-bit counter/timers – Boolean processor – Full static operation – Low voltage (2.7V to 5.5V@ 16MHz) operation
• Memory addressing capability – 64k ROM and 64k RAM
• Power control modes: – Clock can be stopped and resumed – Idle mode – Power-down mode
• CMOS and TTL compatible
• TWO speed ranges at VCC = 5V – 0 to 16MHz – 0 to 33MHz
• Three package styles
• Extended temperature ranges
• Dual Data Pointers
• Security bits: – ROM (2 bits) – OTP/EPROM (3 bits)
• Encryption array—64 bytes
• 4 level priority interrupt
• 6 interrupt sources
• Four 8-bit I/O ports
• Full–duplex enhanced UART – Framing error detection – Automatic address recognition
• Programmable clock out
• Asynchronous port reset
• Low EMI (inhibit ALE)
• Wake-up from Power Down by an external interrupt (8XC51)

Philips Semiconductors Product specification 80C51/87C51/80C31 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

2000 Jan 20 3

80C51/87C51 AND 80C31 ORDERING INFORMATION MEMORY SIZE 4K × 8 ROMless TEMPERATURE RANGE °C AND PACKAGE VOLTAGE RANGE FREQ. (MHz) DWG. ROM P80C51SBPN P80C31SBPN 0 to +70 Plastic Dual In line Package27 Vt o55 V 0t o1 6 SOT129 1 OTP P87C51SBPN P80C31SBPN 0 to +70, Plastic D ual In-line Package 2.7V to 5.5V 0 to 16 SOT129 -1 ROM P80C51SBAA P80C31SBAA 0 to +70 Plastic Leaded Chip Carrier 27 Vt o55 V 0t o1 6 SOT187 2 OTP P87C51SBAA P80C31SBAA 0 to +70, Plastic Leaded Chip Carrier 2.7V to 5.5V 0 to 16 SOT187 -2 ROM P80C51SBBB P80C31SBBB 0 to +70 Plastic Quad Flat Pack 27 Vt o55 V 0t o1 6 SOT307 2 OTP P87C51SBBB P80C31SBBB 0 to +70, Plastic Q uad Flat Pack 2.7V to 5.5V 0 to 16 SOT307 -2 ROM P80C51SFPN P80C31SFPN 40 to +85 Plastic Dual In line Package27 Vt o55 V 0t o1 6 SOT129 1 OTP P87C51SFPN P80C31SFPN –40 to +85, Plastic D ual In-line Package 2.7V to 5.5V 0 to 16 SOT129 -1 ROM P80C51SFA A P80C31SFA A 40 to +85 Plastic Leaded Chip Carrier 27 Vt o55 V 0t o1 6 SOT187 2 OTP P87C51SFA A P80C31SFA A –40 to +85, Plastic Leaded Chip Carrier 2.7V to 5.5V 0 to 16 SOT187 -2 ROM P80C51SFBB P80C31SFBB 40 to +85 Plastic Quad Flat Pack 27 Vt o55 V 0t o1 6 SOT307 2 OTP P87C51SFBB P80C31SFBB –40 to +85, Plastic Q uad Flat Pack 2.7V to 5.5V 0 to 16 SOT307 -2 ROM P80C51UBAA P80C31UBAA 0 to +70 Plastic Leaded Chip Carrier 5V 0t o3 3 SOT187 2 OTP P87C51UBAA P80C31UBAA 0 to +70, Plastic Leaded Chip Carrier 5V 0 to 33 SOT187 -2 ROM P80C51UBPN P80C31UBPN 0 to +70 Plastic Dual In line Package 5V 0t o3 3 SOT129 1 OTP P87C51UBPN P80C31UBPN 0 to +70, Plastic D ual In-line Package 5V 0 to 33 SOT129 -1 ROM P80C51UBBB P80C31UBBB 0 to +70 Plastic Quad Flat Pack 5V 0t o3 3 SOT307 2 OTP P87C51UBBB P80C31UBBB 0 to +70, Plastic Q uad Flat Pack 5V 0 to 33 SOT307 -2 ROM P80C51UFA A P80C31UFA A 40 to +85 Plastic Leaded Chip Carrier 5V 0t o3 3 SOT187 2 OTP P87C51UFA A P80C31UFA A –40 to +85, Plastic Leaded Chip Carrier 5V 0 to 33 SOT187 -2 ROM P80C51UFPN P80C31UFPN 40 to +85 Plastic Dual In line Package 5V 0t o3 3 SOT129 1 OTP P87C51UFPN P80C31UFPN –40 to +85, Plastic D ual In-line Package 5V 0 to 33 SOT129 -1 ROM P80C51UFBB P80C31UFBB 40 to +85 Plastic Quad Flat Pack 5V 0t o3 3 SOT307 2 OTP P87C51UFBB P80C31UFBB –40 to +85, Plastic Q uad Flat Pack 5V 0 to 33 SOT307 -2 80C51/87C51 AND 80C31 ORDERING INFORMATION DEVICE NUMBER (P87C51) OPERATING FREQUENCY, MAX (S) TEMPERATURE RANGE (B) PACKAGE (AA) P80C51 ROM S = 16 MHz B = 0/C0095 to +70/C0095C AA = PLCC P87C51 OTP U = 33 MHz F = –40/C0095C to +85/C0095C BB = PQFP P80C31 ROMless PN = PDIP

Philips Semiconductors Product specification 80C51/87C51/80C31 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

2000 Jan 20 4

DPTR’S MULTIPLE SFRs TIMERS 8 16

Philips Semiconductors Product specification 80C51/87C51/80C31 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

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40T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 RST RxD/P3.0 TxD/P3.1 INT0 /P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 P1.7 WR /P3.6 RD /P3.7 XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE EA /VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 V CC DUAL IN-LINE PACKAGE PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS SU01062 LCC 614 0 18 28 Pin Function

1 NIC*

2 P1.0/T2 3 P1.1/T2EX 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1.6 9 P1.7

10 RST

11 P3.0/RxD

12 NIC*

13 P3.1/TxD 14 P3.2/INT0 15 P3.3/INT1 Pin Function 16 P3.4/T0 17 P3.5/T1 18 P3.6/WR 19 P3.7/RD

20 XTAL2

21 XTAL1

23 NIC*

24 P2.0/A8 25 P2.1/A9 26 P2.2/A10 27 P2.3/A11 28 P2.4/A12 29 P2.5/A13 30 P2.6/A14 Pin Function 31 P2.7/A15

32 PSEN

33 ALE

34 NIC*

/VPP 36 P0.7/AD7 37 P0.6/AD6 38 P0.5/AD5 39 P0.4/AD4 40 P0.3/AD3 41 P0.2/AD2 42 P0.1/AD1 43 P0.0/AD0 44 V CC * NO INTERNAL CONNECTION PLASTIC QUAD FLAT PACK PIN FUNCTIONS SU01064 PQFP 44 34 12 22 Pin Function 1 P1.5 2 P1.6 3 P1.7

4 RST

5 P3.0/RxD

6 NIC*

7 P3.1/TxD 8 P3.2/INT0 9 P3.3/INT1 10 P3.4/T0 11 P3.5/T1 12 P3.6/WR 13 P3.7/RD

14 XTAL2

15 XTAL1

16 V SS

17 NIC*

18 P2.0/A8 19 P2.1/A9 20 P2.2/A10 21 P2.3/A11 22 P2.4/A12 23 P2.5/A13 24 P2.6/A14 25 P2.7/A15

26 PSEN

27 ALE

28 NIC*

/VPP 30 P0.7/AD7 Pin Function 31 P0.6/AD6 32 P0.5/AD5 33 P0.4/AD4 34 P0.3/AD3 35 P0.2/AD2 36 P0.1/AD1 37 P0.0/AD0 38 V CC

39 NIC*

40 P1.0/T2 41 P1.1/T2EX 42 P1.2 43 P1.3 44 P1.4 * NO INTERNAL CONNECTION

Philips Semiconductors Product specification 80C51/87C51/80C31 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

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MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION VSS 20 22 16 I Ground: 0V reference. VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0–0.7 39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification and received code bytes during EPROM programming. External pull-ups are required during program verification. 1–3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Port 1 also receives the low-order address byte during program memory verification. Alternate functions for Port 1 include: 1 2 40 I/O T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable Clock-Out). 2 3 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control. P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Some Port 2 pins receive the high order address bits during EPROM programming and verification. 13–19 7–13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: I IL). Port 3 also serves the special features of the 80C51 family, as listed below: 10 11 5 I RxD (P3.0): Serial input port 11 13 7 O TxD (P3.1): Serial output port 12 14 8 I INT0 (P3.2): External interrupt 13 15 9 I INT1 (P3.3): External interrupt 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC . ALE/PROG 30 33 27 O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG ) during EPROM programming. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When the 8XC51/31 is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA /VPP 31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 0FFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 0FFFH. This pin also receives the 12.75V programming supply voltage (V PP ) during EPROM programming. If security bit 1 is programmed, EA will be internally latched on Reset. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5V or VSS – 0.5V, respectively.

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Table 1. 8XC51/80C31 Special Function Registers # SFRs are modified from or added to the 80C51 SFRs.

1. Reset value depends on reset source.
2. LPEP – Low Power EPROM operation (OTP/EPROM only)

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oscillator, as shown in the logic symbol. the internal clock circuitry is through a divide-by-two flip-flop. the data sheet must be observed. machine cycles (24 oscillator periods), while the oscillator is running. milliseconds) plus two machine cycles. lowest power consumption the Power Down mode is suggested. the processor in the same manner as a power-on reset. disables the wakeup from power down with external interrupt. oscillator to restart and stabilize (normally less than 10ms). For the 80C31, wakeup from power down is always enabled.

• When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. ONCE  Mode The ONCE (“On-Circuit Emulation”) Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the 8XC51/31 is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.

Table 2. External Pin Status During Idle and Power-Down Modes

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A 50% duty cycle clock can be programmed to come out on P1.0.

1. to input the external clock for Timer/Counter 2, or
2. to output a 50% duty cycle clock ranging from 61Hz to 4MHz at a

TR2 (T2CON.2) also must be set to start the timer. taken as a 16-bit unsigned integer. interrupt. This is similar to when it is used as a baud-rate generator. Clock-Out frequency will be the same. (which vectors to the same location as Timer 2 overflow interrupt. counter keeps on counting T2EX pin transitions or osc/12 pulses.). or down depending on the value of the T2EX pin. generated when either TF2 or EXF2 are 1. In Figure 5 DCEN=1 which enables Timer 2 to count up or down. into the timer registers TL2 and TH2. Table 3. Timer 2 Operating Modes

1 X 1 Baud rate generator

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when either RCLK or TCLK = 1. in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. TR2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer. 1 = External event counter (falling edge triggered). Figure 1. Timer/Counter 2 (T2CON) Control Register Figure 2. Timer 2 in Capture Mode

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T2OE Timer 2 Output Enable bit. DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.

• User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.

Figure 3. Timer 2 Mode (T2MOD) Control Register Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0)

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Figure 5. Timer 2 Auto Reload Mode (DCEN = 1) Note availability of additional external interrupt. Figure 6. Timer 2 in Baud Rate Generator Mode

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Timer 1, the other by Timer 2. The timer can be configured for either “timer” or “counter” operation. In many applications, it is configured for “timer” operation (C/T2*=0). RCAP2L taken as a 16-bit unsigned integer. rollover in TH2 does not set TF2, and will not generate an interrupt. will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). can be used as an additional external interrupt, if needed. before accessing the Timer 2 or RCAP2 registers. Table 4. Timer 2 Generated Commonly Used

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Table 5. Timer 2 as a Timer Table 6. Timer 2 as a Counter

1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate

SCON.7 can only be cleared by software. Refer to Figure 8. Mode 0 is the Shift Register mode and SM2 is ignored. address which the master will use for addressing each of the slaves.

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necessary to make bit 2 = 1 to exclude slave 2. the broadcast address will be FF hexadecimal. which do not make use of this feature. frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. Given or Broadcast Address. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. other modes, in any serial transmission. Must be cleared by software. the other modes, in any serial reception (except see SM2). Must be cleared by software. Figure 7. SCON: Serial Port Control Register

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Figure 8. UART Framing Error Detection – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. Figure 9. UART Multiprocessor Communication, Automatic Address Recognition

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interrupt structure possible. The IPH is located at SFR address B7H. interrupt that was stopped will be completed. Table 7. Interrupt Table Enable Bit = 1 enables the interrupt. enabled or disabled by setting or clearing its enable bit. IE.6 — Not implemented. Reserved for future use. IE.5 ET2 Timer 2 interrupt enable bit. IE.4 ES Serial Port interrupt enable bit. IE.3 ET1 Timer 1 interrupt enable bit. IE.2 EX1 External interrupt 1 enable bit. IE.1 ET0 Timer 0 interrupt enable bit. IE.0 EX0 External interrupt 0 enable bit. Figure 10. IE Registers

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IP.7 — Not implemented, reserved for future use. IP.6 — Not implemented, reserved for future use. IP.5 PT2 Timer 2 interrupt priority bit. IP.4 PS Serial Port interrupt priority bit. IP.3 PT1 Timer 1 interrupt priority bit. IP.2 PX1 External interrupt 1 priority bit. IP.1 PT0 Timer 0 interrupt priority bit. IP.0 PX0 External interrupt 0 priority bit. Figure 11. IP Registers IPH.7 — Not implemented, reserved for future use. IPH.6 — Not implemented, reserved for future use. IPH.5 PT2H Timer 2 interrupt priority bit high. IPH.4 PSH Serial Port interrupt priority bit high. IPH.3 PT1H Timer 1 interrupt priority bit high. IPH.2 PX1H External interrupt 1 priority bit high. IPH.1 PT0H Timer 0 interrupt priority bit high. IPH.0 PX0H External interrupt 0 priority bit high. Figure 12. IPH Registers

Philips Semiconductors Product specification 80C51/87C51/80C31 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

2000 Jan 20 19

The AO bit (AUXR.0) in the AUXR register when set disables the ALE output. Reduced EMI Mode AUXR (8EH) 7 6 5432 1 0 AUXR.0 AO Turns off ALE output. Dual DPTR The dual DPTR structure (see Figure 13) enables a way to specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 that allows the program code to switch between them.

• New Register Name: AUXR1#
• SFR Address: A2H
• Reset Value: xxx000x0B AUXR1 (A2H) 76543210 – – – LPEP WUPD 0 – DPS Where: DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1. Select Reg DPS DPTR0 0 DPTR1 1 The DPS bit status should be saved by software when switching between DPTR0 and DPTR1. Note that bit 2 is not writable and is always read as a zero. This allows the DPS bit to be quickly toggled simply by executing an INC DPTR insstruction without affecting the WOPD or LPEP bits. DPS DPTR1 DPTR0 DPH (83H) DPL (82H) EXTERNAL DATA MEMORY SU00745A BIT0 AUXR1 Figure 13. DPTR Instructions The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1/bit 0 register. The six instructions that use the DPTR are as follows: INC DPTR Increments the data pointer by 1 MOV DPTR, #data16 Loads the DPTR with a 16-bit constant MOV A, @ A+DPTR Move code byte relative to DPTR to ACC MOVX A, @ DPTR Move external RAM (16-bit address) to ACC MOVX @ DPTR , A Move ACC to external RAM (16-bit address) JMP @ A + DPTR Jump indirect relative to DPTR The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See application note AN458 for more details.

Philips Semiconductors Product specification 80C51/87C51/80C31 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

2000 Jan 20 20

ABSOLUTE MAXIMUM RATINGS 1, 2, 3 PARAMETER RATING UNIT Operating temperature under bias 0 to +70 or –40 to +85 °C Storage temperature range –65 to +150 °C Voltage on EA/VPP pin to VSS 0 to +13.0 V Voltage on any other pin to VSS –0.5 to +6.5 V Maximum IOL per I/O pin 15 mA Power dissipation (based on package heat transfer limitations, not device power consumption)1.5 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C CLOCK FREQUENCY RANGE –f SYMBOL FIGURE PARAMETER MIN MAX UNIT 1/tCLCL 29 Oscillator frequency Speed versions : S (16MHz) U (33MHz) MHz MHz

Philips Semiconductors Product specification 80C51/87C51/80C31 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

2000 Jan 20 21

DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 2.7V to 5.5V, VSS = 0V (16MHz devices) SYMBOL PARAMETER TEST LIMITS UNITSYMBOL PARAMETER CONDITIONS MIN TYP 1 MAX UNIT V Input low voltage VIL Input low voltage VIH Input high voltage (ports 0, 1, 2, 3, EA) 0.2VCC +0.9 VCC +0.5 V VIH1 Input high voltage, XTAL1, RST 0.7VCC VCC +0.5 V VOL Output low voltage, ports 1, 2, 8 VCC = 2.7V IOL = 1.6mA2 0.4 V VOL1 Output low voltage, port 0, ALE, PSEN8, 7 VCC = 2.7V IOL = 3.2mA2 0.4 V VO Output high voltageports 1 2 33 VCC = 2.7V IOH = –20µA VCC – 0.7 V VOH O utput high voltage, ports 1, 2, 3 3 VCC = 4.5V IOH = –30µA VCC – 0.7 V VOH1 Output high voltage (port 0 in external bus mode), ALE 9, PSEN3 VCC = 2.7V IOH = –3.2mA VCC – 0.7 V IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4V –1 –50 µA ITL Logical 1-to-0 transition current, ports 1, 2, 36 VIN = 2.0V See note 4 –650 µA ILI Input leakage current, port 0 0.45 < VIN < VCC – 0.3 ±10 µA ICC Power supply current (see Figure 21): See note 5 Active mode @ 16MHz µA Idle mode @ 16MHz µA Power-down mode or clock stopped (see Figure 25 f diti ) Tamb = 0°C to 70°C 3 50 µA for conditions) Tamb = –40°C to +85°C 75 µA R RST Internal reset pull-down resistor 40 225 kΩ C IO Pin capacitance10 (except EA) 15 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V OL s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC –0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. See Figures 22 through 25 for ICC test conditions. Active mode: ICC = 0.9 × FREQ. + 1.1mA Idle mode: I CC = 0.18 × FREQ. +1.01mA; See Figure 21. 6. This value applies to Tamb = 0°C to +70°C. For Tamb = –40°C to +85°C, ITL = –750µA. 7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15mA (*NOTE: This is 85 °C specification.) Maximum IOL per 8-bit port: 26mA Maximum total IOL for all outputs: 71mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1 , except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA is 25pF).

Philips Semiconductors Product specification 80C51/87C51/80C31 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

2000 Jan 20 22

DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, 33MHz devices; 5V ±10%; VSS = 0V SYMBOL PARAMETER TEST LIMITS UNITSYMBOL PARAMETER CONDITIONS MIN TYP 1 MAX UNIT VIH Input high voltage (ports 0, 1, 2, 3, EA) 0.2VCC +0.9 VCC +0.5 V VIH1 Input high voltage, XTAL1, RST 0.7VCC VCC +0.5 V VOL Output low voltage, ports 1, 2, 3 8 VCC = 4.5V IOL = 1.6mA2 0.4 V VOL1 Output low voltage, port 0, ALE, PSEN7, 8 VCC = 4.5V IOL = 3.2mA2 0.4 V VOH Output high voltage, ports 1, 2, 33 VCC = 4.5V IOH = –30µA VCC – 0.7 V VOH1 Output high voltage (port 0 in external bus mode), ALE 9, PSEN3 VCC = 4.5V IOH = –3.2mA VCC – 0.7 V IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4V –1 –50 µA ITL Logical 1-to-0 transition current, ports 1, 2, 36 VIN = 2.0V See note 4 –650 µA ILI Input leakage current, port 0 0.45 < VIN < VCC – 0.3 ±10 µA ICC Power supply current (see Figure 21): See note 5 Active mode (see Note 5) Idle mode (see Note 5) Power-down mode or clock stopped (see Figure 25 f diti ) Tamb = 0°C to 70°C 3 50 µA for conditions) Tamb = –40°C to +85°C 75 µA R RST Internal reset pull-down resistor 40 225 kΩ C IO Pin capacitance10 (except EA) 15 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V OL s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC –0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. See Figures 22 through 25 for ICC test conditions. Active mode: ICC(MAX) = 0.9 × FREQ. + 1.1mA Idle mode: I CC(MAX) = 0.18 × FREQ. +1.0mA; See Figure 21. 6. This value applies to Tamb = 0°C to +70°C. For Tamb = –40°C to +85°C, ITL = –750µA. 7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15mA (*NOTE: This is 85 °C specification.) Maximum IOL per 8-bit port: 26mA Maximum total IOL for all outputs: 71mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1 , except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA is 25pF).

Philips Semiconductors Product specification 80C51/87C51/80C31 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

2000 Jan 20 23

AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = +2.7V to +5.5V, VSS = 0V1, 2, 3 16MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 14 Oscillator frequency5 Speed versions :S 3.5 16 MHz tLHLL 14 ALE pulse width 85 2tCLCL –40 ns tAVLL 14 Address valid to ALE low 22 tCLCL –40 ns tLLAX 14 Address hold after ALE low 32 tCLCL –30 ns tLLIV 14 ALE low to valid instruction in 150 4tCLCL –100 ns tLLPL 14 ALE low to PSEN low 32 tCLCL –30 ns tPLPH 14 PSEN pulse width 142 3tCLCL –45 ns tPLIV 14 PSEN low to valid instruction in 82 3tCLCL –105 ns tPXIX 14 Input instruction hold after PSEN 0 0 ns tPXIZ 14 Input instruction float after PSEN 37 tCLCL –25 ns tAVIV 4 14 Address to valid instruction in 207 5tCLCL –105 ns tPLAZ 14 PSEN low to address float 10 10 ns Data Memory tRLRH 15, 16 RD pulse width 275 6tCLCL –100 ns tWLWH 15, 16 WR pulse width 275 6tCLCL –100 ns tRLDV 15, 16 RD low to valid data in 147 5tCLCL –165 ns tRHDX 15, 16 Data hold after RD 0 0 ns tRHDZ 15, 16 Data float after RD 65 2tCLCL –60 ns tLLDV 15, 16 ALE low to valid data in 350 8tCLCL –150 ns tAVDV 15, 16 Address to valid data in 397 9tCLCL –165 ns tLLWL 15, 16 ALE low to RD or WR low 137 239 3tCLCL –50 3tCLCL +50 ns tAVWL 15, 16 Address valid to WR low or RD low 122 4tCLCL –130 ns tQVWX 15, 16 Data valid to WR transition 13 tCLCL –50 ns tWHQX 15, 16 Data hold after WR 13 tCLCL –50 ns tQVWH 16 Data valid to WR high 287 7tCLCL –150 ns tRLAZ 15, 16 RD low to address float 0 0 ns tWHLH 15, 16 RD or WR high to ALE high 23 103 tCLCL –40 tCLCL +40 ns External Clock tCHCX 18 High time 20 20 tCLCL –tCLCX ns tCLCX 18 Low time 20 20 tCLCL –tCHCX ns tCLCH 18 Rise time 20 20 ns tCHCL 18 Fall time 20 20 ns Shift Register tXLXL 17 Serial port clock cycle time 750 12tCLCL ns tQVXH 17 Output data setup to clock rising edge 492 10tCLCL –133 ns tXHQX 17 Output data hold after clock rising edge 8 2tCLCL –117 ns tXHDX 17 Input data hold after clock rising edge 0 0 ns tXHDV 17 Clock rising edge to input data valid 492 10tCLCL –133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 8XC51 and 80C31 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. See application note AN457 for external memory interface. 5. Parts are guaranteed to operate down to 0Hz.

Philips Semiconductors Product specification 80C51/87C51/80C31 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

2000 Jan 20 24

AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3 VARIABLE CLOCK 4 16MHz to fmax 33/C0077Hz CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT tLHLL 14 ALE pulse width 2tCLCL –40 21 ns tAVLL 14 Address valid to ALE low tCLCL –25 5 ns tLLAX 14 Address hold after ALE low tCLCL –25 ns tLLIV 14 ALE low to valid instruction in 4tCLCL –65 55 ns tLLPL 14 ALE low to PSEN low tCLCL –25 5 ns tPLPH 14 PSEN pulse width 3tCLCL –45 45 ns tPLIV 14 PSEN low to valid instruction in 3tCLCL –60 30 ns tPXIX 14 Input instruction hold after PSEN 0 0 ns tPXIZ 14 Input instruction float after PSEN tCLCL –25 5 ns tAVIV 14 Address to valid instruction in 5tCLCL –80 70 ns tPLAZ 14 PSEN low to address float 10 10 ns Data Memory tRLRH 15, 16 RD pulse width 6tCLCL –100 82 ns tWLWH 15, 16 WR pulse width 6tCLCL –100 82 ns tRLDV 15, 16 RD low to valid data in 5tCLCL –90 60 ns tRHDX 15, 16 Data hold after RD 0 0 ns tRHDZ 15, 16 Data float after RD 2tCLCL –28 32 ns tLLDV 15, 16 ALE low to valid data in 8tCLCL –150 90 ns tAVDV 15, 16 Address to valid data in 9tCLCL –165 105 ns tLLWL 15, 16 ALE low to RD or WR low 3tCLCL –50 3tCLCL +50 40 140 ns tAVWL 15, 16 Address valid to WR low or RD low 4tCLCL –75 45 ns tQVWX 15, 16 Data valid to WR transition tCLCL –30 0 ns tWHQX 15, 16 Data hold after WR tCLCL –25 5 ns tQVWH 16 Data valid to WR high 7tCLCL –130 80 ns tRLAZ 15, 16 RD low to address float 0 0 ns tWHLH 15, 16 RD or WR high to ALE high tCLCL –25 tCLCL +25 5 55 ns External Clock tCHCX 18 High time 0.38tCLCL tCLCL –tCLCX ns tCLCX 18 Low time 0.38tCLCL tCLCL –tCHCX ns tCLCH 18 Rise time 5 ns tCHCL 18 Fall time 5 ns Shift Register tXLXL 17 Serial port clock cycle time 12tCLCL 360 ns tQVXH 17 Output data setup to clock rising edge 10tCLCL –133 167 ns tXHQX 17 Output data hold after clock rising edge2tCLCL –80 ns tXHDX 17 Input data hold after clock rising edge 0 0 ns tXHDV 17 Clock rising edge to input data valid 10tCLCL –133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 8XC51 and 80C31 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz “AC Electrical Characteristics”, page 23. 5. Parts are guaranteed to operate down to 0Hz.

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AVLL = Time for address valid to ALE low. tLLPL =Time for ALE low to PSEN low. Figure 14. External Program Memory Read Cycle Figure 15. External Data Memory Read Cycle

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Figure 16. External Data Memory Write Cycle Figure 17. Shift Register Mode Timing Figure 18. External Clock Drive

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AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Figure 19. AC Testing Input/Output OH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 20. Float Waveform Figure 21. ICC vs. FREQ

2000 Jan 20 28

Figure 22. ICC Test Condition, Active Mode Figure 23. ICC Test Condition, Idle Mode Figure 24. Clock Signal Waveform for ICC Tests in Active and Idle Modes Figure 25. ICC Test Condition, Power Down Mode

2000 Jan 20 29

width and number of the ALE/PROG pulses. circuit configuration for normal program memory verification. Figure 26. Note that the device is running with a 4 to 6MHz device is executing internal address and program data transfers. low 5 times as shown in Figure 27. programmed, verification cycles will produce only encrypted data. required on port 0 for this operation. data. The encryption table itself cannot be read out. which satisfies the timing specifications, is suitable. light with wavelengths shorter than approximately 4,000 angstroms. Erasure leaves the array in an all 1s state. programmed, in addition to the above, verify mode is disabled. above apply and all external program memory execution is disabled. 64 bytes of encryption array are initially unprogrammed (all 1s).  Trademark phrase of Intel Corporation.

2000 Jan 20 30

Table 8. EPROM Programming Modes

1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. VCC = 5V±10% during programming and verification.

12.75V. Each programming pulse is low for 100µs (±10µs) and high for a minimum of 10µs. Table 9. Program Security Bits for EPROM Devices

2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes

3 P P U Same as 2, also verify is disabled. 4 P P P Same as 3, external execution is disabled. Internal data RAM is not accessible.

1. P – programmed. U – unprogrammed.
2. Any other combination of the security bits is not defined.

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5 PULSES TO GROUND

Figure 26. Programming Configuration

5 PULSES

Figure 27. PROG Waveform

0 ENABLE

Figure 28. Program Verification

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• FOR PROGRAMMING CONFIGURATION SEE FIGURE 26.

FOR VERIFICATION CONDITIONS SEE FIGURE 28. Figure 29. EPROM Programming and Verification

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are programmed, in addition to the above, verify mode is disabled. 64 bytes of encryption array are initially unprogrammed (all 1s). Table 10. Program Security Bits 1 U U No Program Security features enabled. is sampled and latched on Reset, and further programming of the EPROM is disabled.

1. P – programmed. U – unprogrammed.
2. Any other combination of the security bits is not defined.
3. 64 byte ROM encryption key
4. External MOVC is disabled, and

Security Bit 2:When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. Encryption: /C0086No /C0086Yes If Yes, must send key file.

Philips Semiconductors Product specification 80C51/87C51/80C31 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

2000 Jan 20 34

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

Philips Semiconductors Product specification 80C51/87C51/80C31 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

2000 Jan 20 35

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

Philips Semiconductors Product specification 80C51/87C51/80C31 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

2000 Jan 20 36

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2

Philips Semiconductors Product specification 80C51/87C51/80C31 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

2000 Jan 20 37

Philips Semiconductors Product specification 80C51/87C51/80C31 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

2000 Jan 20 38

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 01-00 Document order number: 9397 750 06795 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.