P80C51HFPN

80CL31 PHILIPS | Alldatasheet

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/C0109 /C0110 /C0114 80CL31/80CL51 Low-voltage single-chip 8-bit microcontrollers Product specification 1995 January INTEGRATED CIRCUITS IC20 Data Handbook

Philips Semiconductors Product specification 80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers 2January 1995

FEATURES

• Full static 80C51 CPU
• 8-bit CPU, ROM, RAM, 1/0 in a single 40-lead DIL / mini-pack
• 4K x 8 ROM, expandable externally to 64K bytes
• 128 bytes RAM, expandable externally to 64K bytes
• Four 8-bit ports, 321/0 lines
• Two 16-bit timer / event counters
• External memory expandable up to 128K, external ROM up to 64K and / or RAM up to 64K
• On-chip oscillator suitable for RC, LC, quartz crystal or ceramic resonator
• Thirteen source, thirteen vector interrupt structure with two priority levels
• Full duplex serial port (UART)
• Enhanced architecture with: – non-page oriented instructions – direct addressing – four eight byte RAM register banks – stack depth up to 128 bytes – multiply, divide, subtract and compare instructions
• Power-Down and IDLE instructions
• Wake-up via external interrupts at Port 1
• Single supply voltage of 1.8V to 6.0V (5.0V ±10% for P80C51)
• Frequency range of 0 to 16MHz (3.5MHz to 16MHz for P80C51)
• Very low current consumption
• Operating temperature range: -40 to +85oC

DESCRIPTION

The 80CL51 is manufactured in an advanced CMOS technology. The instruction set of the 80CL51 is based on that of the 8051. The 80CL51 is a general purpose microcontroller especially suited for battery-powered applications. The device has low power consumption and a wide range of supply voltage. For emulation purposes, the 85CL000 (Piggy-back version) with 256 bytes of RAM is recommended. The 80CL51 has two software selectable modes of reduced activity for further power reduction: Idle and Power-down. The 80CL51 also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 46 two-byte, and 16 three-byte. The P80CL31 is the ROMless version of the P80CL51. P80C51 is a 5V version of the low voltage P80CL51. The P80CL31 is the ROMless version of the P80CL51. P80C51 is a 5V version of the low voltage P80CL51. PIN CONFIGURATIONS PLASTIC QUAD FLAT PACKAGE P3.6/WR P3.7/RD XTAL2 XTAL1 V P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 NC SS P1.4/INT6 P1.3/INT5 P1.2/INT4 P1.1/INT3 P1.0/INT2 NC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 VDD 39 38 37 36 35 34 2221 4041424344 12 13 14 15 16 17 18 19 20 P1.5/INT7 P1.6/INT8 P1.7/INT9 RST P3.0/RXD NC P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13 NC 20 21 40INT2 /P1.0 RST RXD/DATA/P3.0 TXD/CLOCK/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR /P3.6 RD /P3.7 XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 V DD PLASTIC DUAL IN-LINE AND SMALL OUTLINE PACKAGES INT3/P1.1 INT4/P1.2 INT5/P1.3 INT6/P1.4 INT7/P1.5 INT8/P1.6 INT9/P1.7

Philips Semiconductors Product specification 80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers January 1995 3

ORDERING INFORMATION

PART ORDER NUMBER TEMPERATURE RANGE oC AND PACKAGE DRAWING NUMBER ROMless ROM ROMless ROM AND PACKAGE NUMBER P80CL31HFP P80CL51HFP P80CL31HFP N P80CL51HFP N –40 to +85; 40-lead Plastic Dual In-line Package (1.8V to 6V)SOT129-1 P80CL31HFT P80CL51HFT P80CL31HFT D P80CL51HFT D –40 to +85; 40-lead Plastic Small Outline Package (1.8V to 6V)SOT158-1 P80CL31HFH P80CL51HFH P80CL31HFH B P80CL51HFH B –40 to +85; 44-lead Plastic Quad Flat Package (1.8V to 6V)SOT307-2 P80C51HFP P80C51HFP N –40 to +85; 40-lead Plastic Dual In-line Package (5.0V ±10%) SOT129-1 P80C51HFT P80C51HFT D –40 to +85; 40-lead Plastic Small Outline Package (5.0V ±10%) SOT158-1 P80C51HFH P80C51HFH B –40 to +85; 44-lead Plastic Quad Flat Package (5.0V ±10%) SOT307-2 NOTE: 1. Parts ordered by the Philips North America part number will be marked with the Philips part marking.

Philips Semiconductors Product specification 80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers January 1995 4 PIN DESCRIPTIONS PIN DESIGNATION FUNCTION QFP DIP DESIGNATION FUNCTION 40 1 P1.O/INT2 Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that have 1s written to them are pulled HIGH by the internal pullups and in that state can be used as inputs The Port 141 2 P1.1/lNT3 to them are pulled HIGH by the internal pullups, and in that state can be used as inputs. The Port 1 output buffer can sink/source 4 LS TTL loads As inputs Port 1 pins that are externally pulled LOW42 3 P1.2/lNT4 output buffer can sink/source 4 LS TTL loads. As inputs, Port 1 pins that are externally pulled LOW will source current (IlLin the characteristics) due to the internal pullups Port 1 also serves the43 4 P1.3/INT5 w ill source current (IlL in the characteristics) due to the internal pullups. Port 1 also serves the alternative functions INT2 to INT944 5 P1.4/lNT6 alternative functions INT2 to INT9. 1 6 P1.5/lNT7 2 7 P1.6/lNT8 3 8 P1.7/lNT9 4 9 RST Reset: A high level on this pin for two machine cycles while the oscillator is running resets the device. 5–13 10-17 Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source 4 LS TTL inputs. Port 3 pins that have 1s written to them are pulled HIGH by the internal pull ups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally pulled LOW will source current (IlL in the characteristics) due to the internal pull ups. 5 10 P3.0/RXD/data RXD/data: Serial port receiver data input (asynchronous)or data input/output (synchronous) 7 11 P3.1/TXD/clock TXD/clock: Serial port transmitter data output (asynchronous) or clock output (synchronous) 8 12 P3.2/lNT0 INT0: External interrupt 0. 9 13 P3.3/lNT1 INT1: External interrupt 1. 10 14 P3.4/T0 T0: Timer 0 external input. 11 15 P3.5/T1 T1: Timer 1 external input. 12 16 P3.6/WR WR : External data memory write strobe. 13 17 P3.7/RD RD : External data memory read strobe. 14 18 XTAL2 Crystal output: Output of the inverting amplifier of the oscillator. Left open when external clock is used. Crystal input: Input to the inverting amplifier of the oscillator; also the input for an externally gen- erated clock source. 15 19 XTAL1 Crystal input: Input to the inverting amplifier of the oscillator; also the input for an externally generated clock source. 16 20 Vss Ground: Circuit ground potential. 18-25 21-28 P2.0-P2.7 Port 2: Port 2 is an 8-bit bidirectional 1/0 port with internal pullups. Port 2 pins that have 1s written to them are pulled HIGH by the internal pullups, and in that state can be used as inputs. The Port 2 output buffer can sink/source 4 LS TTL loads. Port 2 emits the high-order address byte during accesses to external memory that use 1 6-bit ad- dresses (MOVX @DPTR). In this application it uses the strong internal pullups when emitting 1s. During accesses to external memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the con- tents of the P2 Special Function Register. 26 29 PSEN Program store enable output: Read strobe to external program memory. When executing code out of external program memory, PSEN is activated twice each machine cycle. However, during each access to external data memory two PSEN activations are skipped. 27 30 ALE Address Latch Enable: Output pulse for latching the low byte of the address during access to external memory. ALE is emitted at a constant rate of 1/6 of the oscillator frequency, and may be used for external timing or clocking purposes. 29 31 EA External Access: When EA is held High the CPU executes out of internal program memory (un- less the program counter exceeds 0FFFH). Holding EA LOW forces the CPU to execute out of external memory regardless of the value of the program counter. 30-37 32-39 P0.0-P00.7 Port 0: Port 0 is an 8-bit open drain bidirectional I/O port. As an open drain output port it can sink 8 LS TTL loads. Port 0 pins that have 1s written to them float, and in that state will function as high impedance inputs. Port 0 is also the multiplexed low order address and data bus during access to external memory. In this application it uses strong internal pull-ups when emitting logic 1s. 38 40 VDD Power supply.

Philips Semiconductors Product specification 80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers January 1995 5 BLOCK DIAGRAM PROGRAMMABLE I/O TWO 16-BIT TIMER/ EVENT COUNTERS DATA MEMORY (128 BY 8 RAM) PROGRAM MEMORY (4K BY 8 ROM) 64K BYTE BUS EXPANSION CONTROL OSCILLATOR AND TIMING CPU PROGRAMMABLE SERIAL PORT, FULL DUPLEX UART, SYNCHRONOUS SHIFT RXD TXD (1) PARALLEL PORTS ADDRESS/DATA BUS I/O PINS CONTROL 10 3 INTERNAL INTERRUPTS XTAL2 XTAL1 FREQUENNCY REFERENCE T0 T1 COUNTER 1 80CL51 EXTERNAL ENTERRUPTS 1 1. Pins shared with parallels ports pins. FUNCTIONAL DIAGRAM PORT 0 PORT 1 PORT 2PORT 3 ADDRESS AND DATA BUS ADDRESS BUS RxD/data TxD/clock INT0 INT1 WR RD ALTERNATIVE EA PSEN ALE VSS VDD RST INT2/INT9 XTAL1 XTAL2 FUNCTIONS

Philips Semiconductors Product specification 80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers January 1995 6

1.0 FUNCTIONAL DESCRIPTION

The 80CL51 is a stand-alone high-performance CMOS microcontroller designed for use in real-time applications such as instrumentation, industrial control, intelligent computer peripherals and consumer products. The device provides hardware features, architectural enhancements and new instructions to function as a controller for applications requiring up to 64K bytes of program memory and/or up to 64K bytes of data storage. The 80CL51 contains a non-volatile 4K byte × 8 read-only program memory; a static 128 byte × 8 read/write data memory; 32 1/0 lines; two 16-bit timer/event counters; a thirteen- source two priority-level, nested interrupt structure and on-chip oscillator and timing circuit. The device has two software selectable modes of reduced activity for power reduction: IDLE and Power-down. The Idle mode freezes the CPU while allowing the RAM, timers, serial I/O and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator causing all other chip functions to be inoperative. The P80C51 is a 5V version of the low voltage microcontroller P80CL51. Hereafter the generic term P80CL51 will be used for the functional description of both types. The special features of the P80C51 are handled in chapter 1.9. CPU timing A machine cycle consists of a sequence of 6 states. Each state time lasts for two oscillator periods, thus a machine cycle takes 12 oscillator periods or 1µs if the oscillator frequency is 12MHz.

1.1 Memory organization

The 80CL51 has a 4K Program Memory (ROM) plus 128 bytes of Data Memory (RAM) on board. The device has separate address spaces for Program and Data Memory (see Memory Map). Using Ports P0 and P2, the 80CL51 can address up to 64K bytes of external memory. The CPU generates both read and write signals (RD and WR) for external Data Memory accesses, and the read strobe (PSEN) for external Program Memory.

1.1.1 Program Memory

The 80CL51 contains 4K bytes of internal ROM. After reset the CPU begins execution at location 0000H. The lower 4K bytes of Program Memory can be implemented in either on- chip ROM or external Memory. If the EA pin is strapped to V DD , then program memory fetches from addresses 000H through 0FFFH are directed to the internal ROM. Fetches from addresses 1000H through FFFFH are directed to external ROM. Program counter values greater than 0FFFH are automatically addressed to external memory regardless of the state of the EA pin.

1.1.2 Data Memory

The 80CL51 contains 128 bytes of internal RAM and 25 Special Function Registers (SFR). The Memory Map below shows the internal Data Memory space divided into the Lower 128, the Upper 128, and the SFR space. The lower 128 bytes of the internal RAM are organized as mapped in Figure 1. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions refer to these registers R0 through R7. Two bits in the Program Status Word select which register bank is in use. The next 16 bytes above the register banks form a block of bit-addressable memory space. The 128 bits in this area can be directly addressed by the single-bit manipulation instructions. The remaining registers (30H to 7FH) are directly and indirectly byte addressable.

1.1.3 Special Function Registers

The upper 128 bytes are the address locations of the SFRs. Figure 2 shows the Special Function Register (SFR) space. SFRs include the port latches, timers, peripheral control, serial I/O registers, etc. These registers can only be accessed by direct addressing. There are 128 addressable locations in the SFR address space (SFRs with addresses divisible by eight).

1.1.4 Addressing

The 80CL51 has five methods for addressing source operands: – Register – Direct – Register-lndirect – Immediate – Base-Register-plus Index-Register-indirect MEMORY MAP SPECIAL FUNCTION REGISTERS 64K EXTERNAL 4096 4095 4095 INTERNAL (EA = 0) INTERNAL (EA = 1) 225 127 INTERNAL DATA RAM OVERLAPPED SPACE 64K EXTERNAL DATA RAM INTERNAL DATA MEMORYPROGRAM MEMORY

4 BANKS OF 8 REGISTERS

Figure 1. The Lower 128 Bytes of Internal RAM – Internal RAM (128 bytes) through direct or register-indirect. – Special Function Register through Direct.

1.2 I/O Facilities

1.2.1 Ports

Port 1: provides the inputs for the external interrupts INT2/lNT9. device with external program or data memory. only 2 oscillator periods after a 0-to-1 transition in the port latch. pin can be used as a high-impedance input.

1.2.2 Port Options

an external pull up resistor (see Figure 3(c)). Option 3: Push-Pull; output with drive capability in both polarities.

Figure 2. Special Function Registers

2 OSCILLATOR PERIODS

Figure 3. Ports memory (strong pull up is used). will be on for 2 oscillator periods. No weak pull up exists. an external pull up resistor (see Figure 3(c)). Option 3: Push-Pull; output with drive capability in both polarities. Under this option, pins can only be used as outputs. RESET or 2R for an open-drain I/O to be reset after RESET).

1.3 Timer/event counter

count rate is 1/12 of the oscillator frequency. it should be held for at least one full machine cycle.

1.4 Idle and Power-down operation

blocks to continue functioning while the clock to the CPU is halted.

1.4.1 Power control register

Special Function Register PCON. Its hardware address is 87H. PCON is byte addressable only. Double baud-rate bit, see description of the UART, chapter 1.5. Figure 4. Idle and Power-down Hardware

1.4.2 Power-down mode

stopped. The contents of the on-chip RAM and SFRs are preserved. held active until the oscillator has restarted and stabilized.

1.4.2.1 Wake-up using INT2 to INT9

1.4.2.2 Wake-up using RESET

1.4.3 Idle mode

Idle mode activation. ALE and PSEN hold at the logic HIGH level. the service routine can examine the status of the flag bits. complete the reset operation. Reset redefines all SFRs, but does not affect the on-chip RAM. transistor p1 (see Figure 3(a)). Table 1. Status of the External Pins During Idle and Power-down Mode Figure 5. Wake-up Operation

1536 PERIODS

Philips Semiconductors Product specification 80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers January 1995 12

1.5 Standard serial interface SI0: UART

This serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (However, if the first byte still hasn’t been read by the time reception of the second byte is complete, one of the bytes will be lost). The serial port receive and transmit registers are both accessed at Special Function Register S0BUF. Writing to S0BUF loads the transmit register, and reading S0BUF loads the transmit register, and reading S0BUF accesses a physically separate receive register. The serial port can operate in 4 modes: Mode 0: Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/ received (LSB first). The baud is fixed at 1/12 the oscillator frequency. Mode 1: 10 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SCON. The baud rate is variable. Mode 2: 11 bits are transmitted (through TxD) or received (through RxD): start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On Transmit, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. Mode 3: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable. In all four modes, transmission is initiated by any instruction that uses S0BUF as a destination register. Reception is initiated in Mode 0 by the condition Rl = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1.

1.5.1 Multiprocessor communications

Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that weren’t being addressed leave their SM2s set and go on about their business, ignoring the coming data bytes. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.

1.5.2 Serial port control register

The serial port control and status register is the Special Function Register S0CON, shown in Figure 6. The register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (T1 and R1). See next page. Baud Rates The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = Oscillator Frequency /12. The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Register PCON. If SMOD = 0 (which is the value on reset), the baud rate is 1/64 the oscillator frequency. If SMOD = 1, the baud rate is 1/32 the oscillator frequency. Mode 2 Baud Rate = (2 SMOD /64)(Oscillator Frequency) The baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate. Using Timer 1 to generate baud rates When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: (2SMOD /32)(Timer 1 Overflow Rate) The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either “timer” or “counter” operation, and in any of its 3 running modes. In the most typical applications, it is configured for “timer operation, in the auto-reload mode (high nibble of TMOD = 0010B). In that case the baud rate is given by the formula: Mode 1, 3 Baud Rate = {(2SMOD /32) (Oscillator Frequency)} / {12 (256 - (TH 1 )} One can achieve very low baud rates with Timer 1 by leaving the Timer 1 interrupt enabled, and configuring this Timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt to do a 16-bit software reload. Table 2 lists various commonly used baud rates and how they can be obtained from Timer 1. More about Mode 0 Figure 7 shows a simplified functional diagram of the serial port in Mode 0, and associated timing. Transmission is initiated by any instruction that uses S0BUF as a destination register. The “write to S0BUF” signal at S6P2 also loads a 1 into the 9th position of the transmit shift register and tells the TX Control block to commence a transmission. The internal timing is such that the one full machine cycle will elapse between “write to S0BUF”, and activation of SEND. SEND enables the output of the shift register to the alternate output function line of P3.0 and also enables SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK is low during S3, S4, and S5 of every machine cycle, and high during S6, S1 and S2. At S6P2 of every machine cycle in which SEND is active, the contents of the transmit shift are shifted to the right one position. As data bits shift out to the right, zeros come in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control block to do one last shift and then deactivate SEND and set T1. Both of these actions occur at S1P1 of the 10th machine cycle after “write to S0BUF”. Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2 of the next machine cycle, the RX Control unit writes the bits 11111110 to the receive shift register, and in the next clock phase activates RECEIVE.

was not received. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 Is the 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. other modes, in any serial transmission. Must be cleared by software. the other modes, in any serial reception except (see SM2). Must be cleared by software. Figure 6. Serial Port control (SCON) Register Table 2. Timer 1 Generated Commonly Used Baud Rates

Philips Semiconductors Product specification 80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers January 1995 14 RECEIVE enables SHIFT CLOCK to the alternate output function line of P3.1. SHIFT Clock makes transitions at S3P1 and S6P1 of every machine cycle. at S6P2 of every machine cycle in which RECEIVE is active, the contents of the receive shift register are shifted to the left one position. The value that comes in from the right is the value that was sampled at the P3.0 pin at S5P2 of the same machine cycle. As data bits come in from the right, 1s shift out to the left. When the 0 that was initially loaded into the right-most position arrives at the left-most position in the shift register, it flags the RX Control block to do one last shift and load S0BUF. At S1P1 of the 10th machine cycle after the write to SCON that cleared Rl, RECEIVE is cleared as Rl is set. More about Mode 1 Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1 ). On receive, the stop bit goes into RB8 in SCON. In the 8051 the baud rate is determined by the Timer 1 overflow rate. Figure 8 shows a simplified functional diagram of the serial port in Mode 1, and associated timings for transmit/receive. Transmission is initiated by any instruction that uses S0BUF as a destination register. The “write to S0BUF” signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to S0BUF” signal). The transmission begins with activation of SEND which sends the start bit to pin TxD. One bit time later, DATA is activated, enabling the transmission of the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set Tl. This occurs at the 10th divide-by-16 rollover after “write to S0BUF”. Reception is initiated by a detected 1 -to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16th. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the left-most position in the shift register, (which in mode 1 is a 9-bit register), it flags the RX Control block to do one last shift, loads S0BUF and RB8, and set Rl. The signal to load S0BUF and RB8, and to set Rl, will generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1. R1 = 0, and 2. Either SM2 = 0, or the received stop bit = 1 If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into S0BUF, and Rl is activated. At this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in RxD. More about modes 2 and 3 Eleven bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of 0 or 1. On receive, the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1. Figures 9 and 10 show a functional diagram of the serial port in Modes 2 and 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register. Transmission is initiated by any instruction that uses S0BUF as a destination register. The “write to S0BUF” signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter (thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to S0BUF” signal). The transmission begins with activation of SEND, which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. Then TB8 is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that contains zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set Tl. This occurs at the 11th divide-by-16 rollover after “write to S0BUF”. Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFFH is written to the input shift register. At the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the left-most position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift, load S0BUF and RB8, and set Rl.

Figure 7. Serial Port Mode 0

Figure 8. Serial Port Mode 1

Figure 9. Serial Port Mode 2

Figure 10. Serial Port Mode 3

1. Either SM2 = 0 or the received 9th data bit = 1

1.6 Interrupt System

(IP0, IP1). All enabled sources can be globally disabled or enabled.

1.6.1 External Interrupts INT2/INT9

register, each pin may be initialized to either active HIGH or LOW. Figure 11. Interrupt System

Figure 12. External Interrupt Configuration

1.6.2 Interrupt Vectors

Each interrupt priority source can be set to either high or low priority. branch to the high priority vector. interrupt. A high priority interrupt routine cannot be interrupted.

1.6.3 Related registers

1.7 Oscillator registers

to the internal clocking circuitry is split sing a flip-flop.

1.7.1 Oscillator options (see Figure 14)

performance. Please state option when ordering. resistor is needed for use in parallel with the crystal. operations using LC components. Osc. 3: An option for medium frequency range applications. Osc. 4: An option for high frequency range applications. RC: Figure 14(g): An option for an RC oscillator. Figure 13. Oscillator

Figure 14. Alternative Oscillator Configurations

Philips Semiconductors Product specification 80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers January 1995 23 OSCILLATOR TYPE SELECTION GUIDE C1 EXT. (pF) C2 EXT. (pF) MAX. RESONATOR RESONATOR f(MHz) OPTION MIN. MAX. MIN. MAX. SERIES RESISTANCE Quartz 0.032 OSC. 1 0 0 5 15 15 kΩ 1 Quartz 1.0 OSC. 2 0 30 0 30 600 Ω Quartz 3.58 OSC. 2 0 15 0 15 100 Ω Quartz 4.0 OSC. 2 0 20 0 20 75 Ω Quartz 6.0 OSC. 3 0 10 0 10 60 Ω Quartz 10.0 OSC. 4 0 15 0 15 60 Ω Quartz 12.0 OSC. 4 0 10 0 10 40 Ω Quartz 16.0 OSC. 4 0 15 0 15 20 Ω PXE 0.455 OSC. 2 40 50 40 50 10 Ω PXE 1.0 OSC. 2 15 50 15 50 100 Ω PXE 3.58 OSC. 2 0 40 0 40 10 Ω PXE 4.0 OSC. 2 0 40 0 40 10 Ω PXE 6.0 OSC. 2 0 20 0 20 5 Ω PXE 10.0 OSC. 3 0 15 0 15 6 Ω PXE 12.0 OSC. 4 10 40 10 40 6 Ω LC OSC. 2 20 90 20 90 10 µH = 1 Ω 100 µH = 5 Ω 1 mH = 75 Ω NOTES: 1. 32 kHz quartz crystals with a series resistance higher than 15 kΩ will reduce the guaranteed supply voltage range to 2.5 -3.5V. 2. The equivalent circuit data of the internal oscillator compares with that of matched crystals. OSCILLATOR EQUIVALENT CIRCUIT PARAMETERS (SEE FIGURE 15) SYMBOL PARAMETER OPTION CONDITION MIN. TYP. MAX. UNIT gm Transconductance Osc.1 T = +25 °C; VDD = 4.5V - 15 - µs gm Osc.2 T = +25 °C; VDD = 4.5V 200 600 1000 µs gm Osc.3 T = +25 °C; VDD = 4.5V 400 1500 4000 µs gm Osc.4 T = +25 °C; VDD = 4.5V 1000 4000 10000 µs C1 i Input Capacitance Osc.1 - 3.0 - pF C1 i pp Osc. 2 - 8.0 - pF C1 i Osc. 3 - 8.0 - pF C1 i Osc. 4 - 8.0 - pF C2 i Output Capacitance Osc.1 - 23 - pF C2 i pp Osc. 2 - 8.0 - pF C2 i Osc. 3 - 8.0 - pF C2 i Osc. 4 - 8.0 - pF R2 Output Capacitance Osc.1 - 3800 - kΩ R2 Osc. 2 - 65 - kΩ R2 Osc. 3 - 18 - kΩ R2 Osc. 4 - 5.0 - kΩ

1.7.2 RC Oscillator (see Figure 16)

The externally adjustable RC-oscillator has a frequency range from 100 kHz to 500 kHz. Figure 15. Equivalent Circuit Diagram Figure 16. Frequency as a Function of RC

1.8 Reset Circuitry

therefore be defined by the user. The standard reset value for port P0-P3 is 1111 1111. trigger is sampled by the reset circuitry every machine cycle. pins adopt their reset state immediately after RST goes HIGH. During reset ALE and PSEN are held HIGH. every cycle until RST goes LOW. the RAM contents are indeterminate.

1.8.1 Power-on reset

CPU is held in a reset state. level of 1.3 V will ensure correct operation. typically 800µA and can be chosen if external reset circuitry is used. time required is the oscillator start-up time, plus 2 machine cycles.

1.9 P80CL31: ROMless version of P80CL51

• Port options: all ports have option “1S”, i.e., standard port, high after reset
• Oscillator option: OSC3
• Power-on Reset option: OFF

1.10 P80C51: 5V standard version

maintained in the P80C51 with the exception of the mask options.

• Port options: all ports have option “1S”, i.e., standard port, high after reset.
• Oscillator options: OSC3
• Power-on Reset option: OFF

Figure 17. Reset Configuration at RST Pin

Figure 18. Power-on Reset Switching Level

1536 OSCILLATOR

Figure 19. Recommended Power-on Reset Circuitry

Philips Semiconductors Product specification 80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers January 1995 27

2.0 RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER MIN. MAX. UNIT VDD Supply voltage (pin 40) -0.5 + 6.5 V VI All input voltages -0.5 VDD +0.5 V II, IO DC current into any input or output - 5 mA PTOT Total power dissipation - 300 mW TSTG Storage temperature range -65 +150 °C TAMB Operating ambient temperature range -40 +85 °C TJ Operating junction temperature - 125 °C

3.0 DC CHARACTERISTICS P80CL31/P80CL51

VSS = 0V; TAMB = -40 to +85°C; all voltages with respect to VSS unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDD Supply voltage VSS = 0V 1.8 - 6.0 V VDD RAM retention in power down mode 1.0 – – V Supply current operating (Note 1, Note 4) IDD OSC 1 option fcIk = 32 KHz; VDD = 1.8V TAMB - 25°C - - 50 µA IDD OSC 2 option fcIk = 3.58 MHz; VDD = 3V - - 2.5 mA IDD OSC 3 option fcIk = 16 MHz; VDD = 5V - - 24 mA IDD OSC 4 option fcIk = 16 MHz; VDD = 5V - - 26 mA Idle Mode (Note 2, Note 4) IDD OSC 1 option fcIk = 32 KHz; VDD = 1.8V TAMB = 25°C - - 25 µA IDD OSC 2 option fcIk = 3.58 MHz; VDD = 3V - - 1.0 mA IDD OSC 3 option fcIk = 16 MHz; VDD = 5V - - 10 mA IDD OSC 4 option fcIk = 16 MHz; VDD = 5V - - 12 mA IPD Power down (Note 3, Note 4) VDD = 1.8V, TAMB = 25°C - 10 µA Inputs VIL Input voltage LOW VSS - 0.3VDD V VIH Input voltage HIGH 0.7VDD - VDD V IIL Input current logic 0 (Port 1 2 3) VDD = 5V, VIN = 0.4V - - 100 µA IIL Input current logic 0 (Port 1, 2, 3) VDD = 2.5V, VIN = 0.4V - - 50 µA ITL Input current logic 1 to 0 transition VDD = 5V, VIN = VDD /2 - - 1.0 mA ITL Input current logic 1 to 0 transition (Port 1, 2, 3) VDD = 2.5V, VIN = VDD /2 - - 500 µA +/IIL Input leakage current (Port 0, EA) VSS < VI < VDD - - 10 µA Outputs IOL Output sink current LOW VDD = 5V, VOL = 0.4V 1.6 - - mA IOL O utput sink current LOW VDD = 2.5V, VOL = 0.4V 0.7 - - mA -IOH Output source current HIGH VDD = 5V; VOH = VDD -0.4V 1.6 - - mA -IOH Output source current HIGH (push-pull options only) VDD = 2.5V; VOH = VDD -0.4V 0.7 - - mA R RST RST pull-down resistor 10 – 200 kΩ NOTES: 1. The operating supply current is measured with all output pins disconnected; XTAL 1 driven with tr = tf = 10ns; VIL = VSS ; VIH = VDD ; XTAL 2 not connected; EA = RST = Port 0 = VDD ; all open drain outputs connected to VSS . 2. The idle mode supply current is measured with all output pins disconnected; XTAL 1 driven with tr = tf = 10ns; VIL = VSS . XTAL 2 not connected; EA = Port 0 = VDD ; RST = VSS ; all open drain outputs connected to VSS. 3. The power-down current is measured with all output pins disconnected; XTAL 1 not connected; EA = Port 0 = VDD ; RST = VSS ; all open drain outputs connected to VSS. 4. Circuits with Power-on Reset option “OFF” are tested at VDD minimum = 1.8V; with option “ON” (typically 1.3V) they are tested at VDD minimum = 2.3V. Please note, option “ON” is only available on P80CL51.

Philips Semiconductors Product specification 80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers January 1995 28

4.0 DC CHARACTERISTICS P80C51

VSS = 0V; VDD = 5V ± 10%; fclk = 3.5 to 16MHz; TAMB = -40 to +85°C; all voltages with respect to VSS unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDD Supply voltage VSS = 0V 4.5 - 5.5 V Supply Current IDD Operating (Note 1) fCLK = 16MHz, VDD = 5V – – 24 mA IDD Idle mode (Note 2) fCLK = 16MHz, VDD = 5V – – 10 mA IPD Power down (Note 3) VDD = 5V – – 50 µA Inputs VIL Input voltage LOW VSS – 0.3VDD V VIH Input voltage HIGH 0.7VDD – VDD V IIL Input current logic 0 (Port 1, 2, 3) VIN = 0.4V – – 100 µA IIL Input current logic 1 to 0 transition (Port 1, 2, 3)VIN = VDD /2 – – 1.0 mA IIL Input leakage current (Port 0, EA) VSS < VI < VDD – – 10 µA Outputs IOL Output sink current LOW VOL = 0.4V 1.6 – – mA IOH Output source current HIGH (push-pull options only) VOH = VDD – 0.4V 1.6 – – mA R RST RST pull-down resistor 10 – 200 kΩ NOTES: 1. The operating supply current is measured with all output pins disconnected; XTAL 1 driven with tR = tF = 10ns; VIL = VSS ; VIH = VDD ; XTAL 2 not connected; EA = RST = Port 0 = VDD ; all open drain outputs connected to VSS . 2. The idle mode supply current is measured with all output pins disconnected; XTAL 1 driven with tR = tF = 10ns; VIL = VSS . XTAL 2 not connected; EA = Port 0 = VDD ; RST = VSS ; all open drain outputs connected to VSS. 3. The power-down current is measured with all output pins disconnected; XTAL 1 not connected; EA = Port 0 = VDD ; RST = VSS ; all open drain outputs connected to VSS . 4. Please note, option “ON” is only available on P80CL51.

Philips Semiconductors Product specification 80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers January 1995 29

5.0 AC CHARACTERISTICS

VDD = 5 V; VSS = 0V; Tamb = -40 to +85°C; CL = 50 pF for Port 0, ALE and PSEN; CL = 40pF for all other outputs, unless otherwise specified. PROGRAM MEMORY (See Figure 20) SYMBOL PARAMETER VARIABLE CLOCK SYMBOL PARAMETER MIN. TYP. MAX. UNIT tLL ALE pulse duration 2TCK -40 - - ns tAL Address set-up time to ALE TCK -40 - - ns tLA Address hold time to ALE TCK -35 - - ns tLC Time from ALE to control pulse PSEN TCK -25 - - ns tLIV Time from ALE to valid instruction input - - 4TCK -100 ns tCC Control pulse duration PSEN 3TCK -35 - - ns tCIV Time from PSEN to valid instruction input - - 3TCK -125 ns tCI Input instruction hold time after PSEN 0 - - ns tCIF Input instruction float delay after PSEN - - TCK -20 ns tAIV Address to valid instruction input - - 5TCK -115 ns tAFC Address float time to PSEN 0 - - ns EXTERNAL DATA MEMORY (See Figures 21 and 22) SYMBOL PARAMETER VARIABLE CLOCK SYMBOL PARAMETER MIN. TYP. MAX. UNIT tRR RD pulse duration 6TCK -100 - - ns tWW WR pulse duration 6TCK -100 - - ns tLA Address hold time after ALE TCK -35 - - ns tRD RD to valid data input TCK -35 - 5TCK -165 ns tDFR Data float delay after RD - - 2TCK -70 ns tLD Time from ALE to valid data input - - 8TCK -150 ns tAD Address to valid data input - - 9TCK -165 ns tLW Time from ALE to RD and WR 3TCK -50 - 3TCK +50 ns tAW Time from address to RD and WR 4TCK -130 - - ns tWHLH Time from RD or WR HIGH to ALE HIGH TCK -40 - TCK -40 ns tDWX Data valid to WR transition TCK -60 - - ns tDW Data set-up time before WR TCK -150 - - ns tWD Data hold time after WR TCK -50 - - ns tWAFR Address float delay after RD (Note 1) - - 12 ns NOTE: 1. Interfacing the 80CL51 or P80C51 to devices with float times up to 75ns is permitted. This limited bus connection will not cause damage to Port 0 drivers.

Figure 22. Write to Data Memory

Figure 23. Instruction Cycle Timing

6.0 CHARACTERISTICS CURVES

Figure 24. AC Testing Input Waveform Figure 25. Input Current at VDD = 5V

Figure 26. P80CL51/31 Frequency Operating Range

8 MHz

3.58 MHz

12 MHz

Figure 27. P80CL51/31 Typical Operating Current vs Frequency and VDD , Tamb = 25oC. Figure 28. P80CL51/31 Typical Idle Current vs Frequency and VDD , Tamb = 25oC. Figure 29. P80CL51/31 Typical Power-Down Current vs Frequency and VDD , Tamb = 25oC.

16 MHz

Philips Semiconductors Product specification 80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers January 1995 35 DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

Philips Semiconductors Product specification 80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers January 1995 36 PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

Philips Semiconductors Product specification 80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers January 1995 37 QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2

Philips Semiconductors Product specification 80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers January 1995 38 NOTES

Philips Semiconductors Product specification 80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers January 1995 39 NOTES

Philips Semiconductors Product specification 80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act.  Copyright Philips Electronics North America Corporation 1995 All rights reserved. Printed in U.S.A.