80C453 PHILIPS | Alldatasheet
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Philips Semiconductors Preliminary specification 80C453/83C453/87C453CMOS single-chip 8-bit microcontrollers 3-3111996 Aug 15
DESCRIPTION
The Philips 8XC453 is an I/O expanded single-chip microcontroller fabricated with Philips high-density CMOS technology. Philips epitaxial substrate minimizes latch-up sensitivity. The 8XC453 is a functional extension of the 87C51 microcontroller with three additional I/O ports and four I/O control lines. The 8XC453 is available in 68-pin LCC packages. Four control lines associated with port 6 facilitate high-speed asynchronous I/O functions. The 87C453 includes an 8k × 8 EPROM, a 256 × 8 RAM, 56 I/O lines, two 16-bit timer/counters, a seven source, two priority level, nested interrupt structure, a serial I/O port for either a full duplex UART, I/O expansion, or multi-processor communications, and on-chip oscillator and clock circuits. The 87C453 has two software selectable modes of reduced activity for further power reduction; idle mode and power-down mode. Idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. Power-down mode freezes the oscillator, causing all other chip functions to be inoperative while maintaining the RAM contents.
FEATURES
- 80C51 based architecture
- Seven 8-bit I/O ports
- Port 6 features: – Eight data pins – Four control pins – Direct MPU bus interface – ISA Bus Interface – Parallel printer interface – IBF and OBF interrupts – A flag latch on host write
- On the microcontroller: – 8k × 8 EPROM Quick pulse programming algorithm Two-level program security system – 256 × 8 RAM – Two 16-bit counter/timers – Two external interrupts
- External memory addressing capability – 64k ROM and 64k RAM
- Low power consumption: – Normal operation: less than 24mA at 5V, 16MHz – Idle mode – Power-down mode
- Reduced EMI
- Full-duplex enhanced UART – Framing error detection – Automatic address recognition LCC PIN FUNCTIONS LCC 916 1 27 43 Pin Function 1E A /VPP 2 P2.0/A8 3 P2.1/A9 4 P2.2/A10 5 P2.3/A11 6 P2.4/A12 7 P2.5/A13 8 P2.6/A14 9 P2.7/A15 10 P0.7/AD7 11 P0.6/AD6 12 P0.5/AD5 13 P0.4/AD4 14 P0.3/AD3 15 P0.2/AD2 16 P0.1/AD1 17 P0.0/AD0 18 V CC 19 P4.7 20 P4.6 21 P4.5 22 P4.4 23 P4.3 Pin Function 24 P4.2 25 P4.1 26 P4.0 27 P1.0 28 P1.1 29 P1.2 30 P1.3 31 P1.4 32 P1.5 33 P1.6 34 P1.7
35 RST
36 P3.0/RxD 37 P3.1/TxD 38 P3.2/INTO 39 P3.3/INT1 40 P3.4/T0 41 P3.5/T1 42 P3.6/WR 43 P3.7/RD 44 P5.0 45 P5.1 46 P5.2 Pin Function 47 P5.3 48 P5.4 49 P5.5 50 P5.6 51 P5.7
52 XTAL2
53 XTAL1
55 ODS
56 IDS
57 BFLAG
58 AFLAG
59 P6.0 60 P6.1 61 P6.2 62 P6.3 63 P6.4 64 P6.5 65 P6.6 66 P6.7
67 PSEN
68 ALE/PROG
Philips Semiconductors Preliminary specification 80C453/83C453/87C453CMOS single-chip 8-bit microcontrollers
1996 Aug 15 3-312
ORDERING INFORMATION
EPROM 1 ROMLESS ROM TEMPERATURE °C AND PACKAGE FREQ. (MHz) PKG. DWG # P87C453EBAA OTP P80C453EBAA P83C453EBAA 68–Pin Plastic Leaded Chip Carrier, 0 to +703.5 to 16SOT188-3 P87C453EFAA OTP P80C453EFAA P83C453EFAA 68–Pin Plastic Leaded Chip Carrier, –40 to +853.5 to 16SOT188-3 P87C453EBLKA UV 68-Pin Ceramic Leaded Chip Carrier with window, 0 to +70 3.5 to 16 1473A P87C453EFLKA UV 68-Pin Ceramic Leaded Chip Carrier with window, –40 to +85 3.5 to 16 1473A NOTE: 1. OTP = One-Time Programmable EPROM. UV = Erasable EPROM. LOGIC SYMBOL PORT 0PORT 1PORT 2 PORT 3 ADDRESS AND DATA BUS ADDRESS BUS RxD TxD INT0 INT1 WR RD SECONDARY FUNCTIONS RST EA /VPP PSEN ALE/PROG VSSVCC XTAL1 XTAL2PORT 6 PORT 4 PORT 5 PORT 6 CONTROL ODS IDS BFLAG AFLAG SU00085
Philips Semiconductors Preliminary specification 80C453/83C453/87C453CMOS single-chip 8-bit microcontrollers
1996 Aug 15 3-313
256 BYTES
INTERRUPT, SERIAL PORT AND TIMER BLOCKS PORT 4 DRIVERS PORT 4 LATCH P4.0–P4.7 PORT 5 DRIVERS PORT 5 LATCH P5.0–5.7 PORT 6 LATCH PORT 6 DRIVERS P6.0–P6.7 PORT 6 CONTROL/STATUS IDS ODS AFLAG BFLAG 8K x 8 EPROM PSW CSR DPH DPL AUXR SU00158
Philips Semiconductors Preliminary specification 80C453/83C453/87C453CMOS single-chip 8-bit microcontrollers
1996 Aug 15 3-314
MNEMONIC PIN NO. TYPE NAME AND FUNCTION VSS 54 I Ground: 0V reference. VCC 18 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0–0.7 17-10 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 is also the multiplexed data and low-order address bus during accesses to external memory. External pull-ups are required during program verification. Port 0 can sink/source eight LS TTL inputs. P1.0–P1.7 27-34 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 receives the low-order address bytes during program memory verification. Port 1 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups. P2.0–P2.7 2-9 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 emits the high-order address bytes during access to external memory and receives the high-order address bits and control signals during program verification. Port 2 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups. P3.0–P3.7 36-43 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups. Port 3 also serves the special functions listed below: 36 I RxD (P3.0): Serial input port 37 O TxD (P3.1): Serial output port 38 I INT0 (P3.2): External interrupt 39 I INT1 (P3.3): External interrupt 40 I T0 (P3.4): Timer 0 external input 41 I T1 (P3.5): Timer 1 external input 42 O WR (P3.6): External data memory write strobe 43 O RD (P3.7): External data memory read strobe P4.0–P4.3 P4.0–P4.7 26-19 I/O I/O Port 4: Port 4 is an 8-bit bidirectional I/O port with internal pull-ups. Port 4 can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. P5.0–P5.7 44-51 I/O Port 5: Port 5 is an 8-bit bidirectional I/O port with internal pull-ups. Port 5 can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. P6.0–P6.7 59-66 I/O Port 6: Port 6 is a specialized 8-bit bidirectional I/O port with internal pull-ups. This special port can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 6 can be used in a strobed or non-strobed mode of operation. Port 6 works in conjunction with four control pins that serve the functions listed below: ODS 55 I ODS : Output data strobe IDS 56 I IDS: Input data strobe BFLAG 57 I/O BFLAG: Bidirectional I/O pin with internal pull-ups AFLAG 58 I/O AFLAG: Bidirectional I/O pin with internal pull-ups RST 35 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal pull-down resistor permits a power-on reset using only an external capacitor connected to VCC . ALE/PROG 68 I/O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except during an external data memory access, at which time one ALE is skipped. ALE can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. This pin is also the program pulse during EPROM programming. PSEN 67 O Program Store Enable: The read strobe to external program memory. PSEN is activated twice each machine cycle during fetches from external program memory. However, when executing out of external program memory, two activations of PSEN are skipped during each access to external program memory. PSEN is not activated during fetches from internal program memory. PSEN can sink/source eight LS TTL inputs and drive CMOS inputs without an external pull-up. This pin should be tied low during programming. EA /VPP 1 I Instruction Execution Control/Programming Supply Voltage: When EA is held high, the CPU executes out of internal program memory, unless the program counter exceeds 1FFFH. When EA is held low, the CPU executes out of external program memory. EA must never be allowed to float. This pin also receives the 12.75V programming supply voltage (VPP ) during EPROM programming. XTAL1 53 I Crystal 1: Input to the inverting oscillator amplifier that forms the oscillator. This input receives the external oscillator when an external oscillator is used. XTAL2 52 O Crystal 2: An output of the inverting amplifier that forms the oscillator. This pin should be floated when an external oscillator is used.
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Table 1. 87C453 Special Function Registers # SFRs are modified from or added to the 80C51 SFRs.
- REset value depends on reset source.
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Figure 1. 8XC453 Interrupt Control System source is individually enabled or disabled by setting or clearing its enable bit. register through Port 6 by the external host pulsing ODS low. Buffer by the host strobing IDS low. Serial Port interrupt is disabled. IE.3 ET1 Enables or disables the Timer 1 Overflow interrupt. If ET1=0, the Timer 1 interrupt is disabled. IE.2 EX1 Enables or disables External Interrupt 1. If EX1=0, External Interrupt 1 is disabled. IE.1 ET0 Enables or disables the Timer 0 Overflow interrupt. If ET0=0, the Timer 0 interrupt is disabled. IE.0 EX0 Enables or disables External Interrupt 0. If EX0=0, external Interrupt 0 is disabled. Figure 2. 8XC453 Interrupt Enable (IE) Register
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IP.4 PS Defines the Serial Port interrupt priority level. PS=1 programs it to the higher priority level. IP.3 PT1 Defines the Timer 1 interrupt priority level. PT1=1 programs it to the higher priority level. IP.2 PX1 Defines the External Interrupt 1 priority level. PX1=1 programs it to the higher priority level. IP.0 PX0 Defines the External Interrupt 0 priority level. PX0=1 programs it to the higher priority level. Figure 3. 8XC453 Interrupt Priority (IP) Register is used in modes 1, 2, or 3. if a warm start has occurred. PCON.3 GF1 General-purpose flag bit. PCON.2 GF0 General-purpose flag bit. PCON.0 IDL Idle mode bit. Setting this bit activates the idle mode. If logic 1s are written to PD and IDL at the same time, PD takes precedence. Figure 4. Power Control Register (PCON)
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frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. Given or Broadcast Address. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. other modes, in any serial transmission. Must be cleared by software. the other modes, in any serial reception (except see SM2). Must be cleared by software. Figure 5. Serial Port Control Register (SCON) Figure 6. UART Framing Error Detection
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– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. Figure 7. UART Multiprocessor Communication, Automatic Address Recognition SCON.7 can only be cleared by software. Refer to Figure 6. Mode 0 is the Shift Register mode and SM2 is ignored. address which the master will use for addressing each of the slaves.
Philips Semiconductors Preliminary specification 80C453/83C453/87C453CMOS single-chip 8-bit microcontrollers
1996 Aug 15 3-320
In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary t make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are teated as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. this effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature. The 87C453 UART has all of the capabilities of the standard 80C51 UART plus Framing Error Detection and Automatic Address Recognition. As in the 80C51, all four modes of operation are supported as well as the 9th bit in modes 2 and 3 that can be used to facilitate multiprocessor communication. OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. Reset A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on V CC and RST must come up at the same time for a proper start-up. Idle Mode In the idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. Power-Down Mode To save even more power, a Power Down mode can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power Down mode is terminated. On the 87C453 either a hardware reset or external interrupt can cause an exit from Power Down. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. To properly terminate Power Down the reset or external interrupt should not be executed before V CC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10ms). With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down. Power Off Flag The Power Off Flag (POF) in PCON is set by on-chip circuitry when the VCC level on the 87C453 rises from 0 to 5V. The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown. The VCC level must remain above 3V for the POF to remain unaffected by the V CC level. Design Consideration
- When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal rest algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. ONCE Mode The ONCE (“On-Circuit Emulation”) Mode facilitates testing and debugging of systems using the 87C453 without having to remove the IC from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the 87C453 is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied. PORTS 4 AND 5 Ports 4 and 5 are bidirectional I/O ports with internal pull-ups. Port 4 is an 8-bit port. Port 4 and port 5 pins with ones written to them, are pulled high by the internal pull-ups, and in that state can be used as inputs. Ports 4 and 5 are addressed at the special function register addresses shown in Table 2. PORT 6 Port 6 is a special 8-bit bidirectional I/O port with internal pull-ups (see Figure 8). This port can be used as a standard I/O port, or in strobed modes of operation in conjunction with four special control lines: ODS , IDS, AFLAG, and BFLAG. Port 6 operating modes are controlled by the port 6 control status register (CSR). Port 6 and the CSR are addressed at the special function register addresses shown in Table 2. The following four control pins are used in conjunction with port 6: ODS – Output data strobe for port 6. ODS can be programmed to control the port 6 output drivers and the output buffer full flag (OBF), or to clear only the OBF flag bit in the CSR (output-always mode).
Philips Semiconductors Preliminary specification 80C453/83C453/87C453CMOS single-chip 8-bit microcontrollers
1996 Aug 15 3-321
ODS is active low for output driver control. The OBF flag can be programmed to be cleared on the negative or positive edge of ODS. Can produce an IOB interrupt (see Figure 2). IDS – Input data strobe for port 6. IDS is used to control the port 6 input latch and input buffer full flag (IBF) bit in the CSR. The input data latch can be programmed to be transparent when IDS is low and latched on the positive transition of IDS, or to latch only on the positive transition of IDS. Correspondingly, the IBF flag is set on the negative or positive transition of IDS. Can produce an IIB interrupt (see Figure 2). AFLAG – AFLAG is a bidirectional I/O pin which can be programmed to be an output set high or low under program control, or to output the state of the output buffer full flag. AFLAG can also be programmed to be an input which selects whether the contents of the output buffer, or the contents of the port 6 control status register will output on port 6. This feature grants complete port 6 status to external devices. BFLAG – BFLAG is a bidirectional I/O pin which can be programmed to be an output, set high or low under program control, or to output the state of the input buffer full flag. BFLAG can also be programmed to input an enable signal for port 6. When BFLAG is used as an enable input, port 6 output drivers are in the high-impedance state, and the input latch does not respond to the IDS strobe when BFLAG is high. Both features are enabled when BFLAG is low. This feature facilitates the use of the 87C453 in bused multiprocessor systems. CONTROL STATUS REGISTER The control status register (CSR) establishes the mode of operation for port 6 and indicates the current status of port 6 I/O registers. All control status register bits can be read and written by the CPU, except bits 0 and 1, which are read only. Reset writes ones to bits 2 through 7, and writes zeros to bits 0 and 1 (see Table 3). CSR.0 Input Buffer Full Flag (IBF) (Read Only) – The IBF bit is set to a logic 1 when port 6 data is loaded into the input buffer under control of IDS . This can occur on the negative or positive edge of IDS, as determined by CSR.2. When IBF is set, the Interrupt Enable Register bit IIB (IE.5) is set. The Interrupt Service Routine vector address for this interrupt is 002BH. IBF is cleared when the CPU reads the input buffer register. CSR.1 Output Buffer Full Flag (OBF) (Read Only) – The OBF flag is set to a logic 1 when the CPU writes to the port 6 output data buffer. OBF is cleared by the positive or negative edge of ODS, as determined by CSR.3. When OBF is cleared, the Interrupt Enable Register bit IOB (IE.6) is set. The Interrupt Service Routine vector address for this interrupt is 0033H. CSR.2 IDS Mode Select (IDSM) – When CSR.2 = 0, a low-to-high transition on the IDS pin sets the IBF flag. The Port 6 input buffer is loaded on the IDS positive edge. When CSR.2 = 1, a high-to-low transition on the IDS pin sets the IBF flag. Port 6 input buffer is transparent when IDS is low, and latched when IDS is high. CSR.3 Output Buffer Full Flag Clear Mode (OBFC) – When CSR.3 = 1, the positive edge of the ODS input clears the OBF flag. When CSR.3 = 0, the negative edge of the ODS input clears the OBF flag. CSR.4, CSR.5 AFLAG Mode Select (MA0, MA1) – Bits 4 and 5 select the mode of operation for the AFLAG pin as follows: MA1 MA0 AFLAG Function 0 0 Logic 0 output 0 1 Logic 1 output 1 0 OBF flag output (CSR.1) 1 1 Select (SEL) input mode The select (SEL) input mode is used to determine whether the port 6 data register or the control status register is output on port 6. When the select feature is enabled, the AFLAG input controls the source of port 6 output data. A logic 0 on AFLAG input selects the port 6 data register, and a logic 1 on AFLAG input selects the control status register. The value of the AFLAG input is latched into the Auxiliary Register (AUXR) bit 1 (AUXR.1). Checking this bit (AF) will allow the 87C453’s program to determine if Port 6 was loaded with data or a UPI command. CSR.6, CSR.7 BFLAG Mode Select (MB0, MB1) – Bits 6 and 7 select the mode operation as follows: MB1 MB0 BFLAG Function 0 0 Logic 0 output 0 1 Logic 1 output 1 0 IBF flag output (CSR.0) 1 1 Port enable (PE In the port enable mode, IDS and ODS inputs are disabled when BFLAG input is high. When the BFLAG input is low, the port is enabled for I/O. Reduced EMI Mode – The on–chip clock distribution drivers have been identified as the cause of most of the EMI emissions from the 80C51 family. By tailoring the clock drivers properly, a compromise between maximum operating speed and minimal EMI emissions can be achieved. Typically, an order in magnitude of reduction is possible over previous designs. This feature has been implemented on this chip along with the additional capability of turning off the ALE output. Setting the AO bit (AUXR.0) in the AUXR special function register will disable the ALE output. Reset forces a 0 into AUXR.0 to enable normal 80C51 type operation. Auxiliary Register (AUXR) 76543210 Latched value of AFLAG when Port 6 inputs data from IDS strobe 0 = ALE enabled 1 = ALE disabled
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Figure 8. Port 6 Block Diagram Table 2. Special Function Register Addresses Table 3. Control Status Register (CSR)
- Output-always mode: MB1 = 0, MA1 = 1, and MA0 = 0. In this mode, port 6 is always enabled for output. ODS only clears the OBF flag.
Philips Semiconductors Preliminary specification 80C453/83C453/87C453CMOS single-chip 8-bit microcontrollers
1996 Aug 15 3-323
ABSOLUTE MAXIMUM RATINGS 1, 2, 3 PARAMETER RATING UNIT Operating temperature under bias 0 to +70 –40 to +85 Storage temperature range –65 to +150 °C Voltage on any other pin to VSS –0.5 to +6.5 V Power dissipation (based on package heat transfer limitations, not device power consumption)1.5 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. Voltages are with respect to VSS unless otherwise noted. DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V TEST LIMITS SYMBOL PARAMETER CONDITIONS MIN TYP 1 MAX UNIT VIL Input low voltage; ports 0, 1, 2, 3, 4, 5, 6, IDS, ODS, AFLAG, BFLAG; except EA –0.5 0.2VCC –0.1 V VIL1 Input low voltage to EA 0 0.2VCC –0.3 V VIH Input high voltage; except XTAL1, RST 0.2VCC +0.9 VCC +0.5 V VIH1 Input high voltage; XTAL1, RST 0.7VCC VCC +0.5 V VOL Output low voltage; ports 1, 2, 3, 4, 5, 6, AFLAG, BFLAG IOL = 1.6mA2 0.45 V VOL1 Output low voltage; port 0, ALE, PSEN IOL = 3.2mA2 0.45 V VOH Output high voltage; ports 1, 2, 3, 4, 5, 6, AFLAG, BFLAG IOH = –60µA, IOH = –25µA IOH = –10µA 2.4 0.75VCC 0.9VCC V V V VOH1 Output high voltage (port 0 in external bus mode, ALE, PSEN IOH = –800µA, IOH = –300µA IOH = –80µA 2.4 0.75VCC 0.9VCC V V V IIL Logical 0 input current,; ports 1, 2, 3, 4, 5, 6VIN = 0.45V –50 µA ITL Logical 1-to-0 transition current; ports 1, 2, 3, 4, 5, 6See note 4 –650 µA ILI Input leakage current; port 0 VIN = VIL or VIH ±10 µA ICC Power supply current: Active mode @ 16MHz5 Idle mode @ 16MHz5 Power down mode See note 6 11.5 1.3 mA mA µA R RST Internal reset pull-down resistor 50 300 kΩ C IO Pin capacitance7 – PLCC package 10 pF NOTES: 1. Typical ratings are based on a limited number of samples from early manufacturing lots, and not guaranteed. Values are room temp., 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOL s of ALE and the other ports. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.. 3. Capacitive loading on ports 0 and 2 may cause the V OH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address bits are stabilizing. 4. Pins of ports 1, 2, 3, 4, 5 and 6 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. ICC MAX at other frequencies is given by: Active mode: ICC MAX = 0.94 X FREQ + 13.71 Idle mode: ICC MAX = 0.14 X FREQ +2.31 where FREQ is the external oscillator frequency in MHz. ICC MAX is given in mA. See Figure 20. 6. See Figures 21 through 24 for ICC test conditions. 7. CIO applies to ports 1 through 6, IDS, ODS, AFLAG, BFLAG, XTAL1, XTAL2.
Philips Semiconductors Preliminary specification 80C453/83C453/87C453CMOS single-chip 8-bit microcontrollers
1996 Aug 15 3-324
AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V 16MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL Oscillator frequency 3.5 16 MHz tLHLL 9 ALE pulse width 85 2tCLCL –40 ns tAVLL 9 Address valid to ALE low 22 tCLCL –40 ns tLLAX 9 Address hold after ALE low 32 tCLCL –30 ns tLLIV 9 ALE low to valid instruction in 150 4tCLCL –100 ns tLLPL 9 ALE low to PSEN low 32 tCLCL –30 ns tPLPH 9 PSEN pulse width 142 3tCLCL –45 ns tPLIV 9 PSEN low to valid instruction in 82 3tCLCL –105 ns tPXIX 9 Input instruction hold after PSEN 0 0 ns tPXIZ 9 Input instruction float after PSEN 37 tCLCL –25 ns tAVIV 9 Address to valid instruction in 207 5tCLCL –105 ns tPLAZ 9 PSEN low to address float 10 10 ns Data Memory tRLRH 10, 11 RD pulse width 275 6tCLCL –100 ns tWLWH 10, 11 WR pulse width 275 6tCLCL –100 ns tRLDV 10, 11 RD low to valid data in 147 5tCLCL –165 ns tRHDX 10, 11 Data hold after RD 0 0 ns tRHDZ 10, 11 Data float after RD 65 2tCLCL –60 ns tLLDV 10, 11 ALE low to valid data in 350 8tCLCL –150 ns tAVDV 10, 11 Address to valid data in 397 9tCLCL –165 ns tLLWL 10, 11 ALE low to RD or WR low 137 239 3tCLCL –50 3tCLCL +50 ns tAVWL 10, 11 Address valid to WR low or RD low 122 4tCLCL –130 ns tQVWX 10, 11 Data valid to WR transition 13 tCLCL –50 ns tWHQX 10, 11 Data hold after WR 13 tCLCL –50 ns tRLAZ 10, 11 RD low to address float 0 0 ns tWHLH 10, 11 RD or WR high to ALE high 23 103 tCLCL –40 tCLCL +40 ns Shift Register tXLXL 12 Serial port clock cycle time 750 12tCLCL ns tQVXH 12 Output data setup to clock rising edge 492 10tCLCL –133 ns tXHQX 12 Output data hold after clock rising edge 8 2tCLCL –117 ns tXHDX 12 Input data hold after clock rising edge 0 0 ns tXHDV 12 Clock rising edge to input data valid 492 10tCLCL –133 ns Port 6 input (input rise and fall times = 5ns) tFLFH 15 PE width 209 3tCLCL +20 ns tILIH 15 IDS width 209 3tCLCL +20 ns tDVIH 15 Data setup to IDS high or PE high 0 0 ns tIHDZ 15 Data hold after IDS high or PE high 30 30 ns tIVFV 16 IDS to BFLAG (IBF) delay 130 130 ns
Philips Semiconductors Preliminary specification 80C453/83C453/87C453CMOS single-chip 8-bit microcontrollers
1996 Aug 15 3-325
AC ELECTRICAL CHARACTERISTICS (Continued) 16MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT Port 6 output tOLOH 13 ODS width 209 3tCLCL +20 ns tFVDV 14 SEL to data out delay 85 85 ns tOLDV 13 ODS to data out delay 80 80 ns tOHDZ 13 ODS to data float delay 35 35 ns tOVFV 13 ODS to AFLAG (OBF) delay 100 100 ns tFLDV 13 PE to data out delay 120 120 ns tOHFH 14 ODS to AFLAG (SEL) delay 100 100 ns External Clock tCHCX 17 High time 20 20 ns tCLCX 17 Low time 20 20 ns tCLCH 17 Rise time 20 20 ns tCHCL 17 Fall time 20 20 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
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Examples: tAVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low. Figure 9. External Program Memory Read Cycle Figure 10. External Data Memory Read Cycle
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Figure 11. External Data Memory Write Cycle Figure 12. Shift Register Mode Timing
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Figure 13. Port 6 Output Figure 14. Port 6 Select Mode Figure 15. Port 6 Input Figure 16. IBF Flag Output
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Figure 17. External Clock Drive AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Figure 18. AC Testing Input/Output OH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 19. Float Waveform VALID ONLY WITHIN FREQUENCY SPECIFICATIONS OF THE DEVICE UNDER TEST. Figure 20. ICC vs. FREQ
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Figure 21. ICC Test Condition, Active Mode Figure 22. ICC Test Condition, Idle Mode Figure 23. Clock Signal Waveform for ICC Tests in Active and Idle Modes Figure 24. ICC Test Condition, Power Down Mode
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number of the ALE/PROG pulses. circuit configuration for normal program memory verification. Figure 26. Note that the 87C453 is running with a 4 to 6MHz device is executing internal address and program data transfers. low 15 to 25 times, as shown in Figure 26. Figure 27. The other pins are held at the ‘Verify Code Data’ levels encryption table itself cannot be read out. which satisfies the timing specifications, is suitable. light with wavelengths shorter than approximately 4,000 angstroms. Erasure leaves the array in an all 1s state. Table 4. EPROM Programming Modes
- ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
- VCC = 5V ±10% during programming and verification.
Trademark phrase of Intel Corporation.
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15 TO 25 100µs PULSES TO GROUND
Figure 25. Programming Configuration
15 TO 25 PULSES
Figure 26. PROG Waveform
0 ENABLE
Figure 27. Program Verification
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- FOR PROGRAMMING VERIFICATION SEE FIGURE 25.
FOR VERIFICATION CONDITIONS SEE FIGURE 27. Figure 28. EPROM Programming and Verification