P80C35

Toshiba Semiconductor

CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER (TLCS-48C)

Manufacturer: Toshiba Semiconductor

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TMP80C48A TOSHIBA | Alldatasheet

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CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER (TLCS-48C) TMP80C48AP /TMP80C48AP- 6 TMP80C35AP/TMP80C35AP- 6 TMP80C48AU/TMP80C48AU-6 1. GENERAL DESCRIPTION AND FEATURES The TMP80C48A is a single chip microcomputer fabricated in Silicon Gate CMOS technology which provides internal 8-bit parallel architecture. The following basic architectural functions of a computer have been included in a single chip; an 8-bit CPU, 64X8 RAM data memory, 1KX8 ROM program memory, 27 1/0 lines and an 8-bit timer/event counter. ‘The TMP80C48A is particularly efficient as a controller. It has extensive bit handling capability as well as facilities for both binary and BCD arithmetic. The TMP80C35A/-6 is the equivalent of a TMP80C48A/-6 without ROM program memory on chip. By using this device with external EPROM or RAM, software debugging becomes easy. The TMP80C48AP/-6 and TMP80C35AP/-6 are in a standard Dual Inline Package. ‘The TMP80C48AU/-6 is in a 44-pin Micro Flat Package.

FEATURES

© — TMP80C48AP/TMP80C35AP/TMP80C48AU 1.36ps Instruction Cycle Time —40°C to 85°C, 5V+10% © — TMP80C48AP-6/TMP80C35AP-6/TMP80C48AU-6 2.5ns Instruction Cycle Time —40°C to 85°C, 5V+20% © Software Upward Compatible with TMP8048A P/INTEL's 8048 ® 1K xX 8 masked ROM/64 X 8RAM © Low Power 10mA MAX. in Normal Operation (Voc=5V, fx aL =6MHz) 10pA MAX. in Power Down Mode (Voc=5V, fx rau: DC) © Power Down Mode (Stand-by Mode) © Halt Mode (Idle Mode) MCU48-1

PIN CONNECTIONS AND PIN FUNCTIONS

2.1 Pin Connections (Top View)

To 1 40 1 Vec(+5V) XTAL) 42 39 fT XTAL2 43 38 fl P27 RESET 4 371 Pa¢ 3s qs 36 fl Pas INT (6 35 0 P2a EA d7 34.0 Piz RD 8 33 1) Pig PSEN 49 32 1 Pas WR 10 310 Pig ALE G11 30 f Pis DB 412 29 fh Pr2 DB, q13 28 fl Pay Bz 414 27 f Pro DB3 G15 26 p PS DB, 116 25 | PROG . DBs 017 24 P23 DB. 418 23D P22 DB, 419 22) Pat Vss 420 211) Pao 020909 Figure 2.1 DIP Pin Connections sgagu 3 8848 25k aE HARRAH AH ABE '3332313029282726252423 DBs CoO 34 22fa RESET 08; Com 35 2ifo5 Nc De. 11] 36 20f XTALy DB, (1437 19—0I— XTAL; Vss od 38 18H To P2o Co} 39 17 EE Vee Pay oa0 16fT 7; Pn Corda 1H Pay Pn ora 14h Pig PROG Cor} 43 13/9 Ps Ne coo we) 12poo Ne 123456789101 UUUUUUOUUUG RE&EsFELLEES 020989 Figure 2.1 Micro Flat Package Pin Connections MCU48-2

2.2 Pin Names And Pin Description

@ ~~ Vgg (Power Supply) Circuit GND potential © — Voc (Power Supply) +5V during operation e = PS (Input) The control signal for the power saving at the power down mode (Active Low) e@ ~— PROG (Output) Output strobe for the TMP82C43P I/O expander. © — Pyo-P17 (Input/Output) Portl 8-bit quasi-bidirectional port (Internal Pullup=50KQ). © — P29-P27 (Input/Output) Port2 8-bit quasi-bidirectional port (Internal Pullup~50KQ). P2o-P93 contain the four high order program counter bits during an external program memory fetch and serve as a 4-bit I/O expander bus for the TMP82C43P. © — DBo-DBy (Input/Output, Tri-State) True bidirectional port which can be written or read synchronously using the RD, WR strobes. The port can also be statically latched. Contains the 8 low order program counter bits during an external program memory fetch, and receives the addressed instruction under the control of PSEN. Also contains the address and data during an external RAM data store instruction, under control of ALE, RD, and WR. ® = Tp Unput/Output) Input pin testable using the conditional transfer instructions JTO and JNTO. TO can be designated as a clock output using ENTO CLK instruction. © — T, (Input) Input pin testable using the JT1 and JNT1 instruction. Can be designated the event counter input using the timer/STRT CNT instruction. e INT Unput) External interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is disabled after a reset. Also testable with conditional jump instruction. (Active low) McUu48-3

e = RD (Output) Output strobe activated during a Bus read. Can be used to enable data onto the Bus from an external device. Used as a Read Strobe to External Data Memory (Active Low). © = WR (Output) Output strobe during a Bus write (Active Low). Used as a Write Strobe to External Data Memory. e RESET (Input) Active Low signal which is used to initialize the Processor. Also used during the power down mode. © ALE (Output) Address Latch Enable. This signal occurs once during each cycle and is useful asa clock output. The negative edge of ALE strobes address into external data and program memory. © — PSEN (Output) Program Store Enable. This output occurs only during a fetch to external program memory (Active Low). e SS (Input) Single step input can be used in conjunction with ALE to “single step” processor through each instruction when SS is low the CPU is placed into a wait state after it has completed the instruction being executed. Also used during the power down mode. ; e® EA (Input) External Access input which forces all program memory fetches to reference external memory. Useful for emulation and debug and essential for testing and program verification. (Active High) e = XTAL; (Input) One side of crystal input for internal oscillator. Also input for external source. e@ = XTAL» (Input) Other side of crystal input. McU48-4

TOSHIBA TMP80C48A/35A, 2.3. Block Diagram DBo - By Pio- Paz Pog -Pa7 mr a 1K x 8 [ [cnn fi ACCUMULATOR: Jo TINT POWER ttt XTAL; XTAL) RESET INT EA SS ALE PSEN RD WR PROG 6e 2S2 co £88 8 sy 88 ae 22262 “SE £ gS Ze SS S- 84 ww BS B 82 EF z 2 7 Fa = 2 2 5 i 020989 Note1: The lower order 4 bit of port 2 output latch are used also for input/output operations with the /O expander. Note 2: The output latch of port 0 is also used for address output. Figure 2.3 Block Diagram MCU48-5

MACHINE INSTRUCTION The following symbols and codes are used in the list of machine instruction. see [ee Re Working register (0<r<7) Pp VO port address P; (0<p<7) ‘JBb Branch instruction in accordance with bit content (b) of operand aH Higher order 3 bits of a aM Medium order 4 bits of a aL Lower order 4 bits of a aml Medium order or lower order 8 bits of a (a) Content of a [ (a) ] Content of RAM addressed by a EXTE (a) J Content of external RAM addressed by a PRO[ (a) J Content of ROM addressed by a acm> Value at bit position mof a a<m:n> Value at bit position mto nofa atb Store a into b aeb Exchange a for b . Connection a 1 complement of a atb a plus b (Addition) a-b a minus b (Subtraction) aAb Logical AND for a and b ayb Logical OR for a and b avb Exclusive OR for a and b a=b ais equal tob ad>b aisnot equal to b (a) BCD Converted value of accumulator poser) MCU48-6

List of TLCS-48 Machine Instruction (1/4) = Assembler (ist) Flag E ic . ADD__A_, Rr |OdlOirrr [oBer__|(A)*(A)*(Rr), F=0~7 T ADD A ,@Rr [0110000r |60+r | (A)e(A)+E(Rr)] r=0,1 t 1 ADD A Hi 00000011 | 03 |(A)+(A)+i T 2 Viitit7 ii ADOC AY Rr JOritirrr [78+ | (A)e(A)+(Rr)+(c) r0~7 t i ADDC A ,@Rr |0111000r |70+r | (A)e(A)+[(Rr)]#(c) r=0,1 tI i ADDC A #i 0010011 | 13° | (A)#(A)+i+(c) T 2 qiiiiiii |i AML AS Re O0dteer |saer | (A)e(A) A(R) 60-7 1 ANL A ,@Rr 0101000r |50+r | (A)e(A) AL(Rr)} r20,1 1

6 JAN A Hi 01010011 | 53”) (A)e(A) Ai 2

= iiiitiii | ii y fort A’, Rr jotooterr |4eer | (A)e(A). V(Rr) 20-7 1 = fort A vere ~~ |o100000r )ao%r” | (a)e(A) VE(Rr)] 20,1 1 % fort AA Oido0011 | 43) (A)e(A) Vi 2 £ cf AAVVGAT | Ta XRL A. Re [ai0aterr |Datr | (A)e(A) V(Rr) 70-7 1 5 [xRLT A eRe | 1101000r oor“) caye(A). WE(Rr) ] 720.1 1 © xR A Hi 11010011 | D3” |(A)e(A) Vi 2 = Viiiiiii | ii Zz INC A _ Ooo10i11 | 17° | (Aje(a)+4 1 5 {DEC A oooooi1i | 07” | (A)e(A)-1 i o [cir “A ooido1i1 |" 27" | (A)<o i < fope A Voortoiat |" 37 | cayenot(a) 1 DAA Oi0i0111 | 57. | (a)+(a)BCcD t 1 ROA iii00111 [EF] (A)<n¥i> €(A)<nd> i (C)#(A)<7> (A)<O> #(C) n=0~6 RRA oiinoidt |°77° | (Ay<n> (A) <n+4> n=0-6 | 1 RRC A Oiioo1ii | 67 | (A)<n> #(A)<n+t> t 1 (C)#(A)<O> INA, Pp. |000010pp [08+p__|(A)«(Pp) P=1,2 2 OUTL Pp, A |001110pp |38+p | (Pp) +(A) P=1,2 2 © [aN ep ai 100110pp |98+p |(Pp) <(Pp)Ai P=1,2 2 + aitiiti | oii ORL Pp. Ai 100010pp |88+p |(Pp) <(Pp)vi P21,2 2 iiiiiiit ii 020989 Mcu4s-7

List of TLCS-48 Machine Instruction (2/4) = Assembler (ist) Flag 5 ionic . INS A, BUS 00001000 | 08 |(A)+(BUS) __ z ANC” “BUS #1") 10011000" |" "Sa “F(BUS)«(BUS) AT 2 . iiiiiiti | ii oo poate” Bus;## | 10001000" | “as | (euis)<(HUS) Vi 2 Qh. _fatasiaaa | aa ~ |Movo A'S Pp” "}o0001%pp |ace+p” | (a)<3:09 <(Pp) p-4~7 2 (A)<7:4> #0 MOVD Pp, A O0i1iipp |3C+p “ «(A)<3:0> pe4~7 2 ANLD Pp, A |100111pp |9C+p | (Pp) «(Pp)A(A)<3:0> p=4~7 2 ORLD Pp, A |10001ipp |8c+p | (Pp) +(Pp)(A)<3:0> p=4~7 2 INC Rr [O001irrr |18+r |(Rr) #(Re)+1 r=0~7 1 (1) INC” @Rr 0001000r |10+r /{(Rr)} ef (Rr) ]+4 r=0,1 1 DEC Rr 100irrr [Ce+r | (Rr) ¢(Rr)-1 c=0~7 1 IMP a aH00100 faH+4_{(PC)<i0:0> +a 2 aML (PC)<11> «(DBF) DUNZ” Rr, a [attire |eBer (Rr) @(Rr)-1 r20~7 2 aM. if(Rr) #0then(PC)<7:0>¢aML ; else no operation sea Liiidiio | Fe) 1F(C)=1 then(PC)<7: 05am 2 aML else no operation § Jaca Lit001i0 | EG | 7F(C)=0 then(PC)<7:05eamL 2 2 aM. else no operation y faz a 11000110} C6] i#(A)=0 then(PC)<7:0>"aML 2 fs aM. | Jelse no operation ; Sanz a 10010110 |" 96" | if(A)#0 then(PC)<7:0><aM 2 = aM else no operation i [toa 0110110 | "36 IF TO=1 ‘then(PC)<7:05eamL 2 Fy aM else no operation = ONTO a 00100110 | 26 [if TO=0 then(PC)<7:0>eamL 2 3 aM else no operation dti a O1010110- | 66 AF TA=1 then(PC)<7z05eaML 2 aML else no operation ONTL a 01000110 46 if T1*0 then(PC)<7:0>+aML 2 aM else no operation FO a i0110110 | 86 | iF FO=1 then(PC)<7:0>eaML 2 aML. else no operation dei a O1i101i0 | 76” | iF Fi=1 then(PC)<7:0>"aML 2 aML else no operation JTF a 00010110 16 if TF*1 then(PC)<7:0>+aML 2 aM else_no operation (1) “+ Register Instruction aaoses MCU48-8

List of TLCS-48 Machine Instruction (3/4) Object Code s Assembler (ist) Flag # (and) Function cyde fe a ee WNT a Too00110 | 86 [if INT =O then(PC)<7:0>eaML 2 aM else no operation (2) [dBb a bbbidoid Jb+i2” | iF (A)<b>=1 then 2 aM (PC)<7:0>¢aML else no operation _b=0~7 CALL a alioi00 | ali#ia | [(SP)] (PSW)<7:4>-(PC) 2 aM (SP) ¢(SP)+1 | (PC)<10:0> +a (PC)<11> (DBF) (3) [RET ioooodii [83 | (sP)+(SP)-1 2 (PC) +{(SP)}<11:0> RETR io0100i1 | 93°”) (sP)e(SP)-1 tt 2 cir C Tooioii | 97_ | (C)«0 1 CPL 10100111 | AZ (C)#NoT(C) 1 (a [otk FO io000101 | 85 | (Fo) +o 1 cel FO” 40010101 “95 | (FO) <noT(Fo) - 1 cir Fi 10100101 | AS) (Fi) «0 1 ceL Fa ioiioi0i | BS | (F1) <noT(F1) 1 MOV A, Rr Viilirer |F8+r (A)e(Rr) r=0-7 L MOV "A @Rr -[11i1000r |Foer | (A)eE(Rr)] r=0,1 1 MOV OA Mi 00100011 23 (A) +i 2 diiiiiii | ii ¢ NOV Rr, A |ton0trre |aBer | (Rr)e(A) r=0~7 1 © |NOV @Rr, A” |1010000r |AO+r | [ (Rr) J*(A) r0,1 1 [MOV Rr #i L0ilierr [BB+ | (Ree r0~7 2 sy iiiiiiii | ii | 5 [Mov ere. ai H1o11000r |Borr” | [ (Rr) Jei r=0,1 2 2 jiiiiiis i = {nov "a,Psw”j11000111 | 7 |(Aa) «(Psw) 1 w {MOV PSW.A”|a10a0112 | 7” |(PsW) «(A) 1

3 YXCH A Re O0101rrr |28+r | (A) (Rr) r=0~7 1

S |[xcH A,@Rr — |0010000r j20+r |(A) [(Rr)] r=0,1 1 MOVX @Rr.A |1001000r g0rr | EXTE(Rr)] “(A) r=0,1 1 MOVX A,@Rr | 1000000r |80+r | (A) +EXT[(Rr)] r=0,1 1 iMovP ” A,@A 10100011 | A3 | (A) ©PRO[(PC)<11:8>-(A)] 1 tOVP3_A.GA [iriooo11 [es | (A) +PRop(PC)<i1>-011-(A) 1 (2) Branch Instruction (3) ~~ Subroutine Instruction moe (4) «-~ Flag Instruction MCU48-9

List of TLCS-48 Machine Instruction (4/4) ‘Object Code = Assembler (ist) Flag w (2nd) Function cycle - Mnemonic | sin | Hex | CAC eo [MOV T\\A 01100010 | 62 | (TR)+(A) . 1 = [Stet 01010101 |" 55°} Start Timer 1 8 . Y = |STRT CNT 01000101 45 Start Counter 1 € |sior” tent” /o1100101 |" 68" [Stop ‘Timer /Counter 1 fe JEN TCNTI 00100101 25 Enable Timer/Counter Interrupt 1 DIS TCNTI 00110101 35 Disable Timer/Counter Interrupt 1 EN I 00000104 06 Enable External Interrupt 1 OIs 1 |00010101 | 15 |Disabie External Interrupt 1 % [SEL RBO | 42000101 ch (8S)* 0 1 S |seu Rei 11010101 |" ps] (Bs)e 1 i & [SEL MBO 11i00i01 |" 5" | (BF) « 0 1 uo {SEL MBL _.,42110101 F5 (DBF) © 1 . 1 ENTO CLK /01110101 | 75 |Enable Clock Output on To 1 HALT 00000001 o1 Halt 1 Lis) [nop fo0o00000 | 00 [no operation Tt (5) ~~ Other 020989 MCU48-10

TOSHIBA TMP80C48A/35A, 4. ELECTRICAL CHARACTERISTICS

4.1 Absolute Maximum Ratings

Vcc Supply Voltage (with respect to GND (Vss) ) ~0.5Vto +7V Input Voltage (Except EA) =0.5Vto VCC +0.5 Input Voltage (Only EA) = 0.5V to 13V [Po __| Power Dissipation (Ta = 85°C) 250inw Soldering Temperature (Soldering Time 10 sec) “cto 1H =aFeIOOST o70989

4.2 DC Characteristics

TMP80C48AP/C35AP/C48AU . Topr = — 40°C to 85°C, Vec= + 5V + 10%, Vss = OV, unless otherwise noted. SYMBOL PARAMETER TEST CONDITIONS | MIN. | TyP. | MAX. | UNIT vit Except XTAL), XTALy, RESET) | -05] = | os |v Pees | oe vitt TAL, XTAL2, RESET) 0.8 | = | es | v be vi Except XTAL,, XTALz, RESET, PS | 22 | = | ve |v Vint S<TAL, KTALp, RESET, BS) Yee| = [vec |v vou Except Pyo-Py7, Pro-P worsr6ma | = | = | oas |v Output Low Voltage _ | v_| youn Except Pia-Piz, PoP: = |= | - | VOHI2 ExceptP ig Py7, Pao 1OH = = 400nA fs| - | - | v VoHat P10-P17, P2o-P- 2a [ = | = |v [vow | igus bap Pan fee Ps [= = Pf tu INT, EA, PS) vssvinsvec | = [ = | #10] pa [ua __| IgnutLeak current Veg + 0.05VS VIN wa Peay x | = | = | -s00] oa | hoa eee [eseewewe | [= Lo High impedance condition eee | = | = | +0] va | =Vec— 'ec2 Vcc Supply operation _| feray= 11MHz [| - | - | mA = Vcc =0. 70989 MCU48-11

4.3 AC Charactristics

AC CHARACTRISTICS {CONTINUE . Topr= - 40°C to 85°C, Vcc = +5V + 10%, Vss = OV, unless otherwise noted. SYMBOL PARAMETER TEST CONDITION UNIT ie es Port Control Setup Time _ (PROG) ee Port Control Hold Time (PROG) | ae Pol - | | Port 2 Input Data Setup Time _ ter (PROG) 8.5t- 120 Port 2 Input Data Hold Time (PROG) Pf Pf e | | Port 2 Output Data Setup Time tor (PROG) 250 Port 2 Output Data Hold Time . (PROG) P fee fo] | * Port 2 I/O Data Setup Time _ her [eee se Do] coe Note : 1. Control Output CL=80pF. BUS Output CL= 150pF. 2. The f(t) assumes 50% duty cycle on XTAL) and XTAL2. The Max. Clock frequency is 11MHz. and the Min. Clock frequency is 1MHz. cuas-13

4.4 Absolute Maximum Ratings

‘TMP80C48AP-6/TMP80C35AP-6/TMP80C48AU-6 SYMBOL ITEM RATING Vcc Supply Voltage (with respect to GND (Vss) ) =0.5V to +7V Input Voltage (Except EA) =0.5V to Vec +0.5V Input Voltage (Only EA) -0.5V to 13V [Po __| Power Dissipation (Ta = 85°C) 250mW Soldering Temperature (Soldering Time 10 sec) 260°C Storage Temperature — 65°C to 150°C Operating Temperature = 40°C to 85°C 020389

4.5 DC Characteristics (I)

TMP80C48AP-6/TMP80C35AP-6/TMP80C48AU-6 . Topr= ~ 40°C to 85°C, Vec = + 5V + 10%, Vss = OV, unless otherwise noted SYMBOL PARAMETER TEST CONDITIONS [ san. | rye. | max. | ner | Input High Voltage via (Except XTAL1, XTAL2, RESET, PS) vec | Vv Input High Voltage 07 vin (XTAL), XTALa, RESET, PS) x Vee vec | V vou JOL=1.6ma oas | ov (Except P19-P17, P20-P27) VOL1 1OL=1.2mA Vv ‘Output High Voltage VOH11 24 v (Except Pio-P17, P20-P27) VOH12 JOH = - 400pA v (Pso-P7,P20-P27) a 08 vor | Output High Voltage [- [| VOH21 lO = - 50pa v (P0-P17,P20-P27) " Output High Voltage Vec= lv | VOH22 v (P10-P17, P20-P27) 08 Input Leak Current it Leak Cur SVINS + Input Leak Current = vine tu 5S, RESET) Vss= VINS Vee 50 BA Input Leak Current Vss + 0.45V5 VIN 12 ‘ -500} pA Output Leak Current (BUS, To) Vss + 0.45V5 VIN f + A Lo (High impedance condition) Vee aa Normal Vec=5V, Current VIH = Vcc -0.2V ICCH1 HALT Mode ViL=0.2V 25 370988 McU48-14

4.6 DC Characteristics (II)

TMP80C48AP-6/TMP80C35AP-6/TMP80C48AU-6 Topr = — 40°C to 85°C, Vcc = +5V + 20%, Vss = OV, unless otherwise noted Frm [rome [ese] we [vr [oe [ot] fimo Ye ae a Cs a Ce pow [eee fom [= |= [ows | pow lereatem, ome [ie] [- [+ fom [eee fone ee [ =P [= | fe fee ose [= = [ol fa ome = = EL | . = - Cm cn le Cm ul ele MCU48-15

TOSHIBA TMP80C48A/35A,

4.7 ACCharactristics

TMP80C48AP-6/TMP80C35AP-6/TMPBOC4BAU-6 . Topr = - 40°C to 85°C, Vcc = + 5V + 20%, Vss = OV, unless otherwise noted. SYMBOL PARAMETER TEST CONDITION (0) [sme UNIT [aan [| [x __[eeekreros inate? | amet? | vee | 000 | os _| [uc [ateravewat iat] aro | - | me _| Control Pulse Width Contro! Pulse Width Data Setup Time r a Se Data Hold Time juin ‘L = 20pF t-50 Data Hold Time (RD, PSEN) lesamr— [rstao] 0 | 20 | om | Data Input Read Time #8 P fosemel = foe | Data Input Read Time (PSEN) | favo = | m | Address Setup Time Address Setup Time Address Setup Time / ‘aoe (PSEN) | mem | - [me | | / Address Float Time Address Float Time ALE to Control Time ALE to Control Time Control to ALE Time Control to ALE Time o70%89 MCU48-16

AC Charactristics (Continue) . Topr = ~ 40°C to 85°C, Vcc = + 5V + 20%, Vss = OV, unless otherwise noted. SYMBOL PARAMETER TESTCONDITION | F(t) a Port Control Hold Time (PROG) | are pol - | | Port 2 Input Data Setup Time . fie | ‘PRoe) 8.5t~120 1290 t Port 2 Input Data Hold Time °F (PROG) Port 2 Output Data Setup . top [Time (PROG) s-280 | 710 Port 2 Output Data Hold Time - (PROG) | tetrte || - " Port 2/0 Data Setup Time . Port 2 /O Data Hold Time fre [in | oe Pel - ie | rors Note : 1. Control Output CL=80pF. BUS Output CL=150pF. 2. ‘The f(t) assumes 50% duty eycle on XTALy and XTAL2. ‘The Max, Clock frequency is 6MHz, and the Min, Clock frequency is MHz, MCcUA8-17

4.8 Timing Waveform

A. Instruction Fetch from External Program Memory tu tuarc2 i tear >| ALE } a PSEN [<—— tec2 tat [<> “4 tro | Ff *R 020969 B. Read from External Data Memory tact tear} ALE tarct — tro: >| >} [+ tor + tao. ———+| 020989 MCU48-18

C. Write into External Data Memory tLarct tears) fe ALE WR I tow >| |< two eM, 9 UU, Soke Ud, I taw —| 020909 D. Timing of port 2 during Expander Instruction Execution “ (f MK — PSEN I tev | tear >| | — Te Ix— top et} |.t20 PORT 2022 PORAR? XK rot OK POBARE DX cditlon KM oar |) te) | tec | ter = -— ter —" PROG = top —— 20909 MCU48-19

4.9 Stand-By Function

The operation of oscillation circuit is suspended by setting PS terminal to low level after RESET terminal has been set to low level. Consequently, all the data in RAM area can be held in low power consumption. ‘The minimum hold voltage of Vcc in this mode is 2V. PS terminal is set to high level to resume oscillation after Voc has been reset to 5V, and then RESET terminal is set to high level, thus, the normal mode is restarted from the initialize operation (address 0). (1) DC Characteristics TMP80C48AP/C35AP/C4BAU ‘TMP80C48AP-6/C35AP-6/C4BAU-6 :Topr = -40~85C, \\’ss=0V A Vec = 5V, VIH = Vee. 070988 (2) AC Characteristics TMP80C48AP/C35AP/C48AU 1 Vec = +5V + 10%, Vss = 0V TMP80C48AP-6/C35AP-6/C4BAU-6 i Vee = +5V #20%, Vsg = OV [tm [vechoustinew@g | i [is [veeseuptine@® fs PS | Note: tey=2.5ps (fxraL, = 6MHz) 020989 (3) Timing Waveform Vee RESET ti vs i Ps >t 1 tose =| tessr 020989 McU48-20

‘The operation of oscillation circuit is suspended by setting PS terminal to low level after SS terminal has been set to low level. Consequently, all data can be held in low power consumption. The minimum hold voltage of Vcc in this mode is 3V. PS terminal is set to high level to resume oscillation after Voc has been reset to 5V, and then SS terminal is set to high level, thus, the normal mode is restarted continuously form the state just before the power down mode (II). (1) DC Characteristics TMP80C48AP/C35AP/C4BAU TMP80C4BAP-6/C35AP-6/C48AU-6 : Topr= —40 to 85°C, Vss = OV Vcc = 5V, VIH = Veo o20989 (2) AC Characteristics TMP80C48AP/C35AP/C48AU : Vec= +5V 410%, Vsg=0V TMP80C48AP-6/C35AP-6/C48AU-6 2 Vee= +5V 420%, Vs =0V [recs [ rn [econ [ om [vm | wae [ow [trie [Powersuveseuprimess |__| we | - | | m= [xs Westie fds | Note: tey=2.5ps (fx'raL,=6MHz) o209a9 (3) Timing Waveform Vee I< ty — — tvs i Ps 20909 Mcu4s-21

4.9.3 HALT MODE

(1) HALT INSTRUCTION OP code is “01H”. HALT INSTRUCTION is an additional instruction to the standard 8048/8049 instruction set. (2) Entry to HALT MODE On the execution of HALT INSTRUCTION, TMP80C48A/TMP80C35A enter HALT MODE. (3) Status in HALT MODE The oscillator continues its operation, however, the internal clocks and internal logic values just prior to the execution of HALT INSTRUCTION are maintained. Power consumption in HALT MODE is less than 50% of normal operation. The status of each pins are described in the following table. (4) Release from HALT MODE HALT MODE is released by either of two signals (RESET, INT). (4.1) RESET Release Mode: An active RESET input signal causes the normal reset function. TMP80C48A/TMP80C35A start the program at address “000 H”. (4.2) INT ReleaseMode : An active INT input signal causes the normal operation. e In case of interrupt enable mode (EI MODE), TMP80C48A/TMP80C35A execute the interrupt service routine, after the execution of one instruction which is located at the next address after HALT INSTRUCTION. . In case of interrupt disable mode (DI MODE), TMP80C48A/TMPS80C35A execute normal operation from the next address after HALT INSTRUCTION. (5) Supply Voltage Range in HALT MODE ‘The operating supply voltage range and the operating temperature range are same as in normal operation. TMP80C48AP/C35AP/C48AU : Vec=5+10% TMP80C48AP-6/C35AP-6/C48AU-6 : Voc=5+20% MCuU48-22

4.9.4 Pin Status In Power Down Mode (!) (I!) | ewnance | STATUS DBo~DB7 Input abled Pio~Piz Input disabled High Impedance, input disable Output “High” level RESET, 5S Input disabled when oscillator is stopped. Pull-up transistors turn off, input disabled when oscillator is stopped. RD, WR, ALE Pron Sseh High Impedance cone

4.9.5 Pin Status In HALT MODE

DBo~DB7 Values prior to the execution of HALT INSTRUCTION are maintained Status prior to the execution of HALT INSTRUCTION is maintained. XTALi, XTAL2 Continue oscillation RESET, INT Input enabled SS, EA Input disabled RD, WR, igh" FRoe BEN Output “High” level cnanes Mcuas-23

TOSHIBA TMP80C48A/35A, 5. OSCILLATOR QUARTZ CRYSTAL f=IMHzto4MHz — :C1=C2=30pF XTAL f=4MHzto11MHz :C1=C2=20pF at 2 a CERAMIC RESONATOR 3 f=1MHzto3MHz — : C1 =C2= 100pF ° XTALp f=3MHzto11MHz =: C1 =C2= 30PF wo Gi 020989 6. TYPICAL CHARACTERISTICS Vec = 5V, Ta = 25°C, unless otherwise noted. Vec tot 1) (mA) 5 10 15 fxTai (MHz) 0 1 2 3 4 5 Vour (Vv) Vee-fimax. TYPICAL CURVE Vourt-lo, TYPICAL CURVE lec +0203 04 5 Your) ™ (| i || tt A . wl LA Ep ann 5 yy, -150 AC 7 rt i ty Zanes ow LL | | tT 5 10 15 fxtay (MHz) (ua) fxtacice TYPICAL CURVE Vout-lo TYPICAL CURVE (PORT 1, 2) 070989 MCU48-24

‘tres! (ims). + 20304 5 Your) vo [+--+ 4 || tt TA eh . 30. | | tet 1 | | Lyre] er 40 LA SCletotH => ann set TT TT 18 PTI 3ti-r] T Tr Try 20 He EE rT ELL Dor OG? OOF BOE OT OF OS Cyeser low QA (mA) Creset-treser TYPICAL CURVE Vout-lon TYPICAL CURVE (DB, CONTROL) ‘020989 7. OUTLINE DRAWING

7.1 Outline Drawing For TMP80C48AP/-6, TMP80C35AP/-6

(DIP: Dual Inline Package) DIP40-P-600 Unit: mm 10 a ; 7 20 3 WHA ID TOY SH |} \\ | z a I - * amy L rater _lloseos pesca S (250) eas Note: 1. This dimension is measured at the center of bending point of leads. 2. Each lead pitch is 2.54mm, and all the leads are located within £0.25mm from their theoritical positions with respect to No. 1 and No. 40 leads. MCU48-25

7.2 Outline Drawing For TMP80C48AU/-6

(Micro Flat Package) QFP44-P-1010A Unit: mm. 13.8403 10.002 | 33 23 s AI of s4eoff 2 = cS} 3| 2 “ = — a, UTEP TITTTT 1 " 1oTye, 03520! epee] oF 2 be . ( ogto2 270209 Notes: 1. ‘The above dimensions don’t include the burr of package and the residue of tie-bar cut. ‘The burr of package and the residue of tie-bar cut should be 0.15 mm (Max.) 2, Applied to the lead flat portion. MCU48-26

CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER (TLCS-48C) TMP80C49AP/TMP80C49AP- 6 TMP80C39AP /TMP80C39AP- 6 TMP80C49AU/TMP80C49AU-6 1. GENERAL DESCRIPTION AND FEATURES The TMP80C49A is a single chip microcomputer fabricated in Silicon Gate CMOS technology which provides internal 8-bit parallel architecture. The following basic architectural functions of a computer have been included in a single chip; an 8-bit CPU, 128x8 RAM data memory, 2K X8 ROM program memory, 27 I/O lines and an 8-bit timer/event counter. The TMP80C49A is particularly efficient as a controller. It has extensive bit handling capability as well as facilities for both binary and BCD arithmetic. The TMP80C39A/-6 is the equivalent of a TMP80C49A/-6 without ROM program memory on chip. By using this device with external EPROM or RAM, software debugging becomes easy. ‘The TMP80C49A P/-6 and TMP80C39AP/-6 are in a standard Dual Inline Package. ‘The TMP80C49A U/-6 is in a 44-pin Micro Flat Package. © — 'TMP80C49AP/TMP80C39AP/TMP80C49AU 1.36ps Instruction Cycle Time —40°C to 85°C, 5V 10% © — TMP80C49AP-6/TMP80C39AP-6/TMP80C49A U-6 2.5us Instruction Cycle Time —40°C to 85°C, 5V +20% © Software Upward Compatible with TMP8049AP/INTEL's 8049 © 2KxX8 masked ROM/128X8 RAM © Low Power 10mA MAX. in Normal Operation (Voc=5V, fyraL =6MHz) 10pA MAX. in Power Down Mode (Voc=5V, fxray : DC) © Power Down Mode (Stand-by Mode) © Halt Mode (Idle Mode) MCU48-27

PIN CONNECTIONS AND PIN FUNCTIONS

To G1 40 ff Vcc (+5V) XTAL: 92 3917 XTAL2 43 38 fi P27 RESET 4 37 Th P26 ss qs 36 fl Pas INT 6 35 f) Pag EA Q7 340 Paz RD Gs 33D Pre PSEN 9 32 fl Pas WR {10 310 Pra ALE 11 30) Pi3 DBo 4 12 29 Pr DB; 413 280 Pin DB. 14 27 f Pro DB3 415 26 1 PS DBs 16 25 | PROG OBs 417 24:1) P23 DBg 18 23 f) P22 DBy 419 22 fl Poy Vss 20 21D P29 oxo9ee Figure 2.1(1) DIP Pin Connections saeeu E bs ag ad zbkesee QOQO000000] HARARRRAR AH '33323130292827 26252823 D8, Cour} 36 225 RESET 08s rr}35 21H ne D8. Cor} 36 20fo xTALy 08; coo 37 19poDS xTAL; Vss Corr] 38 18ft To P29 Co 39 1755 Vee Pry Corr ao 16fo Ty Pee Cor at 15H Pay P23 Comm) 42 14FTI) Pog PROG corr} 43 13EE5 Pps ne ae CO) 12po=4 ne 123456789101 HARHRHHREHHAE UOUUUUUUU0U Recsesesess 0989 Figure 2.1(2) Micro Flat Package Pin Connections Mcu4s-28

° Vgg (Power Supply) Circuit GND potential ® — Voc (Power Supply) +5V during operation e = PS (Input) The control signal for the power saving at the power down mode (Active Low) © — PROG (Output) Output strobe for the TMP82C43P I/O expander. © — Pyo-Pz7 (Input/Output) Port 1 8-bit quasi-bidirectional port (Internal Pullup=50KQ). © — P29-P27 (Input/Output) Port 2 8-bit quasi-bidirectional port (Internal Pullup~50KQ). P2o-Pa3 contain the four high order program counter bits during an external program memory fetch and serve as a 4-bit I/O expander bus for the TMP82C43P. © — DBo-DB; (Input/Output, Tri-State) True bidirectional port which can be written or read synchronously using the RD, WR strobes. The port can also be statically latched. Contains the 8 low order program counter bits during an external program memory fetch, and receives the addressed instruction under the control of PSEN. Also contains the address and data during an external RAM data store instruction, under control of ALE, RD, and WR. ® — To (Input/Output) Input pin testable using the conditional transfer instructions JTO and JNTO. TO can be designated as a clock output using ENTO CLK instruction. © Ty (Input) Input pin testable using the JT1 and JNT1 instruction. Can be designated the event counter input using the timer/STRT CNT instruction. e — INTdnput) External interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is disabled after a reset. Also testable with conditional jump instruction. (Active low) McU48-29

TOSHIBA TMP80C49A/39A, e ~=RD (Output) Output strobe activated during a Bus read. Can be used to enable data onto the Bus from an external device. Used as a Read Strobe to External Data Memory (Active Low). © =WR (Output) Output strobe during a Bus write (Active Low). Used as a Write Strobe to External Data Memory. e RESET (Input) Active Low signal which is used to initialize the Processor. Also used during the power down mode. © ALE (Output) Address Latch Enable. This signal occurs once during each cycle and is useful asa clock output. The negative edge of ALE strobes address into external data and program memory. © — PSEN (Output) Program Store Enable. This output occurs only during a fetch to external program memory (Active Low). e 88 (Input) Single step input can be used in conjunction with ALE to “single step” processor through each instruction when SS is low the CPU is placed into a wait state after it has completed the instruction being executed. Also used during the power down mode. e EA (Input) External Access input which forces all program memory fetches to reference external memory. Useful for emulation and debug and essential for testing and program verification. (Active High) © = XTAL (Input) One side of crystal input for internal oscillator. Also input for external source. © = XTAL 2 (Input) Other side of crystal input. Mcu48-30

TOSHIBA TMP80C49A/39A, 2.3. Block Diagram DBp - By Pro~ Pay P29 - Par a4 FP] lo Tp ‘ beats LATCH tATCH tar = t *K x 8 INTERRUPT TIMER, AccuMU- | [ TeMPO- Lt fram aDoress wstRUC- REGISTER ACCUMULA REGISTER’ TIMER| 128 x 8 LS DECODER ry AAG \\ a / 7 CONDITIONAL To Ty __ INT POWER t Ft save, [py XTAL; XTAL2 RESET INT EA SS ALE PSEN RD WR PROG Se BE } Seu ] & 5 23 3%, £222 8 © 8. % Ze Seo “Se2 F <9 28 ig . He Bd Sesh 2 gE BE

32 Fd Fa g

= 040989 Note1: The lower order 4 bit of port 2 output latch are used also for input/output operations with the /O expander. Note2: The output latch of port 0 is also used for address output. Figure 2.3 Block Diagram . MCU48-31

MACHINE INSTRUCTION The following symbols and codes are used in the list of machine instruction. Rr Working register (0<r<7) Pp VO port address P; (0<p<7) JBb Branch instruction in accordance with bit content (b) of operand aH Higher order 3 bits of a alt Medium order 4 bits of a al Lower order 4 bits of a aM Medium order or lower order 8 bits of a (a) Content of a C(a)] Content of RAM addressed by a EXTE (a) J Content of external RAM addressed by a PROE (a) J Content of ROM addressed by a a<m> Value at bit position m of a asm:n> Value at bit position m ton ofa ach Store a into b asd Exchange a for b : Connection a 1 complement of a atb a plus b (Addition) a-b a minus b (Subtraction) aA Logical AND for a and b avd Logical OR for a and b avb Exclusive OR for a and b a=b aisequaltob ac aisnot equal tob (a) BCD Converted value of accumulator 20989 MCU48-32

List of TLCS-48 Machine Instruction (1/4) s Assembler (ist) Flag | com. | ae cae | _ Inemonic 1 ADD A, Rr [Oil0irrr [68+r__|(A)e(A)+(Rr), T=0-7 T ADD A ,@Rr 0110000r |60+r | (A)e(A)+[(Rr)} r=0,1 tI ¢ 1 ADD A Hi 00000011 | 03 |(A)e(A)+i tT 2 iisiiiii | ii ADOC AY Rr |O1itiere |78er | (Aje(A)+(Rr)+(c) r=0-7 tt i ADDC A ,@Rr |0111000r |70+r | (A)(A)+E (Rr) }+(c) rs0,1 Tt 1 ADDC A ,#i 00010011 | 13 |(A)+(A)+i+(c) It 2 diiitiii | ii AML A Rr” Joa0d ere [eser | (Aye(A) A(Rr) 0-7 1 ANL A .@Rr 0101000r |50+r | (A)e(A) AL(Rr)] 20,1 1 & [auc A ai 1010011 | 63) (A)e(A) Ai 2 = diiiiiii |i y fort A’, Rr” |01001err /48+r | (A)e(A) (Re) r=0~7 1 = Jor A @Rr |0100000r |ad+r” |(Aye(A) VE(Rr)] r0,1 1 & fort A wi 01000011 | 43°” |(Aye(A) yi 2 £ iiidaidi | ad xR A Re a d0L dere [baer | (Aye(A) V(r) 0-7 i Ss [xRL UA eRe | 42020007 pode” |(aye(ay ¥E(Rr)] r0,1 1 © YR Ai 11010011 | 03” | (A)e(A) Wi 2 2 qitiidii | it, 2 [INC a oooioiia | 47 | (aje(ay+i i 5 bec “A oooooii1 | 07 |(aye(a)-1 i oO YCLR OA ““lootooi1a1 | 27 | (Ajo i < feet A 0110111 | 37” | (AyenoT(A) 1 DAA 01010111 | 67 |(A)«(a)Bcd t 1 SWAP A oiooo1i1 | 47°” | (a)<7:4) (A)<3:09 1 REA i1i00121 | E7 | (A)<n#id (a) <nd 1 RLC OA i1i20it1 | FZ | (A)<n+i> €(Aa)<nd> t 1 (C)#(A)<7> (A)<0> #(C) n=0-6 RRA oritodii | 77° | (ayén> ¢(aysneid n=0~6 1 RRC A o1d0rii | 67° | (A)<n> ©(A)<n#4> tT 1 (C)#(A)<O> (A)<7> #(C) n=0~6 INA, Pp |000010pp |08+p |(A)+(Pp) P=1,2 2 OUTL Pp, A |001110pp |38+p |(Pp) (A) P=1,2 2 © JANL Pp, ai 100110pp |98+p | (Pp) <(Pp)At P=1,2 2 BS Witt | ii ORL Pp wi 100010pp |88+p | (Pp) «(Ppjvi Pei? 2 jiiiiiii ii 20989 McU48-33

List of TLCS-48 Machine Instruction (2/4) = Assembler (ist) Flag rs (2nd) Function Cycle 2] om Le ons INS A, BUS [00001000 | 08 _|(A)+(BUS) OUTL BUS, A” 00000010 | "02" | (BUS)+(AC) ANU BUS, #i 10011000 | 98” | (aUS)+(BUS) “Ai siiiitii | ii fo [ORE Bus. 4 10001000 | 8a | (BUS}«(aUS) Vi g Batti | ad . ~ |wovd “A, Pp |000011pp joc+p |(A)<3:0> «(Pp) p=4~7 sede 7 | (A)S7 24> 60 MOVO Pp, A” [O0Li1ipp |3C+p | (Pp) <(A)<3:0> p=4~7 ANLO' Pp, A [10011ipp |9C+p_ |(Pp) +(Pp)A(A)<3:0> p=4~7 : ORLD “Pp, A |100011pp |aCép _|(Pp) +(Pp)V(A)<3:0> _p=4~7 INC Re [000Airrr [i8+r | (Rr) #(Rr)+2 r=0~7 1 bec Rr 1i00irrr |C8er | (Rr) ¢(Rr)-1 r=0~7 1 oMP a aHo0100 [a4 |(PC)<10:0> «a 2 a ame | | (Pe) <a4>_ +(0BF) . JMPP eA io1100i1 | 83” | (PC)<7:0S«PROT(PC)<i1:8>°(A)] 27 OGNZ” Re, a /11401err Jestr” | (Re) *(Rr)-1 0-7 2 aml, 4f(Rr) *Othen(PC)<7:0>¢aML else no operation aca 1ii10i10 | FE” | it(C)=1 then(PC)<7:0>"aML 2 aml. else no operation § [otic a 11100110 [ES | iF(C)=0 then(PC)<7: 03am 2 pa aml. else no operation . g fora 11000110 [C6 )4#(A)=0 then(PC)<7:0>"aMtt 2 fe aM, else no operation % Yauz a 0010110 |” "96" fif(A)*0 then(PC)<7:0>¢aML 2 £ amt else no operation i. JTO a 00110110 36 if TO=1 then(PC)<7:0>¢aML 2 2 aM, else no operation & INTO a 00100110 | 26) if TO-0 then(PC)<7:0>¢aML 2 o aM else no operation oti a 1010110 |56” ]if Ti=1 then(PC)<7:03+aML 2 aMt, else no operation INTL a ““Yoio00ii0 46 if T1=0 then(PC)<7:0>*aML 2 aM else no operation jf a Loiioiio | a6 | iF FO=1 then(PC)<7:0>¢aML 2 aM else no operation fia 01110110 | 76 | if Fi=1 then(PC)<7:0>eaML 2 aM else no operation JTF a 00010110 | 16 | iF TR=1 then(PC)<7:0>eaML 2 amt. else_no operation 070989 (1) = Register instruction MCU48-34

List of TLCS-48 Machine Instruction (3/4) s Assembler (ist) Flag fa . 2nd) Function Cycle Ef co ors WNT a 10000110 | 86 | if INT =0 then(PC)<7:0>aML . aM. else no operation (2) [a8 a bbbi0010 |b+i2” | iF (A)<b>=1 then aML (PC)<7:0>¢aML else no operation b=0~7 CALL a aHi0100 | aH+a4 | [(SP)] +(PSW)<7:4>-(PC) aM (SP) ¢(SP)+1 (PC)<10:0> a . . (PC)<11> (DBF) (PC) #[(SP)]<11:0> RETR 10010011 93 |(SP)+(SP)-1 Tr (PC) #[(SP)]<11:0> cur C qooiiii | 97 | (C)eo 1 ce toro0tt | az | (C)ewor(c) 1 cpl FO }iooi0101 | 95] (FO) “«noT(Fo) 1 ciR Fi 10100101 | "AS (F1) <0 i cet Ft ioi10101 |" Bs” |” (F1) “+NoT(F1) 1 MOV A, Rr [aitiirer [reer | (A)e(Rr) r=0-7 1 MoV A@Rr fait a000r [Fore | (A)eE(Rr)] r01 | i Mov A Hi ooioo011 | 23° |(a) «i 2 Vitti ii [NOV Rr, A” |t0t0Irre |ABer | (Rr)e(A) r=0~7 1 © |MOV eRr, A 1010000r |AO+r | [ (Rr) J-(A) 10,1 1 = [MOV Rr wi ilirre |B8+r | (Rr)ei 10-7 2 y ditiitii | ai = MOV @Rr,#i 1011000r |BO+r C(Rr) Jei r=0,1 2 ” qiisii7i ii = |wov ~a,Psw”|ano00na1 | c7 | (a) <(Psw) 1 » |MOV PSW,A [42010111 | p7” | (PSW) <(A) 1 3 ]xCH ALR O0L0ierr |28+r | (A) (Rr) r0~7 1 = |xcH “A,@Rr ~Jooi0000r |20+r |(A) [(Rr)} 20,2 1 XCHD A,@Rr 0011000r |30+r (A)<3:0>e+[(Rr)<3:0>] r=0,1 1 MOVX ” @Rr,A 3001000r |90+r | EXTE(Rr)] #(A) r20,1 1 MOVX A,@Rr i000000r |80+r | (A) “EXTE(Rr)] 0,1 1 MOVP A, GA 10100011 | 3” | (A) ¢PRO[(PC)<11:8>- (A) ] 1 MOVP3_A,@A iinoo0i1 | €3_ | (A) +PRO[(PC)<11>-011-(A) i (2) ~~ Branch instruction (3) Subroutine Instruction e098 (4) + Flag Instruction MCU48-35

List of TLCS-48 Machine Instruction (4/4) Object Code = Assembler (ist) Flag fa (and) Function cyde 7 {_ Meemenis [tin [hex | an _ [NOV AST 1000010 | 42_|(A)_(iR) < |strr 7 01010101 |~55° "Start Timer S o FstRT CNT 1000101 |" ~45” Start Counter £ |stop tent /oit00101 | 66” {Stop Timer/Counter i JEN Tenti 00100101 || 25° |Enable Timer/Counter interrupt ois tentT Ooi10101 | 36” [Disable Timer/Counter Interrupt EN I 0000101 | 05 [Enable External Interrupt 1 dist ~~ foooi0i01 }"" 16" |disabie External Interrupt 1 > Set Reo” "11000101 | cs | (BS)« 0 1 S SEL.” RB1 11010101 | D5 |(BS)+ 1 1 < {SEL MBO 1itoo101 | &5” | (0BF) « 0 1 S& [sec wea 41110101 |" FS |(OBF) <1 1 ENTO CLK 01110101 | 78" /Enable Clock Output on To 1 HALT 00000001 o1 Halt 1 Lis) [nop [00000000 | 00” [no operation (5) = Other 920989 MCU48-36

TOSHIBA TMP80C49A/39A, 4. ELECTRICAL CHARACTERISTICS Vcc Supply Voltage (with respect to GND (VSS)) Soldering Temperature (Soldering Time 10 sec) Storage Temperature = 65°C to 150°C Operating Temperature = 40°C to 85°C owo309

4.2 DCCharacteristics

TMP80C49AP/C39AP/C49AU . Topr = - 40°C to 85°C, VCC = +5V + 10%, Vss = OV, unless otherwise noted. SYMBOL PARAMETER TESTCONDITIONS | MIN. | TyP. | MAX. | UNIT | he __ vib Except XTALs, XTAL2, RESED os] — | oa | v [ver | Beara ASE |v | vit XTAL, XTALz, RESET) os} = | o6 |v vis Except XTAL}, XTALz, RESET, PS 2.2 vec | OV vik} XTALs, XTAL2, RESET, PS) Vee] = | vee |v Output Low Voltage 7 Vout Pup Ph Voltage IOH = ~1.6mA 2a | | v Vou12 Except Pa-P47, Paa-P. !OH = ~400nA 0.8 v voxa21 Qutput High JOH = - 50a 24 v Output High Voltage . Vee VOH22 Pay Py PoP. IOH = -25pA 8 v Input Leak Current =ye _ tT INT, EA, PS Vss=VinsVec | | t10 | pa | Input Leak Current =Vin= jue | Output Leak Current Vss +0.45V= Vin _ ~ We P1o-Py7, Pao-P, =v, mT 500 | wa | Jio | Output Leak Current (BUS, To) Vss + 0.45V= Vin [va | ito High impedace condition: =V. | = | = | +1 | va Normal Vec=5V, = tec1 Vcc Supply operation fra SMe 10 | =Vec — _ ICCHT Current HALT Mode | Wit ao59 25 Normal Vee = 5V, — Vee Supply c= tiMig ma e903 MCU48-37.

TOSHIBA TMP80C49A/39A, TMP80C49AP/C39AP/C49AU . Topr = ~ 40°C to 85°C, Vcc = +5V + 10%, Vss = OV, unless otherwise noted. SYMBOL PARAMETER TESTCONDITION | f(t) [ume | UNIT [an [wa Control Pulse Width (RD, WA) a ee i Control Pulse Width cco (PSEN) Data Setup Time Data Hold Time He = 20pF ces aoe [ee] ol] - fo | Data Hold Time . jm | (RD, PSEN) cr 20°F sex] a | ve | oo | Data Input Read Time feo | (RD) ad " Data Input Read Time troz (SER) 240 ns Address Setup Time taw we) 5t-150 | 300 ns Address Setup Time tao (RD) 10t- 170 730 ns ‘Address Setup Time ‘Address Float Time . (RO, WR) ae Ll - | " Address Float Time . (PSEN) crs 20PF ost 40 Fels) | ALE to Control Time ALE to Control Time i fase pga est | | Control to ALE Time (RD, WR, PROG) ee ee Control to ALE Time (PSEN) i pace fae] = | om | 000989 MCU48-38

AC Charactrstics (Continue) , Topr = — 40°C to 85°C, Vcc = + 5V + 10%, Vss = OV, unless otherwise noted. SYMBOL PARAMETER TEST CONDITION f(t) [mee UNIT Port Control Setup Time . FE Ge meee Le] - || Port Control Hold Time fm [rss a7 po f-fim | Port 2 Input Data Setup Time _ ter PROG) 8.5t-120 Port 2 Input Data Hold Time Port 2 Output Data Setup Time . top PROG) 6t-290 | 250 Port 2 Output Data Hold Time _ i [eaagpronstecrine | ress pel -[ | n Port 2/0 Data Setup Time Pe (ALE) [ier —lewerme ie se 010969 Note: 1. Control Output CL=80pF. BUS Output CL=150pF. 2. The f(t) assumes 50% duty cycle on XTAL) and XTALg. ‘The Max. Clock frequency is 11MHz. and the Min. Clock frequency is IMHz. MCU48-39

TMP80C49AP-6/TMP80C39AP-6/TMPB0C49AU-6 SYMBOL TEM RATTING Vec Supply Voltage (with respect to GND (Vss)) =0.5Vto +7V input Voltage (Except EA) =0.5V to VCC + 0.5V [Po __| _ Power Dissipation (Ta = 85°C) 250mW Soldering Temperature (Soldering Time 10 sec) Storage Temperature = 65°C to 150°C Operating Temperature = 40°C to 85°C owes TMP80C49AP-6/TMP80C39AP-6/TMPB0C49AU-6 - Topr = - 40°C to 85°C, Vcc = + 5V + 10%, Vss = OV, unless otherwise noted SYMBOL PARAMETER TEST CONDITIONS | MIN. | TyP. [| MAX. | UNIT input High Voltage — vid (Except XTAL;, XTAL2, RESET, PS) 22 Vec | Vv Input High Voltage O7 vit (XTAL), XTALa, RESET, PS) xVec Vec | Vv Output Low Voltage . vou (Except Pi0-Pi7, P20-P27) 1OL= 1.6mA v Output Low Voltage 7 vou Pane Lew pol 1OL=1.2ma v Output High Voltage __ VOHI1 | except PrP 7, PaoP27) lOH=-1.6ma | 24 v Output High Voltage __ Vee. voui2 | Gurrut High vor 1oH=-400pa | VEC, v Output High Voltage __ vor21 | Qutput High Vor JOH = - S0pa 24 v Output High Voltage __ Vee VOH22 | (Pig:Pi7,P20-P27) 1OH= ~25HA 08 v Input Leak Current < iu LGRAINT Bass) Vos Vin = Vee. #10 | vA | Input Leak Current - = a Gs, RESET) Vss= Vin Vec | - | =50 | BA Input Leak Current Vss + 0.45V5 Vin _ We (10-17, P20-P27) _| vce 500 | BA Output Leak Current (BUS, To) Vss + 0.45V= Vin 1Lo (High impedance condition) =Vec z10 | pA cca y cc = 5V, 10 Vcc Supply operation fxtat = 6MHz mA | Current VIH = Vee - 0.20 ict | Hatt Mode | VIt= Yee 25 10589 mcuas-40

TMP80C49AP-6/TMP80C39AP-6/TMPBOC49AU-6 , Topr = ~ 40°C to 85°C, Vec = +5V # 20%, Vss = OV, unless otherwise noted SYMBOL PARAMETER TEST CONDITIONS UNIT 0.15% vit Input Low Voltage Vv fm frwntowvorase vos f= |v Input High Voltage 05x a Me Vv viH {Except XTAL1, XTAL2, RESET, PS) Vee sc Input High Voltage 07x a Vv viKt (XTAL, XTALz, RESET, P3) Vee vec ‘Output Low Voltage 1OL=1.6mA 0.45 v vou (Except Pio-P17, P20-P27) ™ ‘Output Low Voltage 1OL=1.2mA 0.45 Vv VOLT [t@10-P17,P2o-Pa0) ors tam ‘Output High Voltage Vee = =- Vv VOH12 (Except P19-P17, P2o-P27) 10H 400pA 08 ‘Output High Voltage Vee I-|- |] VOH22 1OH = ~ 25pA Vv Input Leak Current <VN + tu (11, INT, EA, PS) ss VINS Voc #10 input Leak Current Esra ut ESE) Vss VINS Vcc == — iA we (P10-P17, P2o-P27) SV oor | Output Leak Current (BUS, To) Vss +0.45V5 VIN £10 'to {High impedance condition) SV * tee Normal Vec = 5V,, operation | fyrar=6MHz Vec Supply Current vil Vce-0.2V HALT Mode Vit = 0.2V i- [= [| coe mcuas-41

‘TMP80C49AP-6/TMP80C39AP-6/TMP80C49AU-6 . Topr = — 40°C to 85°C, Vcc = + 5V t 20%, Vss = OV, unless otherwise noted. SEMBOL PARAMETER TEST f(y) |__smre__| UNIT Control Pulse Width an - 1 Control Pulse Width (PSEN) | seme | ow |= fm Data Setup Time _ Data Hold Time ty CL =20pF t-50 Data Hold Time = (RD,PSEN) fest [ren | 0 | 0 | om | Data Input Read Time . Data Input Read Time Address Setup Time _ taw (WR) 5t-150 680 ns Address Setup Time _ a eee Address Setup Time 7t=171 tor | (SEN) ° Address Float Time . . (RD, WR) ce 20PF [0 |e] - |» | Address Float Time . _ (PSEN) CL = 20pF O.st-40 40 Al Ti i ALE to Control Time Control to ALE Time (RD,WR,PROG) fee [wf [| Control to ALE Time 0889 mcuas-42

AC Charactristics (Continue) , Topr= —40°C to 85°C, Vcc = +5V t 10%, Vss = OV, unless otherwise noted. SYMBOL PARAMETER TEST CONDITION f(t) UNIT [ao [wa | Port Control Setup Time _ fo [coer [| terre | | | * Port Control Hold Time jm [rsogenerrrr f| “7% pol - [| Port 2 Input Data Setup Time _ ter (PROG) 8.5t-120 Port 2 Input Data Hold Time Port 2 Output Data Setup top Time (PROG) 6t-290 | 710 ns Port 2 Output Data Hold Time [vo [oracereonsteerine| | eee elf | r Port 2 1/0 Data Setup Time ia (ALE) Port 2/0 Data Hold Time fur [ixgroorstorme [| one pf - | | fier —owetine iP i isp es Po | (040989 Note : 1. Control Output CL=80pF. BUS Output CL=150pF. 2. The f(t) assumes 50% duty cycle on XTAL; and XTAL2. ‘The Max. Clock frequency is MHz, and the Min. Clock frequency is 1MHz. MCU48-43

A. Instruction Fetch from External Program Memory tu | fp teaser tar >| ALE } PSEN I-— tec2 | tat [> “ tor | tf OR I tap2 >} 10989 B. Read from External Data Memory tlarci toate} hE ALE ——— tan | 040909 MCU48-44

C. Write into External Data Memotry tLarct tcai+| l<— ALE wr Toe tl Le to (ADDR 4 D. Timing of Port 2 during Expandar Instruction Execution “ a PSEN -—— TOS top 21) |.teo te "| te ter — MCU48-45

4.9.1 PoweR Down Mode (I) ----- Data Hold Mode in RAM

The operation of oscillation circuit is suspended by setting PS terminal to low level after RESET terminal has been set to low level. Consequently, all the data in RAM area can be held in low power consumption. The minimum hold voltage of Vcc in this mode is 2V. PS terminal is set to high level to resume oscillation after Vcc has been reset to 5V, and then RESET terminal is set to high level, thus, the normal mode is restarted from the initialize operation (address 0). (1) DC Characteristics TMP80C49AP/C39AP/C49AU TMP80C49AP-6/C39AP-6/C49AU-6 : Topr = - 40°C to 85°C, Vss = 0V Freee vssirs—[vsrcoonon [om [vr [ne [or Vec=5V, VIH = Vcc [a iewcomn Paar] = [ee] » [| 010989 (2) AC Characteristics TMP80C49AP/C39AP/C49AU Vcc = +5V t 10%, Vs5 = 0V TMP80C49AP-6/C39AP-6/C50AU-6 Vee = +5V 420%, Veg = OV [sn _[PowersoveseTine ese | fo | | — | me | [im Wvecnowrtnews Sd | Lv |vecseuptines | ids |] = P= Note: toy =2.5ns (fxraL = 6MH2) 010909 (3) Timing Waveform Vee RESET a vs PS — |= trsur + trssr 040989 MCU48-46

4.9.2 Power Down Mode (II) «+s ALL Data Hold Mode

‘The operation of oscillation circuit is suspended by setting PS terminal to low level after SS terminal has been set to low level. Consequently, all data can be held in low power consumption. The minimum hold voltage of Vcc in this mode is 3V. PS terminal is set to high level to resume oscillation after Voc has been reset to 5V, and then SS terminal is set to high level, thus, the normal mode is restarted continuously from the state just before the power down mode (ID). (1) AC Characteristics TMP80C49AP/C39AP/C49AU TMP80C49AP-6/C39AP-6/C49AU-6, : Topr = — 40°C to 85°C, Vsg = OV Fru | vreowron [wm [vw [wm [or [i fnens— SRREE| — [oe ® Po 020989 (2) AC Characteristics TMP80C49AP/C39AP/C49AU :Vec= +5V +10%, Vss =0V TMP80C49AP-6/C39AP-6/C49AU-6 :Vec= +5V 20%, Vss = 0V Fama [ rs [con [wm [vr [| [im Nectarine) Ps | [ous —veeseuptimeoy | ss PP Lo Note : tcy =2.5ps (fx TAL = 6MHz) omses (3) Timing Waveform Vee i<— tvn ™ — tvs SS PS | He tosis Kk trsss 040989 MCU48-47

(1) HALT INSTRUCTION OP code is “01H”. HALT INSTRUCTION is an additional instruction to the standard - 8048/8049 instruction set. (2) Entry to HALT MODE On the execution of HALT INSTRUCTION, TMP80C49A/TMP80C39A enter HALT MODE. (3) Status in HALT MODE The oscillator continues its operation, however, the internal clocks and internal logic values just prior to the execution of HALT INSTRUCTION are maintained. Power consumption in HALT MODE is less than 50% of normal operation. The status of each pins are described in the following table. (4) Release from HALT MODE HALT MODE is released by either of two signals (RESET, INT). (4.1) RESET Release Mode : Anactive RESET input signal causes the normal reset function. TMP80C49A/TMP80C39A start the program at address “O00H”. (4.2) INT Release Mode : An active INT input signal causes the normal operation. e. In case of interrupt enable mode (EI MODE), TMP80C49A/TMP80C39A execute the interrupt service routine, after the execution of one instruction which is located at the next address after HALT INSTRUCTION. e In case of interrupt disable mode (DI MODE), TMP80C49A/TMP80C39A execute normal operation from the next address after HALT INSTRUCTION. (5) Supply Voltage Range in HALT MODE . The operating supply voltage range and the operating temperature range are same as in normal operation. TMP80C49AP/C39AP/C49AU : Veo=5V+10% TMP80C49AP-6/C39AP-6/C49AU-6 > Voco=5V+20% MCU48-48

4.9.4 Pin Status in Power Down Mode (!) (I!) PIN NAME STATUS DBo~DB7 Ingutdisabled Pio~ Pir Input disabled High impedance, input disabled Input disabled XTALY High impedance XTAL2 Output “High” Level RESET, SS Input disabled when oscillator is stopped. Pull-up transistors turn off. INT, EA Input disabled when oscilltor is stopped RD, WR, ALE . prog, SEN |Highimpedance 040909 Values prior to the execution of HALT INSTRUCTION are maintained. Status prior to the execution of HALT INSTRUCTION is maintained. Input disabled RESET, INT Input enabled PROG. PSEN | OUtPUt "High" level Output "Low" level rer) MCU48-49

OSCILLATOR QUARTZ CRYSTAL f=IMHzto 4MHz :C1=C2=30pF XTALL fs4MHzto11MHz :C1=C2=20pF at 2 a CERAMIC RESONATOR 3 f= IMHzto 3MHz — : C1=C2=100pF o XTAL f=3MHzto11MHz : C1 =C2= 30PF > 7 osose9 6. TYPICAL CHARACTERISTICS : Vee = 5V,Ta = 25°C, unless Otherwise noted. Vee lou Ww) (mA) 5 10°15 fxTaL (MHz) 0 1 2 3 4 5 Vour (Vv) Vee ~ fax. TYPICAL CURVE Vout - fot TYPICAL CURVE lec 1 2 3 4 5 Your) “ Pt] | [| ty Ay . wot LE | | | ~ ow LL | TTT 5 10 15 fxra(MHz) (ua) fxtat- icc TYPICAL CURVE Vout—lon TYPICAL CURVE (PORT 1, 2) 00989 MCU48-50

(ms) +0203. 4 5 Your) eg 6 | ds ai ; sot} | | Teri | . 2 ft | oe -10 wt Le EL TT oft TT TT 1 ste" tT T TTT se rs a | -20 Li | | tT tty 0.01 0.02 003 0.06 01 02 03 Caeser lon GF) (ma) Creser~treser TYPICAL CURVE Vout—lon TYPICAL CURVE (DB, CONTROL) 040989 7. OUTLINE DRAWING

7.1 Outline Drawing For TMP80C49AP/-6,TMP80C39AP/-6

(DIP:Dual Inline Package) DIP40-P-600 Unit : mm 40 2 4 7 20 8 50,7202 | aaron CS Bt WOT TO OY st) m zt ES sine 5: ° ares Note: 1. This dimension is measured at the center of bending point of leads. 2, Each lead pitch is 2.54mm, and all the leads are located within +0.25mm from their theoritieal positions with respect to No.1 and No.40 leads. MCU48-51

7.2 Outline Drawing For TMP80C49AU/-6

(Micro Flat Package) QFP44-P-1010A

138403 Unit: mm

| 33 23. ¢ LILLIA — Lo2 = FS sa ta = Mt a P g | ( __) Note: 1, The above dimensions don’t include the burr of package and the residue of tie-bar cut. The burr of package and the residure of tie-bar cut should be 0.15 mm (Max.). 2. Applied ti the lead flat porttion. MCU48-52

TOSHIBA TMP80C50A/40A, CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER (TLCS-48C) TMP80CS5SOAP/TMP80CS0AP- 6 TMP80C40AP /TMP80C40AP- 6 TMP80C50AU/TMP80C50AU-6 1. GENERAL DESCRIPTION AND FEATURES The TMP80C50A is a single chip microcomputer fabricated in Silicon Gate CMOS technology which provides internal 8-bit parallel architecture. The following basic architectural functions of a computer have been included in a single chip; an 8-bit CPU, 2568 RAM data memory, 4K X8 ROM program memory, 27 I/O lines and an 8-bit timer/event counter. The TMP80C50A is particularly efficient as a controller. It has extensive bit handling capability as well as facilities for both binary and BCD arithmetic. The TMP80C40A/-6 is the equivalent of a TMP80C50A/-6 without ROM program memory on chip. By using this device with external EPROM or RAM, software debugging becomes easy. The TMP80C50AP/-6 and TMP80C40AP/-6 are in a standard Dual Inline Package. The TMP80C50A U/-6 is in a 44-pin Micro Flat Package. e TMP80C50A P/TMP80C40A P/TMP80C50A U 1.36ps Instruction Cycle Time — 40°C to 85°C, 5V £10% @ — TMP80C50AP-6/TMP80C40A P-6/TMP80C50AU-6 2.5ps Instruction Cycle Time —40°C to 85°C, 5V £20% . Software Upward Compatible with TMP8049A P/INTEL's 8049. e 4K X8 masked ROM / 256 x8 RAM . Low Power 10mA MAX. in Normal Operation(Vgc=5V, fx raL=6MHz) 10pA MAX. in Power Down Mode (Voc=5V, fyraL: DC) e Power Down Mode (Stand-by Mode) . Halt Mode (Idle Mode) MCU48-53

PIN CONNECTIONS AND PIN FUNCTIONS

To G1 40 0 Vcc(+5V) XTAL; 42 397 XTAL2 43 38D P27 RESET 4 37D P26 SSq5 36 fi Pas INT 16 35 11 Pag Ea 7 340 Piz RO de 33 f Pig PSEN 9 320 Pis WR (10 310 Pig ALE 11 301 P13 DBo 12 29 fl Piz DB; 413 28 fl Pit Bz (14 27 f Pio DB3 415 26 p PS DB, 416 25 [| PROG DBs 417 24 1) P23 Be 18 23 1 P22 DB7 419 220 Par Vss 420 21D P20 000589 Figure 2.1(1) DIP Pin Connections eeu cf aad zbke sk qNoAngnpone 33323130292827 26252423 08. oo 34 22fc RESET D8; Cm35 2i fre Ne DB, C1136 20f xTAL; 08, C437 igfor xTaL, Vss Carr] 38 teh Tp P29 C0 39 173 Vee Poy Com a0 6b Ty Poo Cour at 1sfo Pay Po; Com}a2 14 Pog PROG Cour) 43 13Fo Pg NC Comfaa 12fo3 NC ie) 123456789101 HABRHHAHHHHH DOGUCUUUUU wecsedezesd 40989 Figure 2.1(2) Micro Flat Package Pin Connections MCU48-54

° Vgg (Power Supply) Circuit GND potential © — Vcc (Power Supply) +5V during operation © PS (Input) The control signal for the power saving at the power down mode (Active Low) © PROG (Output) Output strobe for the TMP82C43P I/O expander. © — Pyo-Py7 (Input/Output) Port1 8-bit quasi-bidirectional port (Internal Pullup=50KQ). © — Po9-Po7 (Input/Output) Port2 8-bit quasi-bidirectional port (Internal Pullup=50KQ). Po9-Pog contain the four high order program counter bits during an external program memory fetch and serve as a 4-bit I/O expander bus for the TaiP82C43P. . DBo-DBz (Input/Output, Tri-State) ‘True bidirectional port which can be written or read synchronously using the RD, WR strobes. The port can also be statically latched. Contains the 8 low order program counter bits during an external program memory fetch, and receives the addressed instruction under the control of PSEN. Also contains the address and data during an external RAM data store instruction, under control of ALE, RD, and WR. © — To (Input/Output) Input pin testable using the conditional transfer instructions JT0 and JNTO. To can be designated as a clock output using ENTO CLK instruction. © 1, (Input) Input pin testable using the JT1 and JNT! instruction. Can be designated the event counter input using the timer/STRT CNT instruction. e — INT (Input) External interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is disabled after a reset. Also testable with conditional jump instruction. (Active low) MCU48-55.

e ~=RD (Output) Output strobe activated during a Bus read. Can be used to enable data onto the Bus from an external device. Used as a Read Strole to External Data Memory (Active Low). e =WR(Output) Output strobe during a Bus write (Active Low). Used as a Write Strobe to External Data Memory. ¢ RESET (Input) Active Low signal which is used to initialize the Processor. Also used during the power down mode. © ALE (Output) Address Latch Enable. This signal occurs once during each cycle and is useful as aclock output. The negative edge of ALE strobes address into external data and program memory. © — PSEN (Output) Program Store Enable. This output occurs only during a fetch to external program memory (Active Low). e = $8 (Input) Single step input can be used in conjunction with ALE to “single step” processor through each instruction when 5S is low the CPU is placed into a wait state after it has completed the instruction being executed. Also used during the power down mode. ° EA (Input) External Access input which forces all program memory fetches to reference external memory. Useful for emulation and debug and essential for testing and program verification. (Active High) e@ = XTAL ; (Input) One side of crystal input for internal oscillator. Also input for external source. © = XTAL 2 (Input) Other side of crystal input. MCU48-56

2.3 Block Diagram

frat =) LATOR RARY REG FlaGs tak TOR LATCH pi \\4 a ACCUMULATOR To 7) _ INT power tt ot XTAL; XTAL) RESET INT EA 3S ALE = PSEN RD «WR PROG tot ft tl ht t SO kok 2 aw se 2 ag 3% #- Sie $3 2 ow Pi 2 €. 05 & 258 88 eo 2o se — #2 £65 wu ze GE £2 so ge FE GRR g Sh ee BR Sh Ze a < 2 o~ = a on0989 Note 1: The lower order 4 bit of port 2 output latch are used also for input/output operations with the /O expander. Note 2: The output latch of port 0 is also used for address output. Figure 2.3 Block Diagram MCU48-57

MACHINE INSTRUCTION The following symbols and codes are used in the list of machine instruction. Re Working register (0<r<7) Pp VO port address P; (0<p<7) Bb Branch instruction in accordance with bit content (b) of operand alt Higher order 3 bits of a aM Medium order 4 bits of a al Lower order 4 bits of a aML Medium order or lower order 8 bits of a (a) Contentofa Ca) J Content of RAM addressed by a EXTE (a) J Content of external RAM addressed by a PROE (a) J Content of ROM addressed by a a<m> Value at bit position m of a a<m:n> Value at bit position m ton ofa arb Store a into b ach Exchange a for b : Connection a 1. complement of a arb aplusb (Addition) a-b a minus b (Subtraction) ab Logical AND for a and b ayo Logical OR for aand b aVb Exclusive OR for a and b a=b ais equal tob ag>b ais not equal to b (a) BCD Converted value of accumulator 020989 MCU48-58

List of TLCS-48 Machine Instruction (1/4) = | assembler Flag fd ; (2nd) Function cac | OP 5 Mnemonic Tsin | Hex | . ‘ADD A, Rr [Oli0irrr |68+r | (A)*(A)+(Rr) T=0~7 T ADD A ,@Rr 0110000r |60+r | (A)#(A)+[(Rr)] r=0,1 tT { 1 ADA wi Goo0d011 | 03] (A)e(A) +i t 2 Viitiiti ii ADOC A Re) OLi Lire [7aer | (A)e(A)+(Rr)+(c)r=0~7 Tp a ADDC A ,@Rr 0111000r [70+r | (A)<(A)+[(Rr) J+(c) r=0,1 It 1 ADDC A ,#i 00010011 13 | (A)#(A)+i+(c) tt 2 iitititi | it ; ANL A, Re /O10tirre |58+r | (A)e(A) AC Rr) r=0~7 1 ANL A ,@Rr 0101000r |50+r |(A)«(A) AL(Rr)] 20,1 1 S fan A wi 01010011 | 63° |(A)ye(A) AG 2 z siiitiit | ii . y JORL” A, Re Jo1001rrr |a+r | (A)e(A) v(Rr) r=0~7 1 = fort” A ,@Rr Jo100000r |ao+r | (A)e(A) VE(Rr)] t=0,1 1 % oR A wi oiooo011 | 43 | (A)e(A) Vi 2 £ itiisitt |i XRU A Re fad0rtere [oBer |(A)e(A) V( Re) r20~7 1 5 ]xRU A eRe) at01000r. |ooer | (A)e(A) WE(Rr) J. r=0,1 1 2 [KRU A Ai 11010011 | 03” | (A)e(A) Vi 2 < iiiiiiti | ii 2 [ic A 0010111 | 17° | (Aje(A)+a 1 5 |bEC A Ooo0o1ii | 07 | (A)e(A)=1 i o YClR OA 00100111 | 27 |(A)+o ° L < Jepu A Joodtoiaa | 37 | (ayenior(a) 1 DAA 01010111 | 67° | (A)ye(a)aco t “a1 SWAP A iooo111 | 47 | (A)<7:4> <(A)<3:0> 1 RLC OA 11110111 F7 |(A)<n#1> €(A)<n> t 1 (C)#(A)<7> (A)<0> ©(C) n=0~6 RRA o1iioii1 | 77° |(A)<n> #(A)<n+1> n=0~6 1 (A)<7 €(A)<0> RRC A oaiddiii | 67 | (A)<m> «(A)cn+id t 1 (C)*(A)<0> INA, Pp |000010pp [08+p |(A)+(Pp) P=1,2 2 OUTL Pp, A O0i1710pp |38+p |(Pp) <(A) P=4,2 2 © JANL” Pp. #i 00i10pp |98+p | (Pp) «(Pp)Ai P12 2 x iiiiditi | aii | ORL Pp. wi 100010pp |88+p |(Pp) «(Pp)vi Pe1,2 2 jiitiiii ii 020989 McU48-59

TOSHIBA TMPB9C50A/40A, List of TLCS-48 Machine Instruction (2/4) = Assembler (ist) Flag fa (2nd) Function cycle INS A, BUS [00001000 | 08 _|(A)«(BUS) 2 OUTL BUS, A” [00000010 | G2) (BUS) (AC) 2 ANL™ BUS, #i 10611000 |" 98 "| (BUS)«(BUS) Ai 2 aititiii | i ORL BUS Hi i0001000| 88 | (BUs)+(BUS) Vi 2 x iiiiiiii |i . ~ wovo"“A™, Pp" /000011pp Joc+p }(A)<3:0 «(Pp) p=4-7 2 (A)<7:4> 0 . MOVO Pp, A [O0ii1ipp [3C+p|(Pp) «(A)<3:0 p=4-7 2 ANLO Pp, A 100111pp [9C+p_|(Pp) «(Pp)A(A)<3:09_p=4-7 2 ORLD Pp, A 100011pp |8Ctp | (Pp) +(Pp)V(A)<3:0> _ p=4~7 2 INC Rr O001irre [Ber |(Rr) €(Rr)+1 r=0~7 (1) JING” @Rr 0001000r |1o+r |[(Rr)] <[(Rr) +2 r=0,1 DEC Rr 1100irre [Caer | (Rr) ¢(Rr)-1 r=0~7 OMP a aH00100 [ata | (PC)<10:0> «a 2 aML (PC)<11> (DBF) NPP GA Yoii0di1 | BS” | (PC)<7: Ode PROE (PC)<A1:85- (Ajj 2 DINZ Re a adder fEser | (Rr) @(Re)=1 0-7 2 aML if (Rr) *O0then(PC)<7:0>¢aML else no operation Joa Litioiio | Fe”) i#(C)=1 then(PC)<7:0><ani 2 aML else no operation & onc iiooiio | ES] 1F(C)=0 then( PC) <7: 0>eant. 2 = nu aML. else no operation gy fora 11000110 |” C6 |i#(A)=0 then(PC)<7:0>«aML. 2 5 aM else no operation % fond a" o0LdT10 | 96 "FFF (A) #0 then(PC)<7:03¢aML 2 = aML else no operation i |T0 a “looitoi10 [36 iF TO-1 then(PC)<7:0>¢aNL 2 y aM. else no operation = JoNTO a 00100110 | 26 Jif TO=0 then(PC)<7:0>¢amL. re a aM else no operation oa 01010110 |" 66 Jif Ti=1 then(PC)<7:05¢aMt 2 aML else no operation JNTi a 01000110} 46] if T1-0 ‘then(PC)<7:03eaML 2 aM. else no operation SFO a 10110110 | B6 | if FO=1 then(PC)<7:0>"aML 2 aML else no operation dria 110110 | 76°) if Fi=1 then(PC)<7:09¢aMi 2 aML. else no operation JTF a 00010110 | 16°) iF TF=1 then(PC)<7:0>¢aML 2 aM. else no operation 020989 (1) --~ Register Instruction MCU48-60

List of TLCS-48 Machine Instruction (3/4) Object Code = Assembler (ist) Flag ee r emonic 7 UND a 10000110 | 66 | if INT =0 then(PC)<7:0>-aML 2 aML else no operation (2) [dba bbb100i0 fo+iz | if (A)<b>=1 then 2 | amt (PC)<7:0>¢aML | else no operation _b=0~7 CALL a faHioi00 | alivid | [(SP)] (PSW)<7:4>-(PC) 2 1 amt (SP) #(SP)#1 | (PC)<10:0> ¢a (PC)<11>_¢(DBF) (3) RET iooo00ii | e3” |(sP)«(sP)-1 2 (PC) €[(SP)]<11:0> RETR 10010011 | 93 | (SP)«(SP)-1 tt 2 (PC) +{(SP)]<i1:0> cir C Tooi0iii | 97 | (C)*0 T cee 10100111 | A7 (C)eNoT(C) 1 (ay {OLR FO io000101 |” 85 | (Fo) «0 1 cel Fo ioo10101 | 96° | (Fo) Nor(FO) : 1 ciR” “Fi 10100101 | AS | (FL) +0 1 cpl Fi i0i10101 | 85 | (Fi) NoT(F1) 1 MOV A, Rr [iiilirre |F8er_ | (A)*(Rr) r=0-7 1 MOV A .@Rr |1111000r |Foer | (A)e[(Rr)] r0,1 1 MOV A wi ooidd011 | 23° | (a) «i 2 iiiiiiii |i | ~ [MOV Rr, A |t0t01eer JAB+r | (Rr)+(A) 10-7 toa © |MoV @Rr, A |1010000r |Ao+r | [ (Rr) }e(A) 10,1 1 D fwov Re ai 10ilierr |B8+r | (Ree r0-7 | 2 3 iiiiiiii ii { [MOV Re i Toi1000r [Bore | E(Rr) Jed reO.1 2 ” Viiiiiii ii < |wov a.psw |ino00111 | C7” |(A) <(PSwW) 1 o |wov'‘Psw.A”"/a1010111 |” 07” | (PSW) <(A) 1 3 [xcH A,Rr O010irrr |28+r |(A) (Rr) r=0~7 1 = |xcH “A,err —|o010000r J20+r (A) SE (Re)] r=0,1 1 XCHD A,@Rr 0011000r |30+r (A)<3:0>e[(Rr)<3:0>] r=0,1 1 MOVx “@Rr,A” "| 1001000r j90er |EXTE(Rr)] «(A) r=0,4 a MOVX A,@Rr [1000000 |80+r | (A) “EXT[(Rr)} r=0,1 1 MOVP AOA 10100011 | A3 | (A) “PRO[(PC)<11:8>-(A)] 1 Move3 A.@A iiiooo11 | €3 | (A) PROE(PC)<11>-011-(A) 1 (2) Branch Instruction (3) ~~ Subroutine Instruction 020989 (4) Flag Instruction MCU48-61

ELECTRICAL CHARACTERISTICS

TMPS80CS50AP/C40AP/C50AU, [ro] PowerBisipation Tans) S*dC asm TMP80CS50AP/C40AP/C50AU . Topr = —40°C to 85°C, Vcc = +5V + 10%, Vsg = OV, unless otherwise noted. [Sweot | rarawerer [est conomions [wn [ ve, [wai [ on] fu Emm | ses | - [oe |v | [wer eRe Tos | = | os |v | [we fect ee mes.) | | 22 | = | vec |v | [war eget e — | vee | | Mee | | fo [ees ecto [T= fos a [vou | uearePrerady [He -t6ma | 24¢ | - | |v | [vowi2 | ueeiicucpes [Hs -aoona | MGS | = | = |v | [vores [Seisnsatioe” ——Trowe-sonn [24 [= | = | wv | [vow2 [itera [tone 25a GS] = | = |v | Ca eo fa Teter seme [TT Ton a Fn [uo [paste [Rarer | = Tee To fe — ecco Pen Yc, Ff =I om | MCU48-63

TMP80CS50AP/C40AP/C50AU . Topr = — 40°C to°85 C, VCC = +5V + 10%, VSS = OV, unless otherwise noted. PARAMET! NDITION | f(t) UNIT SYMBOL AMETER TEST Col (t) i [an [on | Control Pulse Width a vo -200| 480 (RO, WR) a ee Control Pulse Width (PSEN) erm] oso | m | Data Setup Time . . (WR) | oot 200 | | Data Hold Time . 7 cre 20°F i | | Data Hold Time fon | (RD, PSEN) c= 2008 fro] | " Data Input Read Time _ [vo | (RD) Ls | ” Data Input Read Time . [vo | (PSEN) fem] = | a“ [= | Address Setup Time - [| (wR) { ae ‘Address Setup Time . taot ‘@D) 10t- 170 730 ns ‘Address Setup Time — 7t= 171 4 [ao | (PSEN) ‘ ° ° * Address Float Time | ss Flo. = =a (RO, WR) cee 20eF ae [| Address Float Time SF = at (PSEN) chs 20eF 1 ost 40 | ALE to Control Time | tars (RD, WR) t ALE to Control Time Marc (PSEN) t Control to ALE Time CAN (RD, WR, PROG) t Control to ALE Time Aa (PSEN) pa09e9 McUu48-64

AC Charactrjctics (Continue) . Topp = - 40°C to85°C, Voc = + 5V + 10%, Vss = OV, unless otherwise noted. ono 9 SYMBOL PARAMETER TEST C TION. (t) UNIT [| | to Port Control Setup Time P (PROG) Port Control Hold Time (PROG) [| aa po] - |e | Port 2 input Data Setup Time . ter (PROG) 8.5t- 120 650 Port 2 input Data Hold Time (PROG) ee Port 2 Output Data Setup Time . top (PROG) 6t-290 Port 2 Output Data Hold Time 1.5t- (PROG) [fee] oe | = fm | Port 21/0 Data Setup Time . (ate) emf | | Port 2 1/0 Data Hold Time co 1 (ALE) | | oste% Le i- |» | 220988 Note: 1. Control Output CL=80pF. BUS Output CL=150pF. 2, The f(t) assumes 50% duty cycle on XTAL) and XTAL2. The Max. Clock frequency is 11MHz. and the Min. Clock frequency is 1MHz. McUu48-65

TMP80CS0AP-6/TMP80C40AP-6/TMP80C50AU-6 Vcc Supply Voltage (with respect to GND (Vss) ) Input Voltage (Except EA) =0.5V to Vec +0.5V Input Voltage (Only EA) -0.5V to 13V Soldering Temperature (Soldering Timer 10 seq) Storage Temperature ~ 65°C to 150°C Operating Temperature = 40°C to 85°C oa0389 TMP80CS5OAP-6/TMP80C40AP-6/TMP80C50AU-6 . Topr= — 40°C to 85°C, Vcc = + 5V + 10%, Vsg = OV, unless otherwise noted InputHigh Voltage VK (Except XTALs, XTAL2, RESET, PS) 22 vec | ¥ Input High Voltage 7x Vint (XTALt, XTALz, RESET, P5) Vee vec | V Output Low Voltage . Vol (Except Pio-Pi7, P20-P27) 1Ok= 1.6mA v Output Low Voltage Z vou (Pyo-P17, P20-P27) lOL=1.2ma v Output High Voltage _- vourt | RyrBet pig vortegs 1OH = -1.6mA 24 v Output High Voltage __ Vec= Voui2 | puthut High vor 1OH= - 4000 oS v Output High Voltage _ vor21 | utput High Yolt IOH= -50nA 24 v Output High Voltage =- Vee = VOH22 (P10-P 17, P29-P27) IOH = ~25pA 8 Vv Input Leak Current < Vn Input Leak Current < s - Input Leak Current Vos +0.45V= Vin ~ (ue (P0-P17, P2o-P27) =Vec 500 | HA Output Leak Current (BUS, To) Vss + 0.45V5 Vin ito (High impedance condition) = Vee #10 | BA lect cc= SV, 10 Vcc Supply operation fxtaL = 6MHz mA Current VIH = Vec ~0.2V =| 25 | iccH1 HALT Mode | ViHt= Mec 25 ove MCU48-66

TMP80C50AP-6/TMP80C40AP-6/TMP80CSOAU-6 . Topr = - 40°C to 85°C, Vcc = +5V + 20%, Vss = OV, unless otherwise noted. SYMBOL PARAMETER TEST CONDITIONS. [ win. | rye. | max. | UNIT Vec VIM input High Voltage Z 05x Vee Vv (Except XTALy, XTAL2, RESET, PS) Voc Input High Voltage 07x VIH1 eee ee Vv Vv (XTAL, XTALz, RESET, PS) Vee “ ‘Output Low Voltage VOL 1OL = 1.6mA 0.45 v (Except P1o-P17, Pz0-P27) (P10-P17, P20-P27) Output High Voltage Vec- VOH12 1OH = -400pA Vv (Except P1o-P17, P20-P27) x 0.8 VOH22 1OH = -25pA Vv (P10-P 17, P20-P27) » 08 u Input Leak Current Ves =VINEV. +10 (11, INT, EA, PS) st sc - qL 5, RESET) Vss = VINS Vec kh qLI2 Ss (P10-P 17, P20-P27) sv oor | A Output Leak * (BUS, T = Lo utput Leak Current ( 0) Vss +0.45V = VIN tio | pa (High impedance condition) =V ae L- | - |] 1cc1 10 Vcc Supply Current opration fxtat = 6MHz Vit =0.2V 090989 MCU48-67

4.7 AC Characteristics

TMP80C50AP-6/TMP80C40AP-6/T MP80C50AU-6 . Topr = ~ 40°C to 85°C, Vcc = + 5V # 20%, Vss = OV, unless otherwise noted. SYMBOL PARAMETER CONDITION F(t) am Pac] UNIT Control Pulse Width (RD, WR) | | 7985200 [me | - fom | Control Pulse Width (PSEN) || oan po | - |i | Data Setup Time (wr) Lf eseam [co [= | | Data Hold Time (wR) Cts 20nF Le fm] |» | | Data Hold Time 7 ‘or (RD, PSEN) cre 20PF [ase |e | | | Data Input Read Time . tro1 (RD) 5.5t- 120 800 ns Data Input Read Time . ‘teo2 (PSEN) 4t- 120 ns Address Setup Time (wR) | fee fom | Lm | ‘Address Setup Time . taot RD) 10t- 170 ns Address Setup Time . Address Float Time (RD, WR) St=20PF [ao [ae] - | " Address Float Time (PSER) St=200F [oso | wo | " ALE to Control Time (8, WR) ae ee ” ALE to Control Time tl Control to ALE Time Al (RD, WR PROG) Control to ALE Time | . _ tear | pseR | 4t-70 | 590 ns ; erry MCU48-68

AC Characteristics (Continue) . Topr= — 40°C to 85°C, Vec = + 5V + 20%, Vss = OV, unless otherwise noted. Port 2 Input Data Setup Time _ ter (PROG) 8.5t- 120 1290 Port 2 Input Data Hold Time (PROS) fe fells | Port 2 Output Data Setup Time _ n top (PROG) 6t-290 10 ns Port 2 Output Data Hold Time ‘eo (PROG) ns [ee Jrosrusewiat [| von as0 [i500 [|| [or Jovtetime seas Piso Note: 1. Control Output CL=80pF, BUS Output CL=150pF. 2. The f(t) assumes 50% duty cycle on XTAL and XTAL2. ‘The Max. Clock frequency is 11MHz. and the Min. Clock frequency is LMHz. MCU48-69

A. Instruction Fetch from External Program Memory tu | fe] ture It tcar > ALE 1 Se] PSEN i<— tcc2z | tar [| ta | aor] «tf toe 020989 B. Read from External Data Memory tuarcr tear} ALE °

0 I< tec) ——

207 ZL 8 MLL RL

C. Write into External Data Memory tlarcr teas} ALE wr I tow >| |= two DOR 4 — tw — 00989 D. Timing of Port 2 during Expander Instruction Execution “ (| /&— PSEN le tey >| tear >| J I<— top =f} [120 te tec ter _ -— tpr —" PROG | trp ——— 00989 MCU48-71

The operation of oscillation circuit is suspended by setting PS terminal to low level after RESET terminal has been set to low level. Consequently, all the data in RAM area can be held in low power consumption. ‘The minimum hold voltage of Vcc in this mode is 2V. PS terminal is set to high level to resume oscillation after Voc has been reset to 5V, and then RESET terminal is set to high level, thus, the normal mode is restarted from the initialize operation (address 0). (1) DC Characteristics TMP80C50AP/C40AP/CSOAU TMP80C50AP-6/C40AP-6/C50AU-6 : Topr = — 40°C to 85°C, VSS = OV Frome] mince [rercomron [om [vw [wm | Vec = 5V, VIH = Vcc for soon aay = fe» | 00989 (2) AC Characteristics TMPBOCS5OAP/C40AP/C50AU : Vee =5V + 10%, Vsg = OV TMPBOC50AP-6/C40AP-6/C50AU-6 : Vee =5V # 20%, Veg = OV a asm] os0989 Note : toy=2.5ps (fx TAL = 6MHz) (3) Timing Waveform Vee * { I — <— t RESET wH vs PS 1H} tesa | >| trssr 040989 Mcua8-72

‘The operation of oscillation circuit is suspended by setting PS terminal to low level after SS terminal has been set to low level. Consequently, all data can be held in low power consumption. The minimum hold voltage of Vcc in this mode is 3V. PS terminal is set to high level to resume oscillation after Voc has been reset to 5V, and then SS terminal is set to high level, thus, the normal mode is restarted continuously from the state just before the power down mode (II). (1) DC Characteristics TMP80CS0AP/C40AP/CSOAU. TMP80C50AP-6/C40AP-6/CSOAU-6 : TOPR = - 40°C to 85°C, VSS =0V VCC = 5V, VIH = VCC 020989 (2) AC Characteristics TMP80C50AP/C40AP/CS5O0AU > Vcc =5V + 10%, Vss = OV TMP80CS50AP-6/C40AP-6/CS0AU-6 : Vee =5V 20%, Vss = OV Frm] ramen [racn [om [vw [ wn or] [inss [ronersnesetprine sy || _w P - | =m | [ow enone ps P| [is [eseuprme sy Ps P= P= | 040389 Note : tey=2.5ps (fyra1,=6MHz) (3) Timing Waveform Vee =< — tv — [vs PS | 4 tosis I tess 010989 MCU48-73

(1) HALT INSTRUCTION OP code is “01H”. HALT INSTRUCTION is an additional instruction to the standard 8048/8049 instruction set. (2) Entry to HALT MODE On the execution of HALT INSTRUCTION, TMP80C50A/TMP80C40A enter HALT MODE. (3) Status in HALT MODE The oscillator continues its operation, however, the internal clocks and internal logic values just prior to the execution of HALT INSTRUCTION are maintained. Power consumption in HALT MODE is less than 50% of normal operation. The status of each pins are described in the following table. (4) Release from HALT MODE HALT MODE is released by either of two signals (RESET, INT). (4.1) RESET Release Mode : An active RESET input signal causes the normal reset function. TMP80C50A/TMP80C40A start the program at address “000 H”. (4.2) INTReleaseMode : An active INT input signal causes the normal operation. e In case of interrupt enable mode (EI MODE), TMP80C50A/TMP80C40A. execute the interrupt service routine, after the execution of one instruction which is located at the next address after HALT INSTRUCTION. e In case of interrupt disable mode (DI MODE), TMP80C50A/TMP80C40A execute normal operation from the next address after HALT INSTRUCTION. (5) Supply Voltage Range in HALT MODE ‘The operating supply voltage range and the operating temperature range are same as in normal operation. TMP80C50AP/C40AP/C50AU : Voc=5V+10% TMP80C50AP-6/C40AP-6/C50AU-6 : Voco=5V 420% MCU48-74

4.9.4 Pin Status In Power Down Mode (I) (|!) Cree [a rete er | | Po~Pir | High impedance Input disabled 00009 Values prior to the execution of HALT INSTRUCTION are maintained. oa Mcu4s-75

OSCILLATOR QUARTZ CRYSTAL f=1MHzto4MHz : C1=C2=30pF XTAL f=4MHz to 11MHz ; C1=C2=20pF 1 Ze CERAMIC RESONATOR fat Vv f= 1MHzto3MHz : C1=C2=100pF 3 ¥ f=3MHzto 11MHz : C1=C2= 30PF Z 2 xTan Y a = 6. TYPICAL CHARACTARISTICS Vcc = 5V, Ta = 25°C, unless otherwise noted. Vec tou. ° met TTT ott 5 [TAT TT 20 [Z| ‘ [At | tt wt 4 ; AGERE 5 10 15 fxTat (MHz) 0 1 2 3 4 5 Vour(y) Vec-fmax. TYPICAL CURVE Vour-lot TYPICAL CURVE lec 12,3 4 5 Your) / (mA) | ot tt TA I / . wot | | LAT EP ane -150 E> ac ° 4 rt} | tT Zann “on || wow LLL | Tt | 5 10 15 fxray (MHz) (uA) fxtav-icc TYPICAL CURVE Vour-lon TYPICAL CURVE (PORT 1, 2) 040909 MCU48-76

TOSHIBA TMP&OC50A/40A ‘tRESET (ms) 1 2.3. 4 5 Your) roo Fe) TILL. col} | Tr 5 5 es ce ~10 LA oi EPZane Sete eo ste Ty 20 5. ee Li | yt TT Te 007 0.02 003 006 0.1 0.2 03 Creser ‘om A) (ma) Creset-treseT TYPICAL CURVE Vout-lon TYPICAL CURVE (DB, CONTROL) 0aoses 7. OUTLINE DRAWING

7.1 Outline Drawing For TMP80CSOAP/-6, TMP80C40AP/-6

(DIP : Dual Inline Package) DIP40-P-600 Unit: mm 40 24 ir 1 20 3° | | oss NHIUIUULONUBICINIOIEININIBINIBIONN alet., B a | aS poe Note: 1. This dimension is measured at the center of bending point of leads. 2. Each lead pitch is 2.54mm, and all the leads are located within +0.25mm from their theoritical positions with respect to No.1 and No.40 leads. Mcu48-77

7.2 Outline Drawing For TMP80C50AU/-6

(Micro Flat Package) QFP44-P-1010A. Unit : mm 13.8403 10.0202 | 33 23. ¢ MON 108 z | UUUELEIL I | . ose I 22 = Ec aa : a i Love 038201 Bea] — 97-5 08202 Note: 1. The above dimensions don’t include the burr of | package and the residue of tie-bar cut. ‘The burr of package and the residue of tie-bar cut should be 0.15 mm (Max,). 2. Applied to the lead flat portion. MCU48-78

CMOS INPUT/OUTPUT EXPANDER (TLCS-48C) TMP82C43P 1. GENERAL DESCRIPTION AND FEATURES The TMP82C43P is an input/output expander designed specifically to provide a low cost means of I/O expansion for the TLCS-48C family. The I/O ports of the TMP82C43P serve as a direct extension of the resident I/O facilities of the TLCS-48C microcomputers and are accessed by their own MOVD, ANLD and ORLD instructions.

CMOS LSI for low power dissipation © Simple interface to TLCS-48C microcomputers © Four 4-bit 1/0 ports © Single 5V supply ¢ High output drive © PIN compatible with intel’s 8243 © Extended operation temperature range —40°C to 85°C MCU48-79

PIN CONNECTION AND PIN FUNCTIONS

2.1 Pin Connection (Top View)

Vss C] 12 13D P29 ooses Figure 2.1. DIP Pin Connections

2.2 BLock Diagram

vont? (2 l Roos TEMPORARY Ul i PORT 6 REGISTER Idi |S AND/OR LOGIC Ct LATCH POR’ RESET {INPUT BUFFER CIRCUIT cxoses Figure 2.2 Block Diagram MCcU48-80

2.3. Pin Names And Pin Description PROG (Input) Clock input. A high to low transistion on PROG signifies that address and control are available on P29-23, and a low to high transition signifies that data is available on Pg9-93. CS (Input) Chip Select Input. A high on CS inhibits any change of output or internal status. Pa9-93 (Input/Output, 3-state) Four (4) bit bi-directional port contains the address and control bits on a high to low transition of PROG. During a low to high transition it, contains the data for a selected output port if a write operation, or the data from a selected port before the low to high transition if a read operation. P 40-43, P50-53, Peo-63, P70-73 (Input/Output, 3-state) Four (4) bit bi-directional I/O ports. May be programmed to be input (during read), low impedance latched output (after write) or a 3-state (after read), Data on pins P29-23 may be directly written, ANDed or ORed with previous data. Voc (Power) +5 volt supply Vgg (Power) 0 volt supply MCU48-81

FUNCTIONAL DESCRIPTION 3.1. General Operation The TMP82C48P contains four 4-bit I/O ports which serve as an extension of the on- chip I/O and are addressed as ports 4-7. The following operations may be performed on these ports. © Transfer accumulator to port . Transfer port to accumulator ¢ ~— ANDaccumulator to port ¢ — ORaccumulator to port All communication between the microcomputer (TMP80C49A) and the TMP82C43P occurs over Port 2 (P29-23) with timing provided by an output pulse on the PROG pin of the processor. Each transfer consists of two 4-bit nibbles. A high to low transition of the PROG line indicates that address is present while a low to high transition indicates the presence of data. Additional TMP82C43P may be added to the 4-bit bus and chip select signal using additional output lines from the microcomputer.

3.2 Power On Initialization

Initial application of power to the device forces input/output ports 4, 5, 6, and 7 to the tri-state and port 2 to the input mode. The PROG pin may be either high or low when power is applied. The first high to low transition of PROG causes device to exit power on mode. The power on sequence is initiated if Vcc drops below 1V. [ew [oem [ee] mm [om | ouenoncooe | CODE [eo [2 rome [ef ee [eff poets [ef ete ce a 20989 MCU48-82

3.3 Write Modes

The device has three write modes. MOVD Pi, A directly writes new data into the selected port and old data is lost. ORLD Pi, A takes new data, OR's it with the old data and then writes it to the port. ANLD Pi, A takes new data AND's it with the old data and then writes it to the port. Operation code and port address are latched from the input port 2 on the high to low transition of the PROG pin. On the low to high transition of PROG data on port 2 is transferred to the logic block of the specified output port. After the logic manipulation is performed, the data is latched and outputed. The old data remains latched until new valid outputs are entered.

3.4 Read Mode

The device has one read mode. The operation code and port address are latched from the input port 2 on the high to low transition of the PROG pin. As soon as the read operation and port address are decoded, the appropriate outputs are 3-stated, and the input buffers switched on. The read operation is terminated by a low to high transition of the PROG pin. The port (4, 5, 6 or 7) that was selected is switched to the 3-stated mode while port 2 is returned to the input mode. Normally, a port will be in an output (write mode) or input (read mode). If modes are changed during operation, the first read following a write should be ignored ; all following reads are valid. This is to allow the external driver on the port to settle after the first read instruction removes the low impedance drive from the TMP82C48P output. A read of any port will leave that port in a high impedance state. MCU48-83

ELECTRICAL CHARACTERISTICS

a Storage Temperature oases 4.2 D.C. Characteristics (I) Topr = — 40°C to 85°C, Vcc = 5V # 10%, Vss = OV a fa [epiowotnge | on =p ee a fee ee Ac frou —loustiowvotugeron? ——fuxeaomn [=f = [fv | [ios —JoustiowvotugerovaJex-dane | = [= [eww] Output High Voltage Ports 4-7 lon= —1.2mA 24 Vv fen feeatgitiag on —fosns Pee] Prosi Jouwcngh atop? =06na—e-08] = [=v] [vn —foupstignvoagerora——on==9ama [vanes] = [=v ] fat fowiesogerone7———wsvnzvee [== [3 a | fcr [row ietage Poa GbE Jssvn=vee [=| = je feemwenen REE] ~ [|= leet Power Supply Current (1) Vin = Vec-0.2V, = mA PROG PERIOD = 5yS = Geno lez Power Supply Current (2) Vin =Vcc-0.2V, pA PROG =Vcc-0.2V, [ix [iomotaiec oteoviae——[smacacrpn [=| = | ma | es MCU48-84

43 D.C. Characteristics (I!) Topr = — 40°C to 85°C, Vcc = SV + 20%, Ves = OV Frowes[rnawnes [sree [ we [ve [wm [ol [vic [inpattowvoroge —=iaa vena | 08 | fi —fnonpage ————fiseceer[oe pte a [vou [OuputtowvoragePersa? —fia=ana | ~ | - | os | v | [vou _lOwruttowvoraseron7 _fxetsma | = [= | 0 |v | [vou [OuputtowvotagePon2 iaeosna | | — | o4s| v | [vows [ouwutrgh votasePersa7 lows 20090 [vee-oa] = | - |v | [vows _[Outrigh votasePon? [lows 009A [vee-o8| =| — |v | [in _[sumofatiqnetieoupus __famatoenrin | - | - | | ma 00988 44 A.C. characteristics Topr = ~ 40°C to 80°C, Vcc = 5V + 20%, Vss = OV Frome [rans | vr [wn [or [on fix eosevetwactoernos =i ner | wo | | — | | fs |eodevateaterenos | Gzor | | = | | ws | sc fio [owwvanaanermos | ezor | > | | pw | fix _[rowtngaterenoc | ear | = | | | [ix _[Procnesniverusewams | | oo] — | - ‘| os | lis _[ESvaiduetowaterenos || SO] | — ‘| os | [so [Ponsa vaiaateronos ‘| _aniomr | - | - | wo | | fie ronsa7vaidsctreatermnos [| wo | = | | m | [ice [Ponavoiaaterrmos | aatr | - [= | ol w | cry MCU48-85

4.5 Timing Waveform

OUTLINE DRAWINGS DIP24-P-600 Unit : mm 1 2 5 | 32.040.2 | + ey |, Zt ES i a: ° 2osrve vaso 5 Note: Each lead pitch is 2.54mm. All leads are located within 0.25mm of their true longitudinal position with respect to No.1 and No.24 leads. MCU48-87

Product Information

P80C35 specifications and overview.

Summary

CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER (TLCS-48C)

Description

CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER (TLCS-48C)

Source title P80C35 Datasheet(PDF) - Toshiba Semiconductor

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