P80C32EBBB

80C32 PHILIPS | Alldatasheet

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/C0109 /C0110 /C0114 80C32/87C52 CMOS single-chip 8-bit microcontrollers Product specification 1996 Aug 16 INTEGRATED CIRCUITS IC20 Data Handbook

Philips Semiconductors Product specification 80C32/87C52CMOS single-chip 8-bit microcontrollers

21996 Aug 16 853–1562 17195

DESCRIPTION

The Philips 80C32/87C52 is a high-performance microcontroller fabricated with Philips high-density CMOS technology. The Philips CMOS technology combines the high speed and density characteristics of HMOS with the low power attributes of CMOS. Philips epitaxial substrate minimizes latch-up sensitivity. The 87C52 contains an 8k × 8 EPROM and the 80C32 is ROMless. Both contain a 256 × 8 RAM, 32 I/O lines, three 16-bit counter/timers, a six-source, two-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits. In addition, the 80C32/87C52 has two software selectable modes of power reduction—idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. See 80C52/80C54/80C58 datasheet for ROM device specifications.

FEATURES

• 80C51 based architecture
• 8032 compatible – 8k × 8 EPROM (87C52) – ROMless (80C32) – 256 × 8 RAM – Three 16-bit counter/timers – Full duplex serial channel – Boolean processor
• Memory addressing capability – 64k ROM and 64k RAM
• Power control modes: – Idle mode – Power-down mode
• CMOS and TTL compatible
• Three speed ranges: – 3.5 to 16MHz – 3.5 to 24MHz – 3.5 to 33MHz
• Five package styles
• Extended temperature ranges
• OTP package available PIN CONFIGURATIONS 20 21 40P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 P1.5 P1.6 RST RxD/P3.0 TxD/P3.1 INT0 /P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 P1.7 WR /P3.6 RD /P3.7 XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG EA /VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 V DD CERAMIC AND PLASTIC DUAL IN-LINE PACKAGE SU00060

Philips Semiconductors Product specification 80C32/87C52CMOS single-chip 8-bit microcontrollers

1996 Aug 16 3

ORDERING INFORMATION

TEMPERATURE RANGE °C AND PACKAGE FREQ MHz DRAWING NUMBER P80C32EBP N P87C52EBP N OTP 0 to +70, Plastic Dual In-line Package 16 SOT129-1 P80C32EBA A P87C52EBA A OTP 0 to +70, Plastic Leaded Chip Carrier 16 SOT187-2 P87C52EBF FA UV 0 to +70, Ceramic Dual In-line Package 16 0590B P87C52EBL KA UV 0 to +70, Ceramic Leaded Chip Carrier 16 1472A P80C32EBB B P87C52EBB B OTP 0 to +70, Plastic Quad Flat Pack 16 SOT307-2 P80C32EFP N P87C52EFP N OTP –40 to +85, Plastic Dual In-line Package 16 SOT129-1 P80C32EFA A P87C52EFA A OTP –40 to +85, Plastic Leaded Chip Carrier 16 SOT187-2 P87C52EFF FA UV –40 to +85, Ceramic Dual In-line Package 16 0590B P80C32EFB B P87C52EFB B OTP –40 to +85, Plastic Quad Flat Pack 16 SOT307-2 P80C32IBP N P87C52IBP N OTP 0 to +70, Plastic Dual In-line Package 24 SOT129-1 P80C32IBA A P87C52IBA A OTP 0 to +70, Plastic Leaded Chip Carrier 24 SOT187-2 P80C32IBB B 0 to +70, Plastic Quad Flat Pack 24 SOT307-2 P87C52IBF FA UV 0 to +70, Ceramic Dual In-line Package 24 0590B P87C52IBL KA UV 0 to +70, Ceramic Leaded Chip Carrier 24 1472A P80C32IFP N P87C52IFP N OTP –40 to +85, Plastic Dual In-line Package 24 SOT129-1 P80C32IFA A P87C52IFA A OTP –40 to +85, Plastic Leaded Chip Carrier 24 SOT187-2 P80C32IFB B –40 to +85, Plastic Quad Flat Pack 24 SOT307-2 P87C52IFF FA UV –40 to +85, Ceramic Dual In-line Package 24 0590B P80C32NBA A 0 to +70, Plastic Leaded Chip Carrier 33 SOT187-2 P80C32NBP N 0 to +70, Plastic Dual In-line Package 33 SOT129-1 P80C32NBB B 0 to +70, Plastic Quad Flat Pack 33 SOT307-2 P80C32NFA A –40 to +85, Plastic Leaded Chip Carrier 33 SOT187-2 P80C32NFP N –40 to +85, Plastic Dual In-line Package 33 SOT129-1 P80C32NFB B –40 to +85, Plastic Quad Flat Pack 33 SOT307-2 NOTE: 1. OTP = One Time Programmable EPROM. UV = UV erasable EPROM 2. For 33MHz ROM 80C52 operation, see 80C52/80C54/80C58 data sheet.

Philips Semiconductors Product specification 80C32/87C52CMOS single-chip 8-bit microcontrollers

1996 Aug 16 4

CERAMIC AND PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS LCC 614 0 18 28 Pin Function

1 NC*

2 T2/P1.0 3 T2EX/P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1.6 9 P1.7

10 RST

11 RxD/P3.0

12 NC*

13 TxD/P3.1

14 INT0

/P3.2 15 INT1 /P3.3 Pin Function 16 T0/P3.4 17 T1/P3.5 18 WR /P3.6 19 RD /P3.7

20 XTAL2

21 XTAL1

23 NC*

24 P2.0/A8 25 P2.1/A9 26 P2.2/A10 27 P2.3/A11 28 P2.4/A12 29 P2.5/A13 30 P2.6/A14 Pin Function 31 P2.7/A15

32 PSEN

33 ALE/PROG

34 NC*

/VPP 36 P0.7/AD7 37 P0.6/AD6 38 P0.5/AD5 39 P0.4/AD4 40 P0.3/AD3 41 P0.2/AD2 42 P0.1/AD1 43 P0.0/AD0 44 V CC SU00061* DO NOT CONNECT PLASTIC QUAD FLAT PACK PIN FUNCTIONS PQFP 44 34 12 22 Pin Function 1 P1.5 2 P1.6 3 P1.7

4 RST

5 RxD/P3.0

6 NC*

7 TxD/P3.1

8 INT0

/P3.2 9 INT1 /P3.3 10 T0/P3.4 11 T1/P3.5 12 WR /P3.6 13 RD /P3.7

14 XTAL2

15 XTAL1

17 NC*

18 P2.0/A8 19 P2.1/A9 20 P2.2/A10 21 P2.3/A11 22 P2.4/A12 23 P2.5/A13 24 P2.6/A14 25 P2.7/A15

26 PSEN

27 ALE/PROG

28 NC*

/VPP 30 P0.7/AD7 Pin Function 31 P0.6/AD6 32 P0.5/AD5 33 P0.4/AD4 34 P0.3/AD3 35 P0.2/AD2 36 P0.1/AD1 37 P0.0/AD0 38 V CC

39 NC*

40 T2/P1.0 41 T2EX/P1.1 42 P1.2 43 P1.3 44 P1.4 SU00062* DO NOT CONNECT LOGIC SYMBOL PORT 0PORT 1PORT 2 PORT 3 ADDRESS AND DATA BUS ADDRESS BUS T2EX RxD TxD INT0 INT1 WR RD SECONDARY FUNCTIONS RST EA /VPP PSEN ALE/PROG VSSVCC XTAL1 XTAL2 SU00063

Philips Semiconductors Product specification 80C32/87C52CMOS single-chip 8-bit microcontrollers

1996 Aug 16 5

INTERRUPT, SERIAL PORT AND TIMER BLOCKS STACK POINTER SU00064

1996 Aug 16 6

Table 1. 8XC52 Special Function Registers # SFRs are modified from or added to the 80C51 SFRs.

1. Bits GF1, GF0, PD, and IDL of the PCON register are not implemented in the NMOS 8XC52.

Philips Semiconductors Product specification 80C32/87C52CMOS single-chip 8-bit microcontrollers

1996 Aug 16 7

PIN NO. MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION VSS 20 22 16 I Ground: 0V reference. VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0–0.7 39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification in the 87C52. External pull-ups are required during program verification. 1–3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Pins P1.0 and P1.1 also. Port 1 also receives the low-order address byte during program memory verification. Port 1 also serves alternate functions for timer 2: 1 2 40 I T2 (P1.0): Timer/counter 2 external count input. 2 3 41 I T2EX (P1.1): Timer/counter 2 trigger input. P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. 13–19 7–13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: I IL). Port 3 also serves the special features of the 80C51 family, as listed below: 10 11 5 I RxD (P3.0): Serial input port 11 13 7 O TxD (P3.1): Serial output port 12 14 8 I INT0 (P3.2): External interrupt 13 15 9 I INT1 (P3.3): External interrupt 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC . ALE/PROG 30 33 27 I/O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG ) during EPROM programming. PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA /VPP 31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to 1FFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 1FFFH. This pin also receives the 12.75V programming supply voltage (V PP ) during EPROM programming. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier.

1996 Aug 16 8

SFR locations, bit locations, and operation are likewise identical. which are selected by bits in the T2CON as shown in Table 2. and set EXF2. The auto-reload mode is illustrated in Figure 3. TCLK = 1. It will be described in conjunction with the serial port. that counter/timer 2 can be used to generate baud rates. baud rate for transmit and receive can be simultaneously different. The timer can be configured for either “timer” or “counter” operation. taken as a 16-bit unsigned integer. TF2 T2CON.7 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1. interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. causes Timer 1 overflow to be used for the receive clock. causes Timer 1 overflows to be used for the transmit clock. being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. TR2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer. 1 = External event counter (falling edge triggered). ignored and the timer is forced to auto-reload on Timer 2 overflow. Figure 1. Timer/Counter 2 (T2CON) Control Register

1996 Aug 16 9

Figure 2. Timer 2 in Capture Mode Figure 3. Timer 2 in Auto-Reload Mode

1996 Aug 16 10

Note availability of additional external interrupt. Figure 4. Timer 2 in Baud Rate Generator Mode Table 2. Timer 2 Operating Modes

1 X 1 Baud rate generator

external interrupt, if desired. accessing the Timer 2 or RCAP registers, in this case. of timer 2 as a timer. See Table 4 for set-up of timer 2 as a counter.

32 Baud Rate

1996 Aug 16 11

are identical sources to those in the 80C51. modified to include the additional 80C32/87C52 interrupt sources. The operation of these registers is identical to the 80C51. interrupts can be canceled in software.

1. TF2 + EXF2 002BH (lowest)

the lowest priority within a level. Table 3. Timer 2 as a Timer Table 4. Timer 2 as a Counter

1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when timer 2 is used in the baud rate

1996 Aug 16 12

oscillator, as shown in the Logic Symbol, page 4. the internal clock circuitry is through a divide-by-two flip-flop. the data sheet must be observed. machine cycles (24 oscillator periods), while the oscillator is running. milliseconds) plus two machine cycles. the same manner as a power-on reset. instruction to invoke power-down is the last instruction executed. same time for a proper start-up. and INT1 should be disabled prior to enterring power down. Table 5. External Pin Status During Idle and Power-Down Modes

Philips Semiconductors Product specification 80C32/87C52CMOS single-chip 8-bit microcontrollers

1996 Aug 16 13

Electrical Deviations from Commercial Specifications for Extended Temperature Range (87C52) DC and AC parameters not included here are the same as in the commercial temperature range table. DC ELECTRICAL CHARACTERISTICS Tamb = –40°C to +85°C, VCC = 5V ±10%, VSS = 0V TEST LIMITS SYMBOL PARAMETER CONDITIONS MIN MAX UNIT VIL Input low voltage, except EA –0.5 0.2VCC –0.15 V VIL1 Input low voltage to EA 0 0.2VCC –0.35 V VIH Input high voltage, except XTAL1, RST 0.2VCC +1 VCC +0.5 V VIH1 Input high voltage to XTAL1, RST 0.7VCC +0.1 VCC +0.5 V IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.45V –75 µA ITL Logical 1-to-0 transition current, ports 1, 2, 3 VIN = 2.0V –750 µA ICC Power supply current: Active mode Idle mode Power-down mode VCC = 4.5–5.5V, Frequency range = 3.5 to 16MHz mA mA µA ABSOLUTE MAXIMUM RATINGS 1, 2, 3 PARAMETER RATING UNIT Operating temperature under bias 0 to +70 or –40 to +85 °C Storage temperature range –65 to +150 °C Voltage on EA/VPP pin to VSS 0 to +13.0 V Voltage on any other pin to VSS –0.5 to +6.5 V Maximum IOL per I/O pin 15 mA Power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V SS unless otherwise noted.

Philips Semiconductors Product specification 80C32/87C52CMOS single-chip 8-bit microcontrollers

1996 Aug 16 14

DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V (87C52) Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V (80C32) TEST LIMITS SYMBOL PARAMETER CONDITIONS MIN TYP 1 MAX UNIT VIL Input low voltage, except EA7 –0.5 0.2VCC –0.1 V VIL1 Input low voltage to EA7 0 0.2VCC –0.3 V VIH Input high voltage, except XTAL1, RST7 0.2VCC +0.9 VCC +0.5 V VIH1 Input high voltage, XTAL1, RST7 0.7VCC VCC +0.5 V VOL Output low voltage, ports 1, 2, 39 IOL = 1.6mA2 0.45 V VOL1 Output low voltage, port 0, ALE, PSEN9 IOL = 3.2mA2 0.45 V VOH Output high voltage, ports 1, 2, 3, ALE, PSEN3 IOH = –60µA, IOH = –25µA IOH = –10µA 2.4 0.75VCC 0.9VCC V V V VOH1 Output high voltage (port 0 in external bus mode)IOH = –800µA, IOH = –300µA IOH = –80µA 2.4 0.75VCC 0.9VCC V V V IIL Logical 0 input current, ports 1, 2, 37 VIN = 0.45V –50 µA ITL Logical 1-to-0 transition current, ports 1, 2, 37 See note 4 –650 µA ILI Input leakage current, port 0 VIN = VIL or VIH ±10 µA ICC Power supply current:7 Active mode @ 16MHz5 Idle mode @ 16MHz Power-down mode T amb = 0 to 70°C Tamb = –40 to +85°C See note 6 11.5 1.3 mA mA µA µA R RST Internal reset pull-down resistor 50 300 kΩ C IO Pin capacitance10 15 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V OL s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I OL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mA. See Figure 12. 6. See Figures 13 through 16 for ICC test conditions. 7. These values apply only to Tamb = 0°C to +70°C. For Tamb = –40°C to +85°C, see table on previous page. 8. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 9. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15mA (*NOTE: This is 85 °C specification.) Maximum IOL per 8-bit port: 26mA Maximum total IOL for all outputs: 67mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 10.This limit is for plastic packages. For ceramic packages, the maximum limit is 20pF.

Philips Semiconductors Product specification 80C32/87C52CMOS single-chip 8-bit microcontrollers

1996 Aug 16 15

AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V (87C52)1, 2, 3 16MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 5 Oscillator frequency Speed versions : E 3.5 16 MHz tLHLL 5 ALE pulse width 85 2tCLCL –40 ns tAVLL 5 Address valid to ALE low 22 tCLCL –40 ns tLLAX 5 Address hold after ALE low 32 tCLCL –30 ns tLLIV 5 ALE low to valid instruction in 150 4tCLCL –100 ns tLLPL 5 ALE low to PSEN low 32 tCLCL –30 ns tPLPH 5 PSEN pulse width 142 3tCLCL –45 ns tPLIV 5 PSEN low to valid instruction in 82 3tCLCL –105 ns tPXIX 5 Input instruction hold after PSEN 0 0 ns tPXIZ 5 Input instruction float after PSEN 37 tCLCL –25 ns tAVIV 5 Address to valid instruction in 207 5tCLCL –105 ns tPLAZ 5 PSEN low to address float 10 10 ns Data Memory tRLRH 6, 7 RD pulse width 275 6tCLCL –100 ns tWLWH 6, 7 WR pulse width 275 6tCLCL –100 ns tRLDV 6, 7 RD low to valid data in 147 5tCLCL –165 ns tRHDX 6, 7 Data hold after RD 0 0 ns tRHDZ 6, 7 Data float after RD 65 2tCLCL –60 ns tLLDV 6, 7 ALE low to valid data in 350 8tCLCL –150 ns tAVDV 6, 7 Address to valid data in 397 9tCLCL –165 ns tLLWL 6, 7 ALE low to RD or WR low 137 239 3tCLCL –50 3tCLCL +50 ns tAVWL 6, 7 Address valid to WR low or RD low 122 4tCLCL –130 ns tQVWX 6, 7 Data valid to WR transition 13 tCLCL –50 ns tWHQX 6, 7 Data hold after WR 13 tCLCL –50 ns tQVWH 7 Data valid to WR high 287 7tCLCL –150 ns tRLAZ 6, 7 RD low to address float 0 0 ns tWHLH 6, 7 RD or WR high to ALE high 23 103 tCLCL –40 tCLCL +40 ns External Clock tCHCX 9 High time 20 20 tCLCL –tCLCX ns tCLCX 9 Low time 20 20 tCLCL –tCHCX ns tCLCH 9 Rise time 20 20 ns tCHCL 9 Fall time 20 20 ns Shift Register tXLXL 8 Serial port clock cycle time 750 12tCLCL ns tQVXH 8 Output data setup to clock rising edge 492 10tCLCL –133 ns tXHQX 8 Output data hold after clock rising edge 8 2tCLCL –117 ns tXHDX 8 Input data hold after clock rising edge 0 0 ns tXHDV 8 Clock rising edge to input data valid 492 10tCLCL –133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 80C32/52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. See application note AN457 for external memory interface.

Philips Semiconductors Product specification 80C32/87C52CMOS single-chip 8-bit microcontrollers

1996 Aug 16 16

AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3 24MHz CLOCK VARIABLE CLOCK 33MHz CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX MIN MAX UNIT 1/tCLCL 5 Oscillator frequency Speed versions : I 3.5 24 3.5 33 MHz tLHLL 5 ALE pulse width 43 2tCLCL –40 21 ns tAVLL 5 Address valid to ALE low 17 tCLCL –25 5 ns tLLAX 5 Address hold after ALE low 17 tCLCL –25 5 ns tLLIV 5 ALE low to valid instruction in 102 4tCLCL –65 56 ns tLLPL 5 ALE low to PSEN low 17 tCLCL –25 5 ns tPLPH 5 PSEN pulse width 80 3tCLCL –45 46 ns tPLIV 5 PSEN low to valid instruction in 65 3tCLCL –60 31 ns tPXIX 5 Input instruction hold after PSEN 0 0 0 ns tPXIZ 5 Input instruction float after PSEN 17 tCLCL –25 5 ns tAVIV 5 Address to valid instruction in 128 5tCLCL –80 72 ns tPLAZ 5 PSEN low to address float 10 10 10 ns Data Memory tRLRH 6, 7 RD pulse width 150 6tCLCL –100 82 ns tWLWH 6, 7 WR pulse width 150 6tCLCL –100 82 ns tRLDV 6, 7 RD low to valid data in 118 5tCLCL –90 62 ns tRHDX 6, 7 Data hold after RD 0 0 0 ns tRHDZ 6, 7 Data float after RD 55 2tCLCL –28 33 ns tLLDV 6, 7 ALE low to valid data in 183 8tCLCL –150 92 ns tAVDV 6, 7 Address to valid data in 210 9tCLCL –165 108 ns tLLWL 6, 7 ALE low to RD or WR low 75 175 3tCLCL –50 3tCLCL +50 41 141 ns tAVWL 6, 7 Address valid to WR low or RD low 92 4tCLCL –75 46 ns tQVWX 6, 7 Data valid to WR transition 12 tCLCL –30 0.3 ns tWHQX 6, 7 Data hold after WR 17 tCLCL –25 5 ns tQVWH 7 Data valid to WR high 162 7tCLCL –130 82 ns tRLAZ 6, 7 RD low to address float 0 0 0 ns tWHLH 6, 7 RD or WR high to ALE high 17 67 tCLCL –25 tCLCL +25 5 5 ns External Clock tCHCX 9 High time 17 17 tCLCL –tCLCX ns tCLCX 9 Low time 17 17 tCLCL –tCHCX ns tCLCH 9 Rise time 5 5 ns tCHCL 9 Fall time 5 5 ns Shift Register tXLXL 8 Serial port clock cycle time 505 12tCLCL 363 ns tQVXH 8 Output data setup to clock rising edge283 10tCLCL –133 170 ns tXHQX 8 Output data hold after clock rising edge3 2tCLCL –80 19 ns tXHDX 8 Input data hold after clock rising edge0 0 0 ns tXHDV 8 Clock rising edge to input data valid 283 10tCLCL –133 170 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 8XC52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz “AC Electrial Characteristics”, page 15.

1996 Aug 16 17

AVLL = Time for address valid to ALE low. tLLPL= Time for ALE low to PSEN low. Figure 5. External Program Memory Read Cycle Figure 6. External Data Memory Read Cycle

1996 Aug 16 18

Figure 7. External Data Memory Write Cycle Figure 8. Shift Register Mode Timing Figure 9. External Clock Drive

1996 Aug 16 19

AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Figure 10. AC Testing Input/Output and begins to float when a 100mV change from the loaded VOH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 11. Float Waveform Figure 12. ICC vs. FREQ

1996 Aug 16 20

Figure 13. ICC Test Condition, Active Mode Figure 14. ICC Test Condition, Idle Mode Figure 15. Clock Signal Waveform for ICC Tests in Active and Idle Modes Figure 16. ICC Test Condition, Power Down Mode

1996 Aug 16 21

number of the ALE/PROG pulses. circuit configuration for normal program memory verification. Figure 17. Note that the 87C52 is running with a 4 to 6MHz device is executing internal address and program data transfers. low 25 times as shown in Figure 18. programmed, verification cycles will produce only encrypted data. encryption table itself cannot be read out. which satisfies the timing specifications, is suitable. light with wavelengths shorter than approximately 4,000 angstroms. Erasure leaves the array in an all 1s state. Table 6. EPROM Programming Modes

1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. VCC = 5V±10% during programming and verification.
3. *ALE/PROG receives 25 programming pulses while VPP is held at 12.75V. Each programming pulse is low for 100µs (±10µs) and high for a

 Trademark phrase of Intel Corporation.

1996 Aug 16 22

Figure 17. Programming Configuration

25 PULSES

Figure 18. PROG Waveform

0 ENABLE

Figure 19. Program Verification

1996 Aug 16 23

• FOR PROGRAMMING VERIFICATION SEE FIGURE 17.

FOR VERIFICATION CONDITIONS SEE FIGURE 19. Figure 20. EPROM Programming and Verification

Philips Semiconductors Product specification 80C32/87C52CMOS single-chip 8-bit microcontrollers

1996 Aug 16 24

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

Philips Semiconductors Product specification 80C32/87C52CMOS single-chip 8-bit microcontrollers

1996 Aug 16 25

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

Philips Semiconductors Product specification 80C32/87C52CMOS single-chip 8-bit microcontrollers

1996 Aug 16 26

0590B 40-PIN (600 mils wide) CERAMIC DUAL IN-LINE (F) PACKAGE (WITH WINDOW (FA) PACKAGE) NOTES: 1. Controlling dimension: Inches. Millimeters are 2. Dimension and tolerancing per ANSI Y14. 5M-1982. 3. “T”, “D”, and “E” are reference datums on the body 4. These dimensions measured with the leads 5. Pin numbers start with Pin #1 and continue 6. Denotes window location for EPROM products. and include allowance for glass overrun and meniscus on the seal line, and lid to base mismatch. constrained to be perpendicular to plane T. counterclockwise to Pin #40 when viewed shown in parentheses. from the top. – D – PIN # 1 – E – 0.225 (5.72) MAX. 0.015 (0.38) 0.165 (4.19) 0.125 (3.18) 0.070 (1.78) 0.050 (1.27) – T – SEATING PLANE 0.620 (15.75) 0.590 (14.99) (NOTE 4) 0.598 (15.19) 0.571 (14.50) BSC 0.600 (15.24) 0.695 (17.65) 0.600 (15.24) (NOTE 4) 0.015 (0.38) 0.010 (0.25) 0.175 (4.45) 0.145 (3.68) 0.055 (1.40) 0.020 (0.51) 0.100 (2.54) BSC 2.087 (53.01) 2.038 (51.77) 0.098 (2.49) 0.040 (1.02) 0.098 (2.49) 0.040 (1.02) SEE NOTE 6 853–0590B 06688

Philips Semiconductors Product specification 80C32/87C52CMOS single-chip 8-bit microcontrollers

1996 Aug 16 27

1472A 44-PIN CERQUAD J-BEND (K) PACKAGE NOTES: 1. All dimensions and tolerances to conform 2. UV window is optional. 3. Dimensions do not include glass protrusion. Glass protrusion to be 0.005 inches maximum 4. Controlling dimension millimeters. 5. All dimensions and tolerances include lead trim offset and lead plating finish. 6. Backside solder relief is optional and dimensions are for reference only. 1.02 (0.040) X 45° 16.89 (0.665) 16.00 (0.630) 17.65 (0.695) 17.40 (0.685) CHAMFER 16.89 (0.665) 16.00 (0.630) 17.65 (0.695) 17.40 (0.685) on each side. to ANSI Y14.5–1982. 2 3 3 X 0.63 (0.025) R MIN. 3.05 (0.120) 2.29 (0.090) 4.83 (0.190) 3.94 (0.155) SEATING PLANE 0.38 (0.015) 0.51 (0.02) X 45° 17.65 (0.656) 17.40 (0.685) 1.27 (0.050) 12.7 (0.500) 8.13 (0.320) 7.37 (0.290) 40X 4.83 (0.190) 3.94 (0.155) SEATING PLANE 0.15 (0.006) MIN. 0.15 (0.006) 90 + 5 –10 0.076 (0.003) MIN. DETAIL B mm/(inch) SEE DETAIL B SEE DETAIL A DETAIL A TYP. ALL SIDES mm/(inch) 1.52 (0.060) REF. SEATING PLANE 1.02 + 0.25 (0.040 + 0.010) BASE PLANE 45 TYP.

4 PLACES

1.27 (0.050) TYP. NOMINAL 8.13 (0.320) 7.37 (0.290) 853-1472A 05854

Philips Semiconductors Product specification 80C32/87C52CMOS single-chip 8-bit microcontrollers

1996 Aug 16 28

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2

Philips Semiconductors Product specification 80C32/87C52CMOS single-chip 8-bit microcontrollers

1996 Aug 16 29

Philips Semiconductors Product specification 80C32/87C52CMOS single-chip 8-bit microcontrollers Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act.  Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A.

/C0109 /C0110 /C0114 80C52/80C54/80C58 CMOS single-chip 8-bit microcontrollers Product specification 1996 Aug 16 INTEGRATED CIRCUITS IC20 Data Handbook

Philips Semiconductors Product specification 80C52/80C54/80C58CMOS single-chip 8-bit microcontrollers

21996 Aug 16 853–1470 17196

The 80C52/80C54/80C58 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 80C52/80C54/80C58 has the same instruction set as the 80C51. This device provides architectural enhancements that make it applicable in a variety of applications for general control systems. The 80C52 contains 8k × 8 ROM memory, the 80C54 contains 16k × 8 ROM memory, and 80C58 contains 32k × 8 ROM memory, a volatile 256 × 8 read/write data memory, four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, four-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. For systems that require extra capability, the 80C52/54/58 can be expanded using standard TTL compatible memories and logic. Its added features make it an even more powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control. It also has a more versatile serial channel that facilitates multiprocessor communications. See 87C52/80C32 and 87C54/87C58 data sheets for EPROM and ROMless devices.

• 80C51 central processing unit
• Full static operation
• 8k × 8 ROM: 80C52; 16k × 8 ROM: 80C54; 32k × 8 ROM: 80C58; all capable of addressing external memory to 64k bytes – Two level program security system – 64 byte encryption array
• 256 × 8 RAM, expandable externally to 64k bytes
• Speed range up to 33MHz
• Operating voltage 5V ±10%
• Three 16-bit timer/counters – T2 is an up/down counter
• 6 interrupt sources
• 4 level priority
• Four 8-bit I/O ports
• Full-duplex enhanced UART – Framing error detection – Automatic address recognition
• Power control modes – Idle mode – Power-down mode
• Once (On Circuit Emulation) Mode
• Five package styles
• Programmable clock out
• Low EMI (Inhibit ALE)
• Second DPTR register
• Asynchronous port reset PIN CONFIGURATIONS 20 21 40T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 P1.7 WR /P3.6 RD /P3.7 XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 V CC DUAL IN-LINE PACKAGE SU00740

Philips Semiconductors Product specification 80C52/80C54/80C58CMOS single-chip 8-bit microcontrollers 8k × 8 ROM 16k × 8 ROM 32k × 8 TEMPERATURE RANGE °C AND PACKAGE FREQ MHz DRAWING NUMBER P80C52EBPN P80C54EBPN P80C58EBPN 0 to +70, Plastic Dual In-line Package 16 SOT129-1 P80C52EBAA P80C54EBAA P80C58EBAA 0 to +70, Plastic Leaded Chip Carrier 16 SOT187-2 P80C52EBBB P80C54EBBB P80C58EBBB 0 to +70, Plastic Quad Flat Pack 16 SOT307-2 P80C52EFPN P80C54EFPN P80C58EFPN –40 to +85, Plastic Dual In-line Package 16 SOT129-1 P80C52EFA A P80C54EFA A P80C58EFA A –40 to +85, Plastic Leaded Chip Carrier 16 SOT187-2 P80C52EFBB P80C54EFBB P80C58EFBB –40 to +85, Plastic Quad Flat Pack 16 SOT307-2 P80C52IBP N P80C54IBP N P80C58IBP N 0 to +70, Plastic Dual In-line Package 24 SOT129-1 P80C52IBA A P80C54IBA A P80C58IBA A 0 to +70, Plastic Leaded Chip Carrier 24 SOT187-2 P80C52IBB B P80C54IBB B P80C58IBB B 0 to +70, Plastic Quad Flat Pack 24 SOT307-2 P80C52IFP N P80C54IFP N P80C58IFP N –40 to +85, Plastic Dual In-line Package 24 SOT129-1 P80C52IFA A P80C54IFA A P80C58IFA A –40 to +85, Plastic Leaded Chip Carrier 24 SOT187-2 P80C52IFB B P80C54IFB B P80C58IFB B –40 to +85, Plastic Quad Flat Pack 24 SOT307-2 P80C52NBAA P80C54NBAA P80C58NBAA 0 to +70, Plastic Leaded Chip Carrier 33 SOT187-2 P80C52NBPN P80C54NBPN P80C58NBPN 0 to +70, Plastic Dual In-line Package 33 SOT129-1 P80C52NBBB P80C54NBBB P80C58NBBB 0 to +70, Plastic Quad Flat Pack 33 SOT307-2 P80C52NFA A P80C54NFA A P80C58NFA A –40 to +85, Plastic Leaded Chip Carrier 33 SOT187-2 P80C52NFPN P80C54NFPN P80C58NFPN –40 to +85, Plastic Dual In-line Package 33 SOT129-1 P80C52NFBB P80C54NFBB P80C58NFBB –40 to +85, Plastic Quad Flat Pack 33 SOT307-2 LOGIC SYMBOL PORT 0PORT 1PORT 2 PORT 3 ADDRESS AND DATA BUS ADDRESS BUS T2EX RxD TxD INT0 INT1 WR RD SECONDARY FUNCTIONS RST EA PSEN ALE VSSVCC XTAL1 XTAL2 SU00732

Philips Semiconductors Product specification 80C52/80C54/80C58CMOS single-chip 8-bit microcontrollers

Table 1. 80C52/80C54/80C58 Special Function Registers # SFRs are modified from or added to the 80C51 SFRs.

1. Reset value depends on reset source.
2. Bit will not be affected by Reset. POF is not present in 80C52.

Philips Semiconductors Product specification 80C52/80C54/80C58CMOS single-chip 8-bit microcontrollers PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS LCC 614 0 18 28 Pin Function 2 P1.0/T2 3 P1.1/T2EX 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1.6 9 P1.7 11 P3.0/RxD 13 P3.1/TxD 14 P3.2/INT0 15 P3.3/INT1 Pin Function 16 P3.4/T0 17 P3.5/T1 18 P3.6/WR 19 P3.7/RD 24 P2.0/A8 25 P2.1/A9 26 P2.2/A10 27 P2.3/A11 28 P2.4/A12 29 P2.5/A13 30 P2.6/A14 Pin Function 31 P2.7/A15

33 ALE

36 P0.7/AD7 37 P0.6/AD6 38 P0.5/AD5 39 P0.4/AD4 40 P0.3/AD3 41 P0.2/AD2 42 P0.1/AD1 43 P0.0/AD0 44 V CC SU00741A* DO NOT CONNECT PLASTIC QUAD FLAT PACK PIN FUNCTIONS PQFP 44 34 12 22 Pin Function 1 P1.5 2 P1.6 3 P1.7 5 P3.0/RxD 7 P3.1/TxD 8 P3.2/INT0 9 P3.3/INT1 10 P3.4/T0 11 P3.5/T1 12 P3.6/WR 13 P3.7/RD

16 V SS

18 P2.0/A8 19 P2.1/A9 20 P2.2/A10 21 P2.3/A11 22 P2.4/A12 23 P2.5/A13 24 P2.6/A14 25 P2.7/A15

27 ALE

30 P0.7/AD7 Pin Function 31 P0.6/AD6 32 P0.5/AD5 33 P0.4/AD4 34 P0.3/AD3 35 P0.2/AD2 36 P0.1/AD1 37 P0.0/AD0 38 V CC 40 P1.0/T2 41 P1.1/T2EX 42 P1.2 43 P1.3 44 P1.4 SU00742A* DO NOT CONNECT PIN DESCRIPTIONS PIN NUMBER MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION VSS 20 22 16 I Ground: 0V reference. VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0–0.7 39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification. External pull-ups are required during program verification. 1–3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Port 1 also receives the low-order address byte during program memory verification. Alternate functions include: 1 2 40 I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout 2 3 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control 3 4 42 I 4 5 43 I/O 5 6 44 I/O 6 7 1 I/O 7 8 2 I/O 8 9 3 I/O P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register.

Philips Semiconductors Product specification 80C52/80C54/80C58CMOS single-chip 8-bit microcontrollers PIN DESCRIPTIONS (Continued) PIN NUMBER MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION 13–19 7–13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: I IL). Port 3 also serves the special features of the 80C51 family, as listed below: 10 11 5 I RxD (P3.0): Serial input port 11 13 7 O TxD (P3.1): Serial output port 12 14 8 I INT0 (P3.2): External interrupt 13 15 9 I INT1 (P3.3): External interrupt 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC . ALE 30 33 27 O Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When the 80C52/80C54/80C58 is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA 31 35 29 I External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 7FFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 7FFFH. If security bit 1 is programmed, EA will be internally latched on Reset. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5V or VSS – 0.5V, respectively.

(which vectors to the same location as Timer 2 overflow interrupt. counter keeps on counting T2EX pin transitions or osc/12 pulses.). or down depending on the value of the T2EX pin. The values in RCAP2L and RCAP2H are preset by software means. generated when either TF2 or EXF2 are 1. In Figure 5 DCEN=1 which enables Timer 2 to count up or down. into the timer registers TL2 and TH2. when either RCLK or TCLK = 1. in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. TR2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer. 1 = External event counter (falling edge triggered).

T2OE Timer 2 Output Enable bit. See details in Programmable Clock-Out. DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.

• User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.

Figure 3. Timer 2 Mode (T2MOD) Control Register

Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0) Figure 5. Timer 2 Auto Reload Mode (DCEN = 1)

Note availability of additional external interrupt. Figure 6. Timer 2 in Baud Rate Generator Mode Table 3. Timer 2 Generated Commonly Used Timer 1, the other by Timer 2. The timer can be configured for either “timer” or “counter” operation. In many applications, it is configured for “timer” operation (C/T2*=0). RCAP2L taken as a 16-bit unsigned integer. rollover in TH2 does not set TF2, and will not generate an interrupt. will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). can be used as an additional external interrupt, if needed.

before accessing the Timer 2 or RCAP2 registers.

32 Baud Rate/C0467

Table 4. Timer 2 as a Timer Table 5. Timer 2 as a Counter

1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate
3. POF not present in 80C52.

the internal clock circuitry is through a divide-by-two flip-flop. the data sheet must be observed. machine cycles (24 oscillator periods), while the oscillator is running. CC and RST must come up at the same time for a proper start-up. IH1 (min.) is applied to RESET. which starts the processor in the same manner as a power-on reset. their values until the Power Down mode is terminated. both the SFRs and the on-chip RAM to retain their values. oscillator to restart and stabilize (normally less than 10ms).

• When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal rest algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. ONCE  Mode The ONCE (“On-Circuit Emulation”) Mode facilitates testing and debugging of systems using the 80C52/54/58 without removing the device from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the 80C52/54/58 is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied. Programmable Clock-Out The 80C52/54/58 has a new feature. A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed: 1. to input the external clock for Timer/Counter 2, or 2. to output a 50% duty cycle clock ranging from 61Hz to 4MHz at a 16MHz operating frequency. To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared and bit T2OE in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation: Oscillator Frequency 4 (65536RCAP2H, RCAP2L) In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will be the same.

Table 6. External Pin Status During Idle and Power-Down Mode

Philips Semiconductors Product specification 80C52/80C54/80C58CMOS single-chip 8-bit microcontrollers The UART operates in all of the usual modes that are described in the first section of Data Handbook IC20, 80C51-Based 8-Bit Microcontrollers. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The 80C52/54/58 UART also fully supports multiprocessor communication as does the standard 80C51 UART. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 8. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 9. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are “don’t care”. The SADEN mask can be logically ANDed with the SADDR to create the “|Given” address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00X0 Slave 1 SADDR = 1100 0000 SADEN = 1111 1110 Given = 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = 1100 0000 SADEN = 1111 1001 Given = 1100 0XX0 Slave 1 SADDR = 1110 0000 SADEN = 1111 1010 Given = 1110 0X0X Slave 2 SADDR = 1110 0000 SADEN = 1111 1100 Given = 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary t make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are teated as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. this effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature.

frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. Given or Broadcast Address. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. other modes, in any serial transmission. Must be cleared by software. the other modes, in any serial reception (except see SM2). Must be cleared by software. Figure 7. SCON: Serial Port Control Register Figure 8. UART Framing Error Detection

– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. Figure 9. UART Multiprocessor Communication, Automatic Address Recognition interrupt structure possible. The IPH is located at SFR address B7H. Table 7. Interrupt Table

Enable Bit = 1 enables the interrupt. enabled or disabled by setting or clearing its enable bit. IE.5 ET2 Timer 2 interrupt enable bit. IE.4 ES Serial Port interrupt enable bit. IE.3 ET1 Timer 1 interrupt enable bit. IE.2 EX1 External interrupt 1 enable bit. IE.1 ET0 Timer 0 interrupt enable bit. IE.0 EX0 External interrupt 0 enable bit. Figure 10. IE Registers IP.7 — Not implemented, reserved for future use. IP.5 PT2 Timer 2 interrupt priority bit. IP.4 PS Serial Port interrupt priority bit. IP.3 PT1 Timer 1 interrupt priority bit. IP.2 PX1 External interrupt 1 priority bit. IP.1 PT0 Timer 0 interrupt priority bit. IP.0 PX0 External interrupt 0 priority bit. Figure 11. IP Registers

allows the program code to switch between them.

• Register Name: AUXR1#
• SFR Address: A2H
• Reset Value: xxxxxxx0B 76543210 Where: DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1. Select Reg DPS DPTR0 0 DPTR1 1 The DPS bit status whould be saved by software when switching between DPTR0 and DPTR1. DPS DPTR1 DPTR0 DPH (83H) DPL (82H) EXTERNAL DATA MEMORY SU00745A BIT0 AUXR1

Figure 12. DPTR Structure

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

of this specification is not implied.

1. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise

Philips Semiconductors Product specification 80C52/80C54/80C58CMOS single-chip 8-bit microcontrollers DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5.0V ±10%; VSS = 0V SYMBOL PARAMETER TEST LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS MIN TYP 1 MAX UNIT VIH Input high voltage (ports 0, 1, 2, 3, EA) 0.2VCC +0.9 VCC +0.5 V VIH1 Input high voltage, XTAL1, RST 0.7VCC VCC +0.5 V VOL Output low voltage, ports 1, 2, 38 VCC = 4.5V IOL = 1.6mA2 0.4 V VOL1 Output low voltage, port 0, ALE, PSEN8, 7 VCC = 4.5V IOL = 3.2mA2 0.4 V VOH Output high voltage, ports 1, 2, 33 VCC = 4.5V IOH = –30µA VCC – 0.7 V VOH1 Output high voltage (port 0 in external bus mode), ALE 9, PSEN3 VCC = 4.5V IOH = –3.2mA VCC – 0.7 V IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4V –1 –50 µA ITL Logical 1-to-0 transition current, ports 1, 2, 36 VIN = 2.0V See note 4 –650 µA ILI Input leakage current, port 0 0.45 < VIN < VCC – 0.3 ±10 µA ICC Power supply current (see Figure 20): Active mode @ 16MHz5 Idle mode @ 16MHz5 Power-down mode See note 5 Tamb = 0 to +70°C Tamb = –40 to +85°C mA mA µA µA R RST Internal reset pull-down resistor 40 225 kΩ C IO Pin capacitance10 (except EA) 15 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V OL s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I OL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the (VCC –0.7) specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. See Figures 21 through 24 for ICC test conditions. Active Mode: ICC = 0.9 × FREQ + 1.1; Idle Mode: I CC = 0.18 × FREQ +1.0; See Figure 20. 6. This value applies to Tamb = 0°C to +70°C. For Tamb = –40°C to +85°C, ITL = –750µA. 7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15mA (*NOTE: This is 85 °C specification.) Maximum IOL per 8-bit port: 26mA Maximum total IOL for all outputs: 71mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1 , except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA it is 25pF).

Philips Semiconductors Product specification 80C52/80C54/80C58CMOS single-chip 8-bit microcontrollers AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3 16MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 13 Oscillator frequency Speed versions : E 3.5 16 MHz tLHLL 13 ALE pulse width 85 2tCLCL –40 ns tAVLL 13 Address valid to ALE low 22 tCLCL –40 ns tLLAX 13 Address hold after ALE low 32 tCLCL –30 ns tLLIV 13 ALE low to valid instruction in 150 4tCLCL –100 ns tLLPL 13 ALE low to PSEN low 32 tCLCL –30 ns tPLPH 13 PSEN pulse width 142 3tCLCL –45 ns tPLIV 13 PSEN low to valid instruction in4 82 3tCLCL –105 ns tPXIX 13 Input instruction hold after PSEN 0 0 ns tPXIZ 13 Input instruction float after PSEN 37 tCLCL –25 ns tAVIV 13 Address to valid instruction in4 207 5tCLCL –105 ns tPLAZ 13 PSEN low to address float 10 10 ns Data Memory tRLRH 14, 15 RD pulse width 275 6tCLCL –100 ns tWLWH 14, 15 WR pulse width 275 6tCLCL –100 ns tRLDV 14, 15 RD low to valid data in 147 5tCLCL –165 ns tRHDX 14, 15 Data hold after RD 0 0 ns tRHDZ 14, 15 Data float after RD 65 2tCLCL –60 ns tLLDV 14, 15 ALE low to valid data in 350 8tCLCL –150 ns tAVDV 14, 15 Address to valid data in 397 9tCLCL –165 ns tLLWL 14, 15 ALE low to RD or WR low 137 239 3tCLCL –50 3tCLCL +50 ns tAVWL 14, 15 Address valid to WR low or RD low 122 4tCLCL –130 ns tQVWX 14, 15 Data valid to WR transition 13 tCLCL –50 ns tWHQX 14, 15 Data hold after WR 13 tCLCL –50 ns tQVWH 15 Data valid to WR high 287 7tCLCL –150 ns tRLAZ 14, 15 RD low to address float 0 0 ns tWHLH 14, 15 RD or WR high to ALE high 23 103 tCLCL –40 tCLCL +40 ns External Clock tCHCX 17 High time 20 20 tCLCL –tCLCX ns tCLCX 17 Low time 20 20 tCLCL –tCHCX ns tCLCH 17 Rise time 20 20 ns tCHCL 17 Fall time 20 20 ns Shift Register tXLXL 16 Serial port clock cycle time 750 12tCLCL ns tQVXH 16 Output data setup to clock rising edge 492 10tCLCL –133 ns tXHQX 16 Output data hold after clock rising edge 8 2tCLCL –117 ns tXHDX 16 Input data hold after clock rising edge 0 0 ns tXHDV 16 Clock rising edge to input data valid 492 10tCLCL –133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 80C52/54/58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. See application note AN457 for external memory interfacing.

Philips Semiconductors Product specification 80C52/80C54/80C58CMOS single-chip 8-bit microcontrollers AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3 24MHz CLOCK VARIABLE CLOCK 4 33MHz CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX MIN MAX UNIT 1/tCLCL 13 Oscillator frequency Speed versions : I (24MHz) : N (33MHz) 3.5 24 3.5 33 3.5 33 MHz tLHLL 13 ALE pulse width 43 2tCLCL –40 21 ns tAVLL 13 Address valid to ALE low 17 tCLCL –25 5 ns tLLAX 13 Address hold after ALE low 17 tCLCL –25 ns tLLIV 13 ALE low to valid instruction in 102 4tCLCL –65 55 ns tLLPL 13 ALE low to PSEN low 17 tCLCL –25 5 ns tPLPH 13 PSEN pulse width 80 3tCLCL –45 45 ns tPLIV 13 PSEN low to valid instruction in 65 3tCLCL –60 30 ns tPXIX 13 Input instruction hold after PSEN 0 0 0 ns tPXIZ 13 Input instruction float after PSEN 17 tCLCL –25 5 ns tAVIV 13 Address to valid instruction in 128 5tCLCL –80 70 ns tPLAZ 13 PSEN low to address float 10 10 10 ns Data Memory tRLRH 14, 15 RD pulse width 150 6tCLCL –100 82 ns tWLWH 14, 15 WR pulse width 150 6tCLCL –100 82 ns tRLDV 14, 15 RD low to valid data in 118 5tCLCL –90 60 ns tRHDX 14, 15 Data hold after RD 0 0 0 ns tRHDZ 14, 15 Data float after RD 55 2tCLCL –28 32 ns tLLDV 14, 15 ALE low to valid data in 183 8tCLCL –150 90 ns tAVDV 14, 15 Address to valid data in 210 9tCLCL –165 105 ns tLLWL 14, 15 ALE low to RD or WR low 75 175 3tCLCL –50 3tCLCL +50 40 140 ns tAVWL 14, 15 Address valid to WR low or RD low 92 4tCLCL –75 45 ns tQVWX 14, 15 Data valid to WR transition 12 tCLCL –30 0 ns tWHQX 14, 15 Data hold after WR 17 tCLCL –25 5 ns tQVWH 15 Data valid to WR high 162 7tCLCL –130 80 ns tRLAZ 14, 15 RD low to address float 0 0 0 ns tWHLH 14, 15 RD or WR high to ALE high 17 67 tCLCL –25 tCLCL +25 5 55 ns External Clock tCHCX 17 High time 17 17 tCLCL –tCLCX ns tCLCX 17 Low time 17 17 tCLCL –tCHCX ns tCLCH 17 Rise time 5 5 ns tCHCL 17 Fall time 5 5 ns Shift Register tXLXL 16 Serial port clock cycle time 505 12tCLCL 360 ns tQVXH 16 Output data setup to clock rising edge283 10tCLCL –133 167 ns tXHQX 16 Output data hold after clock rising edge3 2tCLCL –80 ns tXHDX 16 Input data hold after clock rising edge0 0 0 ns tXHDV 16 Clock rising edge to input data valid 283 10tCLCL –133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 80C52/54/58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz “AC Electrial Characteristics”, page 20.

AVLL = Time for address valid to ALE low. tLLPL =Time for ALE low to PSEN low. Figure 13. External Program Memory Read Cycle Figure 14. External Data Memory Read Cycle

Figure 15. External Data Memory Write Cycle Figure 16. Shift Register Mode Timing Figure 17. External Clock Drive

AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Figure 18. AC Testing Input/Output OH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 19. Float Waveform Figure 20. ICC vs. FREQ

Figure 21. ICC Test Condition, Active Mode Figure 22. ICC Test Condition, Idle Mode Figure 23. Clock Signal Waveform for ICC Tests in Active and Idle Modes Figure 24. ICC Test Condition, Power Down Mode

programmed, in addition to the above, verify mode is disabled. 64 bytes of encryption array are initially unprogrammed (all 1s). Table 8. Program Security Bits 1 U U No Program Security features enabled. is sampled and latched on Reset, and further programming of the EPROM is disabled.

1. P – programmed. U – unprogrammed.
2. Any other combination of the security bits is not defined.
3. 64 byte ROM encryption key
4. External MOVC is disabled, and

Security Bit 2: When programmed, this bit inhibits Verify User ROM. If the ROM Code file does not include the options, the following information must be included with the ROM code. Encryption: No Yes If Yes, must send key file.

Philips Semiconductors Product specification 80C52/80C54/80C58CMOS single-chip 8-bit microcontrollers When submitting ROM code for the 80C54, the following must be specified: 1. 16k byte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS CONTENT BIT(S) COMMENT 0000H to 3FFFH DATA 7:0 User ROM Data 4000H to 401FH KEY 7:0 ROM Encryption Key FFH = no encryption 4020H SEC 0 ROM Security Bit 1 0 = enable security 1 = disable security 4020H SEC 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: Enabled Disabled Security Bit #2: Enabled Disabled Encryption: No Yes If Yes, must send key file.

Philips Semiconductors Product specification 80C52/80C54/80C58CMOS single-chip 8-bit microcontrollers When submitting ROM code for the 80C58, the following must be specified: 1. 32k byte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. If submitting a file, the format is as follows: ADDRESS CONTENT BIT(S) COMMENT 0000H to 7FFFH DATA 7:0 User ROM Data 8000H to 801FH KEY 7:0 ROM Encryption Key FFH = no encryption 8020H SEC 0 ROM Security Bit 1 0 = enable security 1 = disable security 8020H SEC 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. If the ROM code file does not include the options, the following information must be included with the ROM code. For each of the following check the appropriate box and send to Philips along with the code: Security Bit #1: Enabled Disabled Security Bit #2: Enabled Disabled Encryption: No Yes If Yes, must send key file.

Philips Semiconductors Product specification 80C52/80C54/80C58CMOS single-chip 8-bit microcontrollers DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

Philips Semiconductors Product specification 80C52/80C54/80C58CMOS single-chip 8-bit microcontrollers

1996 Aug 16 30

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

Philips Semiconductors Product specification 80C52/80C54/80C58CMOS single-chip 8-bit microcontrollers

1996 Aug 16 31

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2

Philips Semiconductors Product specification 80C52/80C54/80C58CMOS single-chip 8-bit microcontrollers Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Philips Semiconductors P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act.  Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A.