P650-U180-WH

P650-U BOURNS | Alldatasheet

Document overview

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• PDF pages: 6

Technical content

Features

■ Formerly brand ■ Extremely high speed performance ■ Blocks high voltages and currents ■ Low insertion loss ■ Two TBU™ protectors in one small package ■ Very high bandwidth; GHz compatible ■ RoHS compliant*, UL Recognized

Applications

■ Mb Ethernet port protection ■ Gb Ethernet port protection ■ Isolated and fl oating interfaces TBU ™ P650-U and P850-U Protectors *RoHS Directive 2002/95/EC Jan 27 2003 including Annex. Specifi cations are subject to change without notice. Customers should verify actual device performance in their specifi c applications. Transient Blocking Units - TBU™ Devices Bourns® Model P650-U and P850-U products are high speed, unidirectional protection components, constructed using MOSFET semiconductor technology, designed to protect against faults caused by short circuits, AC power cross, induction and lightning surges. The TBU ™ high speed protector, triggering as a function of the MOSFET, blocks surges and provides an effective barrier behind which sensitive electronics are not exposed to large voltages or currents during surge events. The TBU ™ device is provided in a surface mount DFN package and meets industry standard requirements such as RoHS and Pb Free solder refl ow profi les. Electrical Characteristics (Tamb = 25 °C) The P-U Series TBU™ devices are unidirectional; specifi cations are valid for input direction only. For the output direction, the TBU™ device is a resistor. Absolute Maximum Ratings (Tamb = 25 °C) Symbol Parameter Value Unit Vimp Maximum protection voltage for impulse faults with rise time ≥ 1 µsec P650-Uxxx-WH P850-Uxxx-WH 650 850 V Vrms Maximum protection voltage for continuous Vrms faults connected as a series pair (refer to page 3 Test Confi guration Diagram) P650-Uxxx-WH P850-Uxxx-WH 300 425 V Top Operating temperature range -40 to +85 °C Tstg Storage temperature range -65 to +150 °C Agency Approval UL recognized component File # E315805. Industry Standards Description Model Telcordia GR-1089 Port Type 3, 5 P650-U Port Type 2, 4 P850-U ITU-T K.20, K.20E, K.21, K.21E, K.45 P850-U Symbol Parameter Min. Typ. Max. Unit Iop Maximum current through the device that will not cause current blocking P650-U180-WH P650-U260-WH P850-U180-WH P850-U260-WH 180 260 180 260 mA I trigger Typical current for the device to go from normal operating state to protected state P650-U180-WH P650-U260-WH P850-U180-WH P850-U260-WH 220 330 220 330 mA I out Maximum current through the device P650-U180-WH P650-U260-WH P850-U180-WH P850-U260-WH 360 520 360 520 mA R TBU Series resistance of the TBU™ device P650-Uxxx-WH P850-Uxxx-WH 9 Ω Rbal Line-to line series resistance difference between two TBU™ device 0.5 Ω tblock Maximum time for the device to go from normal operating state to protected state P650-Uxxx-WH P850-Uxxx-WH 1µ s Iquiescent Current through the triggered TBU™ device with 50 Vdc circuit voltage 1m A Vreset Voltage below which the triggered TBU™ device will transition to normal operating state P650-Uxxx-WH P850-Uxxx-WH 11 14 V *RoHS COMPLIANT

Specifi cations are subject to change without notice. Customers should verify actual device performance in their specifi c applications. Typical Performance Characteristics TBU™ P650-U and P850-U Protectors V-I Characteristics Time to Block vs. Fault Current Trigger Current vs. Temperature Trigger Current Reset Voltage Threshold 1/R ITRIG I V 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 0.1 1 10 100 1000 Fault Current (A ) Time to Block (sec) 100 120 140 -40 -20 0 20 40 60 80 Temperature (°C) % of Trigger Current

TBU™ P650-U and P850-U Protectors Specifi cations are subject to change without notice. Customers should verify actual device performance in their specifi c applications. Operational Characteristics P650-U Lightning, 650 V P850-U Lightning, 850 V The graphs below demonstrate the operational characteristics of the TBU. For each graph the fault voltage, protected side voltage, and current is presented. P650-U Power Fault, 120 Vrms, 25 A P850-U Power Fault, 230 Vrms, 25 A V1 V2 Load 1 us/div. 100 V/div. 200 mA/div. Ch1 V1 Ch2 V2 Ch3 Current 1 us/div. 100 V/div. 200 mA/div. Ch1 V1 Ch2 V2 Ch3 Current 4 ms/div. 100 V/div. 200 mA/div. Ch1 V1 Ch2 V2 Ch3 Current 4 ms/div. 100 V/div. 200 mA/div. Ch1 V1 Ch2 V2 Ch3 Current TEST CONFIGURATION DIAGRAM

Specifi cations are subject to change without notice. Customers should verify actual device performance in their specifi c applications. TBU™ P650-U and P850-U Protectors Product Dimensions Recommended Pad Layout Pad # Apply

1 In1

3 Out1

4 Out2

6 In2

NC = Solder to PCB; do not make electrical connection, do not connect to ground. Pad Designation TBU™ devices have matte-tin termination fi nish. Suggested layout should use non-solder mask opening size 0.025 mm (.0010 in.) less than the device pad size. As when heat sinking any power device, it is recommended that, wherever possible, extra PCB copper area is allowed. For mini- mum parasitic capacitance, do not allow any signal, ground or power signals beneath any of the pads of the device. Block Diagram Thermal Resistances Symbol Parameter Value Unit Rth(j-a) Junction to leads (package) 105 °C/W Junction to leads (per TBU) 202 °C/W Refl ow Profi le Profi le Feature Pb-Free Assembly Average Ramp-Up Rate (Tsmax to Tp) 3 °C/sec. max. Preheat - Temperature Min. (Tsmin) - Temperature Max. (Tsmax) - Time (tsmin to tsmax) 150 °C 200 °C 60-180 sec. Time maintained above: - Temperature (TL) - Time (tL) 217 °C 60-150 sec. Peak/Classifi cation Temperature (Tp) 260 °C Time within 5 °C of Actual Peak Temp. (tp) 20-40 sec. Ramp-Down Rate 6 °C/sec. max. Time 25 °C to Peak Temperature 8 min. max. PIN 1 A B D C E J J N N H P GK L F TOP VIEW SIDE VIEW BOTTOM VIEW H DIMENSIONS: MM (INCHES) Dim. Min. Typ. Max. A 6.15 (.242) 6.25 (.246) 6.35 (.250) B 7.65 (.301) 7.75 (.305) 7.85 (.309) C 0.80 (.031) 0.85 (.033) 0.90 (.035) D 0.000 (.000) 0.025 (.001) 0.050 (.002) E 0.50 (.020) 0.55 (.022) 0.60 (.024) F 1.20 (.047) 1.25 (.049) 1.30 (.051) G 4.20 (.165) 4.25 (.167) 4.30 (.169) H 2.45 (.096) 2.50 (.098) 2.55 (.100) J 0.20 (.008) 0.25 (.010) 0.30 (.012) K 0.45 (.018) 0.50 (.020) 0.55 (.022) L 0.65 (.026) 0.70 (.028) 0.75 (.030) N 0.20 (.008) 0.25 (.010) 0.30 (.012) P 0.70 (.028) 0.75 (.030) 0.80 (.031) Q 3.20 (.126) 3.25 (.128) 3.30 (.130) 2.525 (.099) 0.50 (.020) 1.25 (.049) 0.575 (.023) 0.375 (.015) 0.70 (.028) 4.275 (.168) 6 4 1 3 TBU™ Device Line Side Load Side

Specifi cations are subject to change without notice. Customers should verify actual device performance in their specifi c applications. 3312 - 2 mm SMD Trimming Potentiometer TBU™ P650-U and P850-U Protectors Typical Part MarkingHow to Order P 650 - U 180 - WH Form Factor P = Two TBU ™ protectors in one device Impulse Voltage Rating 650 = 650 V 850 = 850 V Directional Indication for Paired Devices U = Unidirectional Iop Indicator 180 = 180 mA 260 = 260 mA Packaging Specifi cations (per EIA468-B) B A D C N F G (MEASURED AT HUB) USER DIRECTION OF FEED CENTER LINES OF CAVITY EMBOSSMENT t D TOP COVER TAPE E W P DIMENSIONS: MM (INCHES) Device A B C D G N P650-U, P850-U 326 (12.835) 330.25 (13.002) 1.5 (.059) 2.5 (.098) 12.8 (.504) 13.5 (.531) 20.2 (.795) - 16.5 (.650) 102 (4.016) Device A0 B 0 D D 1 E F P650-U, P850-U 6.5 (.256) 6.7 (.264) 8.0 (.315) 8.2 (.323) 1.5 (.059) 1.6 (.063) 1.5 (.059) - 1.65 (.065) 1.85 (.073) 7.4 (.291) 7.6 (.299) Device K0 P P 0 P 2 t W P650-U, P850-U 1.4 (.055) 1.6 (.063) 11.9 (.469) 12.1 (.476) 3.9 (.159) 4.1 (.161) 1.9 (.075) 2.1 (.083) 0.25 (.010) 0.35 (.014) 15.7 (.618) 16.3 (.642) QUANTITY: 3000 PIECES PER REEL MARKING NUMBER 65UB = P650-U180-WH 65UC = P650-U260-WH 85UB = P850-U180-WH 85UC = P850-U260-WH MANUFACTURER’S TRADEMARK*PIN 1 MANUFACTURING DATE CODE* - 1ST DIGIT INDICATES THE YEAR’S 6-MONTH PERIOD. - 2ND DIGIT INDICATES THE WEEK NUMBER IN THE 6-MONTH PERIOD. - 3RD & 4TH DIGITS INDICATE SPECIFIC LOT FOR THE WEEK. 6-MONTH PERIOD CODES: A = JAN-JUN 2009 C = JAN-JUN 2010 E = JAN-JUN 2011 B = JUL-DEC 2009 D = JUL-DEC 2010 F = JUL-DEC 2011 EXAMPLE: ARBC - 1ST DIGIT ‘A’ = JAN-JUN 2009 - 2ND DIGIT ‘R’ = WEEK 18; WEEK OF APRIL 27 - 3RD & 4TH DIGITS ‘BC’ = LOT SPECIFIC INFORMATION *TRANSITION FROM FULTEC TRADEMARK AND LOT CODE TO BOURNS TRADEMARK AND DATE CODE IN 2009.

2000 V, 22 pF 2000 V, 22 pF

TBU™ P650-U and P850-U Protectors Reference Applications A cost-effective protection solution utilizes the Bourns® TBU™ protection devices. The diagrams below illustrate common confi gurations of these components. The graph at the bottom demonstrates the operational characteristics of the circuit. Typical Confi guration Diagrams GbE Ethernet Protection Up to 1500 V Common-Mode Lightning Protection Asia-Pacifi c: Tel: +886-2 2562-4117  Fax: +886-2 2562-4116 Europe: Tel: +41-41 768 5555  Fax: +41-41 768 5510 The Americas: Tel: +1-951 781-5500  Fax: +1-951 781-5700 www.bourns.com COPYRIGHT©2008, BOURNS, INC. LITHO IN U.S.A. e 12/08 FU0801 REV. 03/10 P850-U with G5200AS 4000 V Lightning 10/700 µsec, 150 A GbE Ethernet Protection Up to 6000 V Common-Mode Lightning Protection 1 µs/div. 100 V/div. 200 mA/div. Ch1 V1 Ch2 V2 Ch3 Current Specifi cations are subject to change without notice. Customers should verify actual device performance in their specifi c applications.