P6049A INTERSIL | Alldatasheet
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Plastic Packages for Integrated Circuits Small Outline Transistor Plastic Packages (SC70-6) D E CL eb CL A2A A1 CL 0.20 (0.008) M 0.10 (0.004) C C -C- SEATING PLANE 12 3 456 E1CL C VIEW C VIEW C L R 4X θ1 4X θ1 GAUGE PLANE SEATING α L2C PLANE c BASE METAL WITH b1PLATING b P6.049A
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
A 0.031 0.039 0.80 1.00 - A1 0.001 0.004 0.025 0.10 - A2 0.034 0.036 0.85 0.90 - b 0.006 0.012 0.15 0.30 - b1 0.006 0.010 0.15 0.25 - c 0.004 0.008 0.10 0.20 6 c1 0.004 0.006 0.10 0.15 6 D 0.073 0.085 1.85 2.15 3 E 0.084 BSC 2.1 BSC - E1 0.045 0.053 1.15 1.35 3 e 0.0256 Ref 0.65 Ref - e1 0.0512 Ref 1.30 Ref - L 0.010 0.018 0.26 0.46 4 L1 0.016 Ref. 0.400 Ref. - L2 0.006 BSC 0.15 BSC - N6 6 5 R 0.004 - 0.10 - - α 0° 8° 0° 8° - Rev. 0 7/05 NOTES: 1. Dimensioning and tolerance per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO203AB. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. 4. Footlength L measured at reference to gauge plane. 5. “N” is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIME TER. Converted inch dimen- sions are for reference only