Microcontroller

P5LS10116ASPGETQ1R

Texas Instruments

16/32-BIT RISC Flash Microcontroller

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PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010 TMS570LSSeries16/32-BITRISCFlashMicrocontroller Check forSamples: TMS570LS20216 ,TMS570LS20206 ,TMS570LS10216 ,TMS570LS10206 ,TMS570LS10116 ,TMS570LS10106

1 TMS570LS Series16/32-BITRISC FlashMicrocontroller

1.1 Features

High-PerformanceAutomotive Grade • Communication Interfaces MicrocontrollerforSafetyCriticalApplications – Three Multi-bufferedSerialPeripheral – Certifiedforuse inSIL3 Applications Interface(MibSPI)each with: – Dual CPU ’s runninginLockstep • Four chipselectsand one Enable pin – ECC on Flashand SRAM • 128 bufferswithparity – CPU and Memory BIST (Built-InSelfTest) • One withparallelmode – ErrorSignalingModule (ESM) w/ ErrorPin – Two UART (SCI)interfaceswithLocal InterconnectNetwork Interface(LIN2.0)• ARM ® Cortex™ -R4F 32-BitRISC CPU – Three CAN (DCAN) Controller– Efficient1.6DMIPS/MHz with8-stage pipeline • Two with64 mailboxes,one with32 – FloatingPointUnitwithSingle/Double • Parityon mailbox RAM Precision – Dual Channel FlexRay™ Controller – Memory ProtectionUnit(MPU) • 8K-Byte message RAM withparity – Open ArchitectureWith Third-PartySupport • TransferUnitwithMPU and parity
OperatingFeatures • High-End Timer (nHET) – Up to160-MHz System Clock – 32 Programmable I/OChannels – Core Supply Voltage(VCC ):1.5V – 128 Words High-End Timer RAM withparity – I/OSupply Voltage(VCCIO ):3.3V – TransferUnitwithMPU and parity
IntegratedMemory • Two 12-BitMulti-BufferedADCs (MibADC) – 1M-Byte or 2M-Byte FlashwithECC – 24 totalADC Inputchannels – 128K-Byte or 160K-Byte RAM withECC – Each has 64 Bufferswithparity
MultipleCommunication interfacesincluding • Trace and CalibrationInterfaces Flexray,CAN, and LIN – Embedded Trace Module (ETMR4)
NHET Timer and 2x 12-bitADC's – Data ModificationModule (DMM)
ExternalMemory Interface(EMIF) – RAM Trace Port(RTP) – 16bitData,22bitAddress,4 Chip Selects – Parameter OverlayModule (POM)
Common TMS470/570 PlatformArchitecture • On-Chip emulationlogicincludingIEEE 1149.1 – ConsistentMemory Map across thefamily JTAG, Boundary Scan and ARM Coresight – Real-TimeInterrupt(RTI)OS Timer components – VectoredInterruptModule (VIM) • FullDevelopment KitAvailable – CyclicRedundancy Checker (CRC) – Development Boards
DirectMemory Access (DMA) Controller – Code Composer StudioIntegrated Development Environment (IDE)– 32 ControlPackets and 16 Channels – HaLCoGen Code GenerationTool– Parityon ControlPacket Memory – HET Assembler and Simulator– DedicatedMemory ProtectionUnit(MPU) – nowFlash FlashProgramming Tool• Frequency-ModulatedZero-PinPhase-Locked Loop (FMZPLL)-Based Clock Module • Packages Supported – Oscillatorand PLL clockmonitor – 144-PinQuad Flatpack(PGE) [Green]
Up to115 PeripheralIO pins – 337-PinBallGridArray(ZWT) [Green] – 16 DedicatedGIO -8 w/ ExternalInterrupts • Community Resources – Programmable ExternalClock (ECLK) – TIE2E Community Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCT PREVIEW informationconcernsproductsintheformative Copyright© 2010,Texas InstrumentsIncorporatedor design phase of development.Characteristicdata and other specificationsaredesigngoals.Texas Instrumentsreservestheright tochange ordiscontinuetheseproductswithoutnotice.

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1.2 Description

The TMS570LS seriesisa highperformanceautomotivegrade microcontrollerfamilywhich has been certifiedforuse in IEC 61508 SIL3 safetysystems.The safetyarchitectureincludesDual CPUs in lockstep,CPU and Memory Built-InSelfTest(BIST)logic,ECC on boththeFlashand thedataSRAM, parityon peripheralmemories,and loopback capabilityon peripheralIOs. The TMS570LS familyintegratestheARM ® Cortex™ -R4F FloatingPointCPU whichoffersan efficient1.6 DMIPS/MHz, and has configurationswhichcan runup to160 MHz providingmore than250 DMIPS. The TMS570LS seriesalsoprovidesdifferentFlash(1MB or2MB) and dataSRAM (128KB or160KB) options withsinglebiterrorcorrectionand doublebiterrordetection. The TMS570LS devicesfeatureperipheralsforreal-timecontrol-basedapplications,includingup to 32 nHET timerchannelsand two 12-bitA to D converterssupportingup to 24 inputs.There are multiple communicationinterfacesincludinga 2-channelFlexray,3 CAN controllerssupporting64 mailboxeseach, and 2 LIN/UART controllers. WithintegratedSIL3 certifiedsafetyfeaturesand a wide choiceofcommunicationand controlperipherals, theTMS570LS seriesisan idealsolutionforhighperformancerealtimecontrolapplicationswithsafety criticalrequirements. The devicesincludedintheTMS570LS seriesand describedinthisdocument are:

TMS570LS20216
TMS570LS20206
TMS570LS10216
TMS570LS10206
TMS570LS10116
TMS570LS10106 The TMS570LS seriesmicrocontrollerscontainthefollowing:
DualTMS570 16/32-BitRISC (ARM Cortex™ -R4F)inLockstep
Up to2M-ByteProgram FlashwithECC
Up to160K-ByteStaticRAM (SRAM) withECC
Real-TimeInterrupt(RTI)OperatingSystem Timer
VectoredInterruptModule (VIM)
CyclicRedundancy Checker(CRC) withParallelSignatureAnalysis(PSA)
DirectMemory Access (DMA) Controller
Frequency-ModulatedPhase-LockedLoop (FMZPLL)-Based ClockModule WithPrescaler
ThreeMulti-bufferedSerialPeripheralInterfaces(MibSPI)
Two UARTs (SCI)withLocalInterconnectNetworkInterfaces(LIN)
ThreeCAN Controllers(DCAN)
High-EndTimer(NHET) withdedicatedTransferUnit(HTU)
AvailableFlexRayControllerwithdedicatedPLL and TransferUnit(FTU)
ExternalClockPrescale(ECP) Module
Two 16-Channel12-BitMulti-BufferedADCs (MibADC) -8 sharedchannelsbetween thetwo ADCs
System Bus ParitywithFailureDetection
ErrorSignalingModule (ESM) withexternalerrorpin
VoltageMonitor(VMON) withoutofrangeresetassertion
Embedded TraceModule (ETMR4)
Data ModificationModule (DMM)
RAM TracePort(RTP)
ParameterOverlayModule (POM)

2 TMS570LS Series16/32-BITRISC FlashMicrocontroller Copyright© 2010,Texas InstrumentsIncorporated

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16 DedicatedGeneral-PurposeI/O(GIO)PinsforZWT; 8 DedicatedGIO PinsforPGE
115 TotalPeripheralI/OsforZWT; 68 TotalPeripheralI/OsforPGE
16-BitExternalMemory Interface(EMIF) The devicesutilizethebig-endianformatwhere themost significantbyteofa word isstoredatthelowest numbered byteand theleastsignificantbyteatthehighestnumbered byte. The devicememory includesgeneral-purposeSRAM supportingsingle-cycleread/writeaccessesinbyte, halfword,and word modes. The flashmemory on thisdeviceisa nonvolatile,electricallyerasableand programmable memory implementedwitha 64-bit-widedatabus interface.The flashoperateson a 3.3V supplyinput(same levelas I/O supply)forallread,program and erase operations.When in pipeline mode, theflashoperateswitha systemclockfrequencyofup to160 MHz. The devicehas nine communicationinterfaces:threeMibSPIs,two LIN/SCIs,threeDCANs and one FlexRay™ controller(optional).The SPI providesa convenientmethod ofserialinteractionforhigh-speed communicationsbetween similarshift-registertype devices.The LIN supportsthe Local Interconnect standard2.0 and can be used as a UART infull-duplexmode usingthe standardNon-Return-to-Zero (NRZ) format.The DCAN supportsthe CAN 2.0B protocolstandardand uses a serial,multimaster communicationprotocolthatefficientlysupportsdistributedreal-timecontrolwithrobustcommunication ratesofup to1 megabitper second (Mbps).The DCAN isidealforapplicationsoperatinginnoisyand harsh environments(e.g.,automotiveand industrialfields)thatrequirereliableserialcommunicationor multiplexedwiring.The FlexRay uses a dualchannelserial,fixedtimebase multimastercommunication protocolwithcommunicationratesof 10 megabitsper second (Mbps) per channel.A FlexRay Transfer Unit(FTU) enablesautonomous transfersofFlexRaydatatoand frommain CPU memory. Transfersare protectedby a dedicated,built-inMemory ProtectionUnit(MPU). The NHET is an advanced intelligenttimerthatprovidessophisticatedtimingfunctionsforreal-time applications.The timerissoftware-controlled,usinga reduced instructionset,witha specializedtimer micromachineand an attachedI/O port.The NHET can be used forpulsewidthmodulated outputs, captureor compare inputs,or general-purposeI/O..Itisespeciallywellsuitedforapplicationsrequiring multiplesensorinformationand driveactuatorswithcomplex and accuratetimepulses.A High End Timer TransferUnit(HET-TU) providesfeaturesto transferNHET data to or from main memory. A Memory ProtectionUnit(MPU) isbuiltintotheHET-TU toprotectagainsterroneoustransfers. The devicehas two 12-bit-resolutionMibADCs with24 totalchannelsand 64 words of parityprotected bufferRAM each.The MibADC channelscan be convertedindividuallyorcan be groupedby softwarefor sequentialconversionsequences.Eightchannelsare shared between the two ADCs. There are three separategroupings,two ofwhicharetriggerableby an externalevent.Each sequence can be converted once when triggeredorconfiguredforcontinuousconversionmode. The frequency-modulatedphase-lockedloop (FMZPLL) clockmodule containsa phase-lockedloop,a clock-monitorcircuit,a clock-enablecircuit,and a prescaler.The functionoftheFMZPLL istomultiplythe externalfrequencyreferencetoa higherfrequencyforinternaluse.The FMZPLL providesone ofthesix possibleclocksourceinputstotheglobalclockmodule (GCM). The GCM module providessystem clock (HCLK), real-timeinterruptclock(RTICLK1),CPU clock(GCLK), NHET clock(VCLK2), DCAN clock (AVCLK1),and peripheralinterfaceclock(VCLK) toallotherperipheralmodules. The devicealsohas an externalclockprescaler(ECP) module thatwhen enabled,outputsa continuous externalclockon the ECLK pin.The ECLK frequencyisa user-programmableratioof the peripheral interfaceclock(VCLK) frequency. The DirectMemory Access Controller(DMA) has 16 channels,32 controlpacketsand parityprotectionon itsmemory. The DMA providesmemory to memory transfercapabilitieswithoutCPU interaction.A Memory ProtectionUnit(MPU) isbuiltintotheDMA toprotectmemory againsterroneoustransfers. The ErrorSignalingModule (ESM) monitorsalldeviceerrorsand determineswhether an interruptor externalErrorpinistriggeredwhen a faultisdetected. Copyright© 2010,Texas InstrumentsIncorporated TMS570LS Series16/32-BITRISC FlashMicrocontroller 3 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com The ExternalMemory Interface(EMIF)providesa memory extensiontoasynchronousmemories orother slavedevices. Severalinterfacesareimplementedtoenhance thedebuggingcapabilitiesofapplicationcode.Inaddition to the builtin ARM Cortex™ -R4F CoreSight™ debug features,an ExternalTrace Macrocell(ETM) providesinstructionand datatraceofprogramexecution.Forinstrumentationpurposes,a RAM TracePort Module (RTP) isimplementedtosupporthigh-speedoutputofRAM accessesby theCPU or any other master.A DirectMemory Module (DMM) givestheabilitytowriteexternaldataintothedevicememory. BoththeRTP and DMM have no oronlyminimum impacton theprogramexecutiontimeoftheapplication code.A ParameterOverlayModule (POM) can re-routeFlashaccesses to the EMIF, thusavoidingthe re-programmingstepsnecessaryforparameterupdatesinFlash.

4 TMS570LS Series16/32-BITRISC FlashMicrocontroller Copyright© 2010,Texas InstrumentsIncorporated

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PRODUCT□PREVIEW Flash 2.0MB with ECC CRC OSC NHET SYS LIN2 MiBSPI1 DCAN1 OSCIN OSCOUT TRST TMS TCK TDI TDO RST PORRST TEST NHET[31:0] LIN2RX LIN2TX MIBSPI1SIMO MIBSPI1SOMI MIBSPI1CLK MIBSPI1SCS[3:0] CAN1RX CAN1TX FLTP1 ECLK MIBSPI3SIMO MIBSPI3SOMI MIBSPI3CLK DCAN2 CAN2RX CAN2TX

128 Words

128 Buffers

MIBSPI3SCS[3:0] VIM HET TU

8 DCP

64 Messages

16 Channels

RTPDATA[15:0] RTPSYNCRTPCLK

1 Port

ETMDATA[31:0] MIBSPI3ENA FLTP2 with MPU RTPENA

8 Transfer

64 Channel

2 Channel

Kelvin_GND DAP DMMENA DMMSYNC DMMCLK DMMDATA[1:0] with Parity Periph Bridge Cortex-R4F Msg RAM Flexray with MPU with Parity RTI SCR2 TU SCR1 Note: Priorities SCR2 : round robin SCR : round robin SCR1 : 1=DMA, 2=DMM, 3=DAP DMMDATA[15:2]* MiBADC2

64 Words

AD2IN[7:0] AD2EVT MiBSPIP5 MIBSPI5SIMO[3:0]* MIBSPI5SOMI[3:0]* MIBSPI5CLK* MIBSPI5SCS[3:0]* MIBSPI5ENA*

32 Regions

with DMMDATA[15:2] pins

2 RAM blocks

AD1IN[7:0] V SSAD AD REFHI AD REFLO AD1EVT 12Bit 12Bit with MPU Cortex-R4F with MPU GIO GIOA[7:0]/INT[7:0] GIOB[7:0] LIN1 LIN1RX LIN1TX STC LBIST EMIFADD[21:0] EMIFDATA[15:0] EMIFCS[3:0] EMIFWE EMIFOE EMIF EMIFBADD[1:0] V CCAD ADSIN[15:8] P O M * MIBSPIP5 pins are multiplexed ETMTRACECLKIN EMIFDQM[1:0] SCR PCR FPLL for Flexray VMONVccIO Vcc TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010

1.3 FunctionalBlock Diagram

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6 Contents Copyright© 2010,Texas InstrumentsIncorporated

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2 Device Overview

2.1 Device Characteristics

The tablebelowshows thedifferentconfigurationsoptionsofferedintheTMS570LS seriesofdevices: Table2-1.CharacteristicsoftheTMS570LS SeriesDevices Feature TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Package 337 144 QFP 337 144 QFP 337 144 QFP 337 144 QFP 337 144 QFP 337 144 QFP BGA BGA BGA BGA BGA BGA Type (ZWT) (PGE) (ZWT) (PGE) (ZWT) (PGE) (ZWT) (PGE) (ZWT) (PGE) (ZWT) (PGE) Speed 160MHz 140MHz 160MHz 140MHz 160MHz 140MHz 160MHz 140MHz 160MHz 140MHz 160MHz 140MHz Flash 2MB 2MB 2MB 2MB 1MB 1MB 1MB 1MB 1MB 1MB 1MB 1MB Size RAM Size 160KB 160KB 160KB 160KB 160KB 160KB 160KB 160KB 160KB 160KB 128KB 128KB FlexRay 2ch 2ch - - 2ch 2ch - - 2ch 2ch - - CAN 3 2 3 2 3 2 3 2 3 2 3 2 MibSPI 3 3 3 3 3 3 3 3 3 3 3 3 UART / 2 2 2 2 2 2 2 2 2 2 2 2 LIN NHET 32 25 32 25 32 25 32 25 32 25 32 25 Channels

12 Bit 24 20 24 20 24 20 24 20 24 20 24 20

EMIF 16-bit - 16-bit - 16-bit - 16-bit - 16-bit - 16-bit - GIO 16 8 16 8 16 8 16 8 16 8 16 8 ETM 32-bit - 32-bit - 32-bit - 32-bit - 32-bit - 32-bit - RTP 16-bit - 16-bit - 16-bit - 16-bit - 16-bit - 16-bit - DMM 16-bit - 16-bit - 16-bit - 16-bit - 16-bit - 16-bit - Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 7 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW Flash (2MB) RAM (160kB) 0x00000000 0x001FFFFF 0x08000000 0x08027FFF CRC0xFE000000 0xFEFFFFFF Peripherals0xFF000000 0xFFF7FFFF SYSTEM Modules0xFFF80000 0xFFFFFFFF Flash-ECC 0x00400000 0x004FFFFF RAM - ECC 0x08400000 0x08427FFF EMIF (256MB) 0x60000000 0x6FFFFFFF CS1 CS0 CS2 CS3 0x60000000 POM (4MB) 0x603FFFFF Flash (2MB) 0x20000000 0x201FFFFF Flash - ECC 0x20400000 0x204FFFFF RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Flash (1MB) RESERVED 0x00000000 0x000FFFFF 0x001FFFFF (2MB) Flash - ECC (1MB) 0x00400000 0x0047FFFF 0x004FFFFFRESERVED RAM (128kB) RESERVED 0x08000000 0x0801FFFF 0x08027FFF (160kB) RAM - ECC(128kB) RESERVED 0x08400000 0x08427FFF 0x08401FFF (Mirrored Image) Flash (1MB) (Mirrored Image) RESERVED 0x20000000 0x201FFFFF 0x200FFFFF (2MB Mirrored Image) Flash - ECC(1MB) RESERVED 0x20400000 0x204FFFFF 0x2047FFFF (a) (a) (a) (a) (b) (b) (b) (b) ( )c ( )c (d) (d) (a) 2MB Flash Devices (b) 1MB Flash Devices ( ) 160kB RAM Devices (d) 128kB RAM Devices c TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com

2.2 Memory

2.2.1 Memory Map

The memory map includingallavailableFlashand RAM memory configurationsforthedevicefamilyare shown intheFigure2-1figurebelow. Figure2-1.Memory Map

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PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010 The ParameterOverlaymemory space maps to the lower4MB of the EMIF CS0 memory space.ECC must be disabledby softwareviatheCPU CP15 registerifPOM isused tooverlaytheprogram memory to the EMIF space;otherwiseECC errorswillbe generated.The contentsof memory connectedto the EMIF are notguaranteedaftera power on reset.The addressableEMIF memory range islimitedtothe lower32MB ofeach EMIF chipselectfor16bitmemories,and tothelower16MB ofeach EMIF chipselect for8bitmemories.The defaultEMIF datawidthis16bit. Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 9 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

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2.2.2 FlashMemory

The F035 (130nm FlashProcess)Flashmemory isa nonvolatileelectricallyerasableand programmable memory. The Flashhas a statemachine forsimplifyingtheprogramand erasefunctions. Thisdevice’s 2M-byteflashmemory containsfour512K-bytememory arrays(orbanks)consistingof22 totalsectors.1M-byteversionsofthedevicecontainonlythefirsttwo 512K-bytebanks (Bank 0 and Bank 1)and have a totalof14 sectors.The bank and sectorconfigurationsareshown inFlashMemory Banks and Sectors.When inpipelinemode, theFlashoperateswitha system clockfrequencyofup to160MHz (versusa system clockinnon-pipelinemode ofup to36MHz). The flashinpipelinemode iscapableof accessing128 bitsata timeand providestwo 64-bitpipelinedwords totheCPU. The minimum sizeforan erase operationisone sector.A singleprogram operationcan program eitherone 32-bitword or one 16-bithalfword ata time. Table2-2.FlashMemory Banks and Sectors MEMORY ARRAYS (ORSectorNO. Segment Low Address High address BANKS) Bank 0:512K Bytes 0 32K Bytes 0x0000_0000 0x0000_7FFF 1 32K Bytes 0x0000_8000 0x0000_FFFF 2 32K Bytes 0x0001_0000 0x0001_7FFF 3 8K Bytes 0x0001_8000 0x0001_9FFF 4 8K Bytes 0x0001_A000 0x0001_BFFF BANK0 (512kBytes) 5 16K Bytes 0x0001_C000 0x0001_FFFF 6 64K Bytes 0x0002_0000 0x0002_FFFF 7 64K Bytes 0x0003_0000 0x0003_FFFF 8 128K Bytes 0x0004_0000 0x0005_FFFF 9 128K Bytes 0x0006_0000 0x0007_FFFF Bank 1:512K Bytes 0 128K Bytes 0x0008_0000 0x0009_FFFF 1 128K Bytes 0x000A_0000 0x000B_FFFF BANK1 (512kBytes) 2 128K Bytes 0x000C_0000 0x000D_FFFF 3 128K Bytes 0x000E_0000 0x000F_FFFF Bank 2:512K Bytes 0 128K Bytes 0x0010_0000 0x0011_FFFF 1 128K Bytes 0x0012_0000 0x0013_FFFF BANK2 (512kBytes) 2 128K Bytes 0x0014_0000 0x0015_FFFF 3 128K Bytes 0x0016_0000 0x0017_FFFF Bank 3:512K Bytes 0 128K Bytes 0x0018_0000 0x0019_FFFF 1 128K Bytes 0x001A_0000 0x001B_FFFF BANK3 (512kBytes) 2 128K Bytes 0x001C_0000 0x001D_FFFF 3 128K Bytes 0x001E_0000 0x001F_FFFF NOTE The externalflashpump voltage(VccP)isrequiredforallflashoperations(program,erase, and read). NOTE Aftera system reset,pipelinemode isdisabled(FRDCNTL[2:0]isa "000").Inotherwords, thedevicepowers up and comes outofresetinnon-pipelinemode.

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2.2.3 System Modules Assignment

Thistableshows the memory map forthe CyclicRedundancy Check (CRC) module,the Cortex™ -R4F CoreSight™ debug module,and theSystem modules. Table2-3.System Modules Assignment Frame Name Address Range Frame StartAddress Frame Ending Address CRC 0xFE00_0000 0xFEFF_FFFF CoreSightDebug ROM Register 0xFFA0_0000 0xFFA0_0FFF Cortex-R4FDebug Register 0xFFA0_1000 0xFFA0_1FFF ETM-R4 Register 0xFFA0_2000 0xFFA0_2FFF CoreSightTPIU Register 0xFFA0_3000 0xFFA0_3FFF POM Register 0xFFA0_4000 0xFFA0_4FFF DMA RAM 0xFFF8_0000 0xFFF8_0FFF VIM RAM 0xFFF8_2000 0xFFF8_2FFF RTP RAM 0xFFF8_3000 0xFFF8_3FFF FlashWrapper Register 0xFFF8_7000 0xFFF8_7FFF PCR Register 0xFFFF_E000 0xFFFF_E0FF FlexrayPLL/STC CLK Register 0xFFFF_E100 0xFFFF_E1FF PBIST Register 0xFFFF_E400 0xFFFF_E5FF STC Register 0xFFFF_E600 0xFFFF_E6FF EMIF Register 0xFFFF_E800 0xFFFF_E8FF DMA Register 0xFFFF_F000 0xFFFF_F3FF ESM Register 0xFFFF_F500 0xFFFF_F5FF CCMR4 Register 0xFFFF_F600 0xFFFF_F6FF DMM Register 0xFFFF_F700 0xFFFF_F7FF RAM ECC even Register 0xFFFF_F800 0xFFFF_F8FF RAM ECC odd Register 0xFFFF_F900 0xFFFF_F9FF RTP Register 0xFFFF_FA00 0xFFFF_FAFF RTI Register 0xFFFF_FC00 0xFFFF_FCFF VIM ParityRegister 0xFFFF_FD00 0xFFFF_FDFF VIM Register 0xFFFF_FE00 0xFFFF_FEFF System Register 0xFFFF_FF00 0xFFFF_FFFF Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 11 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

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2.2.4 PeripheralSelects

The peripheralframe containsthe memory map forthe peripheralregistersas wellas the peripheral memories.The firsttableshows thememory map fortheperipheralmodule registersand followingtable shows thememory map fortheperipheralmodule memories. Table2-4.PeripheralSelectAssignment PeripheralModule Address Range PeripheralSelects Base Address Ending Address MIBSPIP5 0xFFF7_FC00 0xFFF7_FDFF PS[0] MIBSPI3 0xFFF7_F800 0xFFF7_F9FF PS[1] MIBSPI1 0xFFF7_F400 0xFFF7_F5FF PS[2] LIN2 0xFFF7_E500 0xFFF7_E5FF PS[6] LIN1 0xFFF7_E400 0xFFF7_E4FF DCAN3 0xFFF7_E000 0xFFF7_E1FF PS[7] DCAN2 0xFFF7_DE00 0xFFF7_DFFF PS[8] DCAN1 0xFFF7_DC00 0xFFF7_DDFF Flexray 0xFFF7_C800 0xFFF7_CFFF PS[12]+PS[13] MIBADC2 0xFFF7_C200 0xFFF7_C3FF PS[15] MIBADC1 0xFFF7_C000 0xFFF7_C1FF GIO 0xFFF7_BC00 0xFFF7_BCFF PS[16] NHET 0xFFF7_B800 0xFFF7_B8FF PS[17] HET TU 0xFFF7_A400 0xFFF7_A4FF PS[22] FlexrayTU 0xFFF7_A000 0xFFF7_A1FF PS[23] Table2-5.PeripheralMemory Selects PeripheralModule Memory Address Range PeripheralSelects Base Address Ending Address MIBSPIP5 RAM 0xFF0A0000 0xFF0BFFFF PCS[5] MIBSPI3 RAM 0xFF0C0000 0xFF0DFFFF PCS[6] MIBSPI1 RAM 0xFF0E0000 0xFF0FFFFF PCS[7] DCAN3 RAM 0xFF1A0000 0xFF1BFFFF PCS[13] DCAN2 RAM 0xFF1C0000 0xFF1DFFFF PCS[14] DCAN1 RAM 0xFF1E0000 0xFF1FFFFF PCS[15] MIBADC2 RAM 0xFF3A0000 0xFF3BFFFF PCS[29] MIBADC1 RAM 0xFF3E0000 0xFF3FFFFF PCS[31] NHET RAM 0xFF460000 0xFF47FFFF PCS[35] HET TU RAM 0xFF4E0000 0xFF4FFFFF PCS[39] FlexrayTU RAM 0xFF500000 0xFF51FFFF PCS[40]

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2.2.5 Memory Auto-Initialization

Thisdeviceallowssome oftheon-chipmemories tobe initializedviathememory hardwareinitialization controlregistersintheSystem module.The purposeofhavingthehardwareinitializationistoprogram the memory arrayswitherrordetectioncapabilityto a known statebased on theirerrordetectionscheme (odd/evenparityor ECC). The MINITGCR registerenablesthe memory initializationsequence,and the MSINENA registerselectsthememories thataretobe initialized.PleaserefertotheArchitecturechapter oftheTechnicalReferenceManual (TRM) formore information. The mapping of the differentmemories to the specificbitsin the MSINENA registerisshown in the followingtable. Table2-6.Memory Initialization Connecting Module Address Range RAM Select Base Address Ending Address RAM 0x08000000 0x0801FFFF 0 MIBSPIP5 RAM 0xFF0A0000 0xF0BFFFFF 12 MIBSPI3 RAM 0xFF0C0000 0xFF0DFFFF 11 MIBSPI1 RAM 0xFF0E0000 0xFF0FFFFF 7 DCAN3 RAM 0xFF1A0000 0xFF1BFFFF 10 DCAN2 RAM 0xFF1C0000 0xFF1DFFFF 6 DCAN1 RAM 0xFF1E0000 0xFF1FFFFF 5 FlexrayRAM RAM isnotvisible 9 MIBADC2 RAM 0xFF3A0000 0xFF3BFFFF 14 MIBADC1 RAM 0xFF3E0000 0xFF3FFFFF 8 NHET RAM 0xFF460000 0xFF47FFFF 3 HET TU RAM 0xFF4E0000 0xFF4FFFFF 4 DMA RAM 0xFFF80000 0xFFF80FFF 1 VIM RAM 0xFFF82000 0xFFF82FFF 2 FlexrayTU RAM 0xFF500000 0xFF51FFFF 13 Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 13 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

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2.2.6 PBIST RAM SelfTest

The PBIST (Programmable Built-InSelfTest)architectureprovidesa run-time-programmablememory BIST engineforvaryinglevelsoftestcoverageacrossthedevice’s embedded RAM memory. The PBIST architectureconsistsof a smallCPU withan instructionset targetedspecificallytowardstestingRAM memories.ThisCPU includesboth controland instructionregistersnecessaryto executethe individual memory algorithms.In order to minimizetestload overhead,once an algorithmis loaded intothe instructionregisters,itcan be run on multiplememories of differentsizesor types.The memory configurationinformationand testalgorithmcode isstoredinan on-chipROM. The PBIST RAM groups implementedon thisdeviceareshown inthefollowingtable.More informationaboutmemory selftestcan be foundinthePBIST chapterofthedeviceTRM. Table2-7.PBIST RAM Grouping RAM Module Memory RGS/RD TestPattern(Algorithm) Group Type S Triple Triple March Down 1A Pre- Map DTXN 2A PMOS slow fastread 13N[cycl charge column open read es]

1 PBIST ROM 0/1 x x

2 STC ROM 13/1 x x

3 DCAN1 SP 1/0..2 12600 x x x x x 4 DCAN2 SP 2/0..2 12600 x x x x x 5 DCAN3 SP 3/0..2 6360 x x x x x 6 ESRAM SP, 4/21..22 266320 x x x x x multi- strobew/ page mode 7 MibSPI SP 5/0..5 50160 x x x x x

8 VIM SP Jun-00 4200 x x x x x

9 MibADC 2P,sync 7/0..1 8400 x x x x x write async read 10 DMA 2P,sync 8/0..5 18960 x x x x x write async read 11 NHET 2P,sync 9/0..11 25440 x x x x x write async read 12 HET TU 2P,sync 10/0..5 6480 x x x x x write async read 13 RTP 2P,sync 11/0..8 37800 x x x x x write async read 14 Flexray SP 12/0..7 175040 x x x x x

15 ESRAM SP, 20-Apr 133160 x x x x x

SP = SinglePortRAM; 2P = Two PortRAM

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The March13N testalgorithmisrecommended forapplicationtesting.
The maximum PBIST testexecutionspeed islimitedto100MHz.
The supplycurrentwhileperformingPBIST selftestisdifferentthanthedeviceoperating mode current.These valuescan be foundintheIcc sectionofthedeviceelectrical specifications. Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 15 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW (TOP VIEW) FRA YTXEN2 GIOA[3]/INT[3] 144 143 141 140 139 138 137 136 135 134GIOA[1]/INT[1] 133VSSIO 132 131FRA YRX2 130 129 128 127 126 125 124 123 122 121 VSSIO 120 VCCIO 119 GIOA[0]/INT[0] 118 117 116 115 114 NHET[15] 113 112 VCC VSS VSSIO VCCIO NHET[3] NHET[1] NHET[24] NHET[5] NHET[20] VSS VCC NHET[6] CAN1RX VCCAD 111 110 109 NHET[8] LIN1TX LIN1RX CAN2TX CAN2RX NHET[2] TEST AD2EVT AD2IN[0] AD2IN[1] AD2IN[2] AD2IN[3] VSSAD ADREFLO ADREFHI ADSIN[15] ADSIN[13] ADSIN[14] ADSIN[12] ADSIN[11] nERROR NHET[16] GIOA[2]/INT[2] LIN2RX LIN2TX NHET[14] NHET[30] VSS FRA YTX2 VCCP VSS FRA YRX1 FRA YTXEN1 FRA YTX1 FL TP2 FL TP1 NHET[11] NHET[10] VSS GIOA[5]/INT[5] GIOA[4]/INT[4] NHET[7] NHET[4] VCCIO VCC GIOA[7]/INT[7] NHET[9] CAN1TX 142 ADSIN[10]ADSIN[9]ADSIN[8]AD1IN[7]AD1IN[6]AD1IN[5]AD1IN[4]AD1IN[3]AD1IN[2]AD1IN[1]AD1IN[0]AD1EVTnRSTVSS ECLKVSSIOVCCIODMMDA T A[4]/MIBSPI5CLKDMMDA T A[5]/nMIBSPI5CS[0]DMMDA T A[7]/nMIBSPI5ENADMMDA T A[8]/MIBSPI5SIMO[0]DMMDA T A[9]/MIBSPI5SIMO[1]DMMDA T A[10]/MIBSPI5SIMO[2]DMMDA T A[11]/MIBSPI5SIMO[3]DMMDA T A[12]/MIBSPI5SOMI[0]DMMDA T A[13]/MIBSPI5SOMI[1]DMMDA T A[14]/MIBSPI5SOMI[2]DMMDA T A[15]/MIBSPI5SOMI[3]VCCNHET[28] NHET[0]VSSIOVCCIO VCCDMMDA T A[6]/nMIBSPI5CS[1]VSS 363534333231302928272625242322212019181716151413121110987654321 7374767778798081828384858687888990919293949596979899100101102103104105106107108 75 TMS NHET[13] nMIBSPI1CS[2]nMIBSPI1CS[0] NHET[23]NHET[21]NHET[18] MIBSPI3SOMIMIBSPI3SIMO RTCK TDITDOVSSVCCTCK nTRST nPORRST VSS OSCOUT VCC nMIBSPI1ENAMIBSPI1CLK VSSIOVCCIO MIBSPI1SIMO NHET[22]NHET[12] NMIBSPI3CS[0]nMIBSPI3ENAMIBSPI3CLK VSSIOVCCIO MIBSPI1SOMI nMIBSPI1CS[1]GIOA[6]/INT[6] OSCIN VCC TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com

2.3 Pin Assignments

2.3.1 PGE QFP Package Pinout(144pin)

Figure2-2.PGE Pinout(144pin)[Top View]

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19 VSS VSS

SIMO[1] ETM DA T A[06] VCCIO VCC VCC VSS VCC EMIF_ ADDR[19] EMIF_ ADDR[13] EMIF_ ADDR[12] EMIF_ ADDR[18] EMIF_ ADDR[16] EMIF_ BA[0] EMIF_ OE EMIF_ DQM[1] EMIF_ DQM[0] ETM DATA [07] ETM DA T A[12] ETM DAT A[ 13] ETM DA T A[14] ETM DA T A[15] DMM ENA ETM DATA [05] VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO ETM DA T A[04] ETM DA T A[03] MIBSPI5 SOMI[2] MIBSPI5 SOMI[3] VSS VCC VSS VSS VSS VCC VSS VSS VSS VSS VSS JHGFEDCA B LK 1 1 JHGFEDCA B LK TMS NHET [10] MIBSPI5 CS[0] MIBSPI1 SIMO MIBSPI1 ENA MIBSPI5 CLK MIBSPI5 SIMO[0] NHET [28] DMM DA T A[0] VSS TCK TDO TRST NHET [08] MIBSPI1 CLK MIBSPI1 SOMI MIBSPI5 ENA MIBSPI5 SOMI[0] NHET [0] DMM DA T A[1] TDI RST EMIF_ ADDR[21] EMIF _WE MIBSPI5 SOM[1] DMM CLK MIBSPI5 SIMO[3] MIBSPI5 SIMO[2] NHET [31] EMIF_ CS[1] EMIF_ CS[0] RTCK FRA Y TXEN1 EMIF_ ADDR[20] EMIF_ BA[1] EMIF_ DA T A[1] ETM DA T A[17] EMIF_ DA T A[0] ETM DA T A[16] DMM SYNC ETM DA T A[02] FRA Y RX1 FRA Y TX1 ERRORNHET [26] NHET [17] ECLK NHET [14] CAN1 TX CAN1 RX NHET [30] NHET [04] NHET [19] EMIF_ ADDR[15] EMIF_ ADDR[15] EMIF_ ADDR[14] TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010

2.3.2 ZWT BGA Package Pinout(337ball)

Figure2-3.ZWT Package PinoutTop LeftQuadrant (337ball)[Top View] Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 17 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW 1 1 VCCIO VCC VCCIO VCCIO NC VCC 1 1 VUTRPNMK L W VCCVSS VSS VSS VSS VSS VSS VSS VCC GIOB[3] VUTRPNMK L W VCCIOVCCIOVCCIOVCC NHET [28] DMM DA T A[0] CAN3 RX AD1 EVT ADS IN[15] AD2 IN[6] AD1 IN[6] ADS IN[1 1] VSSAD VSSAD VSSADAD1 IN[2] NHET [0] DMM DA T A[1] CAN3 TX NC ADS IN[8] ADS IN[14] EMIF_ CS[1] EMIF_ DA T A[0] ETM DA T A[16] EMIF_ CS[0] EMIF_ DA T A[1] ETM DA T A [17] EMIF_ CS[2] EMIF_ DA T A[2] ETM DA T A[18] EMIF_ CS[3] EMIF_ DA T A[3] ETM DA T A[19] ADS IN[13] AD1 IN[4] ADS IN[9] VSSAD VCCAD AD1 IN[0] AD2 EVT LIN1 RX RTP CLK AD1 IN[1] ADREF HI AD1 IN[7] NC NC NC AD1 IN[5] AD2 IN[7] NC NC AD1 IN[3] ADS IN[10] AD2 IN[3] AD2 IN[2] ADREF LO AD2 IN[4] ADS IN[12] MIBSPI3 CS[0] RTP DA T A[3] RTP DA T A[2] ETM TRACE CLKOUT RTP DA T A[0] RTP DA T A[1] RTP SYNC ETM TRACE CTL LIN1 TX RTP ENA MIBSPI5 CS[3] ETM DA T A[0] AD2 IN[0] AD2 IN[1]NCETM DA T A[1] AD2 IN[5] TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com Figure2-4.ZWT Package PinoutTop RightQuadrant (337ball)[Top View]

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10 CAN1TX CAN1RX

EMIF_ ADDR[12] EMIF_ DQM[0] ETM_ DA T A[15] VCC VCC VSS VSS VSS VSSVSSVSSVSS VSSVCCVSSVSS VCC VCCP VCCIO VCCIO NHET [27] FRA Y TXEN2 EMIF_ ADDR[11 ] EMIF_ ADDR[5] FRA Y RX2 FRA Y TX2 EMIF_ ADDR[10] EMIF_ ADDR[4] LIN2 RX LIN2 TX EMIF_ ADDR[9] EMIF_ ADDR[3] ETM DATA [8] ETM DA T A[9] ETM DA T A[10] ETM DAT A[1 1] EMIF_ ADDR[2] EMIF_ ADDR[8] MIBSPI5 CS[1] GIOA [4] GIOA [0] NHET [16] NHET [29] VSS VSS VSS MIBSPI3 CS[2] NHET [22] NHET [12] GIOA [5] GIOA [2] GIOA [1] MIBSPI3 CS[3] EMIF_ ADDR[6] EMIF_ ADDR[7] EMIF_ ADDR[1] EMIF_ ADDR[0] NC NC NC GIOA [3] NC NHET [1 1] EMIF_ DA T A[4] ETM DA T A[20] GIOB [7] GIOB [2] MIBSPI1 CS[1] EMIF_ DA T A[5] ETM DA T A[21] GIOB [4] GIOB [5] MIBSPI1 CS[2] EMIF_ DA T A[6] ETM DAT A[2 2] VCCIO VCCIO VCCIO VCC VCC FLT P2 FL TP1 ETM DA T A[23] ETM DA T A[24] NHET [21] NHET [23] EMIF_ DA T A[7] EMIF_ DAT A[8 ] GIOA [6] MIBSPI1 CS[3] NC NC CAN2 TX GIOB [6] GIOB [1] KELV IN GND CAN2 RX NHET [18] OSCIN OSCOUT JHGFEDCA B LK JHGFEDCA B LK TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010 Figure2-5.ZWT Package PinoutBottom LeftQuadrant (337ball)[Top View] Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 19 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW VUTRPNMK L W NC OSCIN VCC VCC OSCOUT NC NC VCCIO VCCIO VCCIO VCC VSS VSS VSS VSS VCCIO VCCIO VCCIO ETM DA T A[23] EMIF_ DA T A[7] GIOB [1] ETM DA T A[24] EMIF_ DA T A[8] KEL VIN GND GIOA [7] GIOB [0] NHET [25] EMIF_ DA T A[9] ETM DA T A[25] ETM DA T A[26] EMIF_ DA T A[10] NC NC NHER [13] NHET [15] NHET [24] NHET [20] EMIF_ DA T A[1 1] ETM DA T A[27] NC MIBSPI1 CS[0] NC NC ETM DA T A[28] ETM DA T A[29] NHET [7] NHET [3] TEST RTP DA T A[13] RTP DA T A[15] NHET [1] RTP DA T A[12] NHET [6] RTP DA T A[14] VSS VSS VCC VSS VSS VSS VCC VSS VSS VUTRPNMK L W RTP DA T A[1 1] EMIF_ DA T A[12] EMIF_ DA T A[13] RTP DA T A[19] RTP DA T A[9] MIBSPI3 CS[1] NHET [2] MIBSPI5 CS[2] ETM DA T A[30] NHET [5] RTP DA T A[8] PORRSTNHET [9] RTP DA T A[7] EMIF_ DA T A[14] MIBSPI3 SIMO MIBSPI3 SOMI RTP DA T A[6] EMIF_ DA T A[15] ETM DA T A[31] MIBSPI3 ENA MIBSPI3 CLK RTP DA T A[5] RTP DA T A[4] RTP DA T A[4] ETM TRACE CLKOUT RTP DA T A[2] RTP DA T A[3] MIBSPI3 CS[0] GIOB[3] TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com Figure2-6.ZWT Package PinoutBottom RightQuadrant (337ball)[Top View]

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2.4 TerminalFunctions

Thisfollowingtabledescribesthepinson thedevice. Table2-8.TerminalFunctions Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown337 144 337 144 HIGH-END TIMER (NHET) NHET[0] K18 105 K18 105 Timerinputcaptureoroutputcompare. The applicableNHET pinscan beNHET[1] V2 42 V2 42 programmed as general-purpose NHET[2] W5 56 W5 56 input/output(GIO)pins.NHET pinsare high-resolution.NHET[3] U1 41 U1 41 The high-resolution(HR) SHARE feature NHET[4] B12 121 B12 121 allowseven HR pinstosharethenext higherodd HR pinstructures.The nextNHET[5] V6 44 V6 44 higherodd HR pinstructureisalways NHET[6] W3 48 W3 48 implemented,even ifthenexthigherodd HR pad and/orpinitselfisnot.The HRNHET[7] T1 109 T1 109 sharingisindependentofwhetherornot NHET[8] E18 112 E18 112 theodd pinisavailableexternally.Ifan odd pinisavailableexternallyandNHET[9] V7 57 V7 57 shared,thentheodd pincan onlybeNHET[10] D19 116 D19 116 used as a general-purposeI/O. NHET[0] providesSPI clockwhen usedNHET[11] E3 117 E3 117 forSPI emulation.NHET[12] B4 8 B4 8 Each NHET pinisequippedwithan input suppressionfilterthatcan be used toNHET[13] N2 26 N2 26 eliminatethesamplingofpulsesthatareNHET[14] A11 138 A11 138 smallerthana programmabledurationprogram NHET[15] N1 113 N1 113 GIOA[0]/INT[0]isalsoconnectedtothemable3.3VI/O 2mA -z NHET PinDisableinputoftheNHETIPDNHET[16] A4 142 A4 142 module.(20mA)NHET[17] A13 A13 NHET pinscan be programmed as a GIO pinswhen notused as NHETNHET[18] J1 10 J1 10 functionalpins. NHET[19] B13 B13 NHET[20] P2 45 P2 45 NHET[21] H4 11 H4 11 NHET[22] B3 9 B3 9 NHET[23] J4 12 J4 12 NHET[24] P1 43 P1 43 NHET[25] M3 M3 NHET[26] A14 A14 NHET[27] A9 A9 NHET[28] K19 106 K19 106 NHET[29] A3 A3 NHET[30] B11 137 B11 137 NHET[31] J17 J17 Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 21 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com Table2-8.TerminalFunctions(continued) Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown337 144 337 144 GENERAL-PURPOSE I/O(GIO) General-purposeinput/outputpin. GIOA[0]/INT[0]isan interrupt-capable GIOA[0]/INT0 A5 118 A5 118 pin.GIOA[0]/INT[0]isalsoconnectedto theNHET PinDisableinputoftheNHET module. GIOA[1]/INT1 C2 134 C2 134 GIOA[2]/INT2 C1 141 C1 141 GIOA[3]/INT3 E1 144 E1 144 General-purposeinput/output GIOA[4]/INT4 A6 110 A6 110 pins.GIOA[7:1]/INT[7:1]are interrupt-capablepins.GIOA[5]/INT5 B5 111 B5 111 Program mableGIOA[6]/INT6 H3 27 H3 27 3.3VI/O 2mA -z IPD GIOA[7]/INT7 M1 51 M1 51 (20mA) GIOB[0] M2 M2 GIOB[1] K2 K2 GIOB[2] F2 F2 GIOB[3] W10 W10 General-purposeinput/outputpins. GIOB[4] G1 G1 GIOB[5] G2 G2 GIOB[6] J2 J2 GIOB[7] F1 F1 FlexrayController(FLEXRAY ) NOTE: DeviceswithouttheFlexRayoptionshouldleaveallFlexRaypinsunconnected(NC) Program mableFRAYRX1 A15 126 3.3VI Flexraydatareceive(channel1)pinIPD (20mA) FRAYTX1 B15 124 8mA Flexraydatatransmit(channel1)pin 3.3VO FRAYTXEN1 B16 125 8mA Flexraytransmitenable(channel1)pin Program mableFRAYRX2 A8 131 3.3VI Flexraydatareceive(channel2)pinIPD(20m FRAYTX2 B8 129 8mA Flexraydatatransmit(channel2)pin 3.3VO FRAYTXEN2 B9 130 8mA Flexraytransmitenable(channel2)pin CAN Controller(DCAN1) CAN1TX A10 50 A10 50 Program CAN1 transmitpinorGIO pin mable3.3VI/O 2mA -z IPUCAN1RX B10 49 B10 49 CAN1 receivepinorGIO pin (20mA) CAN Controller(DCAN2 ) CAN2TX H2 54 H2 54 Program CAN2 transmitpinorGIO pin mable3.3VI/O 2mA -z IPUCAN2RX H1 55 H1 55 CAN2 receivepinorGIO pin (20mA) CAN Controller(DCAN3) CAN3TX M18 M18 program CAN3 transmitpinorGIO pin mable3.3VI/O 2mA -z IPUCAN3RX M19 M19 CAN3 receivepinorGIO pin (20mA)

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PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010 Table2-8.TerminalFunctions(continued) Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown337 144 337 144 SerialCommunications Interface(SCI)/LocalInterconnectNetwork (LIN1) LIN1RX W12 53 W12 53 Program LIN1 datareceivepinorGIO pin mable3.3VI/O 2mA -z IPULIN1TX V12 52 V12 52 LIN1 datatransmitpinorGIO pin (20mA) SerialCommunications Interface(SCI)/LocalInterconnectNetwork (LIN2) LIN2RX A7 140 A7 140 Program LIN2 datareceivepinorGIO pin mable3.3VI/O 2mA -z IPULIN2TX B7 139 B7 139 LIN2 datatransmitpinorGIO pin (20mA) MultibufferedSerialPeripheralInterface(MIBSPI1) MIBSPI1 slavechipselectpinsorGIOMIBSPI1CLK F18 17 F18 17 4mA pins MIBSPI1CS[0] R2 23 R2 23 MIBSPI1CS[1] F3 24 F3 24 2mA -z MIBSPI1 clockpinorGIO pinProgramMIBSPI1CS[2] G3 25 G3 25 mable3.3VI/OMIBSPI1CS[3] J3 J3 IPU (20µA)MIBSPI1ENA G19 218 G19 218 2mA -z MIBSPI1 enablepinorGIO pin MIBSPI1 datastream-Slavein/masterMIBSPI1SIMO F19 14 F19 14 outpinorGIO pin 4mA MIBSPI1 datastream-Slaveout/masterMIBSPI1SOMI G18 13 G18 13 inpinorGIO pin MultibufferedSerialPeripheralInterface(MIBSPI3) MIBSPI3 slavechipselectpinsorGIOMIBSPI3CLK V9 3 V9 3 4mA pins MIBSPI3CS[0] V10 7 V10 7 MIBSPI3CS[1] V5 V5 2mA -z MIBSPI3 clockpinorGIO pinProgramMIBSPI3CS[2] B2 B2 mable3.3VI/OMIBSPI3CS[3] C3 C3 IPU (20mA)MIBSPI3ENA W9 6 W9 6 2mA -z MIBSPI3 enablepinorGIO pin MIBSPI3 datastream-Slavein/masterMIBSPI3SIMO W8 4 W8 4 outpinorGIO pin 4mA MIBSPI3 datastream-Slaveout/masterMIBSPI3SOMI V8 5 V8 5 inpinorGIO pin Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 23 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com Table2-8.TerminalFunctions(continued) Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown337 144 337 144 MultibufferedSerialPeripheralInterface-Parallel(MIBSPIP5) MIBSPI5CLK/DM MIBSPI5 clockpinorGIO pin;H19 91 H19 91 4mAMDATA[4] multiplexedwithDMMDATA[4] pin MIBSPI5CS[0]/DM E19 92 E19 92MDATA[5] MIBSPI5CS[1]/DM B6 93 B6 93MDATA[6] MIBSPI5 slavechipselectpinsorGIO pins;multiplexedwithDMMDATA pinsMIBSPI5CS[2]/DM W6 W6 2mA -zMDATA[2] MIBSPI5CS[3]/DM T12 T12MDATA[3] MIBSPI5ENA/DM MIBSPI5 enablepinorGIO pin;H18 94 H18 94MDATA[7] multiplexedwithDMMDATA[7] pin MIBSPI5SIMO[0]/ ProgramJ19 95 J19 95DMMDATA[8] mable3.3VI/O IPUDMMDATA[9]/MIB E16 96 E16 96 MIBSPI5 datastream-Slavein/master(20mA)SPI5SIMO[1] outpinsorGIO pins;multiplexedwith MIBSPI5SIMO[2]/ DMMDATA pinsH17 97 H17 97DMMDATA[10] MIBSPI5SIMO[3]/ G17 98 G17 98DMMDATA[11] 4mA MIBSPI5SOMI[0]/ J18 99 J18 99DMMDATA[12] MIBSPI5SOMI[1]/ E17 100 E17 100 MIBSPI5 datastream-Slaveout/masterDMMDATA[13] inpinsorGIO pins;multiplexedwith MIBSPI5SOMI[2]/ DMMDATA pinsH16 101 H16 101DMMDATA[14] MIBSPI5SOMI[3]/ G16 102 G16 102DMMDATA[15]/ MultibufferedAnalog-To-DigitalConverter(MIBADC1) Program mableAD1EVT N19 84 N19 84 3.3VI/O 2 mA -z MibADC1 eventinputpinorGIO pinIPD (20mA) AD1IN[0] W14 83 W14 83 AD1IN[1] V17 82 V17 82 AD1IN[2] V18 81 V18 81 AD1IN[3] T17 80 T17 80 3.3VI MibADC1 analoginputpins AD1IN[4] U18 79 U18 79 AD1IN[5] R17 78 R17 78 AD1IN[6] T19 77 T19 77 AD1IN[7] V14 76 V14 76

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PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010 Table2-8.TerminalFunctions(continued) Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown337 144 337 144 MultibufferedAnalog-To-DigitalConverter(MIBADC2) Program mableAD2EVT W13 59 W13 59 3.3VI/O 2 mA -z MibADC2 eventinputpinorGIO pinIPD (20mA) AD2IN[0] V13 60 V13 60 AD2IN[1] U13 61 U13 61 AD2IN[2] U14 62 U14 62 AD2IN[3] U16 63 U16 63 3.3V I MibADC2 analoginputpins AD2IN[4] U15 U15 AD2IN[5] T15 T15 AD2IN[6] R19 R19 AD2IN[7] R16 R16 MultibufferedAnalog-To-DigitalConverter-shared signals(MIBADC1, MIBADC2) ADSIN[8] P18 75 P18 75 ADSIN[9] W17 74 W17 74 ADSIN[10] U17 73 U17 73 ADSIN[11] U19 72 U19 72 MibADC1, MibADC2 sharedanaloginput3.3V I pinsADSIN[12] T16 71 T16 71 ADSIN[13] T18 70 T18 70 ADSIN[14] R18 69 R18 69 ADSIN[15] P19 68 P19 68 3.3-V MibADC1, MibADC2 moduleADREFHI V15 66 V15 66 REF high-voltagereferenceinput GND MibADC1, MibADC2 module low-voltageADREFLO V16 65 V16 65 REF referenceinput 3.3-V MibADC1, MibADC2 analogsupplyVCCAD W15 67 W15 67 PWR voltage VSSAD V19 64 V19 64 VSSAD W16 W16 MibADC1, MibADC2 analoggroundGND referenceVSSAD W18 W18 VSSAD W19 W19 Oscillator(OSC) OscillatorinputconnectionpinorOSCIN K1 20 K1 20 1.5VI externalclockinputpin OSCOUT L1 21 L1 21 1.5VO Oscillatorouptutconnectionpin Kelvin_GND L2 L2 GND Kelvin_GND foroscillator Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 25 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com Table2-8.TerminalFunctions(continued) Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown337 144 337 144 System Module (SYS) Power on ResetPin.Externalpower PORRST W7 28 W7 28 3.3VI supplymonitorcircuitrymust asserta power-onreseton thispin. ActiveLow BidirectionalResetpin.An externaldevicecan asserta devicereset on thispin.IPD The outputbufferon thispinis(100µA) implementedas an open drain(drivesRST B17 85 B17 85 4mA lowonly). 3.3VI/O To ensurean externalresetisnot arbitrarilygenerated,TIrecommends thatan externalpullupresistoris connectedtothispin. IPD ExternalClockPrescalermodule outputECLK A12 88 A12 88 8mA (20µA) pinorGIO pin Tset/Debug (T/D) IPD JTAG testclockpin.ClockstheJTAGTCK B18 30 B18 30 3.3VI (100mA) debug logic. RTCK A16 35 A16 35 3.3VO JTAG returntestclockpin.(JTAG) TDI A17 34 A17 34 JTAG testdatainpin. TDO C18 33 C18 33 JTAG testdataoutpin.8 mA 3.3VI/O JTAG serialinputpinforcontrollingthe TMS C19 36 C19 36 stateoftheCPU testaccessport(TAP) controller. IPU JTAG testhardwareresettoTAP. IEEE(100mA)TRST D18 29 D18 29 Standard1149-1(JTAG) Boundary-Scan Logic 3.3VI Testenablepin.ReservedforinternalTI use only.Forproperoperation,thispinTEST U2 58 U2 58 must be connectedtoground,e.g.using a externalresistor. ErrorSignalingModule (ESM) IPDERROR B14 143 B14 143 3.3VI/O 8mA ErrorSignalingpin(20mA) Flash FlashTestPad 1 pin.Forproper operationthispinmust connectonlytoa testpad ornotbe connectedatall[noFLTP1 J5 122 J5 122 connect(NC)].The testpad must notbe exposed inthefinalproductwhere it mightbe subjectedtoan ESD event. FlashTestPad 2 pin.Forproper operationthispinmust connectonlytoa testpad ornotbe connectedatall[noFLTP2 H5 123 H5 123 connect(NC)].The testpad must notbe exposed inthefinalproductwhere it mightbe subjectedtoan ESD event. Flashpump voltagesupply(3.3V).This3.3VVCCP F8 128 F8 128 pinisrequiredforFlashread,programPWR and eraseoperations.

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PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010 Table2-8.TerminalFunctions(continued) Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown337 144 337 144 ExternalMemory InterfaceModule (EMIF) EMIFBADD[0] D13 D13 3.3VI/O 8mA EMIF ByteAddresspins EMIFBADD[1] D16 D16 EMIFDATA[0] K16 K16 EMIFDATA[1] L16 L16 EMIFDATA[2] M16 M16 EMIFDATA[3] N16 N16 EMIFDATA[4] E4 E4 EMIFDATA[5] F4 F4 EMIFDATA[6] G4 G4 Program EMIFDATA[7] K4 K4 mable3.3VI/O 8mA EMIF Data pinsIPUEMIFDATA[8] L4 L4 (20mA)EMIFDATA[9] M4 M4 EMIFDATA[10] N4 N4 EMIFDATA[11] P4 P4 EMIFDATA[12] T5 T5 EMIFDATA[13] T6 T6 EMIFDATA[14] T7 T7 EMIFDATA[15] T8 T8 EMIFADD[0] D4 D4 EMIFADD[1] D5 D5 EMIFADD[2] D6 D6 EMIFADD[3] D7 D7 EMIFADD[4] D8 D8 EMIFADD[5] D9 D9 EMIFADD[6] C4 C4 EMIFADD[7] C5 C5 EMIFADD[8] C6 C6 EMIFADD[9] C7 C7 EMIFADD[10] C8 C8 3.3VI/O 8mA EMIF Addresspins EMIFADD[11] C9 C9 EMIFADD[12] C10 C10 EMIFADD[13] C11 C11 EMIFADD[14] C12 C12 EMIFADD[15] C13 C13 EMIFADD[16] D14 D14 EMIFADD[17] C14 C14 EMIFADD[18] D15 D15 EMIFADD[19] C15 C15 EMIFADD[20] C16 C16 EMIFADD[21] C17 C17 EMIFCS[0] L17 L17 EMIFCS[1] K17 K17 3.3VI/O 8mA EMIF ChipSelectpins EMIFCS[2] M17 M17 EMIFCS[3] N17 N17 Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 29 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

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2.5 Device Support

2.5.1 Device and Development-Support Tool Nomenclature

To designatethestagesintheproductdevelopmentcycle,TI assignsprefixestothepartnumbers ofall devicesand supporttools.Each commercialfamilymember has one ofthreeprefixes:TMX, TMP, orTMS (e.g.,TMS570LS20216ASPGEQQ1). Texas Instrumentsrecommends two of three possibleprefix designatorsforitssupporttools:TMDX and TMDS. These prefixesrepresentevolutionarystages of product development from engineeringprototypes(TMX/TMDX) through fullyqualifiedproduction devices/tools(TMS/TMDS). Devicedevelopmentevolutionaryflow: TMX Experimentaldevicethatis not necessarilyrepresentativeof the finaldevice'selectrical specifications. TMP Finalsilicondiethatconformstothedevice'selectricalspecificationsbuthas notcompleted qualityand reliabilityverification. TMS Fully-qualifiedproductiondevice. Supporttooldevelopmentevolutionaryflow: TMDX Development-supportproduct that has not yet completed Texas Instrumentsinternal qualificationtesting. TMDS Fullyqualifieddevelopment-supportproduct. TMX and TMP devices and TMDX development-supporttoolsare shipped againstthe following disclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." TMS devicesand TMDS development-supporttoolshave been characterizedfully,and the qualityand reliabilityofthedevicehave been demonstratedfully.TI'sstandardwarrantyapplies. Predictionsshow thatprototypedevices(TMX or TMP) have a greaterfailureratethan the standard productiondevices.Texas Instrumentsrecommends thatthesedevicesnot be used inany production systembecause theirexpectedend-usefailureratestillisundefined.Onlyqualifiedproductiondevicesare tobe used. TI devicenomenclaturealso includesa suffixwiththe devicefamilyname. This suffixindicatesthe package type (forexample, PGE), the temperaturerange (forexample, "Blank"is the commercial temperaturerange),and thedevicespeed rangeinmegahertz.

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PRODUCT□PREVIEW Prefix: TM S = Fully TMS Qualified P = TMP Prototype X = TMX Samples Core Technology: 5 = 570 Cortex R4 Architecture: LS = Lockstep CPUs Flash Memory Size: 20 = 2MB 10 = 1MB RAM Memory Size: 2 = 160kB 1 = 128kB Peripheral Set: 16 = Flexray 06 = No Flexray Die Revision: Blank = Initial Die A = 1st Die Revision B = 2nd Die Revision Technology/Core Voltage: S = F035 (130nm), 1.5 V nominal core voltage Package Type: PGE = 144p QFP Package [Green] ZWT = 337p BGA Package [Green] Temperature Range: I = -40...+85 C o T = -40...+105 C o Q = -40...+125 C o Quality Designator: Q1 = Automotive Shipping Options: R = Tape and Reel Full Part # TMS 570 LS 20 2 16 A S PGE Q Q1 R Orderable Part # S 5 LS 20 2 16 A S PGE Q Q1 R TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010 A. Foractualdevicepartnumbers (P/Ns)and orderinginformation,see theTIwebsite(http://www.ti.com). Figure2-7.Device Numbering Conventions(A) Copyright© 2010,Texas InstrumentsIncorporated DeviceOverview 35 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

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3 Reset /Abort Sources

3.1 Reset /Abort Sources

The deviceResetsand Abortsarehandledas shown inthefollowingtable.The tableshows thesourceof the error,the system mode, the typeof errorresponseand the correspondingErrorSignalingModule (ESM) channel.OnlystandardARM exceptionhandlersand ESM errorsareused. Table3-1.Reset /Abort Sources ErrorSource System Mode ErrorResponse ESM Hookup group channel 1)CPU transactions Precisewriteerror(Strongly User/Privilege PreciseAbort(CPU) n/a Ordered) Precisereaderror(Deviceor User/Privilege PreciseAbort(CPU) n/a Normal) Imprecisewriteerror(Deviceor User/Privilege ImpreciseAbort(CPU) n/a Normal) Illegalinstruction User/Privilege UndefinedInstructionTrap n/a (CPU)(1) MPU accessviolation User/Privilege Abort(CPU) n/a 2)SRAM B0 TightlyCoupledMemory User/Privilege ESM 1.26 (TCM) (even)ECC singleerror (correctable) B0 TCM (even)ECC doubleerror User/Privilege Abort(CPU),ESM => nERROR (non-correctable) ESM => nERROR 3.3 B0 TCM (even)uncorrectable User/Privilege ESM => NMI 2.6 error(i.e.redundantaddress decode) B0 TCM (even)addressbus User/Privilege ESM => NMI 2.1 parityerror B1 TCM (odd)ECC singleerror User/Privilege ESM 1.28 (correctable) B1 TCM (odd)ECC doubleerror User/Privilege Abort(CPU),ESM => nERROR (non-correctable) ESM => nERROR 3.5 B1 TCM (odd)uncorrectable User/Privilege ESM => NMI 2.8 error(i.e.redundantaddress decode) B1 TCM (odd)addressbus parity User/Privilege ESM => NMI 2.12 error 3)FlashwithECC INTEGRATED INTO CPU ECC singleerror(correctable) User/Privilege ESM 1.6 ECC doubleerror User/Privilege Abort(CPU),ESM => nERROR (non-correctable) ESM => nERROR 3.7 Uncorrectableerror(i.e. redundantaddresstag, redundantsyndrome compare,addressbus parity, User/Privilege ESM => NMI 2.4 etc.) 4)DMA transactions (1) The UndefinedInstructionTRAP isNOT detectableoutsidetheCPU. The trapistakenonlyiftheCode reachestheexecutestageof theCPU.

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PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010 Table3-1.Reset /Abort Sources (continued) ErrorSource System Mode ErrorResponse ESM Hookup group channel Externalimpreciseerroron read User/Privilege ESM 1.5 (Illegaltransactionwithok response) Externalimpreciseerroron write User/Privilege ESM 1.13 (Illegaltransactionwithok response) Memory accesspermission User/Privilege ESM 1.2 violation Memory parityerror User/Privilege ESM 1.3 5)DMM transactions Externalimpreciseerroron read User/Privilege ESM 1.5 (Illegaltransactionwithok response) Externalimpreciseerroron write User/Privilege ESM 1.13 (Illegaltransactionwithok response) 6)AHB-AP transactions Externalimpreciseerroron read User/Privilege ESM 1.5 (Illegaltransactionwithok response) Externalimpreciseerroron write User/Privilege ESM 1.13 (Illegaltransactionwithok response) 7)HET TU NCNB (StronglyOrdered) User/Privilege Interrupt=> VIM n/a transactionwithslaveerror response Externalimpreciseerror(Illegal User/Privilege Interrupt=> VIM n/a transactionwithok response) Memory accesspermission User/Privilege ESM 1.9 violation Memory parityerror User/Privilege ESM 1.8 8)NHET Memory parityerror User/Privilege ESM 1.7 9)MibSPI MibSPI1 memory parityerror User/Privilege ESM 1.17 MibSPI3 memory parityerror User/Privilege ESM 1.18 MibSPIP5 memory parityerror User/Privilege ESM 1.24 10)MibADC MibADC1 memory parityerror User/Privilege ESM 1.19 MibADC2 memory parityerror User/Privilege ESM 1.1 11)DCAN DCAN1 memory parityerror User/Privilege ESM 1.21 DCAN2 memory parityerror User/Privilege ESM 1.23 DCAN3 memory parityerror User/Privilege ESM 1.22 12)PLL PLL sliperror User/Privilege ESM 1.1 13)Clock monitor Clockmonitorinterrupt User/Privilege ESM 1.11 14)CCM Selftestfailure User/Privilege ESM 1.31 Compare failure User/Privilege ESM => NMI 2.2 Copyright© 2010,Texas InstrumentsIncorporated Reset/AbortSources 37 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com Table3-1.Reset /Abort Sources (continued) ErrorSource System Mode ErrorResponse ESM Hookup group channel 15)Flexray Memory parityerror User/Privilege ESM 1.12 16)FlexrayTU NCNB (StronglyOrdered) User/Privilege Interrupt=> VIM n/a transactionwithslaveerror response Externalimpreciseerror(Illegal User/Privilege Interrupt=> VIM n/a transactionwithok response) Memory accesspermission User/Privilege ESM 1.16 violation Memory parityerror User/Privilege ESM 1.14 17)VIM Memory parityerror User/Privilege ESM 1.15 18)voltagemonitor VMON outofvoltagerange n/a Reset n/a 19)CPU Selftest(LBIST) CPU Selftest(LBIST)error User/Privilege ESM 1.27 20)errorsreflectedintheSYSESR register Power-Up Reset;VCC outof n/a Reset n/a voltagerange Oscillatorfail/PLL slip(2) n/a Reset n/a Watchdog timelimitexceeded n/a Reset n/a CPU Reset n/a Reset n/a SoftwareReset n/a Reset n/a ExternalReset n/a Reset n/a (2) Oscillatorfail/PLLslipcan be configuredinthesystemregisterPLLCTL1 togeneratea reset.

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4 Peripherals

4.1 ErrorSignalingModule (ESM)

The ErrorSignalingModule (ESM) isused to indicatea severe devicefailureviainterruptsand the externalERROR pin.The errorpinisnormallyused by an externaldevicetoeitherresetthecontroller and/orkeep thesystemina failsafestate. The ESM module consistsofthreeerrorgroupswith32 inputseach.The generationoftheinterruptsand the activationof the ERROR Pin isshown inthe followingtable.The nexttableshows the ESM error sourcesand theircorrespondinggroupand channelnumbers. Table4-1.ESM Groups ErrorGroup Interrupt,Level Influenceon Errorpin Group1 maskable,low/high configurable Group2 non-maskable,high fixed Group3 none,none fixed Table4-2.ESM Assignments ERROR Sources Group Channels Reserved Group1 0 MibADC2 -parity Group1 1 DMA -MPU Group1 2 DMA -parity Group1 3 Reserved Group1 4 DMA/DMM/AHB-AP -imprecisereaderror Group1 5 Flash(ATCM) -correctableerror Group1 6 NHET -parity Group1 7 HET TU -parity Group1 8 HET TU -MPU Group1 9 PLL -slip Group1 10 ClockMonitor-interrupt Group1 11 Flexray-parity Group1 12 DMA/DMM/AHB-AP -imprecisewriteerror Group1 13 FlexrayTU -parity Group1 14 VIM RAM -parity Group1 15 FlexrayTU -MPU Group1 16 MibSPI1 -parity Group1 17 MibSPI3 -parity Group1 18 MibADC1 -parity Group1 19 Reserved Group1 20 DCAN1 -parity Group1 21 DCAN3 -parity Group1 22 DCAN2 -parity Group1 23 MibSPIP5 -parity Group1 24 Reserved Group1 25 RAM even bank (B0TCM) -correctableerror Group1 26 CPU -selftest Group1 27 RAM odd bank (B1TCM) -correctableerror Group1 28 Reserved Group1 29 Copyright© 2010,Texas InstrumentsIncorporated Peripherals 39 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com Table4-2.ESM Assignments (continued) ERROR Sources Group Channels Reserved Group1 30 CCM-R4 -selftest Group1 31 Reserved Group2 0 Reserved Group2 1 CCM-R4 -compare Group2 2 Reserved Group2 3 Flash(ATCM) -uncorrectableerror Group2 4 Reserved Group2 5 RAM even bank (B0TCM) -uncorrectableerror Group2 6 Reserved Group2 7 RAM odd bank (B1TCM) -uncorrectableerror Group2 8 Reserved Group2 9 RAM even bank (B0TCM) -addressbus parityerror Group2 10 Reserved Group2 11 RAM odd bank (B1TCM) -addressbus parityerror Group2 12 Reserved Group2 13 Reserved Group2 14 Reserved Group2 15 Flash(ATCM) -ECC livelockdetect Group2 16 Reserved Group2 17 Reserved Group2 18 Reserved Group2 19 Reserved Group2 20 Reserved Group2 21 Reserved Group2 22 Reserved Group2 23 Reserved Group2 24 Reserved Group2 25 Reserved Group2 26 Reserved Group2 27 Reserved Group2 28 Reserved Group2 29 Reserved Group2 30 Reserved Group2 31 Reserved Group3 0 Reserved Group3 1 Reserved Group3 2 RAM even bank (B0TCM) -ECC uncorrectableerror Group3 3 Reserved Group3 4 RAM odd bank (B1TCM) -ECC uncorrectableerror Group3 5 Reserved Group3 6 Flash(ATCM) -ECC uncorrectableerror Group3 7 Reserved Group3 8 Reserved Group3 9 Reserved Group3 10 Reserved Group3 11 Reserved Group3 12

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PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010 Table4-2.ESM Assignments (continued) ERROR Sources Group Channels Reserved Group3 13 Reserved Group3 14 Reserved Group3 15 Reserved Group3 16 Reserved Group3 17 Reserved Group3 18 Reserved Group3 19 Reserved Group3 20 Reserved Group3 21 Reserved Group3 22 Reserved Group3 23 Reserved Group3 24 Reserved Group3 25 Reserved Group3 26 Reserved Group3 27 Reserved Group3 28 Reserved Group3 29 Reserved Group3 30 Reserved Group3 31 Copyright© 2010,Texas InstrumentsIncorporated Peripherals 41 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

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4.2 DirectMemory Access (DMA)

The direct-memoryaccess(DMA) controllertransfersdatatoand fromany specifiedlocationinthedevice memory map. The DMA supportsdatatransferforbothon-chipmemories and peripherals. The DMA controlleron thisdevicesupports16 channelsand 32 requestlines.Each of the 32 DMA requestsare assignedby defaultto one of the 32 availablechannels.For DMA requestsmultiplexed between multiplesources,theDMA controllercannotdifferentiatebetween themultiplesourcesand the user has to ensure thatmultiplesourcesare not enabledat the same time.Please referto the DMA SpecificationintheTRM formore details. The DMA requestconfigurationisshown inthefollowingtable. Table4-3.DMA Request LineConnection Modules DMA Request Sources DMA Request MIBSPI1 MIBSPI11 DMAREQ[0] MIBSPI1 MIBSPI10 DMAREQ[1] Reserved Reserved DMAREQ[2] Reserved Reserved DMAREQ[3] MIBSPI1 /MIBSPI3 /DCAN2 MIBSPI1[2]/MIBSPI3[2]/DCAN2 IF3 DMAREQ[4] MIBSPI1 /MIBSPI3 /DCAN2 MIBSPI1[3]/MIBSPI3[3]/DCAN2 IF2 DMAREQ[5] MIBSPIP5 /DCAN1 MIBSPIP5[2]/DCAN1 IF2 DMAREQ[6] MIBADC1 /MIBSPIP5 MIBADC1 event/MIBSPIP5[3] DMAREQ[7] MIBSPI1 /MIBSPI3 /DCAN1 MIBSPI1[4]/MIBSPI3[4]/DCAN1 IF1 DMAREQ[8] MIBSPI1 /MIBSPI3 /DCAN2 MIBSPI1[5]/MIBSPI3[5]/DCAN2 IF1 DMAREQ[9] MIBADC1 /MIBSPIP5 MIBADC1 G1 /MIBSPIP5[4] DMAREQ[10] MIBADC1 /MIBSPIP5 MIBADC1 G2 /MIBSPIP5[5] DMAREQ[11] RTI /MIBSPI1 /MIBSPI3 RTI DMAREQ0 /MIBSPI1[6]/MIBSPI3[6] DMAREQ[12] RTI /MIBSPI1 /MIBSPI3 RTI DMAREQ1 /MIBSPI1[7]/MIBSPI3[7] DMAREQ[13] MIBADC2 /MIBSPI3 /MIBSPIP5 MIBADC2 event/MIBSPI3[1]*/MIBSPIP5[6] DMAREQ[14] MIBSPI3 /MIBSPIP5 MIBSPI3[0]† /MIBSPIP5[7] DMAREQ[15] MIBADC2 /MIBSPI1 /MIBSPI3 /DCAN1 MIBADC2 G1 /MIBSPI1[8]/MIBSPI3[8]/DCAN1 DMAREQ[16] IF3 MIBADC2 /MIBSPI1 /MIBSPI3 /DCAN3 MIBADC2 G2 /MIBSPI1[9]/MIBSPI3[9]/DCAN3 DMAREQ[17] IF1 RTI /MIBSPIP5 RTI DMAREQ2 /MIBSPIP5[8] DMAREQ[18] RTI /MIBSPIP5 RTI DMAREQ3 /MIBSPIP5[9] DMAREQ[19] LIN2 /NHET /DCAN3 LIN2 receive/NHET DMAREQ[4] /DCAN3 IF2 DMAREQ[20] LIN2 /NHET /DCAN3 LIN2 transmit/NHET DMAREQ[5] /DCAN3 IF3 DMAREQ[21] MIBSPI1 /MIBSPI3 /MIBSPIP5 MIBSPI1[10]/MIBSPI3[10]/MIBSPIP5[10] DMAREQ[22] MIBSPI1 /MIBSPI3 /MIBSPIP5 MIBSPI1[11]/MIBSPI3[11]/MIBSPIP5[11] DMAREQ[23] NHET /MIBSPIP5 NHET DMAREQ[6] /MIBSPIP5[12] DMAREQ[24] NHET /MIBSPIP5 NHET DMAREQ[7] /MIBSPIP5[13] DMAREQ[25] CRC /MIBSPI1 /MIBSPI3 CRC DMAREQ[0] /MIBSPI1[12]/MIBSPI3[12] DMAREQ[26] CRC /MIBSPI1 /MIBSPI3 CRC DMAREQ[1] /MIBSPI1[13]/MIBSPI3[13] DMAREQ[27] LIN1 /MIBSPIP5 LIN1 receive/MIBSPIP5[14] DMAREQ[28] LIN1 /MIBSPIP5 LIN1 transmit/MIBSPIP5[15] DMAREQ[29] MIBSPI1 /MIBSPI3 /MIBSPIP5 MIBSPI1[14]/MIBSPI3[14]/MIBSPIP5[1]* DMAREQ[30] MIBSPI1 /MIBSPI3 /MIBSPIP5 MIBSPI1[15]/MIBSPI3[15]/MIBSPIP5[0]† DMAREQ[31] (1) SPI1,SPI3,SPI5 receiveinstandardSPI/compatibilitymode (2) SPI1,SPI3,SPI5 transmitinstandardSPI/compatibilitymode

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4.3 High End Timer TransferUnit(HET-TU)

The High End Timer TransferUnit(HET-TU) is a localDirectMemory Access (DMA) module. Itis specificallydesignedtotransferHigh End Timer(NHET) datato(orfrom)theCPU dataSRAM .The HET softwarecontrolswhichHET instructionsgeneratetransferrequeststothetransferunit.More information about the NHET and the HET-TU can be found inthe technicalreferencemanual (TRM). The HET-TU supports8 channels. The HET-TU requestassignmentisshown inthefollowingtable. Table4-4.NHET Request LineConnection Modules Request Source HET TRANSFER UNIT Request NHET HTUREQ[0] HET TU DCP[0] NHET HTUREQ[1] HET TU DCP[1] NHET HTUREQ[2] HET TU DCP[2] NHET HTUREQ[3] HET TU DCP[3] NHET HTUREQ[4] HET TU DCP[4] NHET HTUREQ[5] HET TU DCP[5] NHET HTUREQ[6] HET TU DCP[6] NHET HTUREQ[7] HET TU DCP[7] Copyright© 2010,Texas InstrumentsIncorporated Peripherals 43 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

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4.4 VectoredInterruptManager (VIM)

The VectoredInterruptManager (VIM)provideshardware assistanceforprioritizingand controllingthe many interruptsourcespresenton thedevice.Interruptrequestsoriginatingfromthedevicemodules (i.e., SPI,LIN,SCI,etc.)are assignedtochannelswithinthe64-channelVIM. Programming multipleinterrupt sourcestothesame VIM channeleffectivelysharestheVIM channelbetween sources.The VIM request channelsare maskable so thatindividualchannelscan be selectivelydisabled.Allinterruptrequestscan be programmed intheVIM tobe ofeithertype:

Fastinterruptrequest(FIQ)
Normal interruptrequest(IRQ)
Non maskableinterrupt(NMI)-Programmable viaCPU CP15 registersetting The VIM prioritizesinterrupts,whose precedenceofrequestchannelsdecreasewithascendingchannel orderintheVIM (0[highest]and 64[lowest]priority).For VIM defaultmapping,channelpriorities,and their associatedmodules see the tablebelow.More informationon the VIM can be found in the technical referencemanual (TRM). Table4-5.InterruptRequest Assignments Modules InterruptSources DefaultVIM InterruptRequest ESM ESM Highlevelinterrupt(NMI) 0 Reserved (NMI) 1 RTI RTI compare interrupt0 2 RTI RTI compare interrupt1 3 RTI RTI compare interrupt2 4 RTI RTI compare interrupt3 5 RTI RTI overflowinterrupt0 6 RTI RTI overflowinterrupt1 7 RTI RTI timebase 8 GIO GIO interruptA 9 NHET NHET level1 interrupt 10 HET TU HET TU level1 interrupt 11 MIBSPI1 MIBSPI1 level0 interrupt 12 LIN1 (incl.SCI) LIN1 level0 interrupt 13 MIBADC1 MIBADC1 eventgroupinterrupt 14 MIBADC1 MIBADC1 sw group1 interrupt 15 DCAN1 DCAN1 level0 interrupt 16 Reserved Reserved 17 Flexray Flexraylevel0 interrupt 18 CRC CRC Interrupt 19 ESM ESM Low levelinterrupt 20 SYSTEM Softwareinterrupt(SSI) 21 CPU PMU Interrupt 22 GIO GIO interruptB 23 NHET NHET level2 interrupt 24 HET TU HET TU level2 interrupt 25 MIBSPI1 MIBSPI1 level1 interrupt 26 LIN1 (incl.SCI) LIN1 level1 interrupt 27 MIBADC1 MIBADC1 sw group2 interrupt 28 DCAN1 DCAN1 level1 interrupt 29 Reserved Reserved 30 MIBADC1 MIBADC1 magnitudeinterrupt 31

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4.5 MIBADC Event TriggerSources

Allthreeconversiongroupscan be configuredforevent-triggeredoperation,providingup tothreeevent triggeredgroups. The triggersourceand polaritycan be selectedindividuallyforgroup1,group2 and theeventgroupfrom the optionsidentifiedin the firsttablefollowingforMibADC1 and in the second tablefollowingfor MibADC2. Table4-6.MIBADC1 Event TriggerSources Event # SOURCE SELECT BITS forG1, G2 or Hookup EVENT (G1SRC[2:0],G2SRC[2:0] or EVSRC[2:0]) 1 0 AD1EVT 2 1 NHET[8] 3 10 NHET[10] 4 11 RTI compare 0 5 100 NHET[17] 6 101 NHET[19] 7 110 GIOB[0] 8 111 GIOB[1] NOTE The Triggerispresent,even ifthepinisnotavailable. Table4-7.MIBADC2 Event TriggerSources Event # SOURCE SELECT BITS forG1, G2 or Hookup EVENT (G1SRC[2:0],G2SRC[2:0] or EVSRC[2:0]) 1 0 AD2EVT 2 1 NHET[8] 3 10 NHET[10] 4 11 RTI compare 0 5 100 NHET[17] 6 101 NHET[19] 7 110 GIOB[0] 8 111 GIOB[1] NOTE The Triggerispresent,even ifthepinisnotavailable. The applicationcan generatethe triggerconditionusingthesesignalsby configuringthe corresponding devicepinsas inputpinsand drivingthem froman externalsource,orby configuringthem as outputpins and drivingthem by software.The pindoesn'thave tobe presenton thepackage tobe abletobe used as a trigger. The interruptrequestsignals(RTIcompare 0)aredrivenHIGH when theinterruptconditionoccurs.So if theADC isrequiredtobe triggeredon theinterruptbeingasserted,selecttherisingedge forthistrigger source.The ADC can be stilltriggeredusingthefallingedge on theinterruptline.Inthiscase,thefalling edge occurswhen theinterruptlineisdeasserted.

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4.6 MIBSPI

4.6.1 MIBSPI Event TriggerSources

The Multi-bufferedSerialPeripheralInterfaces(MIBSPIs) have a programmable buffermemory that enables data transmissionto be completed withoutCPU intervention.The buffersare combined in differentTransferGroups (TGs)thatcan be triggeredby externaleventssuch as I/Oactivity,timersorby theinternaltickcounter.The internaltickcountersupportstheperiodictriggerofevents.Each bufferofthe MibSPI can be associatedwithdifferentDMA channelsindifferentTGs, allowingtheusertomove data between internalmemory and an externalslavewithminimalCPU interaction. Table4-8.MIBSPI1 Event TriggerSources Event TGxCTRL TRIGSRC[3:0] Hookup Disabled 0 No triggersource EVENT0 1 GIOA[0] EVENT1 10 GIOA[1] EVENT2 11 GIOA[2] EVENT3 100 GIOA[3] EVENT4 101 GIOA[4] EVENT5 110 GIOA[5] EVENT6 111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 NHET[8] EVENT9 1010 NHET[10] EVENT10 1011 NHET[12] EVENT11 1100 NHET[14] EVENT12 1101 NHET[16] EVENT13 1110 NHET[18] EVENT14 1111 InternalTickcounter Table4-9.MIBSPI3 Event TriggerSources Event TGxCTRL TRIGSRC[3:0] Hookup Disabled 0 No triggersource EVENT0 1 GIOA[0] EVENT1 10 GIOA[1] EVENT2 11 GIOA[2] EVENT3 100 GIOA[3] EVENT4 101 GIOA[4] EVENT5 110 GIOA[5] EVENT6 111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 NHET[8] EVENT9 1010 NHET[10] EVENT10 1011 NHET[12] EVENT11 1100 NHET[14] EVENT12 1101 NHET[16] EVENT13 1110 NHET[18] EVENT14 1111 InternalTickcounter Copyright© 2010,Texas InstrumentsIncorporated Peripherals 47 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com Table4-10.MIBSPI5 Event TriggerSources Event TGxCTRL TRIGSRC[3:0] Hookup Disabled 0 No triggersource EVENT0 1 GIOA[0] EVENT1 10 GIOA[1] EVENT2 11 GIOA[2] EVENT3 100 GIOA[3] EVENT4 101 GIOA[4] EVENT5 110 GIOA[5] EVENT6 111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 NHET[8] EVENT9 1010 NHET[10] EVENT10 1011 NHET[12] EVENT11 1100 NHET[14] EVENT12 1101 NHET[16] EVENT13 1110 NHET[18] EVENT14 1111 InternalTickcounter

4.6.2 MIBSPIP5/DMM Pin Multiplexing

The multiplexingofMIBSPIP5 and DMM pinsare controlledby thestatusoftheMIBSPIP5 module and theDMM module.The pinswillhave DMM functionalityiftheDMM module isenabledand theMIBSPIP5 module isdisabled;iftheMIBSPIP5 isenabledthepinswillhave MIBSPI functionality,regardlessofthe DMM module status.DMMCLK, DMMSYNC, DMMENA and DMMDATA[1:0] are always functional independentof the MIBSPIP5 configurationbecause theyare not multiplexed.The relatedpinnumbers can be foundintheMIBSPI5 and theDMM sectionoftheTerminalFunctionschapter.The followingtable shows theMIBSPI5 and DMM Data pinmultiplexing. Table4-11.MIBSPIP5 Pin Multiplexing MIBSPIP5 enabled DMM enabled & MIBSPIP5 disabled MIBSPI5CLK DMMDATA[4] MIBSPI5CS[0] DMMDATA[5] MIBSPI5CS[1] DMMDATA[6] MIBSPI5CS[2] DMMDATA[2] MIBSPI5CS[3] DMMDATA[3] MIBSPI5ENA DMMDATA[7] MIBSPI5SIMO[0] DMMDATA[8] MIBSPI5SIMO[1] DMMDATA[9] MIBSPI5SIMO[2] DMMDATA[10] MIBSPI5SIMO[3] DMMDATA[11] MIBSPI5SOMI[0] DMMDATA[12] MIBSPI5SOMI[1] DMMDATA[13] MIBSPI5SOMI[2] DMMDATA[14] MIBSPI5SOMI[3] DMMDATA[15]

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4.7 ETM

The devicecontainsan ARM Cortex™ -R4F ExternalTraceMacrocell(ETM-R4) witha 32bitdataport.The ETM-R4 module isconnectedtoa TestPortInterfaceUnit(TPIU)witha 32bitdatabus.The ETM-R4 is CoreSightcompliantand followstheARM ETM v3 specification;formore detailssee ARM CoreSight™ ETM-R4 TRM specificationRevr0p0.The ETM-R4 supports"halfrateclocking"only. The ETM clocksource can be selectedas eitherVCLK or the externalETMTRACECLKIN pin.The selectionisdone by theEXTCTRLOUT[1:0] controlbitsoftheTPIU;thedefaultis'00'. Table4-12.ETMTRACECLKIN Selection EXTCTRLOUT[1:0] TPIU/TRACECLKIN 0 tied-low

1 VCLK

10 ETMTRACECLKIN

4.8 Debug Scan Chains

The devicecontainsan ICEPICK module toaccessthedebug scan chains.Debug scan chain#0 handles the access to the CPU, to the ETM-R4 (ExternalTrace Macrocell),to the POM (ParameterOverlay Module)and totheTPIU (TestPortInterfaceUnit).Debug scan chain#1 handlestheaccesstotheRam TracePort(RTP) and theData ModificationModule (DMM) whicheach incorporatea dedicatedTAP (Test Access Port)controller.Each module isselectedviaitsscan chainnumber. The IcePickscan ID is 0x80206D05,whichisthesame number as thedeviceID. Figure4-1.Debug Scan Chains Copyright© 2010,Texas InstrumentsIncorporated Peripherals 49 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

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4.8.1 JTAG

The 32bitJTAG ID code forthisdeviceis0x0B7B302F.

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4.9 CCM

4.9.1 Dual Core Implementation

The microcontrollerhas two Cortex-R4cores,where theoutputsignalsofbothCPUs arecompared inthe CCM-R4 (Core Compare Module).To avoid common mode impactsthe signalsof the CPUs to be compared aredelayedina differentway as shown inthefollowingfigure.. Figure4-2.Dual Core Implementation

4.9.2 CCM-R4

To avoid an erroneousCCM-R4 compare error,the applicationsoftwaremust ensure thatthe CPU registersofbothCPUs areinitializedwiththesame valuesbeforethe1stfunctioncallorotheroperation thatpushes theCPU registersontothestack.AllCCM-R4 errorforcingtestmodes arelimitedto100MHz HCLK speed. Copyright© 2010,Texas InstrumentsIncorporated Peripherals 51 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

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4.10 LPM

TMS570 Platformdevicessupportmultiplelow power modes. These differentmodes allowthe user to trade-offthe amount of currentconsumptionduringlow power mode versusfunctionalityand wake-up time. SupportedLow Power modes on thisdevicesareDoze, Snooze and Sleep;fordetaileddescriptionplease refertotheArchitecturesectionoftheTechnicalReferenceManual.

4.11 VoltageMonitor

A voltagemonitorhas been implemented on thisdevice.The purpose of thisvoltagemonitoris to eliminatetherequirementfora specificsequence when poweringup thecoreand I/Ovoltagesupplies.It alsoreducestheriskofcorruptingmemory orglitcheson I/Opinsduringpower-up,power-down orbrown outs.The voltagemonitordoes noteliminatetheneed ofa voltagesupervisorcircuittoguaranteethatthe deviceisheldinresetwhen thevoltagesuppliesareoutofrange.The voltagemonitorthresholdscan be foundintheVmon sectionofthedeviceelectricalspecifications. When thevoltagemonitordetectsa low voltageon theI/Osupply,itwillasserta reset.When thevoltage monitordetectsa lowvoltageon thecoresupply,itasynchronouslymakes alloutputpinshighimpedance, and assertsa reset.The voltagemonitorisdisabledwhen thedeviceisinhaltmode. The voltagemonitorhas threefilterfunctions:

Itrejectsshortlow-goingglitcheson thePORRST pin
Itrejectsnoiseon theVCCIO supply
Itrejectsnoiseon theVCC supply Please note thatsuch glitcheson VCC and VCCIO couldstillcorruptthe system dependingon many factors.The widthofnoisethatcan be filteredby thevoltagemonitoron theVCC and VCCIO suppliesis shown inthetablebelow.The durationofglitchesthatwillbe filteredon thePORRST pincan be foundin Table7-5,TimingRequirementsforPORRST . Table4-13.VMON Supply GlitchFilterCapability Parameter Min Max Widthofglitchon VCC thatcan be filteredout 250ns 1us Widthofglitchon VCCIO thatcan be filteredout 300ns 1us

4.12 CRC

MCRC Controllerisa module which isused to performCRC (CyclicRedundancy Check) to verifythe integrityof memory system.A signaturerepresentingthe contentsof the memory isobtainedwhen the contentsof the memory are read intoMCRC Controller.The responsibilityof MCRC controlleris to calculatethe signaturefora set of data and then compare the calculatedsignaturevalueagainsta pre-determinedgood signaturevalue.MCRC controllerprovidesup to fourchannelsto performCRC calculationon multiplememories inparalleland can be used on any memory system.Channel 1 can also be put intodata tracemode. In data tracemode, MCRC controllercompresses each data beingread throughtheCPU readdatabus. When usingtheMCRC module inPSA mode whileECC isenabled,bus masters(e.g.FTU, HTU, DMA or CPU) shouldnotwritetothedataRAM (TCRAM) toavoidcorruptingthePSA value.

4.13 System Module

The systemmodule accessmodes and accessrightsareshown inthefollowingtable.

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4.14 Debug ROM

The Debug ROM storesthelocationofthecomponents on theDebug APB bus. Table4-15.Debug ROM Table Address Description Value Components Table 0x000 pointertoCortex-R4 0x00001003 0x000 ETM 0x00002003 0x000 TPIU 0x00003003 0x000 POM 0x00004003 0x001 end oftable 0x00000000 Copyright© 2010,Texas InstrumentsIncorporated Peripherals 53 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

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4.15 CPU SelfTestController:STC /LBIST

The CPU SelfTestController(STC) isused totesttheARM CPU coreusinga DeterministicLogicBIST (LBIST)Controlleras thetestengine.The STC has thecapabilityofdividingthecompletetestrun into smallerindependenttestsets(intervals).The testcoverageand number oftestexecutioncyclesforeach testintervalisshown inthetablebelow. The maximum clockratefortheSTC /LBIST is:

53.333MHz when HCLK = 160MHz /VCLK = 80MHz on BGA package
50MHz when HCLK = 100MHz /VCLK = 100MHz on QFP and BGA packages
46.666MHz when HCLK = 140MHz /VCLK = 70MHz on QFP and BGA packages InordertoachievetheproperclockrateduringCPU selftesta STC clockdividerhas been implemented. The clockdividerissetby theCLKDIV bitsinSTCCLKDIV registerinthesecondarysystem module frame atlocation0xFFFF E108.The defaultvalueoftheCPU SelfTestLBIST clockdividerissettodivide-by-1’. NOTE The supplycurrentwhileperformingCPU selftestisdifferentthan the deviceoperating mode current.These values can be found in the Icc sectionof the device electrical specifications. Table4-16.STC/LBIST TestCoverage and Duration Intervals TestCoverage TestCycles 0 0 0 1 57,14 1555 2 65,82 3108 3 70,56 4661 4 73,56 6214 5 76,06 7767 6 78,07 9320 7 79,62 10873 8 80,92 12426 9 82,1 13979 10 82,94 15532 11 83,76 17085 12 84,51 18638 13 85,12 20191 14 85,62 21744 15 86,19 23297 16 86,56 24850 17 86,97 26403 18 87,33 27956 19 87,67 29509 20 88,01 31062 21 88,31 32615 22 88,58 34168 23 88,87 35721 24 89,11 37274 25 89,34 38827 26 89,59 40380 27 89,82 41933

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5 Device Registers

5.1 Device IdentificationCode Register

The deviceidentificationcode registeridentifiesseveralaspectsofthedeviceincludingthesiliconversion. The detailsofthedeviceidentificationcode registerareshown inFigure11.The deviceidentificationcode registervalueforthisdeviceis:

Rev 0 = 0x80206D05
Rev A = 0x80206D0D Figure5-1.Device ID BitAllocationRegister 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CP-15 UNIQUE ID 16 R-1 R-00000 0000 10000 R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TECH I/O PERIP FLASH ECC RAM VERSION 1 0 1 VOLT HERA ECC AGE L PARIT Y R-0 R-0 R-1 R-10 R-1 R-1 R-1 R-0 R-1 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset;D= devicedependent Table5-1.Device ID BitAllocationRegisterFieldDescriptions Bit Field Value Description

31 CP15 Indicatesthepresenceofcoprocessor15

0 CP15 notpresent

1 CP15 present

30-17 UNIQUE ID 1 Siliconversion(revision)bitsThisbitfieldholdsa uniquenumber fora dedicateddeviceconfiguration (die). 16-13 TECH Processtechnologyon whichthedeviceismanufactured.

0000 C05

0001 F05

0010 C035

0011 F035

12 I/O I/Ovoltageofthedevice. VOLTAGE 0 I/Oare3.3v

1 I/Oare5v

11 PERIPHERA PeripheralParity

0 No parityon peripherals

1 Parityon peripherals

00 No errordetection/correction

01 Program memory withparity

10 Program memory withECC

11 Reserved

8 RAM ECC IndicatesifRAM memory ECC ispresent.

0 No ECC implemented

1 ECC implemented

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5.2 Die-IDRegisters

The two registers(DIEIDLand DIEIDH) forma 64-bitnumber thatcontainsinformationaboutthedevice’s dielotnumber,wafernumber and X, Y wafercoordinates.The dieidentificationinformationwillvaryfrom unitto unit.Thisinformationisprogrammed by TI as partof the initialdevicetestprocedure.The data formatoftheDie-IDregistersisshown here. Figure5-2.DIEIDL Register(Location:0xFFFF FF7C) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LOT (LOWER 10 BITS) WAFER # R-D R-D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Y WAFER COORDINATES X WAFER COORDINATES R-D R-D LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset;D= devicedependent Figure5-3.DIEIDH Register(Location:0xFFFF FF80) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED R-D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED LOT # (UPPER 14 BITS) R-D LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset;D= devicedependent

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5.3 PLL Registers

The defaultvaluesforthePLL (Phase Locked Loop)controlregistersareshown inthissection.PLLCTL1 and PLLCTL2 areused toconfigurePLL1 (F035 FMzPLL) and PLLCTL3 isused toconfigurePLL2 (F035 FPLL). Figure5-4.PLLCTL1 Register(Location:0xFFFF FF70) 31 30 29 28 27 26 25 23 223 21 20 19 18 17 16 ROS BPOS[1:0] PLLDIV[4:0] ROF RESERVED REFCLKDIV[5:0] R/WP- R/WP-01 R/WP-111 R/WP- R-0 R/WP-000010 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PLLMUL[15:0] R/WP-01011111000000000101 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset;D= devicespecific Figure5-5.PLLCTL2 Register(Location:0xFFFF FF74) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FMEN SPREADINGRATE[8:0] RESV EWADJ[8:4] A R/WP- R/WP-111111111 R-0 R/WP-00000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BWADJ[3:0] ODPLL SPR_AMOUNT[8:0] R/WP-0111 R/WP-001 R/WP-000000000 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset;D = devicespecific NOTE There are severalcombinationsofthemodulationdepthand modulationfrequencythatare notallowed.Validsettingsforthisdeviceincludethefollowing:TBD Figure5-6.PLLCTL3 Register(Location:0xFFFF E100) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED OSC RESERVED DIV R/W-000000000 R/WP- R/W-000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PLL_MUL[3:0] RESERVED PLL_DIV [2:0] R/W-000000 R/WP-011 R/W-00000 R/WP 111 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset;D= devicespecific Copyright© 2010,Texas InstrumentsIncorporated DeviceRegisters 59 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

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6 Device ElectricalSpecifications

6.1 OperatingConditions

6.2 AbsoluteMaximum RatingsOver OperatingFree-AirTemperature Range (unless

otherwisenoted)(1) Supplyvoltageranges VCC (2) -0.3V to2.1V VCCIO ,VCCAD ,VCCP (Flashpump) (seeNote 1) -0.3V to4.1V Inputvoltagerange Allinputpins -0.3V to4.1V Inputclamp current IIK(VI<0 orVI> VCCIO ) ±20 mA AllpinsexceptAD1IN[7:0],AD2IN[7:0], ADSIN[15:8] IIK (VI<0 orVI>VCCAD ) AD1IN[7:0],AD2IN[7:0],ADSIN[15:8] ±10 mA total ±40 mA Operatingfree-airtemperature A version -40°C to85°C ranges,TA T version -40°C to105°C Q version -40°C to125°C Operatingjunctiontemperaturerange, -40°C to150°C TJ Storagetemperaturerange,Tstg -65°C to150°C (1) Stressesbeyond thoselistedunder“absolutemaximum ratings”may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder“recommended operating conditions”isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability (2) Allvoltagevaluesarewithrespecttotheirassociatedgrounds.

6.3 Device Recommended OperatingConditions(1)

VCC Digitallogicsupplyvoltage(Core) 1.35 1.5 1.65 V VCCIO Digitallogicsupplyvoltage(I/O) 3 3.3 3.6 V VCCAD MibADC supplyvoltage 3 3.3 3.6 V VCCP Flashpump supplyvoltage 3 3.3 3.6 V VSS Digitallogicsupplyground 0 V VSSAD MibADC supplyground -0.1 0.1 V TA Operatingfree-airtemperature A version -40 85 °C T version -40 105 °C Q version -40 125 °C TJ Operatingjunctiontemperature -40 150 °C (1) AllvoltagesarewithrespecttoVSS exceptVCCAD iswithrespecttoVSSAD .

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6.4 ElectricalCharacteristicsOver OperatingFree-AirTemperature Range (1)

Parameter TestConditions MIN TYP MAX Unit Vhys Inputhysteresis 0.15 V VIL Low-levelinputvoltage Allinputs(2) -0.3 0.8 V VIH High-levelinputvoltage Allinputs 2 VCCIO + V 0.3 VOL Low-leveloutputvoltage IOL = IOL MAX 0.2VCCIO V IOL = 50 µA 0.2 VOH High-leveloutputvoltage IOH = IOH MAX 0.8VCCIO V IOH = 50 µA VCCIO - 0.2 VILoscin Low-levelinputvoltage OSCIN -0.3 0.2VCC V VIHoscin High-levelinputvoltage OSCIN 0.8VCC VCC + 0.3 V VMON Voltagemonitoring VCC low 1.1 1.2 1.35 V threshold VCC high 1.7 2 2.38 VCCIO low 2.0 2.4 3.0 IIC Inputclamp current VI< VSSIO -0.3orVI -2 2 mA > VCCIO + 0.3 II Inputcurrent(I/Opins) IILPulldown VI= VSS -1 1 µA IIH Pulldown20 mA VI= VCCIO 5 40 IIH Pulldown100 VI= VCCIO 40 195 mA IILPullup20 mA VI= VSS -40 -5 IILPullup100 mA VI= VSS -195 -40 IIH Pullup VI= VCCIO -1 1 Allotherpins No pulluporpulldown -1 1 (1) Sourcecurrents(outofthedevice)arenegativewhilesinkcurrents(intothedevice)arepositive. (2) Thisdoes notapplytoPORRST pin. Copyright© 2010,Texas InstrumentsIncorporated DeviceElectricalSpecifications 61 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

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PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010 ElectricalCharacteristicsOver OperatingFree-AirTemperature Range (1) (continued) Parameter TestConditions MIN TYP MAX Unit IOH High-leveloutput TDO VOH = VOH MIN -8 mA current TDI TMS RTCK ECLK FRAYRX1 FRAYTX1 FRAYTXEN1 FRAYRX2 FRAYTX2 FRAYTXEN2 DMMENA ETMTRACECTL ETMTRACECLKO UT ETMDATA[31:0] RTPSYNC RTPCLK RTPDATA[15:0] DMMENA EMIFWE EMIFOE EMIFCS[3:0] EMIFDATA[15:0] EMIFADD[21:0] EMIFBADD[1:0] EMIFDQM[1:0] ERROR IOH High-leveloutput RST VOH = VOH MIN -4 mA current MIBSPI1CLK MIBSPI1SIMO MIBSPI1SOMI MIBSPI3CLK MIBSPI3SIMO MIBSPI3SOMI MIBSPI5CLK MIBSPI5SIMO[3:0] MIBSPI5SOMI[3:0] DMMDATA[15:8] DMMDATA[4] Allotheroutput -2 pins Copyright© 2010,Texas InstrumentsIncorporated DeviceElectricalSpecifications 63 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com ElectricalCharacteristicsOver OperatingFree-AirTemperature Range (1) (continued) Parameter TestConditions MIN TYP MAX Unit ICC (3) VCC Digitalsupply Allpackages HCLK = 100MHz, 350 mA current(Operating VCLK = 100MHz mode) HCLK = 140MHz, 390 mA VCLK= 70MHz BGA packages HCLK = 160MHz, 430 mA VCLK = 80MHz VCC Digitalsupply Allpackages LBIST (STC) CLK = 450 mA current(CPU selftest 46.666MHz mode: LBIST) LBIST (STC) CLK = 500 mA 50.0MHz BGA packages LBIST (STC) CLK = 550 mA 53.333MHz VCC Digitalsupply Allpackages HCLK=80MHz, 320 mA current(Mem selftest VCLK=40MHz mode: PBIST) HCLK=100MHz, 400 mA VLCK=100MHz VCC Digitalsupplycurrent(dozemode) OSCIN = 6 MHz, VCC 35 mA = 1.65V (4) VCC Digitalsupplycurrent(snoozemode) Allfrequencies,VCC = 30 mA 1.65V (4) VCC Digitalsupplycurrent(sleepmode) Allfrequencies,VCC = 10 mA 1.65V (4) ICCIO VCCIO Digitalsupplycurrent(operatingmode) No DC load,VCCIO = 15 mA 3.6V (5) VCCIO Digitalsupplycurrent(dozemode) No DC load,VCCIO = 100 mA 3.6V (5) VCCIO Digitalsupplycurrent(snoozemode) No DC load,VCCIO = 100 mA 3.6V (5) VCCIO Digitalsupplycurrent(sleepmode) No DC load,VCCIO = 100 mA 3.6V (5) ICCAD VCCAD supplycurrent(operatingmode) Allfrequencies,VCCAD 30 mA = 3.6V VCCAD supplycurrent(dozemode) Allfrequencies,VCCAD 10 mA = 3.6V (6) VCCAD supplycurrent(snoozemode) Allfrequencies,VCCAD 10 mA = 3.6V (6) VCCAD supplycurrent(sleepmode) Allfrequencies,VCCAD 10 mA = 3.6V (6) ICCP VCCP pump supplycurrent VCCP = 3.6V read 25 mA operation VCCP = 3.6V 90 mA program(7) VCCP = 3.6V erase 90 mA VCCP = 3.6V doze 5 mA mode (6) VCCP = 3.6V snooze 5 mA mode (6) VCCP = 3.6V sleep 5 mA mode (6) C I Inputcapacitance(8) 2 pF (3) TypicalvaluesareatVcc=1.5V and maximum valuesareatVcc=1.65V (4) ForFlashbanks/pumpsinsleepmode. (6) ForFlashbanks/pumpsinsleepmode. (7) Thisassumes readingfromone bank whileprogrammingthesame bank. (8) The maximum inputcapacitanceC IoftheFlexrayRX pin(s)is10pF.

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PRODUCT□PREVIEW OSCIN OSCOUT (see Note A) Crystal (a) (b) External (toggling 0-1.5V) Clock Signal Kelvin_GND (see Note B) OSCOUTOSCIN TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com

7 Peripheraland ElectricalSpecifications

7.1 Clocks

7.1.1 PLL And Clock Specifications

Table7-1.Timing Requirements For PLL CircuitsEnabled Or Disabled MIN MAX Unit f(OSC) Inputclockfrequency 5 20 MHz tc(OSC) Cycletime,OSCIN 50 ns tw(OSCIL) Pulseduration,OSCIN low 15 ns tw(OSCIH) Pulseduration,OSCIN high 15 ns f(OSCRST) OSC FAIL frequency-upperlevel 20 50 MHz f(OSCRST) OSC FAIL frequency-lowerlevel 1.5 5 MHz

7.1.2 ExternalReferenceResonator/CrystalOscillatorClock Option

The oscillatorisenabledby connectingtheappropriatefundamental5–20 MHz resonator/crystaland load capacitorsacrosstheexternalOSCIN and OSCOUT pinsas shown insection(a)ofthefigurebelow.The oscillatorisa singlestageinverterheldinbiasby an integratedbiasresistor.Thisresistorisdisabled duringleakagetestmeasurement and HALT mode. NOTE TI stronglyencourages each customer to submit samples of the device to the resonator/crystalvendorsforvalidation.The vendorsare equippedto determinewhat load capacitorswillbest tune theirresonator/crystalto the microcontrollerdeviceforoptimum start-upand operationovertemperature/voltageextremes. An externaloscillatorsourcecan be used by connectinga 1.5V clocksignaltotheOSCIN pinand leaving theOSCOUT pinunconnected(open)as shown insection(b)ofthefigurebelow. Figure7-1.Recommended Crystal/ClockConnection NOTE Infigure(a),The valuesofC1 and C2 shouldbe providedby theresonator/crystalvendor. Infigure(b),Kelvin_GND shouldnotbe connectedtoany otherGND.

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PRODUCT□PREVIEW guaranteed fail lower- threshold guaranteed pass upper- threshold guaranteed fail f[MHz] 1.5 5.0 20.0 50.0 TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010

7.1.3 LPO And Clock Detection

The LPOCLKDET module consistsofa clockmonitor(CLKDET) and 2 low power oscillators(LPO) -a low frequency(LF)and a highfrequency{HF)oscillator.The CLKDET isa supervisorcircuitforan externally suppliedclocksignal.Incase theexternallysuppliedclockfrequencyfallsoutofa frequencywindow,the clockdetectorflagsthisconditionand switchestotheHF LPO clock(limpmode).The OSCFAIL flagand clockswitch-overremain,regardlessofthebehavioroftheoscillatorclocksignal.The onlyway OSCFAIL can be cleared(andre-enableOSCIN as theclocksource)isa power-on-reset. Table7-2.LPO And Clock Detection Parameter MIN Type MAX Unit Invalidfrequency lowerthreshold 1.5 5 MHz upperthreshold 20 50 MHz Limp mode frequency(HFosc) TBD 10 TBD MHz HFosc frequency TBD 10 TBD MHz LFosc frequency TBD 80 TBD kHz Figure7-2.LPO And Clock Detection Copyright© 2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 67 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW Address Waitstates Data Waitstates RAM Address Waitstates Data Waitstates Flash 0MHz 0MHz 0MHz 0MHz f(HCLK) f(HCLK) f(HCLK) f(HCLK) 100MHz 108MHz72MHz36MHz 0 1 2 3 0 1 TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com

7.1.4 SwitchingCharacteristicsOver Recommended OperatingConditionsFor Clocks

Table7-3.SwitchingCharacteristicsOver Recommended OperatingConditionsFor Clocks Parameter TestConditions MIN MAX Unit f(HCLK) HCLK -System clockfrequency(BGA packages) Pipelinemode enabled 160 MHz Pipelinemode disabled 36 MHz f(HCLK) HCLK -System clockfrequency(144pinQFP Pipelinemode enabled 140 MHz package) Pipelinemode disabled 36 MHz f(GCLK) GCLK -CPU clockfrequency(ratioGCLK : f(HCLK) MHz HCLK = 1:1) f(RTICLK) RTICLK -clockfrequency f(VCLK) MHz f(VCLK) VCLK -Primaryperipheralclockfrequency 100 MHz f(VCLK2) VCLK2 -Secondaryperipheralclockfrequency f(VCLK) MHz f(AVCLK1) AVCLK1 -Primaryasynchronousperipheralclock f(VCLK) MHz frequency f(AVCLK2) AVCLK2 -Secondaryasynchronousperipheral f(VCLK) MHz clockfrequency f(ECLK) (1) ECLK -ExternalclockoutputfrequencyforECP 80 MHz Module f(PROG/ERASE) System clockfrequency-Flash f(HCLK) MHz programming/erase (1) (ECLK) = f(VCLK)/N, where N = {1to65536}.N istheECP prescalevaluedefinedby theECPCNTL.[15:0]registerbitsintheSystem module.Pipelinemode enabledordisabledisdeterminedby theFRDCNTL[2:0].

7.1.4.1 Timing -Wait States

Figure7-3.Wait States NOTE IfFMzPLL frequencymodulationisenabled,specialcaremust be takentoensurethatthe maximum system clockfrequencyf(HCLK)and peripheralclockfrequencyf(VCLK)are not exceeded. The speed of the deviceclocksmay need be deratedto accommodate the modulationdepthwhen FMzPLL frequencymodulationisenabled.

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PRODUCT□PREVIEW ECLK TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010

7.2 ECLK Specification

7.2.1 SwitchingCharacteristicsOver Recommended OperatingConditionsFor External

Table7-4.SwitchingCharacteristicsOver Recommended OperatingConditionsFor ExternalClocks(1)(2) NO. Parameter TestConditions MIN MAX Unit 3 tw(EOL) Pulseduration,ECLK underallprescale 0.5tc(ECL ns low factorcombinations(X K) – tf and N) 4 tw(EOH) Pulseduration,ECLK underallprescale 0.5tc(ECL ns high factorcombinations(X K) – tr and N) (1) X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}.X istheVBUS interfaceclockdividerratiodeterminedby theCLKCNTL.[19:16]bitsinthe SYS module. (2) N = {1to65536}.N istheECP prescalevaluedefinedby theECPCNTL.[15:0]registerbitsintheSystem module. Figure7-4.ECLK Timing Diagram Copyright© 2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 69 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW 3.3 V 1.5 V CCIOPORL PORRST VCC (1.5 V) VCCPORH V VIL(PORRST) VCCIOPORHVCCIOPORH VCCIOPORL VCCPORL VCC VCCIO / VCCP VCCPORH VCCPORL VILVIL VIL VILVIL(PORRST) TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com

7.3 RST And PORRST Timings

7.3.1 Timing Requirements For PORRST

Table7-5.Timing Requirements For PORRST NO. MIN MAX Unit VCCPORL VCC lowsupplylevelwhen PORRST must be activeduringpower up 0.5 V VCCPORH VCC highsupplylevelwhen PORRST must remainactiveduringpower up 1.35 V and become activeduringpower down VCCIOPORL VCCIO /VCCP lowsupplylevelwhen PORRST must be activeduring 1.1 V power up VCCIOPORH VCCIO /VCCP highsupplylevelwhen PORRST must remainactiveduring 3 V power up and become activeduringpower down VIL(PORRST) Low-levelinputvoltageofPORRST VCCIO > 2.5V 0.2VCCIO V Low-levelinputvoltageofPORRST VCCIO < 2.5V 0.5 V 3 tsu(PORRST) Setuptime,PORRST activebeforeVCCIO and VCCP > VCCIOPORL during 0 ms power up 6 th(PORRST) Holdtime,PORRST activeafterVCC > VCCPORH 1 ms 7 tsu(PORRST) Setuptime,PORRST activebeforeVCC <= VCCPORH duringpower down 8 ms 8 th(PORRST) Holdtime,PORRST activeafterVCCIO and VCCP > VCCIOPORH 1 ms 9 th(PORRST) Holdtime,PORRST activeafterVCC < VCCPORL 0 ms tf(PORRST) FiltertimePORRST, pulseslessthanMIN willbe filteredout,pulses 30 150 ns greaterthanMAX areguaranteedtogeneratea reset tf(RST) FiltertimeRST, pulseslessthanMIN willbe filteredout,pulsesgreater 40 150 ns thanMAX areguaranteedtogeneratea reset Figure7-5.PORRST Timing Diagram NOTE Thereisno timingdependency between theramp oftheVCCIO and theVCC supplyvoltage; thisisjustan exemplarydrawing.Allrequirementsare to ensurePORRST isactivewhen VCCIO orVCC isoutofthenormaloperatingrange.

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7.3.2 SwitchingCharacteristicsOver Recommended OperatingConditionsFor RST

Table7-6.SwitchingCharacteristicsOver Recommended OperatingConditionsFor RST (1) Parameter MIN MAX Unit tv(RST) Validtime,RST activeafterPORRST inactive 1048c(OSC) ns Validtime,RST active(allothers) 8tc(VCLK) (1) Specifiedvaluesdo NOT includerise/falltimes.Forriseand falltimings,see theswitchingcharacteristicsforoutputtimingsversusload capacitancetable. Copyright© 2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 71 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW 1 1 TMS TDI TDO RTCK TCK TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com

7.4 DAP -JTAG Scan InterfaceTiming

7.4.1 JTAG clockspecification12-MHz and 50-pF loadon TDO output

Table7-7.JTAG Scan InterfaceTiming NO. MIN MAX Unit f(TCK) TCK frequency(atHCLKmax) 12 MHz f(RTCK) RTCK frequency(atTCKmax and HCLKmax) 10 MHz 1 td(TCK -RTCK) Delaytime,TCK toRTCK 20 ns 2 tsu(TDI/TMS -RTCKr) Setuptime,TDI,TMS beforeRTCK rise(RTCKr) 15 ns 3 th(RTCKr -TDI/TMS) Holdtime,TDI,TMS afterRTCKr 0 ns 4 th(RTCKr -TDO) Holdtime,TDO afterRTCKr 0 ns 5 td(RTCKf -TDO) Delaytime,TDO validafterRTCK fall(RTCKf) 10 ns Figure7-6.JTAG timing

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PRODUCT□PREVIEW 80% 80% 20% 20% 0 Output tr tf VCCIO TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010

7.5 Output Timings

Table7-8.SwitchingCharacteristicsFor Output Timings Versus Load Capacitance© L) Parameter MIN MAX Unit tr 8mA pins C L = 15 pF 2.5 ns C L = 50 pF 5 C L = 100 pF 9 C L = 150 pF 12 tf 8mA pins C L = 15 pF 2.5 ns C L = 50 pF 5 C L = 100 pF 9 C L = 150 pF 12 tr 4mA pins C L = 15 pF 7 ns C L = 50 pF 13 C L = 100 pF 21 C L = 150 pF 29 tf 4mA pins C L = 15 pF 7 ns C L = 50 pF 13 C L = 100 pF 21 C L = 150 pF 29 tr 2mA-z pins C L = 15 pF 10 ns C L = 50 pF 17 C L = 100 pF 25 C L = 150 pF 35 tf 2mA-z pins C L = 15 pF 10 ns C L = 50 pF 17 C L = 100 pF 25 C L = 150 pF 35 Figure7-7.CMOS-Level Outputs Copyright© 2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 73 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW VCCIO80% 80% 20% 20% 0 Input tpw TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com

7.6 InputTimings

7.6.1 Timing Requirements For InputTimings(1)

Table7-9.Timing Requirements For InputTimings MIN MAX Unit tpw Inputminimum pulsewidth tc(VCLK) + 10(1) ns (1) tc(VCLK) = peripheralVBUS clockcycletime= 1 /f(VCLK) (1) The timingshown above isonlyvalidforpinused inGIO mode Figure7-8.CMOS-Level Inputs

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7.7 FlashTimings

Table7-10.Timing Requirements For Program Flash MIN NOM MAX Unit tprog(32-bit) Fullword (32-bit)programmingtime 33 300 µs tprog(Total) 2M-byteprogramming -40°C to125°C 17 74 s time(1) 0°C to60C, forfirst25 17 25 s cycles tprog ECC(16-bit) ECC programmingtime 33 300 µs tprog ECC(total) TotalECC bit -40°C to125°C 4.3 15 s programmingtime 0°C to60°C, forfirst25 4.3 7 s(256k-byte) cycles terase(sector) Sectorerasetime -40°C to125°C 2 15 s (includingcompaction) 0°C to60°C, forfirst25 1.5 10 s cycles terase(bank) Bank erasetime(includingBank 0 7.5 20 s compaction),0Cto60C, Bank 1 5.5 12 sforfirst25 cycles Bank 2 5.5 12 s Bank 3 5.5 12 s twec Write/erasecyclesatTA = 125°C with15 yearData 1000 cycles Retentionrequirement (1) Thisprogrammingtimeincludesoverheadofstatemachine,butdoes notincludedatatransfertime. Copyright© 2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 75 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com

7.8 SPI Master Mode Timing Parameters

7.8.1 SPI Master Mode ExternalTiming Parameters (CLOCK PHASE = 0,SPICLK = output,

SPISIMO = output,and SPISOMI = input) Table7-11.SPI Master Mode ExternalTiming Parameters(1)(2)(3) NO. MIN MAX Unit 1 tc(SPC)M Cycletime,SPICLK (4) 50 256tc(VCLK) ns 2(5) tw(SPCH)M Pulseduration,SPICLK high(clockpolarity= 0) 0.5tc(SPC)M– 3 – tr 0.5tc(SPC)M+ 5 ns tw(SPCL)M Pulseduration,SPICLK low(clockpolarity= 1) 0.5tc(SPC)M– 3 – tf 0.5tc(SPC)M+ 5 3(5) tw(SPCL)M Pulseduration,SPICLK low(clockpolarity= 0) 0.5tc(SPC)M– 3 – tf 0.5tc(SPC)M+ 5 ns tw(SPCH)M Pulseduration,SPICLK high(clockpolarity= 1) 0.5tc(SPC)M– 3 – tr 0.5tc(SPC)M+ 5 4(5) td(SPCH-SIMO)M Delaytime,SPISIMO validbeforeSPICLK low 0.5tc(SPC)M– 10 ns (clockpolarity= 0) td(SPCL-SIMO)M Delaytime,SPISIMO validbeforeSPICLK high 0.5tc(SPC)M– 10 (clockpolarity= 1) 5(5) tv(SPCL-SIMO)M Validtime,SPISIMO datavalidafterSPICLK low 0.5tc(SPC)M– tf(SPC) ns (clockpolarity= 0) -5 tv(SPCH-SIMO)M Validtime,SPISIMO datavalidafterSPICLK high 0.5tc(SPC)M– tr(SPC) (clockpolarity= 1) -5 6(5) tsu(SOMI-SPCL)M Setuptime,SPISOMI beforeSPICLK low(clock tf(SPC) ns polarity= 0) tsu(SOMI-SPCH)M Setuptime,SPISOMI beforeSPICLK high(clock tr(SPC)+ 4 polarity= 1) 7(5) th(SPCL-SOMI)M Holdtime,SPISOMI datavalidafterSPICLK low 10 ns (clockpolarity= 0) th(SPCH-SOMI)M Holdtime,SPISOMI datavalidafterSPICLK high 10 (clockpolarity= 1) 8(6) tC2TDELAY SetuptimeCS activeuntilSPICLK high(clock C2TDELAY*t c(VCLK) + ns polarity= 0) 2*tc(VCLK) -tf(SPICS)+ tr(SPC) SetuptimeCS activeuntilSPICLK low(clock C2TDELAY*t c(VCLK) + ns polarity= 1) 2*tc(VCLK) -tf(SPICS)+ tf(SPC) 9(6) tT2CDELAY HoldtimeSPICLK lowCS untilinactive(clock 0.5*tc(SPC)M + ns polarity= 0) T2CDELAY*t c(VCLK) + tc(VCLK) - tf(SPC)+ tr(SPICS) HoldtimeSPICLK highuntilCS inactive(clock 0.5*tc(SPC)M + ns polarity= 1) T2CDELAY*t c(VCLK) + tc(VCLK) - tr(SPC)+ tr(SPICS) 10 tSPIENA SPIENAn Sample point (C2TDELAY+1)*tc(VCLK) (C2TDELAY+1)*tc(VCLK) ns -tf(SPICS) 11 tSPIENAW SPIENAn Sample pointfromwritetobuffer (C2TDELAY+2)*tc(VCLK) ns (1) The MASTER bit(SPIGCR1.0)issetand theCLOCK PHASE bit(SPIFMTx.16)isset. (2) tc(VCLK)= interfaceclockcycletime= 1 /f(VCLK)\\ (3) Forriseand falltimings,see the"switchingcharacteristicsforoutputtimingsversusloadcapacitance"table. (4) When theSPI isinMastermode, thefollowingmust be true: ForPS valuesfrom1 to255:tc(SPC)M ≥ (PS +1)tc(VCLK)≥ 50 ns,where PS istheprescalevaluesetintheSPIFMTx.[15:8]register bits. ForPS valuesof0:tc(SPC)M = 2tc(VCLK)≥ 50 ns.The externalloadon theSPICLK pinmust be lessthan60pF. (5) The activeedge oftheSPICLK signalreferencediscontrolledby theCLOCK POLARITY bit(SPIFMTx.17). (6) C2TDELAY and T2CDELAY areprogrammed intheSPIDELAY register

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PRODUCT□PREVIEW SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) Master In Data Must Be Valid Master Out Data Is Valid SPICLK (clock polarity = 0) SPISIMO SPICSn Master Out Data Is Valid SPICLK (clock polarity = 1) SPIENAn Write to buffer 1 1 8 9 TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010 Figure7-9.SPI Master Mode ExternalTiming (CLOCK PHASE = 0) Figure7-10.SPI Master Mode Chip Selecttiming(CLOCK PHASE = 0) Copyright© 2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 77 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com

7.8.2 SPI Master Mode ExternalTiming Parameters (CLOCK PHASE = 1,SPICLK = output,

SPISIMO = output,and SPISOMI = input)(7)(8)(9) Table7-12.SPI Master Mode ExternalTiming Parameters NO. MIN MAX Unit 1 tc(SPC)M Cycletime,SPICLK (1) 50 256tc(VCLK) ns 2(2) tw(SPCH)M Pulseduration,SPICLK high(clockpolarity= 0) 0.5tc(SPC)M– 3 – tr 0.5tc(SPC)M+ 5 ns tw(SPCL)M Pulseduration,SPICLK low(clockpolarity= 1) 0.5tc(SPC)M– 3 – tf 0.5tc(SPC)M+ 5 3(2) tw(SPCL)M Pulseduration,SPICLK low(clockpolarity= 0) 0.5tc(SPC)M– 3 – tr 0.5tc(SPC)M+ 5 ns tw(SPCH)M Pulseduration,SPICLK high(clockpolarity= 1) 0.5tc(SPC)M– 3 – tf 0.5tc(SPC)M+ 5 4(2) tv(SIMO-SPCH)M Validtime,SPICLK highafterSPISIMO data 0.5tc(SPC)M– 15 ns valid(clockpolarity= 0) tv(SIMO-SPCL)M Validtime,SPICLK lowafterSPISIMO datavalid 0.5tc(SPC)M– 15 (clockpolarity= 1) 5(2) tv(SPCH-SIMO)M Validtime,SPISIMO datavalidafterSPICLK 0.5tc(SPC)M– tr(SPC) ns high(clockpolarity= 0) tv(SPCL-SIMO)M Validtime,SPISIMO datavalidafterSPICLK 0.5tc(SPC)M– tf(SPC) low(clockpolarity= 1) 6(2) tsu(SOMI-SPCH)M Setuptime,SPISOMI beforeSPICLK high(clock 4 ns polarity= 0) tsu(SOMI-SPCL)M Setuptime,SPISOMI beforeSPICLK low(clock 4 polarity= 1) 7(2) tv(SPCH-SOMI)M Validtime,SPISOMI datavalidafterSPICLK high 6 ns (clockpolarity= 0) tv(SPCL-SOMI)M Validtime,SPISOMI datavalidafterSPICLK low 6 (clockpolarity= 1) 8(3) tC2TDELAY SetuptimeCS activeuntilSPICLK high(clock 0.5*tc(SPC)M + ns polarity= 0) C2TDELAY*t c(VCLK) + 2*tc(VCLK) -tf(SPICS)+ tr(SPC) SetuptimeCS activeuntilSPICLK low(clock 0.5*tc(SPC)M + ns polarity= 1) C2TDELAY*t c(VCLK) + 2*tc(VCLK) -tf(SPICS)+ tf(SPC) 9(3) tT2CDELAY HoldtimeSPICLK lowCS untilinactive(clock T2CDELAY*t c(VCLK) + ns polarity= 0) tc(VCLK) -tf(SPC)+ tr(SPICS) HoldtimeSPICLK highuntilCS inactive(clock T2CDELAY*t c(VCLK) + ns polarity= 1) tc(VCLK) -tr(SPC)+ tr(SPICS) 10 tSPIENA SPIENAn Sample Point (C2TDELAY+1)*tc(VCLK) (C2TDELAY+1)*tc(VCLK) ns -tf(SPICS) 11 tSPIENAW SPIENAn Sample pointfromwritetobuffer (C2TDELAY+2)*tc(VCLK) ns (7) The MASTER bit(SPIGCR1.0)issetand theCLOCK PHASE bit(SPIFMTx.16)isset. (8) tc(VCLK)= interfaceclockcycletime= 1 /f(VCLK) (9) Forriseand falltimings,see the"switchingcharacteristicsforoutputtimingsversusloadcapacitance"table. (1) When theSPI isinMastermode, thefollowingmust be true: ForPS valuesfrom1 to255:tc(SPC)M ≥ (PS +1)tc(VCLK)≥ 50 ns,where PS istheprescalevaluesetintheSPIFMTx.[15:8]register bits. ForPS valuesof0:tc(SPC)M = 2tc(VCLK)≥ 50 ns.The externalloadon theSPICLK pinmust be lessthan60pF. (2) The activeedge oftheSPICLK signalreferencediscontrolledby theCLOCK POLARITY bit(SPIFMTx.17). (3) C2TDELAY and T2CDELAY areprogrammed intheSPIDELAY register

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PRODUCT□PREVIEW Master In Data Must Be Valid Master Out Data Is Valid Data Valid SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) SPICLK (clock polarity = 0) SPISIMO SPICS Master Out Data Is Valid SPICLK (clock polarity = 1) SPIENA Write to buffer 1 1 8 9 TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010 Figure7-11.SPI Master Mode ExternalTiming (CLOCK PHASE = 1) Figure7-12.SPI Master Mode Chip Selecttiming(CLOCK PHASE = 1) Copyright© 2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 79 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com

7.9 SPI SlaveMode Timing Parameters

7.9.1 SPI SlaveMode ExternalTiming Parameters (CLOCK PHASE = 0,SPICLK = input,

SPISIMO = input,and SPISOMI = output)(4)(5)(6)(7) Table7-13.SPI SlaveMode ExternalTiming Parameters NO. MIN MAX Unit 1 tc(SPC)S Cycletime,SPICLK (1) 50 256tc(VCLK) ns 2(2) tw(SPCH)S Pulseduration,SPICLK high(clockpolarity= 0) 0.5tc(SPC)S– 0.5tc(SPC)S+ ns 0.25tc(VCLK) 0.25tc(VCLK) tw(SPCL)S Pulseduration,SPICLK low(clockpolarity= 1) 0.5tc(SPC)S– 0.5tc(SPC)S+ 0.25tc(VCLK) 0.25tc(VCLK) 3(2) tw(SPCL)S Pulseduration,SPICLK low(clockpolarity= 0) 0.5tc(SPC)S– 0.5tc(SPC)S+ ns 0.25tc(VCLK) 0.25tc(VCLK) tw(SPCH)S Pulseduration,SPICLK high(clockpolarity= 1) 0.5tc(SPC)S– 0.5tc(SPC)S+ 0.25tc(VCLK) 0.25tc(VCLK) 4(2) td(SPCH-SOMI)S Delaytime,SPISOMI validafterSPICLK high trf(SOMI)+ 15 ns (clockpolarity= 0) td(SPCL-SOMI)S Delaytime,SPISOMI validafterSPICLK low(clock trf(SOMI)+ 15 polarity= 1) 5(2) tH(SPCH-SOMI)S Holdtime,SPISOMI datavalidafterSPICLK high 0 ns (clockpolarity=0) tH(SPCL-SOMI)S Holdtime,SPISOMI datavalidafterSPICLK low 0 (clockpolarity=1) 6(2) tsu(SIMO-SPCL)S Setuptime,SPISIMO beforeSPICLK low(clock 4 ns polarity= 0) tsu(SIMO-SPCH)S Setuptime,SPISIMO beforeSPICLK high(clock 4 polarity= 1) 7(2) th(SPCL-SIMO)S Holdtime,SPISIMO datavalidafterSPICLK low 6 ns (clockpolarity= 0) th(SPCH-SIMO)S Holdtime,SPISIMO datavalidafterS PICLK high 6 (clockpolarity= 1) 8 td(SPCL-SENAH)S Delaytime,SPIENAn highafterlastSPICLK low 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) ns (clockpolarity= 0) td(SPCH-SENAH)S Delaytime,SPIENAn highafterlastSPICLK high 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) (clockpolarity= 1) 9 td(SCSL-SENAL)S Delaytime,SPIENAn lowafterSPICSn low(ifnew tf(ENAn)+6 ns datahas been writtentotheSPI buffer) (4) The MASTER bit(SPIGCR1.0)issetand theCLOCK PHASE bit(SPIFMTx.16)isset. (5) IftheSPI isinslavemode, thefollowingmust be true:tc(SPC)S >= (PS + 1)tc(VCLK),where PS = prescalevaluesetinSPIFMTx.[15:8]. (6) tc(VCLK) = interfaceclockcycletime= 1 /f(VCLK) (7) Forriseand falltimings,see the"switchingcharacteristicsforoutputtimingsversusloadcapacitance"table. (1) When theSPI isinSlavemode, thefollowingmust be true: ForPS valuesfrom1 to255:tc(SPC)S >= (PS +1)tc(VCLK) >= 50 ns,where PS istheprescalevaluesetintheSPIFMTx.[15:8]registerbits. ForPS valuesof0:tc(SPC)S = 2tc(VCLK) >= 50 ns. (2) The activeedge oftheSPICLK signalreferencediscontrolledby theCLOCK POLARITY bit(SPIFMTx.17).

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PRODUCT□PREVIEW SPISIMO Data Must Be Valid SPISOMI Data Is ValidSPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) SPICLK (clock polarity = 0) SPICSn SPICLK (clock polarity = 1) SPIENAn TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010 Figure7-13.SPI SlaveMode ExternalTiming (CLOCK PHASE = 0) Figure7-14.SPI SlaveMode Enable Timing (CLOCK PHASE = 0) Copyright© 2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 81 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com

7.9.2 SPI SlaveMode ExternalTiming Parameters (CLOCK PHASE = 1,SPICLK = input,

SPISIMO = input,and SPISOMI = output)(3)(4)(5)(6) Table7-14.SPI SlaveMode ExternalTiming Parameters NO. MIN MAX Unit 1 tc(SPC)S Cycletime,SPICLK (1) 50 256tc(VCLK) ns 2(2) tw(SPCH)S Pulseduration,SPICLK high(clockpolarity= 0) 0.5tc(SPC)S– 0.5tc(SPC)S+ ns 0.25tc(VCLK) 0.25tc(VCLK) tw(SPCL)S Pulseduration,SPICLK low(clockpolarity= 1) 0.5tc(SPC)S– 0.5tc(SPC)S+ 0.25tc(VCLK) 0.25tc(VCLK) 3(2) tw(SPCL)S Pulseduration,SPICLK low(clockpolarity= 0) 0.5tc(SPC)S– 0.5tc(SPC)S+ ns 0.25tc(VCLK) 0.25tc(VCLK) tw(SPCH)S Pulseduration,SPICLK high(clockpolarity= 1) 0.5tc(SPC)S– 0.5tc(SPC)S+ 0.25tc(VCLK) 0.25tc(VCLK) 4(2) td(SOMI- Delaytime,SPISOMI datavalidafterSPICLK low trf(SOMI)+15 ns SPCL)S (clockpolarity= 0) td(SOMI- Delaytime,SPISOMI datavalidafterSPICLK high trf(SOMI)+15 SPCH)S (clockpolarity= 1) 5(2) tH(SPCL- Holdtime,SPISOMI datavalidafterSPICLK high 0 ns SOMI)S (clockpolarity=0) tH(SPCH- Holdtime,SPISOMI datavalidafterSPICLK low 0 SOMI)S (clockpolarity=1) 6(2) tsu(SIMO- Setuptime,SPISIMO beforeSPICLK high(clock 4 ns SPCH)S polarity= 0) tsu(SIMO- Setuptime,SPISIMO beforeSPICLK low(clock 4 SPCL)S polarity= 1) 7(2) tv(SPCH- Hightime,SPISIMO datavalidafterSPICLK high 6 ns SIMO)S (clockpolarity= 0) tv(SPCL- Hightime,SPISIMO datavalidafterSPICLK low 6 SIMO)S (clockpolarity= 1) 8 td(SPCH- Delaytime,SPIENAn highafterlastSPICLK high 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) ns SENAH)S (clockpolarity= 0) td(SPCL- Delaytime,SPIENAn highafterlastSPICLK low 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) SENAH)S (clockpolarity= 1) 9 td(SCSL- Delaytime,SPIENAn lowafterSPICSn low(ifnew tf(ENAn)+6 ns SENAL)S datahas been writtentotheSPI buffer) 10 td(SCSL- Delaytime,SOMI validafterSPICSn low(ifnew data trf(SOMI)+6 ns SOMI)S has been writtentotheSPI buffer) (3) The MASTER bit(SPIGCR1.0)issetand theCLOCK PHASE bit(SPIFMTx.16)isset. (4) IftheSPI isinslavemode, thefollowingmust be true:tc(SPC)S >= (PS + 1)tc(VCLK),where PS = prescalevaluesetinSPIFMTx.[15:8]. (5) tc(VCLK) = interfaceclockcycletime= 1 /f(VCLK) (6) Forriseand falltimings,see the"switchingcharacteristicsforoutputtimingsversusloadcapacitance"table. (1) When theSPI isinSlavemode, thefollowingmust be true: ForPS valuesfrom1 to255:tc(SPC)S >= (PS +1)tc(VCLK) >= 50 ns,where PS istheprescalevaluesetintheSPIFMTx.[15:8]registerbits. ForPS valuesof0:tc(SPC)S = 2tc(VCLK) >= 50 ns. (2) The activeedge oftheSPICLK signalreferencediscontrolledby theCLOCK POLARITY bit(SPIFMTx.17).

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PRODUCT□PREVIEW Data Valid SPISIMO Data Must Be Valid SPISOMI Data Is ValidSPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) SPICLK (clock polarity = 0) SPISOMI SPICSn Slave Out Data Is Valid SPICLK (clock polarity = 1) SPIENAn TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010 Figure7-15.SPI SlaveMode ExternalTiming (CLOCK PHASE = 1) Figure7-16.SPI SlaveMode Enable Timing (CLOCK PHASE = 1) Copyright© 2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 83 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com

7.10 CAN ControllerMode Timings

7.10.1 Dynamic CharacteristicsFor The CANnTX And CANnRX Pins

Table7-15.Dynamic CharacteristicsFor The CANnTX And CANnRX Pins Parameter MIN MAX Unit td(CANnTX) Delaytime,transmitshiftregistertoCANnTX pin(1) 15 ns td(CANnRX) Delaytime,CANnRX pintoreceiveshiftregister 5 ns (1) These valuesdo notincluderise/falltimesoftheoutputbuffer.

7.11 FlexrayControllerMode Timings

7.11.1 JitterTiming

Table7-16.JitterTiming Parameter MIN MAX Unit tTx1bit clockjitterand signalsymmetry 98 102 ns tTx10bit FlexRayBSS (bytestartsequence)toBSS 999 1001 ns tTx10bitAvg averageover10000 samples 999.5 1000.5 ns tRxAsymDelay delaydifferencebetween riseand fallfromRx pinto - 2.5 ns sample pointinFlexRaycore

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PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010

7.12 EMIF Timings

Table7-17.EMIF Read/WriteMode SwitchingCharacteristics(1)(2) NO Parameter Description MIN MAX Unit Reads and Writes 1 td(TURNAROUND) Turnaroundtime (TA + 1)*E - (TA + 1)*E + ns TBD TBD Reads 2 tc(EMRCYCLE) EMIF readcycletime (RS + RST + (RS + RST + ns RH + TA +4)* RH + TA +4)* E -TBD E -TBD 3 tsu(EMCSL-EMOEL) Outputsetuptime,EMIFCS[3:0]lowtoEMIFOE (RS +1)*E - (RS +1)*E + ns low(SS=0) TBD TBD Outputsetuptime,EMIFCS[3:0]lowtoEMIFOE TBD TBD ns low(SS=1) 4 th(EMOEH-EMCSH) Outputholdtime,EMIFOE hightoEMIFCS[3:0] (RH +1)*E - (RH +1)*E + ns high(SS=0) TBD TBD Outputholdtime,EMIFOE hightoEMIFCS[3:0] TBD TBD ns high(SS=1) 5 tsu(EMBAV-EMOEL) Outputsetuptime,EMIFBADD[1:0] validto (RS +1)*E - (RS +1)*E + ns EMIFOE low TBD TBD 6 th(EMOEH-EMBAIV) Outputholdtime,EMIFOE highto (RH +1)*E - (RH +1)*E + ns EMIFBADD[1:0] invalid TBD TBD 7 tsu(EMAV-EMOEL) Outputsetuptime,EMIFADD[21:0]validto (RS +1)*E - (RS +1)*E + ns EMIFOE low TBD TBD 8 th(EMOEH-EMAIV) Outputholdtime,EMIFOE hightoEMIFADD[21:0] (RH +1)*E - (RH +1)*E + ns invalid TBD TBD 9 tw(EMOEL) EMIFOE activelowwidth (RST +1)*E - (RST +1)*E + ns TBD TBD 10 tsu(EMDV-EMOEH) Setuptime,EMIFD[15:0]validbeforeEMIFOE TBD ns high 11 th(EMOEH-EMDV) Holdtime,EMIFD[15:0]validafterEMIFOE high TBD Writes 12 tc(EMWCYCLE) EMIF writecycletime (WS + WST + (WS + WST + ns WH + TA +4)* WH + TA +4)* E -TBD E -TBD 13 tsu(EMCSL-EMWEL) Outputsetuptime,EMIFCS[3:0]lowtoEMIFWE (WS +1)*E - (WS +1)*E + ns low(SS=0) TBD TBD Outputsetuptime,EMIFCS[3:0]lowtoEMIFWE TBD TBD ns low(SS=1) 14 th(EMWEH-EMCSH) Outputholdtime,EMIFWE hightoEMIFCS[3:0] (WH +1)*E - (WH +1)*E + ns high(SS=0) TBD TBD Outputholdtime,EMIFWE hightoEMIFCS[3:0] TBD TBD ns high(SS=1 15 tsu(EMBAV-EMWEL) Outputsetuptime,EMIFBADD[1:0] validto (WS +1)*E - (WS +1)*E + ns EMIFWE low TBD TBD 16 th(EMWEH-EMBAIV) Outputholdtime,EMIFWE hightoEMBADD[1:0] (WH +1)*E - (WH +1)*E + ns invalid TBD TBD 17 tsu(EMAV-EMWEL) Outputsetuptime,EMIFADD[21:0]validto (WS +1)*E - (WS +1)*E + ns EMIFWE low TBD TBD 18 th(EMWEH-EMAIV) Outputholdtime,EMIFWE highto (WH +1)*E - (WH +1)*E + ns EMIFADD[21:0]invalid TBD TBD 19 tw(EMWEL) EMIFWE activelowwidth (WST +1)*E - (WST +1)*E + TBD TBD (1) RS = Read setup,RST = Read Strobe,RH = Read Hold,WS = WriteSetup,WST = WriteStrobe,WH = WriteHold,TA = TurnAround, SS= StrobeSelectMode (2) E = VCLK periodinns. Copyright© 2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 85 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW EMIFCS[3:0] EMIFBADD[1:0] EMIFR/W EMIFADD[21:0] EMIFOE EMIFD[15:0] EMIFWE EMIFCS[3:0] EMIFBADD[1:0] EMIFADD[21:0] EMIFWE EMIFD[15:0] EMIFOE 2120 TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com Table7-17.EMIF Read/WriteMode SwitchingCharacteristics(1)(2) (continued) NO Parameter Description MIN MAX Unit 20 tsu(EMDV-ENWEL) Outputsetuptime,EMIFD[15:0]validtoEMIFWE (WS +1)*E - (WS +1)*E + ns low TBD TBD 21 th(EMWEH-EMDIV) Outputholdtime,EMIFD[15:0]validafter (WH +1)*E - (WH +1)*E + ns EMIFWE high TBD TBD

7.12.1 Read Timing (Asynchronous RAM)

Figure7-17.Asynchronous Memory Read Timing forEMIF

7.12.2 WriteTiming (Asynchronous RAM)

Figure7-18.Asynchronous Memory WriteTiming forEMIF

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PRODUCT□PREVIEW t(ETM)cyc t(ETM)r t(ETM)ft(ETM)h t(ETM)l t(ETM)su t(ETM)ho ETMTRACECLK ETMDA T A t(ETM)su t(ETM)ho TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010

7.13 ETM Timings

7.13.1 ETMTRACECLK Timing

Figure7-19.ETMTRACECLK Timing Table7-18.ETMTRACECLK Timing Parameter Minimum Maximum Description f(ETM)cyc 45MHz Clockfrequency t(ETM)cyc 22.22ns Clockperiod t(ETM)l 2ns Low pulsewidth t(ETM)h 2ns Highpulsewidth t(ETM)r 3ns Clockand datarisetime t(ETM)f 3ns Clockand datafalltime

7.13.2 ETMDATA Timing

Figure7-20.ETMDATA Timing Table7-19.ETMDATA Timing Parameter Minimum Maximum Description t(ETM)su 2.5ns Data setuptime t(ETM)ho 1.5ns Data holdtime Note:The ETMTRACECLK and ETMDATA timingisbased on a 50pF load. Copyright© 2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 87 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW t(RTP)cyc tr tft(RTP)h t(RTP)l td(RTPDA T A) t(RTPDA T A)valid RTPSYNC RTPCLK RTPDA T A t(RTPSYNC)validtd(RTPSYNC) TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com

7.14 RTP Timings

7.14.1 RTPCLK Timing

Figure7-21.RTPCLK Timing Table7-20.RTPCLK Timing Parameter Minimum Description t(RTP)cyc tc(HCLK) Clockperiod(dependingon HCLK divide ratio) t(RTP)h (t(RTP)cyc/2)-((tr+tf)/2) Highpulsewidth(dependingon HCLK divide ratioand loadon pin) t(RTP)l (t(RTP)cyc/2)-((tr+tf)/2) Low pulsewidth(dependingon HCLK divide ratioand loadon pin)

7.14.2 RTPDATA Timing

Figure7-22.RTPDATA Timing Table7-21.RTPDATA Timing Parameter Minimum Description td(RTPSYNC) 3ns RTP SYNC delaytime t(RTP)svalid 2ns RTP SYNC valid td(RTPDATA) 3ns RTP DATA delaytime t(RTP)dvalid 2ns SYNC holdtime

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PRODUCT□PREVIEW t(RTP)disable t(RTP)enable HCLK RTPCLK RTPENA RTPSYNC RTPDATA t(RTP)disable t(RTP)enable HCLK RTPCLK RTPENA RTPSYNC RTPDATA t(RTP)enablet(RTP)disable HCLK RTPCLK RTPENA RTPSYNC RTPDATA d1 d2 d3 d4 d5 d6 d7 d8 Divide by 1 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010

7.14.3 RTPENABLE Timing

Figure7-23.RTPENABLE Timing Table7-22.RTPENABLE Timing Parameter Minimum Maximum Description t(RTP)disable 3tc(HCLK) + tr(RTPSYNC) + 12ns timeRTPENA must go high beforewhat wouldbe thenext RTPSYNC, toguarantee delayingthenextpacket t(RTP)enable 4tc(HCLK) + tr(RTPSYNC) 5tc(HCLK) + tr(RTPSYNC) + 12ns timeafterRTPENA goes low beforea packetthathas been halted,resumes Copyright© 2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 89 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW t(DMM)cyc tr tft(DMM)h t(DMM)l t(DMM)dsu t(DMM)dho DMMSYNC DMMCLK DMMDA T A t(DMM) shot(DMM) ssu TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com

7.15 DMM Timings

7.15.1 DMMCLK Timing

Figure7-24.DMMCLK Timing Table7-23.DMMCLK Timing Parameter Minimum Description t(DMM)cyc tc(HCLK * 2 Clockperiod(dependingon HCLK divide ratio) t(DMM)h (t(DMM)cyc/2)-((tr+tf)/2) Highpulsewidth(dependingon HCLK divide ratio) t(DMM)l (t(DMM)cyc/2)-((tr+tf)/2) Low pulsewidth(dependingon HCLK divide ratio)

7.15.2 DMMDATA Timing

Figure7-25.DMMDATA Timing Table7-24.DMMDATA Timing Parameter Minimum Description t(DMM)ssu 2 ns SYNC activetoclkfallingedge setuptime t(DMM)sho 3ns clkfallingedge toSYNC deactiveholdtime t(DMM)dsu 2ns DATA toclkfallingedge setuptime t(DMM)dho 3ns clkfallingedge toDATA holdtime

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PRODUCT□PREVIEW HCLK DMMCLK DMMSYNC DMMDA T A DMMENA D00 D01 D10 D1 1 D20 D21 D30 D31 D40 D41 D50 TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010

7.15.3 DMMENA Timing

Figure7-26.DMMENA Timing The above figureshows a case with1 DMM packetper 2 DMMCLK cycles(Mode = DirectData Mode, datawidth= 8,portwidth= 4) where none ofthepacketsreceivedby theDMM are sentout,leadingto fillingup oftheinternalbuffers.The DMMENA signalisshown asserted,afterthefirsttwo packetshave been receivedand synchronizedtotheHCLK domain.Here,theDMM has thecapacitytoacceptpackets D4, D5, D6, D7. PacketD8 would resultinan overflow.Once DMMENA isasserted,theDMM expectsto stopreceivingpacketsafter4 HCLK cycles;once DMMENA isde-asserted,theDMM can handlepackets immediately(after0 HCLK cycles).

7.16 MibADC

7.16.1 MibADC

The multibufferedA-to-Dconverter(MibADC) has a separatepower bus foritsanalog circuitrythat enhances theA-to-Dperformanceby preventingdigitalswitchingnoiseon thelogiccircuitrywhich could be presenton VSS and VCC from couplingintothe A-to-Danalogstage.AllA-to-Dspecificationsare givenwithrespecttoADREFLO unlessotherwisenoted. Table7-25.MibADC Resolution 12 bits(4096values) Monotonic Assured Output conversionfcode 00h toFFFh [00forVAI ≤AD REFLO ;FFF forVAI ≥ AD REFHI ]

7.16.2 MibADC Recommended OperatingConditions

Table7-26.MibADC Recommended OperatingConditions(1) MIN MAX UNIT AD REFHI A-to-Dhigh-voltagereferencesource 3 3.6 V AD REFLO A-to-Dlow-voltagereferencesource 0 0.3 V VAI Analoginputvoltage AD REFLO AD REFHI V IAIC Analoginputclamp current(2) -2 2 mA (VAI < VSSAD – 0.3orVAI > VCCAD + 0.3) (1) ForVCCAD and VSSAD recommended operatingconditions,see the"devicerecommended operatingconditions"table. (2) Inputcurrentsintoany ADC inputchanneloutsidethespecifiedlimitscouldaffectconversionresultsofotherchannels. Copyright© 2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 91 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com

7.16.3 OperatingCharacteristicsOver FullRanges Of Recommended OperatingConditions

Table7-27.OperatingCharacteristicsOver FullRanges Of Recommended OperatingConditions(1) Parameter Description/Conditions Min TYP Max Unit R mux Analoginputmux on-resistance 250 Ω R samp ADC sample switch 150 250 Ω on-resistance C mux Inputmux capacitance 16 pF C samp ADC sample capacitance 11 12 13 pF IAIL Analoginputleakagecurrent InputleakageperADC inputpin –200 200 nA IADREFHI AD REFHI inputcurrent AD REFHI = 3.6V,AD REFLO = VSSAD 5 mA CR Conversionrangeoverwhich AD REFHI -AD REFLO 3 3.6 V specifiedaccuracyismaintained EDNL Differentialnonlinearityerror Differencebetween theactualstepwidthand the ±2 LSB idealvalue. EINL Integralnonlinearityerror Maximum deviationfromthebeststraightline ± 2 LSB throughtheMibADC. MibADC transfer characteristics,excludingthequantizationerror. ETOT Totalerror/Absoluteaccuracy Maximum valueofthedifferencebetween an ± 4 LSB analogvalueand theidealmidstepvalue. (1) 1 LSB = (ADREFHI – AD REFLO )/212 fortheMibADC

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PRODUCT□PREVIEW Vsrc0 Rs0 ADIN[0] Rmux Rs1 ADIN[1] RsX ADIN[X] RsampSample Switch To ADC Comparator Cmux Csamp Mux Switch Mux Switch Mux Switch Rmux Rmux Vsrc1 VsrcX IAIL IAIL IAIL External Internal TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010

7.16.4 MibADC InputModel

Figure7-27.MibADC InputEquivalentCircuit Copyright© 2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 93 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com

7.16.5 MibADC Timings

Table7-28.MibADC Timings Min NOm MAX Unit tc(ADCLK) Cycletime,MibADC clock 33 ns td(SH) Delaytime,sample and holdtime 200 ns td© ) Delaytime,conversiontime 400 ns td(SHC)(1) Delaytime,totalsample/holdand conversiontime 600 ns (1) Thisistheminimum sample/holdand conversiontimethatcan be achieved.These parametersaredependenton many factors,e.gthe prescalesettings.

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PRODUCT□PREVIEW 0 1 2 3 4 5 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 ... 110 Analog Input Value (LSB) Digital Output Code Differential Linearity Error (1/2 LSB)

1 LSB

Error (–1/2 LSB)1 LSB 0 1 2 3 4 5 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 ... 110 Analog Input Value (LSB) At Transition (– 1/2 LSB) End-Point Lin. Error At Transition Ideal Transition Actual Transition 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 111 0 ... 110 Digital Output Code 0 ... 000 At Transition (–1/2 LSB) TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010

7.16.6 MibADC NonlinearityError

The differentialnonlinearityerrorshown inthefigurebelow (sometimesreferredtoas differentiallinearity) isthedifferencebetween an actualstepwidthand theidealvalueof1 LSB. Figure7-28.DifferentialNonlinearity(DNL) The integralnonlinearityerrorshown inthefigurebelow (sometimesreferredtoas linearityerror)isthe deviationofthevalueson theactualtransferfunctionfroma straightline. Figure7-29.IntegralNonlinearity(INL)Error Copyright© 2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 95 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

PRODUCT□PREVIEW 0 1 2 3 4 5 6 7 0 ... 101 0 ... 100 0 ... 01 1 0 ... 010 0 ... 001 0 ... 000 0 ... 11 1 0 ... 1 10 Analog Input Value (LSB) Digital Output Code T otal Error At Step T ot al E r r o r At Step 0 ... 101 ( 1 1/4 LSB)– TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141 –MARCH 2010 www.ti.com

7.16.7 MibADC TotalError

The absoluteaccuracyortotalerrorofan MibADC as shown inthefigurebelow isthemaximum valueof thedifferencebetween an analogvalueand theidealmidstepvalue. Figure7-30.AbsoluteAccuracy (Total)Error

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PRODUCT□PREVIEW TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141 –MARCH 2010

8 MechanicalPackaging and OrderableInformation

The followingtable(s)show the thermalresistanceforthe PBGA-ZWT and PQFP-PGE mechanical packages.

8.1 Thermal Data

8.1.1 PGE (S-PQFP-G144) plasticQuad FlatPack

Table8-1.PGE (S-PQFP-G144) Thermal ResistanceCharacteristics PARAMETER °C /W RQJA 45 RQJC 5

8.1.2 ZWT (S-PBGA-N337) Plasticballgridarray

Table8-2.ZWT (S-PBGA-N337) Thermal ResistanceCharacteristics PARAMETER °C /W RQJA TBD RQJC TBD

8.2 Packaging Information

The followingpackaging informationand addendum reflectthe most currentdata availableforthe designateddevice(s).The dataissubjecttochange withoutnoticeand withoutrevisionofthisdocument. Copyright© 2010,Texas InstrumentsIncorporated MechanicalPackagingand OrderableInformation 97 SubmitDocumentationFeedback ProductFolderLink(s):TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) X5LS20216ASPGEQQ1 ACTIVE LQFP PGE 144 1 TBD Call TI Call TI X5LS20216ASZWTQQ1 ACTIVE NFBGA ZWT 337 1 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 5-Mar-2010 Addendum-Page 1

MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 4040147/C 10/96 0,27 0,17 0,13 NOM 0,25 0,75 0,45 0,05 MIN Seating Plane Gage Plane 108 109 144 SQ SQ22,20 21,80 19,80 17,50 TYP 20,20 1,35 1,45 1,60 MAX M0,08 0°–7° 0,08 0,50 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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Product Information

P5LS10116ASPGETQ1R specifications and overview.

Summary

16/32-BIT RISC Flash Microcontroller

Description

16/32-BIT RISC Flash Microcontroller

Source title P5LS10116ASPGETQ1R Datasheet(PDF) - Texas Instruments

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