P51XAG30

XA-G3 PHILIPS | Alldatasheet

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Technical content

/C0109 /C0110 /C0114 XA-G3 XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs Product specification Supersedes data of 1998 Aug 14 IC25 Data Handbook

1999 Apr 07

Philips Semiconductors Product specification XA-G3XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs

21999 Apr 07 853-2052 21197

The Philips Semiconductors XA (eXtended Architecture) family of 16-bit single-chip microcontrollers is powerful enough to easily handle the requirements of high performance embedded applications, yet inexpensive enough to compete in the market for high-volume, low-cost applications. The XA family provides an upward compatibility path for 80C51 users who need higher performance and 64k or more of program memory. Existing 80C51 code can also easily be translated to run on XA microcontrollers. The performance of the XA architecture supports the comprehensive bit-oriented operations of the 80C51 while incorporating support for multi-tasking operating systems and high-level languages such as C. The speed of the XA architecture, at 10 to 100 times that of the 80C51, gives designers an easy path to truly high performance embedded control. The XA architecture supports:

• Upward compatibility with the 80C51 architecture
• 16-bit fully static CPU with a 24-bit program and data address range
• Eight 16-bit CPU registers each capable of performing all arithmetic and logic operations as well as acting as memory pointers. Operations may also be performed directly to memory.
• Both 8-bit and 16-bit CPU registers, each capable of performing all arithmetic and logic operations.
• An enhanced instruction set that includes bit intensive logic operations and fast signed or unsigned 16 × 16 multiply and 32 / 16 divide
• Instruction set tailored for high level language support
• Multi-tasking and real-time executives that include up to 32 vectored interrupts, 16 software traps, segmented data memory, and banked registers to support context switching
• Low power operation, which is intrinsic to the XA architecture, includes power-down and idle modes. More detailed information on the core is available in the XA User Guide. SPECIFIC FEATURES OF THE XA-G3
• 20-bit address range, 1 megabyte each program and data space. (Note that the XA architecture supports up to 24 bit addresses.)
• 2.7V to 5.5V operation
• 32K bytes on-chip EPROM/ROM program memory = XA-G37/XA-G33
• 512 bytes of on-chip data RAM
• Three counter/timers with enhanced features (equivalent to 80C51 T0, T1, and T2)
• Watchdog timer
• Two enhanced UARTs
• Four 8-bit I/O ports with 4 programmable output configurations
• 44-pin PLCC and 44-pin LQFP packages

ORDERING INFORMATION

ROMless ROM EPROM 1 TEMPERATURE RANGE °C AND PACKAGE FREQ (MHz) DRAWING NUMBER P51XAG30KB BD P51XAG33KB BD PXAG37KB BD OTP 0 to +70, Plastic Low Profile Quad Flat Pkg.30 SOT389–1 P51XAG30KB A P51XAG33KB A PXAG37KB A OTP 0 to +70, Plastic Leaded Chip Carrier 30 SOT187–2 P51XAG30KF BD P51XAG33KF BD PXAG37KF BD OTP –40 to +85, Plastic Low Profile Quad Flat Pkg.30 SOT389–1 P51XAG30KF A P51XAG33KF A PXAG37KF A OTP –40 to +85, Plastic Leaded Chip Carrier30 SOT187–2 NOTE: 1. OTP = One Time Programmable EPROM. UV = Erasable EPROM.

Philips Semiconductors Product specification XA-G3XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs

1999 Apr 07 3

2 P1.0/A0/WRH 3 P1.1/A1 4 P1.2/A2 5 P1.3/A3 6 P1.4/RxD1 7 P1.5/TxD1 8 P1.6/T2 9 P1.7/T2EX

10 RST

11 P3.0/RxD0 12 NC 13 P3.1/TxD0 14 P3.2/INT0 15 P3.3/INT1 16 P3.4/T0 17 P3.5/T1/BUSW 18 P3.6/WR L 19 P3.7/RD

20 XTAL2

21 XTAL1

22 V SS

23 V DD

24 P2.0/A12D8 25 P2.1/A13D9 26 P2.2/A14D10 27 P2.3/A15D11 28 P2.4/A16D12 29 P2.5/A17D13 30 P2.6/A18D14 31 P2.7/A19D15

32 PSEN

33 ALE/PROG

35 EA /VPP /WAIT

36 P0.7/A11D7 37 P0.6/A10D6 38 P0.5/A9D5 39 P0.4/A8D4 40 P0.3/A7D3 41 P0.2/A6D2 42 P0.1/A5D1 43 P0.0/A4D0 44 V DD SU00525 44-Pin LQFP Package LQFP 44 34 12 22 Pin Function 1 P1.5/TxD1 2 P1.6/T2 3 P1.7/T2EX

4 RST

5 P3.0/RxD0 6N C 7 P3.1/TxD0 8 P3.2/INT0 9 P3.3/INT1 10 P3.4/T0 11 P3.5/T1/BUSW 12 P3.6/WRL 13 P3.7/RD

14 XTAL2

15 XTAL1

16 V SS

17 V DD

18 P2.0/A12D8 19 P2.1/A13D9 20 P2.2/A14D10 21 P2.3/A15D11 22 P2.4/A16/D12 Pin Function 23 P2.5/A17D13 24 P2.6/A18D14 25 P2.7/A19D15

26 PSEN

27 ALE/PROG

/VPP /WAIT 30 P0.7/A11D7 31 P0.6/A10D6 32 P0.5/A9D5 33 P0.4/A8D4 34 P0.3/A7D3 35 P0.2/A6D2 36 P0.1/A5D1 37 P0.0/A4D0 38 V DD

39 V SS

40 P1.0/A0/WRH 41 P1.1/A1 42 P1.2/A2 43 P1.3/A3 44 P1.4/RxD1 SU00580 LOGIC SYMBOL VDD VSS XTAL1 XTAL2 RST EA /WAIT T2* T2EX* SU00526 A0/WRH PORT 1PORT 2 PSEN ALE PORT 0 ADDRESS AND DATA BUS ADDRESS BUS PORT 3 T1/BUSW WRL RD RxD0 TxD0 INT0 INT1 ALTERNATE FUNCTIONS * NOT AVAILABLE ON 40-PIN DIP PACKAGE TXD1 R XD1

Philips Semiconductors Product specification XA-G3XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs

1999 Apr 07 4

512 BYTES

TIMER 0 & TIMER 1 TIMER 2 WATCHDOG TIMER SU00527 Program Memory Bus Data Bus

Philips Semiconductors Product specification XA-G3XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs

1999 Apr 07 5

PIN. NO. TYPE NAME AND FUNCTIONMNEMONIC PLCC LQFP TYPE NAME AND FUNCTION VSS 1, 22 16 I Ground: 0V reference. VDD 23, 44 17 I Power Supply: This is the power supply voltage for normal, idle, and power down operation. P0.0 – P0.7 43–36 37–30 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. Port 0 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. When the external program/data bus is used, Port 0 becomes the multiplexed low data/instruction byte and address lines 4 through 11. 1–3 I/O Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type. Port 1 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of port 1 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. Port 1 also provides special functions as described below. 2 40 O A0/WRH : Address bit 0 of the external address bus when the external data bus is configured for an 8 bit width. When the external data bus is configured for a 16 bit width, this pin becomes the high byte write strobe. 3 41 O A1: Address bit 1 of the external address bus. 4 42 O A2: Address bit 2 of the external address bus. 5 43 O A3: Address bit 3 of the external address bus. 6 44 I RxD1 (P1.4): Receiver input for serial port 1. 7 1 O TxD1 (P1.5): Transmitter output for serial port 1. 8 2 I/O T2 (P1.6): Timer/counter 2 external count input/clockout. 9 3 I T2EX (P1.7): Timer/counter 2 reload/capture/direction control P2.0 – P2.7 24–31 18–25 I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. Port 2 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. When the external program/data bus is used in 16-bit mode, Port 2 becomes the multiplexed high data/instruction byte and address lines 12 through 19. When the external program/data bus is used in 8-bit mode, the number of address lines that appear on port 2 is user programmable. P3.0 – P3.7 11, 13–19 7–13 I/O Port 3: Port 3 is an 8-bit I/O port with a user configurable output type. Port 3 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. the operation of port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. Port 3 also provides various special functions as described below. 11 5 I RxD0 (P3.0): Receiver input for serial port 0. 13 7 O TxD0 (P3.1): Transmitter output for serial port 0. 14 8 I INT0 (P3.2): External interrupt 0 input. 15 9 I INT1 (P3.3): External interrupt 1 input. 16 10 I/O T0 (P3.4): Timer 0 external input, or timer 0 overflow output. 17 11 I/O T1/BUSW (P3.5): Timer 1 external input, or timer 1 overflow output. The value on this pin is latched as the external reset input is released and defines the default external data bus width (BUSW). 0 = 8-bit bus and 1 = 16-bit bus. 18 12 O WRL (P3.6): External data memory low byte write strobe. 19 13 O RD (P3.7): External data memory read strobe. RST 10 4 I Reset: A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor to begin execution at the address contained in the reset vector. Refer to the section on Reset for details. ALE/PROG 33 27 I/O Address Latch Enable/Program Pulse: A high output on the ALE pin signals external circuitry to latch the address portion of the multiplexed address/data bus. A pulse on ALE occurs only when it is needed in order to process a bus cycle.

Philips Semiconductors Product specification XA-G3XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs

1999 Apr 07 6

MNEMONIC NAME AND FUNCTION TYPE PIN. NO. MNEMONIC NAME AND FUNCTION TYPE LQFPPLCC PSEN 32 26 O Program Store Enable: The read strobe for external program memory. When the microcontroller accesses external program memory, PSEN is driven low in order to enable memory devices. PSEN is only active when external code accesses are performed. EA /WAIT/ VPP 35 29 I External Access/Wait: The EA input determines whether the internal program memory of the microcontroller is used for code execution. The value on the EA pin is latched as the external reset input is released and applies during later execution. When latched as a 0, external program memory is used exclusively, when latched as a 1, internal program memory will be used up to its limit, and external program memory used above that point. After reset is released, this pin takes on the function of bus Wait input. If Wait is asserted high during any external bus access, that cycle will be extended until Wait is released. During EPROM programming, this pin is also the programming supply voltage input. XTAL1 21 15 I Crystal 1: Input to the inverting amplifier used in the oscillator circuit and input to the internal clock generator circuits. XTAL2 20 14 O Crystal 2: Output from the oscillator amplifier. SPECIAL FUNCTION REGISTERS NAME DESCRIPTION SFR ADDRESS BIT FUNCTIONS AND ADDRESSES RESETNAME DESCRIPTION SFR ADDRESS MSB LSB VALUE BCR Bus configuration register 46A — — — WAITD BUSD BC2 BC1 BC0 Note 1 BTRH Bus timing register high byte 469 DW1 DW0 DWA1 DWA0 DR1 DR0 DRA1 DRA0 FF BTRL Bus timing register low byte 468 WM1 WM0 ALEW — CR1 CR0 CRA1 CRA0 EF CS Code segment 443 00 DS Data segment 441 00 ES Extra segment 442 00 33F 33E 33D 33C 33B 33A 339 338 IEH* Interrupt enable high byte 427 — — — — ETI1 ERI1 ETI0 ERI0 00 337 336 335 334 333 332 331 330 IEL* Interrupt enable low byte 426 EA — — ET2 ET1 EX1 ET0 EX0 00 IPA0 Interrupt priority 0 4A0 — PT0 — PX0 00 IPA1 Interrupt priority 1 4A1 — PT1 — PX1 00 IPA2 Interrupt priority 2 4A2 — — — PT2 00 IPA4 Interrupt priority 4 4A4 — PTI0 — PRI0 00 IPA5 Interrupt priority 5 4A5 — PTI1 — PRI1 00 387 386 385 384 383 382 381 380 P0* Port 0 430 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FF 38F 38E 38D 38C 38B 38A 389 388 P1* Port 1 431 T2EX T2 TxD1 RxD1 A3 A2 A1 WRH FF 397 396 395 394 393 392 391 390

Philips Semiconductors Product specification XA-G3XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs

1999 Apr 07 7

BIT FUNCTIONS AND ADDRESSESSFR ADDRESSDESCRIPTIONNAME RESET VALUELSBMSB SFR ADDRESSDESCRIPTION 39F 39E 39D 39C 39B 39A 399 398 P3* Port 3 433 RD WR T1 T0 INT1 INT0 TxD0 RxD0 FF P0CFGA Port 0 configuration A 470 Note 5 P1CFGA Port 1 configuration A 471 Note 5 P2CFGA Port 2 configuration A 472 Note 5 P3CFGA Port 3 configuration A 473 Note 5 P0CFGB Port 0 configuration B 4F0 Note 5 P1CFGB Port 1 configuration B 4F1 Note 5 P2CFGB Port 2 configuration B 4F2 Note 5 P3CFGB Port 3 configuration B 4F3 Note 5 227 226 225 224 223 222 221 220 PCON* Power control register 404 — — — — — — PD IDL 00 20F 20E 20D 20C 20B 20A 209 208 PSWH* Program status word (high byte)401 SM TM RS1 RS0 IM3 IM2 IM1 IM0 Note 2 207 206 205 204 203 202 201 200 PSWL* Program status word (low byte)400 C AC — — — V N Z Note 2 217 216 215 214 213 212 211 210 PSW51* 80C51 compatible PSW 402 C AC F0 RS1 RS0 V F1 P Note 3 RTH0 Timer 0 extended reload, high byte 455 00 RTH1 Timer 1 extended reload, high byte 457 00 RTL0 Timer 0 extended reload, low byte454 00 RTL1 Timer 1 extended reload, low byte456 00 307 306 305 304 303 302 301 300 S0CON* Serial port 0 control register420 SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00 30F 30E 30D 30C 30B 30A 309 308 S0STAT* Serial port 0 extended status 421 — — — — FE0 BR0 OE0 STINT0 00 S0BUF Serial port 0 buffer register 460 x S0ADDR Serial port 0 address register461 00 S0ADEN Serial port 0 address enable register 462 00 327 326 325 324 323 322 321 320 S1CON* Serial port 1 control register424 SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00 32F 32E 32D 32C 32B 32A 329 328 S1STAT* Serial port 1 extended status 425 — — — — FE1 BR1 OE1 STINT1 00 S1BUF Serial port 1 buffer register 464 x S1ADDR Serial port 1 address register465 00 S1ADEN Serial port 1 address enable register 466 00 SCR System configuration register 440 — — — — PT1 PT0 CM PZ 00 21F 21E 21D 21C 21B 21A 219 218 SSEL* Segment selection register 403 ESWEN R6SEG R5SEG R4SEG R3SEG R2SEG R1SEG R0SEG 00 SWE Software Interrupt Enable 47A — SWE7 SWE6 SWE5 SWE4 SWE3 SWE2 SWE1 00

Philips Semiconductors Product specification XA-G3XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs

1999 Apr 07 8

BIT FUNCTIONS AND ADDRESSESSFR ADDRESSDESCRIPTIONNAME RESET VALUELSBMSB SFR ADDRESSDESCRIPTION 357 356 355 354 353 352 351 350 SWR* Software Interrupt Request 42A — SWR7 SWR6 SWR5 SWR4 SWR3 SWR2 SWR1 00 2C7 2C6 2C5 2C4 2C3 2C2 2C1 2C0 T2CON* Timer 2 control register 418 TF2 EXF2 RCLK0 TCLK0 EXEN2 TR2 C/T2 CP/RL2 00 2CF 2CE 2CD 2CC 2CB 2CA 2C9 2C8 T2MOD* Timer 2 mode control 419 — — RCLK1 TCLK1 — — T2OE DCEN 00 TH2 Timer 2 high byte 459 00 TL2 Timer 2 low byte 458 00 T2CAPH Timer 2 capture register, high byte 45B 00 T2CAPL Timer 2 capture register, low byte 45A 00 287 286 285 284 283 282 281 280 TCON* Timer 0 and 1 control register410 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 TH0 Timer 0 high byte 451 00 TH1 Timer 1 high byte 453 00 TL0 Timer 0 low byte 450 00 TL1 Timer 1 low byte 452 00 TMOD Timer 0 and 1 mode control 45C GATE C/T M1 M0 GATE C/T M1 M0 00 28F 28E 28D 28C 28B 28A 289 288 TSTAT* Timer 0 and 1 extended status 411 — — — — — T1OE — T0OE 00 2FF 2FE 2FD 2FC 2FB 2FA 2F9 2F8 WDCON* Watchdog control register 41F PRE2 PRE1 PRE0 — — WDRUN WDTOF — Note 6 WDL Watchdog timer reload 45F 00 WFEED1 Watchdog feed 1 45D x WFEED2 Watchdog feed 2 45E x NOTES: * SFRs are bit addressable. 1. At reset, the BCR register is loaded with the binary value 0000 0a11, where “a” is the value on the BUSW pin. This defaults the address bus size to 20 bits since the XA-G3 has only 20 address lines. 2. SFR is loaded from the reset vector. 3. All bits except F1, F0, and P are loaded from the reset vector. Those bits are all 0. 4. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other purposes in future XA derivatives. The reset value shown for these bits is 0. 5. Port configurations default to quasi-bidirectional when the XA begins execution from internal code memory after reset, based on the condition found on the EA pin. Thus all PnCFGA registers will contain FF and PnCFGB registers will contain 00. When the XA begins execution using external code memory, the default configuration for pins that are associated with the external bus will be push-pull. The PnCFGA and PnCFGB register contents will reflect this difference. 6. The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes. 7. The XA-G3 implements an 8-bit SFR bus, as stated in Chapter 8 of the XA User Guide. All SFR accesses must be 8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return undefined data in the upper byte.

1999 Apr 07 9

two bits (PT1, PT0) in the System Configuration Register (SCR). and speeds up execution but limits memory access to 64k. Figure 1. System Configuration Register (SCR) “TRn” control bit is set. When cleared Timer “n” is enabled whenever “TRn” control bit is set. Set for Counter operation (input from “Tn” input pin). Figure 2. Timer/Counter Mode Control (TMOD) Register

1999 Apr 07 10

8-bit auto-reload mode (Mode 2) instead of TH. where N = the TCLK prescaler value: 4 (default), 16, or 64. Mode 1 is the 16-bit non-auto reload mode. reloads TLn with the contents of RTLn, which is preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer/Counter 0. where N = the TCLK prescaler value: 4, 16, or 64. Mode 3 is provided for applications requiring an extra 8-bit timer. TCON.7 TF1 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. This flag will not be set if T1OE (TSTAT.2) is set. Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. TCON.6 TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off. TCON.5 TF0 Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. This flag will not be set if T0OE (TSTAT.0) is set. Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. TCON.4 TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off. TCON.3 IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. TCON.1 IE0 Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. triggered external interrupts. Figure 3. Timer/Counter Control (TCON) Register

1999 Apr 07 11

T2CON.7 TF2 Timer 2 overflow flag. Set by hardware on Timer/Counter overflow. Must be cleared by software. TF2 will not be set when RCLK0, RCLK1, TCLK0, TCLK1 or T2OE=1. T2CON.5 RCLK0 Receive Clock Flag. T2CON.3 EXEN2 Timer 2 external enable bit allows a capture or reload to occur due to a negative transition on T2EX. T2CON.2 TR2 Start=1/Stop=0 control for Timer 2. T2CON.1 C/T2 Timer or counter select. T2CON.0 CP/RL2 Capture/Reload flag. If CP/RL2 & EXEN2=1 captures will occur on negative transitions of T2EX. If CP/RL2=0, EXEN2=1 auto reloads occur with either Timer 2 overflows or negative transitions at T2EX. If RCLK or TCLK=1 the timer is set to auto reload on Timer 2 overflow, this bit has no effect. Figure 4. Timer/Counter 2 Control (T2CON) Register 30.0MHz oscillator, this range would be 3.58Hz to 3.75MHz. bit. This will cause an interrupt when the timer 2 interrupt is enabled. interrupt is enabled. The capture mode is illustrated in Figure 7. 16-bit value in T2CAPH and T2CAPL when the count overflows. auto-reload mode is shown in Figure 8. up to FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. reloaded into the timer registers TL2 and TH2, respectively.

1999 Apr 07 12

TF2 flag, which can generate an interrupt if enabled. needed. the EXF2 flag does not generate an interrupt in this mode. As the baud rate generator, timer T2 is incremented by TCLK. A 50% duty cycle clock can be programmed to come out on P1.6. 3.58Hz to 3.75MHz at a 30MHz operating frequency. TR2 (T2CON.2) also must be set to start the timer. interrupt. This is similar to when it is used as a baud-rate generator. 1/8 of the Clock-Out frequency. Table 1. Timer 2 Operating Modes

0 X X X Timer off (stopped)

1 X 1 X Baud rate generator

TSTAT.2 T1OE When 0, this bit allows the T1 pin to clock Timer 1 when in the counter mode. When 1, T1 acts as an output and toggles at every Timer 1 overflow. TSTAT.0 T0OE When 0, this bit allows the T0 pin to clock Timer 0 when in the counter mode. When 1, T0 acts as an output and toggles at every Timer 0 overflow. Figure 5. Timer 0 And 1 Extended Status (TSTAT) T2MOD.5 RCLK1 Receive Clock Flag. for UART1 instead of Timer T1. T2MOD.1 T2OE When 0, this bit allows the T2 pin to clock Timer 2 when in the counter mode. When 1, T2 acts as an output and toggles at every Timer 2 overflow. T2MOD.0 DCEN Controls count direction for Timer 2 in autoreload mode. DCEN=1 counter set to count up or down, depending on T2EX (see text). Figure 6. Timer 2 Mode Control (T2MOD)

1999 Apr 07 13

Figure 7. Timer 2 in Capture Mode Figure 8. Timer 2 in Auto-Reload Mode (DCEN = 0) Figure 9. Timer 2 Auto Reload Mode (DCEN = 1)

1999 Apr 07 14

autoload value is FFH), tD is the design time-out value. value to be loaded into the main timer is held in an autoload register. operation is referred to as feeding the watchdog timer. clr ea ; disable global interrupts. setb ea ; re-enable global interrupts. mov.b wdcon,#0 ; set WD control register to clear WDRUN. disable and re-enable interrupts should be added to this sequence. Table 2. Prescaler Select Values in WDCON

• Watchdog run control bit set to ON (1).
• Autoload register WDL set to 00 (min. count).
• Watchdog time-out flag cleared.
• Prescaler is cleared.
• Prescaler tap set to the highest divide.
• Autoload takes place. When coming out of a hardware reset, the software should load the autoload register and then feed the watchdog (cause an autoload). If the watchdog is running and happens to underflow at the time the external RESET is applied, the watchdog time-out flag will be cleared.

1999 Apr 07 15

Figure 10. Watchdog Timer in XA-G3

• Autoload takes place.
• Watchdog time-out flag is set
• Watchdog run bit unchanged.
• Autoload (WDL) register unchanged.
• Prescaler tap unchanged.
• All other device action same as external reset. Note that if the watchdog underflows, the program counter will be loaded from the reset vector as in the case of an internal reset. The watchdog time-out flag can be examined to determine if the watchdog has caused the reset condition. The watchdog time-out flag bit can be cleared by software. WDCON Register Bit Definitions WDCON.7 PRE2 Prescaler Select 2, reset to 1 WDCON.6 PRE1 Prescaler Select 1, reset to 1 WDCON.5 PRE0 Prescaler Select 0, reset to 1 WDCON.4 — WDCON.3 — WDCON.2 WDRUN Watchdog Run Control bit, reset to 1 WDCON.1 WDTOF Timeout flag WDCON.0 — UARTs The XA-G3 includes 2 UART ports that are compatible with the enhanced UART used on the 8xC51FB. Baud rate selection is somewhat different due to the clocking scheme used for the XA timers. Some other enhancements have been made to UART operation. The first is that there are separate interrupt vectors for each UART’s transmit and receive functions. The UART transmitter has been double buffered, allowing packed transmission of data with no gaps between bytes and less critical interrupt service routine timing. A break detect function has been added to the UART. This operates independently of the UART itself and provides a start-of-break status bit that the program may test. Finally, an Overrun Error flag has been added to detect missed characters in the received data stream. The double buffered UART transmitter may require some software changes in code written for the original XA-G3 single buffered UART. Each UART baud rate is determined by either a fixed division of the oscillator (in UART modes 0 and 2) or by the timer 1 or timer 2 overflow rate (in UART modes 1 and 3). Timer 1 defaults to clock both UART0 and UART1. Timer 2 can be programmed to clock either UART0 through T2CON (via bits R0CLK and T0CLK) or UART1 through T2MOD (via bits R1CLK and T1CLK). In this case, the UART not clocked by T2 could use T1 as the clock source. The serial port receive and transmit registers are both accessed at Special Function Register SnBUF. Writing to SnBUF loads the transmit register, and reading SnBUF accesses a physically separate receive register. The serial port can operate in 4 modes: Mode 0: Serial I/O expansion mode. Serial data enters and exits through RxDn. TxDn outputs the shift clock. 8 bits are transmitted/received (LSB first). (The baud rate is fixed at 1/16 the oscillator frequency.) Mode 1: Standard 8-bit UART mode. 10 bits are transmitted (through TxDn) or received (through RxDn): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SnCON. The baud rate is variable. Mode 2: Fixed rate 9-bit UART mode. 11 bits are transmitted (through TxD) or received (through RxD): start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On Transmit, the 9th data bit (TB8_n in SnCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8_n. On receive, the 9th data bit goes into RB8_n in Special Function Register SnCON, while the stop bit is ignored. The baud rate is programmable to 1/32 of the oscillator frequency. Mode 3: Standard 9-bit UART mode. 11 bits are transmitted (through TxDn) or received (through RxDn): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable. In all four modes, transmission is initiated by any instruction that uses SnBUF as a destination register. Reception is initiated in Mode 0 by the condition RI_n = 0 and REN_n = 1. Reception is initiated in the other modes by the incoming start bit if REN_n = 1.

Philips Semiconductors Product specification XA-G3XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs

1999 Apr 07 16

Serial Port Control Register The serial port control and status register is the Special Function Register SnCON, shown in Figure 12. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8_n and RB8_n), and the serial port interrupt bits (TI_n and RI_n). TI Flag In order to allow easy use of the double buffered UART transmitter feature, the TI_n flag is set by the UART hardware under two conditions. The first condition is the completion of any byte transmission. This occurs at the end of the stop bit in modes 1, 2, or 3, or at the end of the eighth data bit in mode 0. The second condition is when SnBUF is written while the UART transmitter is idle. In this case, the TI_n flag is set in order to indicate that the second UART transmitter buffer is still available. Typically, UART transmitters generate one interrupt per byte transmitted. In the case of the XA UART, one additional interrupt is generated as defined by the stated conditions for setting the TI_n flag. This additional interrupt does not occur if double buffering is bypassed as explained below. Note that if a character oriented approach is used to transmit data through the UART, there could be a second interrupt for each character transmitted, depending on the timing of the writes to SBUF. For this reason, it is generally better to bypass double buffering when the UART transmitter is used in character oriented mode. This is also true if the UART is polled rather than interrupt driven, and when transmission is character oriented rather than message or string oriented. The interrupt occurs at the end of the last byte transmitted when the UART becomes idle. Among other things, this allows a program to determine when a message has been transmitted completely. The interrupt service routine should handle this additional interrupt. The recommended method of using the double buffering in the application program is to have the interrupt service routine handle a single byte for each interrupt occurrence. In this manner the program essentially does not require any special considerations for double buffering. Unless higher priority interrupts cause delays in the servicing of the UART transmitter interrupt, the double buffering will result in transmitted bytes being tightly packed with no intervening gaps. 9-bit Mode Please note that the ninth data bit (TB8) is not double buffered. Care must be taken to insure that the TB8 bit contains the intended data at the point where it is transmitted. Double buffering of the UART transmitter may be bypassed as a simple means of synchronizing TB8 to the rest of the data stream. Bypassing Double Buffering The UART transmitter may be used as if it is single buffered. The recommended UART transmitter interrupt service routine (ISR) technique to bypass double buffering first clears the TI_n flag upon entry into the ISR, as in standard practice. This clears the interrupt that activated the ISR. Secondly, the TI_n flag is cleared immediately following each write to SnBUF. This clears the interrupt flag that would otherwise direct the program to write to the second transmitter buffer. If there is any possibility that a higher priority interrupt might become active between the write to SnBUF and the clearing of the TI_n flag, the interrupt system may have to be temporarily disabled during that sequence by clearing, then setting the EA bit in the IEL register. Note Regarding Older XA-G3 Devices Older versions of the XA-G30, XA-G37, and XA-G35 emulation bondout devices do not have the double buffering feature enabled. Contact factory for details.

1999 Apr 07 17

overflow rate (modes 1 and 3). timer overflow divided by 16 i.e. Osc/64.

00 Osc/4

01 Osc/16

where N = the TCLK prescaler value: 4, 16, or 64. and Timer_Range = 256 for timer 1 in mode 2.

1. The maximum baud rate for a UART in mode 1 or 3 is Osc/64.
2. The lowest possible baud rate (for a given oscillator frequency

and N value) may be found by using a timer reload value of 0.

1. The timer reload value may never be larger than the timer range.
2. If a timer reload value calculation gives a negative or fractional

oscillator frequency and N value. SnSTAT.3 FEn Framing Error flag is set when the receiver fails to see a valid STOP bit at the end of the frame. a user program may poll. Cleared by software. received while RI in SnCON is still set. Cleared by software. only way it can be cleared is by a software write to this register. Figure 11. Serial Port Extended Status (SnSTAT) Register

1999 Apr 07 18

Table 3. Vector Locations for UARTs in XA The UARTs in XA has the following error flags; see Figure 11. its SM2 bit and prepare to receive the data bytes that will be coming. go on about their business, ignoring the coming data bytes. address which the master will use for addressing each of the slaves. necessary to make bit 2 = 1 to exclude slave 2. broadcast address will be FF hexadecimal. UART drivers which do not make use of this feature.

1999 Apr 07 19

valid stop bit was not received. In Mode 0, SM2 should be 0. SnCON.4 REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. double buffered. See text for details. received. In Mode 0, RB8 is not used. SnCON.1 TI Transmit interrupt flag. Set when another byte may be written to the UART transmitter. See text for details. Must be cleared by software. in the other modes (except see SM2). Must be cleared by software. Figure 12. Serial Port Control (SnCON) Register Figure 13. UART Framing Error Detection – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. Figure 14. UART Multiprocessor Communication, Automatic Address Recognition

1999 Apr 07 20

Each I/O port pin can be user configured to one of 4 output types. default to push-pull outputs. be found in the DC Characteristic table. Table 4. Port Configuration Register Settings be done with the maximum address size (20 bits). applied to the XA and held until the oscillator is running. most power supply ramp up conditions, this time is 10 milliseconds. RAM contents are indeterminate. Figure 15. Recommended Reset Circuit signal for external bus transactions. power down mode stops the oscillator in order to minimize power.

1999 Apr 07 21

levels and may be globally and/or individually enabled or disabled.

• Exception Interrupts – These are system level errors and other very important occurrences which include stack overflow, divide-by-0, and reset.
• Event interrupts – These are peripheral interrupts from devices such as UARTs, timers, and external interrupt inputs.
• Software Interrupts – These are equivalent of hardware interrupt, but are requested only under software control.
• Trap Interrupts – These are TRAP instructions, generally used to call system services in a multi-tasking system. Exception interrupts, software interrupts, and trap interrupts are generally standard for XA derivatives and are detailed in the XA User Guide. Event interrupts tend to be different on different XA derivatives. The XA-G3 supports a total of 9 maskable event interrupt sources (for the various XA peripherals), seven software interrupts, 5 exception interrupts (plus reset), and 16 traps. The maskable event interrupts share a global interrupt disable bit (the EA bit in the IEL register) and each also has a separate individual interrupt enable bit (in the IEL or IEH registers). Only three bits of the IPA register values are used on the XA-G3. Each event interrupt can be set to occur at one of 8 priority levels via bits in the Interrupt Priority (IP) registers, IPA0 through IPA5. The value 0 in the IPA field gives the interrupt priority 0, in effect disabling the interrupt. A value of 1 gives the interrupt a priority of 9, the value 2 gives priority 10, etc. The result is the same as if all four bits were used and the top bit set for all values except 0. Details of the priority scheme may be found in the XA User Guide. The complete interrupt vector list for the XA-G3, including all 4 interrupt types, is shown in the following tables. The tables include the address of the vector for each interrupt, the related priority register bits (if any), and the arbitration ranking for that interrupt source. The arbitration ranking determines the order in which interrupts are processed if more than one interrupt of the same priority occurs simultaneously.

Table 5. Interrupt Vectors

Philips Semiconductors Product specification XA-G3XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs

1999 Apr 07 22

Operating temperature under bias –55 to +125 °C Storage temperature range –65 to +150 °C Voltage on EA/VPP pin to VSS 0 to +13.0 V Voltage on any other pin to VSS –0.5 to VDD +0.5V V Maximum IOL per I/O pin 15 mA Power dissipation (based on package heat transfer limitations, not device power consumption)1.5 W DC ELECTRICAL CHARACTERISTICS VDD = 2.7V to 5.5V unless otherwise specified; VDD = Tamb = 0 to +70°C for commercial, –40°C to +85°C for industrial, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supplies IDD Supply current operating 30 MHz 60 80 mA IID Idle mode supply current 30 MHz 22 30 mA IPD Power-down current 5 100 A IPDI Power-down current (–40°C to +85°C) 150 A VRAM RAM-keep-alive voltage RAM-keep-alive voltage 1.5 V VIL Input low voltage –0.5 0.22VDD V V Input high voltage except XTAL1 RST At 5.0V 2.2 V VIH Input high voltage, except XTAL1 , RST At 3.3V 2 V VIH1 Input high voltage to XTAL1, RST For both 3.0 & 5.0V 0.7VDD V VO Output low voltage allports ALE PSEN 3 IOL = 3.2mA, VDD = 5.0V 0.5 V VOL O utput low voltage all ports, ALE , PSEN 3 1.0mA, VDD = 3.0V 0.4 V VO Output high voltage allports ALE PSEN 1 IOH = –100A, VDD = 4.5V 2.4 V VOH1 O utput high voltage all ports, ALE , PSEN 1 IOH = –15A, VDD = 2.7V 2.0 V VO Output high voltageports P0 3 ALE PSEN2 IOH = 3.2mA, VDD = 4.5V 2.4 V VOH2 O utput high voltage, ports P0–3, ALE , PSEN 2 IOH = 1mA, VDD = 2.7V 2.2 V C IO Input/Output pin capacitance 15 pF IIL Logical 0 input current, P0–36 VIN = 0.45V –25 –75 A ILI Input leakage current, P0–35 VIN = VIL or VIH ±10 A ITL Logical 1 to 0 transition current all ports4 At 5.5V –650 A NOTES: 1. Ports in Quasi bi-directional mode with weak pull-up (applies to ALE, PSEN only during RESET). 2. Ports in Push-Pull mode, both pull-up and pull-down assumed to be same strength 3. In all output modes 4. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. This current is highest when V IN is approximately 2V. 5. Measured with port in high impedance output mode. 6. Measured with port in quasi-bidirectional output mode. 7. Load capacitance for all outputs=80pF. 8. Under steady state (non-transient) conditions, I OL must be externally limited as follows: Maximum IOL per port pin: 15mA (*NOTE: This is 85°C specification for VDD = 5V.) Maximum IOL per 8-bit port: 26mA Maximum total IOL for all output: 71mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. See Figures 25, 26, 29, and 30 for IDD test conditions, and Figures 27 and 28 for ICC vs. Frequency. Max. 5V Active IDD = (fosc * 1.77 mA) + 7 mA Max. 5V Idle IDD = (fosc * 0.87 mA) + 4 mA Max. 3V Active IDD = (fosc * 0.77 mA) + 7 mA Max. 3V Idle IDD = (fosc * 0.54 mA) + 4 mA

Philips Semiconductors Product specification XA-G3XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs

1999 Apr 07 23

AC ELECTRICAL CHARACTERISTICS (5V) VDD = 4.5V to 5.5V; Tamb = 0 to +70°C for commercial, –40°C to +85°C for industrial. SYMBOL FIGURE PARAMETER VARIABLE CLOCK UNITSYMBOL FIGURE PARAMETER MIN MAX UNIT External Clock fC Oscillator frequency 0 30 MHz tC 22 Clock period and CPU timing cycle 1/fC ns tCHCX 22 Clock high time tC * 0.5 ns tCLCX 22 Clock low time tC * 0.4 ns tCLCH 22 Clock rise time 5 ns tCHCL 22 Clock fall time 5 ns Address Cycle tCRAR 21 Delay from clock rising edge to ALE rising edge 10 46 ns tLHLL 16 ALE pulse width (programmable) (V1 * tC ) – 6 ns tAVLL 16 Address valid to ALE de-asserted (set-up) (V1 * tC ) – 12 ns tLLAX 16 Address hold after ALE de-asserted (tC /2) – 10 ns Code Read Cycle tPLPH 16 PSEN pulse width (V2 * tC ) – 10 ns tLLPL 16 ALE de-asserted to PSEN asserted (tC /2) – 7 ns tAVIVA 16 Address valid to instruction valid, ALE cycle (access time) (V3 * tC ) – 36 ns tAVIVB 17 Address valid to instruction valid, non-ALE cycle (access time) (V4 * tC ) – 29 ns tPLIV 16 PSEN asserted to instruction valid (enable time) (V2 * tC ) – 29 ns tPXIX 16 Instruction hold after PSEN de-asserted 0 ns tPXIZ 16 Bus 3-State after PSEN de-asserted (disable time) tC – 8 ns tIXUA 16 Hold time of unlatched part of address after instruction latched0 ns Data Read Cycle tRLRH 18 RD pulse width (V7 * tC ) – 10 ns tLLRL 18 ALE de-asserted to RD asserted (tC /2) – 7 ns tAVDVA 18 Address valid to data input valid, ALE cycle (access time) (V6 * tC ) – 36 ns tAVDVB 19 Address valid to data input valid, non-ALE cycle (access time) (V5 * tC ) – 29 ns tRLDV 18 RD low to valid data in, enable time (V7 * tC ) – 29 ns tRHDX 18 Data hold time after RD de-asserted 0 ns tRHDZ 18 Bus 3-State after RD de-asserted (disable time) tC – 8 ns tDXUA 18 Hold time of unlatched part of address after data latched 0 ns Data Write Cycle tWLWH 20 WR pulse width (V8 * tC ) – 10 ns tLLWL 20 ALE falling edge to WR asserted (V12 * tC ) – 10 ns tQVWX 20 Data valid before WR asserted (data setup time) (V13 * tC ) – 22 ns tWHQX 20 Data hold time after WR de-asserted (Note 6) (V11 * tC ) – 5 ns tAVWL 20 Address valid to WR asserted (address setup time) (Note 5) (V9 * tC ) – 22 ns tUAWH 20 Hold time of unlatched part of address after WR is de-asserted (V11 * tC ) – 7 ns Wait Input tWTH 21 WAIT stable after bus strobe (RD, WR, or PSEN) asserted (V10 * tC ) – 30 ns tWTL 21 WAIT hold after bus strobe (RD, WR, or PSEN) assertion (V10 * tC ) – 5 ns NOTES ON PAGE 24.

Philips Semiconductors Product specification XA-G3XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs

1999 Apr 07 24

AC ELECTRICAL CHARACTERISTICS (3V) VDD = 2.7V to 5.5V; Tamb = 0 to +70°C for commercial, –40°C to +85°C for industrial. SYMBOL FIGURE PARAMETER VARIABLE CLOCK UNITSYMBOL FIGURE PARAMETER MIN MAX UNIT Address Cycle tCRAR 21 Delay from clock rising edge to ALE rising edge 15 60 ns tLHLL 16 ALE pulse width (programmable) (V1 * tC ) – 10 ns tAVLL 16 Address valid to ALE de-asserted (set-up) (V1 * tC ) – 18 ns tLLAX 16 Address hold after ALE de-asserted (tC /2) – 12 ns Code Read Cycle tPLPH 16 PSEN pulse width (V2 * tC ) – 12 ns tLLPL 16 ALE de-asserted to PSEN asserted (tC /2) – 9 ns tAVIVA 16 Address valid to instruction valid, ALE cycle (access time) (V3 * tC ) – 58 ns tAVIVB 17 Address valid to instruction valid, non-ALE cycle (access time) (V4 * tC ) – 52 ns tPLIV 16 PSEN asserted to instruction valid (enable time) (V2 * tC ) – 52 ns tPXIX 16 Instruction hold after PSEN de-asserted 0 ns tPXIZ 16 Bus 3-State after PSEN de-asserted (disable time) tC – 8 ns tIXUA 16 Hold time of unlatched part of address after instruction latched0 ns Data Read Cycle tRLRH 18 RD pulse width (V7 * tC ) – 12 ns tLLRL 18 ALE de-asserted to RD asserted (tC /2) – 9 ns tAVDVA 18 Address valid to data input valid, ALE cycle (access time) (V6 * tC ) – 58 ns tAVDVB 19 Address valid to data input valid, non-ALE cycle (access time) (V5 * tC ) – 52 ns tRLDV 18 RD low to valid data in, enable time (V7 * tC ) – 52 ns tRHDX 18 Data hold time after RD de-asserted 0 ns tRHDZ 18 Bus 3-State after RD de-asserted (disable time) tC – 8 ns tDXUA 18 Hold time of unlatched part of address after data latched 0 ns Data Write Cycle tWLWH 20 WR pulse width (V8 * tC ) – 12 ns tLLWL 20 ALE falling edge to WR asserted (V12 * tC ) – 10 ns tQVWX 20 Data valid before WR asserted (data setup time) (V13 * tC ) – 28 ns tWHQX 20 Data hold time after WR de-asserted (Note 6) (V11 * tC ) – 8 ns tAVWL 20 Address valid to WR asserted (address setup time) (Note 5) (V9 * tC ) – 28 ns tUAWH 20 Hold time of unlatched part of address after WR is de-asserted (V11 * tC ) – 10 ns Wait Input tWTH 21 WAIT stable after bus strobe (RD, WR, or PSEN) asserted (V10 * tC ) – 40 ns tWTL 21 WAIT hold after bus strobe (RD, WR, or PSEN) assertion (V10 * tC ) – 5 ns NOTES: 1. Load capacitance for all outputs = 80pF. 2. Variables V1 through V13 reflect programmable bus timing, which is programmed via the Bus Timing registers (BTRH and BTRL). Refer to the XA User Guide for details of the bus timing settings. V1) This variable represents the programmed width of the ALE pulse as determined by the ALEW bit in the BTRL register. V1 = 0.5 if the ALEW bit = 0, and 1.5 if the ALEW bit = 1. V2) This variable represents the programmed width of the PSEN pulse as determined by the CR1 and CR0 bits or the CRA1, CRA0, and ALEW bits in the BTRL register. – For a bus cycle with no ALE, V2 = 1 if CR1/0 = 00, 2 if CR1/0 = 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11. Note that during burst mode code fetches, PSEN does not exhibit transitions at the boundaries of bus cycles. V2 still applies for the purpose of determining peripheral timing requirements. – For a bus cycle with an ALE, V2 = the total bus cycle duration (2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10, and 5 if CRA1/0 = 11) minus the number of clocks used by ALE (V1 + 0.5). Example: If CRA1/0 = 10 and ALEW = 1, the V2 = 4 – (1.5 + 0.5) = 2.

Philips Semiconductors Product specification XA-G3XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs

1999 Apr 07 25

V3) This variable represents the programmed length of an entire code read cycle with ALE. This time is determined by the CRA1 and CRA0 bits in the BTRL register. V3 = the total bus cycle duration (2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10, and 5 if CRA1/0 = 11). V4) This variable represents the programmed length of an entire code read cycle with no ALE. This time is determined by the CR1 and CR0 bits in the BTRL register. V4 = 1 if CR1/0 = 00, 2 if CR1/0 = 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11. V5) This variable represents the programmed length of an entire data read cycle with no ALE. this time is determined by the DR1 and DR0 bits in the BTRH register. V5 = 1 if DR1/0 = 00, 2 if DR1/0 = 01, 3 if DR1/0 = 10, and 4 if DR1/0 = 11. V6) This variable represents the programmed length of an entire data read cycle with ALE. The time is determined by the DRA1 and DRA0 bits in the BTRH register. V6 = the total bus cycle duration (2 if DRA1/0 = 00, 3 if DRA1/0 = 01, 4 if DRA1/0 = 10, and 5 if DRA1/0 = 11). V7) This variable represents the programmed width of the RD pulse as determined by the DR1 and DR0 bits or the DRA1, DRA0 in the BTRH register, and the ALEW bit in the BTRL register. Note that during a 16-bit operation on an 8-bit external bus, RD remains low and does not exhibit a transition between the first and second byte bus cycles. V7 still applies for the purpose of determining peripheral timing requirements. The timing for the first byte is for a bus cycle with ALE, the timing for the second byte is for a bus cycle with no ALE. – For a bus cycle with no ALE, V7 = 1 if DR1/0 = 00, 2 if DR1/0 = 01, 3 if DR1/0 = 10, and 4 if DR1/0 = 11. – For a bus cycle with an ALE, V7 = the total bus cycle duration (2 if DRA1/0 = 00, 3 if DRA1/0 = 01, 4 if DRA1/0 = 10, and 5 if DRA1/0 = 11) minus the number of clocks used by ALE (V1 + 0.5). Example: If DRA1/0 = 00 and ALEW = 0, then V7 = 2 – (0.5 + 0.5) = 1. V8) This variable represents the programmed width of the WRL and/or WRH pulse as determined by the WM1 bit in the BTRL register. V8 1 if WM1 = 0, and 2 if WM1 = 1. V9) This variable represents the programmed address setup time for a write as determined by the data write cycle duration (defined by DW1 and DW0 or the DWA1 and DWA0 bits in the BTRH register), the WM0 bit in the BTRL register, and the value of V8. – For a bus cycle with an ALE, V9 = the total bus write cycle duration (2 if DWA1/0 = 00, 3 if DWA1/0 = 01, 4 if DWA1/0 = 10, and 5 if DWA1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1). Example: If DWA1/0 = 10, WM0 = 1, and WM1 = 1, then V9 = 4 – 1 – 2 = 1. – For a bus cycle with no ALE, V9 = the total bus cycle duration (2 if DW1/0 = 00, 3 if DW1/0 = 01, 4 if DW1/0 = 10, and 5 if DW1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1). Example: If DW1/0 = 11, WM0 = 1, and WM1 = 0, then V9 = 5 – 1 – 1 = 3. V10) This variable represents the length of a bus strobe for calculation of WAIT setup and hold times. The strobe may be RD (for data read cycles), WRL and/or WRH (for data write cycles), or PSEN (for code read cycles), depending on the type of bus cycle being widened by WAIT. V10 = V2 for WAIT associated with a code read cycle using PSEN. V10 = V8 for a data write cycle using WRL and/or WRH. V10 = V7–1 for a data read cycle using RD. This means that a single clock data read cycle cannot be stretched using WAIT. If WAIT is used to vary the duration of data read cycles, the RD strobe width must be set to be at least two clocks in duration. Also see Note 4. V11) This variable represents the programmed write hold time as determined by the WM0 bit in the BTRL register. V11 = 0 if the WM0 bit = 0, and 1 if the WM0 bit = 1. V12) This variable represents the programmed period between the end of the ALE pulse and the beginning of the WRL and/or WRH pulse as determined by the data write cycle duration (defined by the DWA1 and DWA0 bits in the BTRH register), the WM0 bit in the BTRL register, and the values of V1 and V8. V12 = the total bus cycle duration (2 if DWA1/0 = 00, 3 if DWA1/0 = 01, 4 if DWA1/0 = 10, and 5 if DWA1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1), minus the width of the ALE pulse (V1). Example: If DWA1/0 = 11, WM0 = 1, WM1 = 0, and ALEW = 1, then V12 = 5 – 1 – 1 – 1.5 = 1.5. V13) This variable represents the programmed data setup time for a write as determined by the data write cycle duration (defined by DW1 and DW0 or the DWA1 and DWA0 bits in the BTRH register), the WM0 bit in the BTRL register, and the values of V1 and V8. – For a bus cycle with an ALE, V13 = the total bus cycle duration (2 if DWA1/0 = 00, 3 if DWA1/0 = 01, 4 if DWA1/0 = 10, and 5 if DWA1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1), minus the number of clocks used by ALE (V1 + 0.5). Example: If DWA1/0 = 11, WM0 = 1, WM1 = 1, and ALEW = 0, then V13 = 5 – 1 – 2 – 1 = 1. – For a bus cycle with no ALE, V13 = the total bus cycle duration (2 if DW1/0 = 00, 3 if DW1/0 = 01, 4 if DW1/0 = 10, and 5 if DW1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1). Example: If DW1/0 = 01, WM0 = 1, and WM1 = 0, then V13 = 3 – 1 – 1 = 1. 3. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA User Guide section on the External Bus for details. 4. When code is being fetched for execution on the external bus, a burst mode fetch is used that does not have PSEN edges in every fetch cycle. Thus, if WAIT is used to delay code fetch cycles, a change in the low order address lines must be detected to locate the beginning of a cycle. This would be A3–A0 for an 8-bit bus, and A3–A1 for a 16-bit bus. Also, a 16-bit data read operation conducted on a 8-bit wide bus similarly does not include two separate RD strobes. So, a rising edge on the low order address line (A0) must be used to trigger a WAIT in the second half of such a cycle. 5. This parameter is provided for peripherals that have the data clocked in on the falling edge of the WR strobe. This is not usually the case, and in most applications this parameter is not used. 6. Please note that the XA-G3 requires that extended data bus hold time (WM0 = 1) to be used with external bus write cycles.

1999 Apr 07 26

• INSTR IN is either D0–D7 or D0–D15, depending on the bus width (8 or 16 bits).

Figure 16. External Program Memory Read Cycle (ALE Cycle)

• INSTR IN is either D0–D7 or D0–D15, depending on the bus width (8 or 16 bits).

Figure 17. External Program Memory Read Cycle (Non-ALE Cycle)

1999 Apr 07 27

• DATA IN is either D0–D7 or D0–D15, depending on the bus width (8 or 16 bits).

Figure 18. External Data Memory Read Cycle (ALE Cycle) Figure 19. External Data Memory Read Cycle (Non-ALE Cycle) 8 Bit Bus Only

1999 Apr 07 28

SU00584C* DATA OUT is either D0–D7 or D0–D15, depending on the bus width (8 or 16 bits). Figure 20. External Data Memory Write Cycle Figure 21. WAIT Signal Timing

1999 Apr 07 29

Figure 22. External Clock Drive AC inputs during testing are driven at VDD –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at the 50% point of transitions. Figure 23. AC Testing Input/Output and begins to float when a 100mV change from the loaded VOH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 24. Float Waveform Figure 25. IDD Test Condition, Active Mode Figure 26. IDD Test Condition, Idle Mode

1999 Apr 07 30

Figure 27. IDD vs. Frequency at VDD = 5.0V Figure 28. IDD vs. Frequency at VDD = 3.0V

1999 Apr 07 31

Figure 29. Clock Signal Waveform for IDD Tests in Active and Idle Modes Figure 30. IDD Test Condition, Power Down Mode

1999 Apr 07 32

the same as that used by the later 80C51 family EPROM parts. However different pins are used for many programming functions. the internet at www.philipsmcu.com/ftp.html. Table 6. Program Security Bits 1 U U U No Program Security features enabled.

2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes

from internal memory and further programming of the EPROM is disabled. 3 P P U Same as 2, also verify is disabled. 4 P P P Same as 3, external execution is disabled. Internal data RAM is not accessible.

1. P – programmed. U – unprogrammed.
2. Any other combination of the security bits is not defined.

 Trademark phrase of Intel Corporation.

Philips Semiconductors Product specification XA-G3XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs

1999 Apr 07 33

LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm SOT389-1

Philips Semiconductors Product specification XA-G3XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs

1999 Apr 07 34

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

Philips Semiconductors Product specification XA-G3XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs

1999 Apr 07 35

Philips Semiconductors Product specification XA-G3XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs

1999 Apr 07 36

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 04-99 Document order number: 9397 750 05538 /C0109 /C0110 /C0114 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.