P50N03LDG ETC2 | Alldatasheet

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Technical content

1 SEP-22-2004

N-Channel Logic Level Enhancement Mode Field Effect Transistor P50N03LDG TO-252 (DPAK) Lead-Free NIKO-SEM ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS Gate-Source Voltage V GS ±20 V TC = 25 °C 50 Continuous Drain Current TC = 100 °C ID Pulsed Drain Current1 I DM 150 Avalanche Current I AR 33 A Avalanche Energy L = 0.1mH E AS 250 Repetitive Avalanche Energy2 L = 0.05mH E AR 8.6 mJ TC = 25 °C 50 Power Dissipation TC = 100 °C PD W Operating Junction & Storage Temperature Range T j, Tstg -55 to 150 Lead Temperature (1/16” from case for 10 sec.) T L 275 THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNITS Junction-to-Case RθJC 2.5 Junction-to-Ambient RθJA 62.5 Case-to-Heatsink RθCS 0.6 °C / W 1Pulse width limited by maximum junction temperature. 2Duty cycle ≤ 1Ĉ ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) LIMITS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT STATIC Drain-Source Breakdown Voltage V (BR)DSS VGS = 0V, ID = 250µA 27 Gate Threshold Voltage V GS(th) VDS = VGS, ID = 250µA 1 1.6 3 V Gate-Body Leakage I GSS V DS = 0V, VGS = ±20V ±250 nA VDS = 20V, VGS = 0V 25 Zero Gate Voltage Drain Current I DSS VDS = 20V, VGS = 0V, TC = 125 °C 250 µA 1. GATE 2. DRAIN 3. SOURCE PRODUCT SUMMARY V (BR)DSS R DS(ON) I D 27 12mƸ 50A G D S

2 SEP-22-2004

N-Channel Logic Level Enhancement Mode Field Effect Transistor P50N03LDG TO-252 (DPAK) Lead-Free NIKO-SEM On-State Drain Current1 I D(ON) V DS = 10V, VGS = 10V 50 A VGS = 4.5V, ID = 20A 15 18 Drain-Source On-State Resistance1 RDS(ON) VGS = 10V, ID = 25A 10 12 mƸ Forward Transconductance1 g fs V DS = 10V, ID = 25A 32 S DYNAMIC Input Capacitance C iss 1200 1800 Output Capacitance C oss 600 1000 Reverse Transfer Capacitance C rss VGS = 0V, VDS = 15V, f = 1MHz 350 500 pF Total Gate Charge2 Q g 25 50 Gate-Source Charge2 Q gs 15 Gate-Drain Charge2 Q gd VDS = 10V, VGS = 10V, ID = 25A 10 nC Turn-On Delay Time2 t d(on) 6 16 Rise Time2 t r VDS = 15V, RL = 1Ƹ 120 250 Turn-Off Delay Time2 t d(off) ID ≅ 50A, VGS = 10V, RGEN = 24Ƹ 40 90 Fall Time2 t f 105 200 nS SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current I S 50 Pulsed Current3 I SM 150 A Forward Voltage1 V SD I S = 25A, VGS = 0V 0.9 1.3 V Reverse Recovery Time t rr 70 nS Peak Reverse Recovery Current I RM(REC) IF = IS, dlF/dt = 100A / µS 200 A Reverse Recovery Charge Q rr 0.043 µC 1Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2Ĉ. 2Independent of operating temperature. 3Pulse width limited by maximum junction temperature. REMARK: THE PRODUCT MARKED WITH “P50N03LDG”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXXG parts name.

3 SEP-22-2004

N-Channel Logic Level Enhancement Mode Field Effect Transistor P50N03LDG TO-252 (DPAK) Lead-Free NIKO-SEM TYPICAL CHARACTERISTICS

4 SEP-22-2004

N-Channel Logic Level Enhancement Mode Field Effect Transistor P50N03LDG TO-252 (DPAK) Lead-Free NIKO-SEM

5 SEP-22-2004

N-Channel Logic Level Enhancement Mode Field Effect Transistor P50N03LDG TO-252 (DPAK) Lead-Free NIKO-SEM TO-252 (DPAK) MECHANICAL DATA mm mm Dimension Min. Typ. Max. Dimension Min. Typ. Max. A 9.35 10.4 H 0.89 2.03 B 2.2 2.4 I 6.35 6.80 C 0.45 0.6 J 5.2 5.5 D 0.89 1.5 K 0.6 1 E 0.45 0.69 L 0.5 0.9 G 5.2 6.2 N G A H J I B C M L K D E F 13 2