P5021

P5021, P5021 QorIQ Integrated Processor Data Sheet - Data Sheet

Document overview

• Manufacturer or author: Freescale Semiconductor, Inc.
• PDF pages: 155

Technical content

Data Sheet: Technical Data © 2013-2014 Freescale Semiconductor, Inc. All rights reserved. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. The P5021 QorIQ integrated communication processor combines two Power Architecture® processor cores with high-performance data path acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and aerospace applications. This chip can be used for combined control, data path, and application layer processing in routers, switches, base station controllers, and general-purpose embedded computing. Its high level of integration offers significant performance benefits compared to multiple discrete devices while also greatly simplifying board design. The chip includes the following function and features:

• Two e5500 Power Architecture cores – Each core has a backside 512 KB L2 cache with ECC – Three levels of instructions: user, supervisor, and hypervisor – Independent boot and reset – Secure boot capability
• CoreNet fabric supporting coherent and non-coherent transactions amongst CoreNet endpoints
• Frontside 2 MB CoreNet platform cache with ECC
• CoreNet bridges between the CoreNet fabric the I/Os, datapath accelerators, and high and low speed peripheral interfaces
• Two 10-Gigabit Ethernet (XAUI) controllers
• Ten 1-Gigabit Ethernet controllers – SGMII, 2.5Gb/s SGMII and RGMII interfaces
• Two 64-bit DDR3/3L SDRAM memory controllers with ECC
• Multicore programmable interrupt controller (PIC)
• F o u r I 2C controllers
• Four 2-pin UARTs or two 4-pin UARTs
• Two 4-channel DMA engines
• Enhanced local bus controller (eLBC)
• Three PCI Express 2.0 controllers/ports
• Two serial ATA (SATA) 2.0 controllers
• Enhanced secure digital host controller (SD/MMC)
• Enhanced serial peripheral interface (eSPI)
• Two high-speed USB 2.0 controllers with integrated PHYs
• RAID 5 and 6 storage acceler ator with support for end-to-end data protection information
• Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: – Frame Manager (FMan) for packet parsing, classification, and distribution – Queue Manager (QMan) for scheduling, packet sequencing and congestion management – Hardware Buffer Manager (B Man) for buffer allocation and deallocation – Encryption/Decryption
• 1295 FC-PBGA package This figure shows the major functional units within the chip. P5021 QorIQ Integrated Processor Data Sheet Document Number: P5021 Rev. 1, 05/2014 P5021 FC-PBGA–1295 37.5 mm × 37.5 mm

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor2 Table of Contents

2.12 Ethernet: data path three-speed Ethernet (dTSEC),

2.16 Multicore programmable interrupt controller (MPIC)

2.18 I

3.5 SerDes block power supply decoupling recommendations

6.2 Orderable part numbers addressed by this document 154

Figure 1. P5021 block diagram

1 Pin assignments and reset states

These figures show the FC-PBGA ball map diagrams.

1600 MT/s DDR-3

Figure 2. 1295 BGA ball map diagram (top view)

2 TDI OVDD

Figure 3. 1295 BGA ball map diagram (detail view A)

Figure 4. 1295 BGA ball map diagram (detail view B)

Figure 5. 1295 BGA ball map diagram (detail view C)

Figure 6. 1295 BGA ball map diagram (detail view D)

1.2 Pinout list

This table provides the pinout listing for the 1295 FC-PBGA package by bus. Table 1. Pins listed by bus

Table 1. Pins listed by bus (continued)

1. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to OVDD.
2. This pin is an open drain signal.
3. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the

a pull up or active driver is needed.

1. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or

because it has other manufacturing test functions. This pin is therefore described as an I/O for boundary scan.

1. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to BV

to possible noise, and so forth.

1. This output is actively driven during reset rather than being three-stated during reset.
2. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
3. These pins are connected to the correspondent power and ground nets internally and may be connected as a differential pair

to be used by the voltage regulators with remote sense function.

1. These pins may be connected to a thermal diode monitoring device such as the ADT7461A only with a clear understanding

that proper thermal diode operation is not implied and the thermal diode feature may not be available in the production device.

1. These are test signals for factory use only and must be pulled up (100 Ω–1 kΩ) to OV

DD for normal device operation.

1. Independent supplies derived from board VDD_PL (Core clusters, Platform, DDR) or SVDD (SerDes).
2. Recommend a pull-up resistor of 1-kΩ be placed on this pin to OVDD if I2C interface is used.
3. This pin requires an external 1-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively
4. For DDR3 and DDR3L, Dn_MDIC[0] is grounded through an 40.2-Ω (half-strength mode) precision 1% resistor and

automatic calibration of the DDR3 and DDR3L IOs.

1. These pins should be pulled up to 1.2V through a 180Ω ± 1% resistor for EM2_MDC and a 330Ω ± 1% resistor for
2. Pin has a weak internal pull-up.
3. These pins should be pulled to ground (GND).
4. Ethernet Management interface 2 pins function as open drain I/Os. The interface shall conform to 1.2 V nominal voltage

levels. LVDD must be powered to use this interface.

1. This pin requires a 200-Ω pull-up to XVDD.
2. This pin requires a 200-Ω pull-up to SVDD.
3. This GPIO pin is on LVDD power plane, not OVDD.
4. Functionally, this pin is an I/O, but may act as an output only or an input only depending on the pin mux configuration defined
5. See Section 3.6, “Connection recommendations,” for additional details on this signal.
6. This signal must be pulled low to GND.
7. Warning, incorrect voltage select settings can lead to irreversible device damage. See Section 3.2, “Supply power default
8. SDHC_DAT[4:7] require CVDD = 3.3 V when muxed extended SDHC data signals are enabled via the RCW[SPI] field.
9. The cfg_xvdd_sel(LAD[26]) reset configuration pin must select the correct voltage that is being supplied on the XVDD pin.

Incorrect voltage select settings can lead to irreversible device damage.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

2 Electrical characteristics

This section provides the AC and DC electrical specifications for the chip. The chip is currently targeted to these specifications, some of which are independent of the I/O cell but are included for a more complete reference. These are not purely I/O buffer design specifications.

2.1 Overall DC electrical characteristics

This section describes the ratings, conditions, and other electrical characteristics.

2.1.1 Absolute maximum ratings

This table provides the absolute maximum ratings. 33. See Section 2.2, “Power-up sequencing and Section 5, “Security fuse processor,” for additional details on this signal. 35. Pin must NOT be pulled down by a resistor or the component it is connected to during power-on reset. 36. This pin should be connected to GND through a 10kΩ ± 0.1% resistor with a low temperature coefficient of ≤ 25ppm/°C for bias generation. 37. A 1uF to 1.5uF capacitor connected to GND is required on this signal. A list of recommended capacitors are shown in Section 3.6.4.2, “USBn_VDD_1P8_DECAP capacitor options.” 39. For systems which boot from local bus (GPCM)-controlled NOR flash or (FCM)-controlled NAND flash, a pullup on LGPL4 is required. 40. Functionally, this pin is an input, but structurally it is an I/O because it either samples configuration input during reset or because it has other manufacturing test functions. This pin is therefore described as an I/O for boundary scan. 41. If migration from a P4 device, this pin is allowed to be powered by AVDD_CC2. If not migrating, do not connect. 42. The VDD_VID_CA_CB pins are inputs at POR. If a voltage regulator is connected directly to the VID_VDD_CA_CB pins, customers need to put weak pull-ups or pull-downs on their board so that their voltage regulator drives a guaranteed-to-work voltage with the cores configured to run at a safe frequency for that voltage. This is needed so that a working voltage can be applied until the operating voltage is determined (for example, so that PLLs can begin to lock, and so on, during this time frame or while the voltage is ramping). The safe boot voltage for the chip is 1.1 V. Note that the P5021 does not require VID to meet it's performance and power envelope. All power rails should be fixed at the operating values specified in Table 3. “Recommended operating conditions.” 43. VDD_LL should be connected directly to VDD_PL. 44. Normally tied to GND. See the applicable migration application note if moving from P3041 (AN4395) or P5020/P5010 (AN4400). Table 2. Absolute maximum operating conditions1

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 53 Fuse programming override supply POV DD –0.3 to 1.65 V 1 DUART, I2C, DMA, MPIC, GPIO, system control and power management, clocking, debug, I/O voltage select, and JTAG I/O voltage OVDD –0.3 to 3.63 V — eSPI, eSHDC CV DD –0.3 to 3.63 –0.3 to 2.75 –0.3 to 1.98 DDR3 and DDR3L DRAM I/O voltage GV DD –0.3 to 1.65 V — Enhanced local bus I/O voltage BV DD –0.3 to 3.63 –0.3 to 2.75 –0.3 to 1.98 Core power supply for SerDes transceivers SV DD –0.3 to 1.1 V — Pad power supply for SerDes transceivers XV DD –0.3 to 1.98 –0.3 to 1.65 Ethernet I/O, Ethernet management interface 1 (EMI1), 1588, GPIO LV DD –0.3 to 3.63 –0.3 to 2.75 Ethernet management interface 2 (EMI2) — –0.3 to 1.32 V 8 USB PHY Transceiver supply voltage USB_V DD_3P3 –0.3 to 3.63 V — USB PHY PLL supply voltage USB_V DD_1P0 –0.3 to 1.1 V — Low-power security monitor supply V DD_LP –0.3 to 1.1 V — Table 2. Absolute maximum operating conditions1 (continued)

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Input voltage7 DDR3 and DDR3L DRAM signals MV IN –0.3 to (GVDD + 0.3) V 2, 7 DDR3 and DDR3L DRAM reference MV REF –0.3 to (GVDD/2+ 0.3) V 2, 7 Ethernet signals (except EMI2) LV IN –0.3 to (LVDD + 0.3) V 3, 7 eSPI, eSHDC CV IN –0.3 to (CVDD + 0.3) V 4, 7 Enhanced local bus signals BV IN –0.3 to (BVDD + 0.3) V 5, 7 DUART, I2C, DMA, MPIC, GPIO, system control and power management, clocking, debug, I/O voltage select, and JTAG I/O voltage OVIN –0.3 to (OVDD + 0.3) V 6, 7 SerDes signals XV IN –0.4 to (XVDD + 0.3) V 7 USB PHY transceiver signals USB_V IN_3P3 –0.3 to (USB_VDD_3P3 + 0.3) Ethernet management interface 2 (EMI2) signals Storage junction temperature range T stg –55 to 150 °C— Notes: 1. Functional operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only; functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. Caution: CVIN must not exceed CVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. Caution: BVIN must not exceed BVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 6. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 7. (C,X,B,G,L,O)VIN may overshoot (for VIH) or undershoot (for VIL) to the voltages and maximum duration shown in Figure 7. 8. Ethernet Management interface 2 pins function as open drain I/Os. The interface shall conform to 1.2 V nominal voltage levels. LVDD must be powered to use this interface. 9. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the sense pin. 10. Implementation may choose either VDD_PL pin for feedback loop. If the platform and core groups are supplied by a single regulator, it is recommended that VDD_CA be used. 11. VDD_PL voltage must not exceed VDD_CA.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 55

2.1.2 Recommended operating conditions

This table provides the recommended operating conditions for this device. Note that proper device operation outside these conditions is not guaranteed. Table 3. Recommended operating conditions

2000 MHz)

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Input voltage DDR3 and DDR3L DRAM signals MVIN GND to GVDD V7 DDR3 and DDR3L DRAM reference MVREF GVDD/2 ± 1% V 7 Ethernet signals (except EMI2) LV IN GND to LVDD V7 eSPI, eSHDC CV IN GND to CVDD V7 Enhanced local bus signals BV IN GND to BVDD V7 DUART, I2C, DMA, MPIC, GPIO, system control and power management, clocking, debug, I/O voltage select, and JTAG I/O voltage OV IN GND to OVDD V7 SerDes signals SV IN GND to SVDD V7 USB PHY Transceiver signals USB_V IN_3P3 GND to USB_VDD_3P3 Ethernet Management interface 2 (EMI2) signals — GND to 1.2V V 4, 7 Operating Temperature range Normal Operation T A, TJ TA = 0 (min) to TJ = 105 (max) (90 (max) core frequency > 2000 MHz) °C— Extended Temperature T A, TJ TA = -40 (min) to TJ = 105 (max) °C— Secure Boot Fuse Programming T A, TJ TA = 0 (min) to TJ = 70 (max) °C2 Notes: 1. VDD_PL voltage must not exceed VDD_CA. 2. POVDD must be supplied 1.5 V and the chip must operate in the specified fuse programming temperature range only during secure boot fuse programming. For all other operating conditions, POVDD must be tied to GND, subject to the power sequencing constraints shown in Section 2.2, “Power-up sequencing.” 3. Selecting RGMII limits LVDD to 2.5V. 4. Ethernet Management interface 2 pins function as open drain I/Os. The interface shall conform to 1.2 V nominal voltage levels. LVDD must be powered to use this interface.6. Supply voltage specified at the voltage sense pin. Voltage input pins must be regulated to provide specified voltage at the sense pin. 7. All input signals must increase/decrease monotonically throughout the entire rise/fall duration. Table 3. Recommended operating conditions (continued)

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 57 This figure shows the undershoot and overshoot voltages at the interfaces of the chip. Figure 7. Overshoot/Undershoot voltage for BVDD/GVDD/LVDD/OVDD provided at the voltages shown in Table 3. The input voltage threshold scales with respect to the associated I/O supply voltage. operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded. For I2C, tCLOCK refers to SYSCLK. For DDR GVDD, tCLOCK refers to Dn_MCK. For eSPI CVDD, tCLOCK refers to SPI_CLK. For eLBC BVDD, tCLOCK refers to LCLK. For SerDes XVDD, tCLOCK refers to SD_REF_CLK. For dTSEC LVDD, tCLOCK refers to EC_GTX_CLK125. For JTAG OVDD, tCLOCK refers to TCK.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

2.1.3 Output driver characteristics

This table provides information about the characteristics of the output driver strengths. The values are preliminary estimates.

2.2 Power-up sequencing

The chip requires that its power rails be applied in a specific sequence in order to ensure proper device operation. These requirements are as follows for power up: 1. Bring up OV DD, LVDD, BVDD, CVDD, and USB_VDD_3P3. Drive POVDD = GND. — PORESET input must be driven asserted and held during this step — IO_VSEL inputs must be driven during this step and held stable during normal operation. —U S B _ V DD_3P3 rise time (10% to 90%) has a minimum of 350 μs. 2. Bring up V DD_PL, VDD_CA, SVDD, A VDD (cores, platform, DDR, SerDes) and USB_VDD_1P0. VDD_PL and USB_VDD_1P0 must be ramped up simultaneously. 3. Bring up GV DD and XVDD. 4. Negate PORESET input as long as the required assertion/hold time has been met per Table 15. 5. For secure boot fuse programmi ng: After negation of PORESET, drive POVDD = 1.5 V after a required minimum delay per Table 5. After fuse programming is completed, it is required to return POVDD = GND before the system is power cycled (PORESET assertion) or powered down (VDD_PL ramp down) per the required timing specified in Table 5. See Section 5, “Security fuse processor,” for additional details. Only two secure boot fuse programming events are permitted per lifetime of a device. reading of the fuse block may only occur while POVDD = GND. Table 4. Output drive capability

1. The drive strength of the DDR3 or DDR3L interface in half-strength mode is at Tj = 105 °C and at GVDD (min).

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 59 WARNING Only 100,000 POR cycles are permitted per lifetime of a device. WARNING While VDD is ramping, current may be supplied from VDD through the P5021 to GVDD. Nevertheless, GVDD from an external supply should follow the sequencing described above. All supplies must be at their stable values within 75 ms. Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. This figure provides the POV DD timing diagram. Figure 8. POVDD timing diagram This table provides information on the power-down and power-up sequence parameters for POVDD. DDR signals being in an indeterminate state during power up, the sequencing for GVDD is not required. Table 5. POVDD timing 5

1. Delay required from the negation of PORESET to driving POVDD ramp up. Delay measured from PORESET negation at 90%
2. Delay required from fuse programming finished to POVDD ramp down start. Fuse programming must complete while POVDD

GND. After fuse programming is completed, it is required to return POVDD = GND.

1. Delay required from POVDD ramp down complete to VDD_PL ramp down start. POVDD must be grounded to minimum 10%

POVDD before VDD_PL is at 90% VDD.

1. Delay required from POVDD ramp down complete to PORESET assertion. POVDD must be grounded to minimum 10% POVDD

before PORESET assertion reaches 90% OVDD.

1. Only two secure boot fuse programming events are permitted per lifetime of a device.

NOTE: POVDD must be stable at 1.5 V prior to initiating fuse programming.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Incorrect voltage select settings can lead to irreversible device damage. See Section 3.2, “Supply power default setting.” NOTE From a system standpoint, if any of the I/O power supplies ramp prior to the VDD_CA, or VDD_PL supplies, the I/Os associated with that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the device.

2.3 Power-down requirements

The power-down cycle must complete such that power supply values are below 0.4 V before a new power-up cycle can be started. If performing secure boot fuse programming per Section 2.2, “Power-up sequencing,” it is required that POVDD = GND before the system is power cycled (PORESET assertion) or powered down (VDD_PL ramp down) per the required timing specified in Table 5. VDD_PL and USB_VDD_1P0 must be ramped down simultaneously. USB_VDD_1P8_DECAP should starts ramping down only after USB_VDD_3P3 is below 1.65 V .

2.4 Power characteristics

This table shows the power dissipations of the VDD_CA, SVDD, and VDD_PL supply for various operating platform clock frequencies versus the core and DDR clock frequencies for the chip. Table 6. Power dissipation

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 61 This table shows the estimated power dissipation on the A VDD and A VDD_SRDS supplies for the chip’s PLLs, at allowable voltage levels. Typical 1800 600 1200 450 1.0 1.1 65 20 — — — — Thermal 105 2 9 ——— — Maximum 30 15 13 13 2.2 Notes: 1. Combined power of VDD_PL, VDD_CA, SVDD with both DDR controllers and all SerDes banks active. Does not include I/O power. 2. Typical power assumes Dhrystone running with activity factor of 80% (on all cores) and executing DMA on the platform with 90% activity factor. 3. Typical power based on nominal processed device. 4. Maximum power assumes Dhrystone running with activity factor at 100% (on all cores) and executing DMA on the platform at 100% activity factor. 5. Thermal power assumes Dhrystone running with activity factor of 80% (on all cores) and executing DMA on the platform at 90% activity factor. 6. Maximum power provided for power supply design sizing. 7. Thermal and maximum power are based on worst case processed device. Table 7. AVDD power dissipation Table 6. Power dissipation (continued)

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 This table shows the estimated power dissipation on the POVDD supply for the chip, at allowable voltage levels. This table shows the estimated power dissipation on the VDD_LP supply for the chip, at allowable voltage levels.

2.5 Thermal

This table shows the thermal characteristics for the chip. Table 8. POVDD power dissipation

1. To ensure device reliability, fuse programming must be performed within the recommended fuse programming temperature

Table 9. VDD_LP Power Dissipation

1. When P5021 is off, V DD_LP may be supplied by battery power to the Zeroizable Master Key and other Trust Architecture

Reference Manual Trust Architecture chapter for more information. Table 10. Package thermal characteristics 6

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 63

2.6 Input clocks

This section discusses the system clock timing specifications for DC and AC power, spread spectrum sources, real time clock timing, and dTSEC gigabit Ethernet reference clocks AC timing.

2.6.1 System clock (SYSCLK) timing specifications

This table provides the system clock (SYSCLK) DC specifications. Junction to board — R ΘJB 3 °C/W 3 Junction to case top — R ΘJCtop 0.44 °C/W 4 Junction to lid top — R ΘJClid 0.17 °C/W 5 Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 3. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 4. Junction-to-Lid-Top thermal resistance determined using the using MIL-STD 883 Method 1012.1. However, instead of the cold plate, the lid top temperature is used here for the reference case temperature. The reported value does not include the thermal resistance of the interface layer between the package and cold plate. 5. Junction-to-lid-top thermal resistance determined using the using MIL-STD 883 Method 1012.1. However, instead of the cold plate, the lid top temperature is used here for the reference case temperature. Reported value does not include the thermal resistance of the interface layer between the package and cold plate. 6. Reference Section 3.8, “Thermal management information,” for additional details. Table 11. SYSCLK DC electrical characteristics (OVDD = 3.3 V) For recommended operating conditions, see Table 3.

1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”

Table 10. Package thermal characteristics (continued)6

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 This table provides the system clock (SYSCLK) AC timing specifications.

2.6.2 Spread-spectrum sources recommendations

Spread-spectrum clock sources is an increasingly popular way to control electromagnetic interference emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and government requirements. These clock sources intentionally add long-term jitter to diffuse the EMI spectral content. The jitter specification given in Table 13 considers short-term (cycle-to-cycle) jitter only. The clock generator’s cycle-to-cycle output jitter should meet the chip’s input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate concerns; the chip is compatible with spread spectrum sources if the recommendations listed in Table 13 are observed. CAUTION The processor’s minimum and maximum SYSCLK and core/platform/DDR frequencies must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is operated at its maximum rated core/platform/DDR frequency should avoid violating the stated limits by using down-spreading only. Table 12. SYSCLK AC timing specifications For recommended operating conditions, see Table 3.

1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency, do not exceed their

respective maximum or minimum operating frequencies.

1. Measured at the rising edge and/or the falling edge at OVDD/2.
2. Slew rate as measured from ±0.3 ΔVAC at center of peak to peak voltage at clock input.
3. Phase noise is calculated as FFT of TIE jitter.

Table 13. Spread-spectrum clock source recommendations For recommended operating conditions, see Table 3.

1. SYSCLK frequencies that result from frequency spreading and the resulting core frequency must meet the minimum and

maximum specifications given in Table 12.

1. Maximum spread spectrum frequency may not result in exceeding any maximum operating frequency of the device.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 65

2.6.3 Real time clock timing

The real time clock timing (RTC) input is sampled by the platform clock. The output of the sampling latch is then used as an input to the counters of the MPIC and the time base unit of the core; there is no need for jitter specification. The minimum pulse width of the RTC signal should be greater than 16× the period of the platform clock with a 50% duty cycle. There is no minimum RTC frequency; RTC may be grounded if not needed. 2.6.4 dTSEC gigabit Ethernet reference clock timing This table provides the dTSEC gigabit Ethernet reference clocks AC timing specifications.

2.6.5 Other input clocks

A description of the overall clocking of this device is available in the applicable chip reference manual in the form of a clock subsystem block diagram. For information on the input clock requirements of functional blocks sourced external of the device, such as SerDes, Ethernet Management, eSDHC, Local bus, see the specific interface section.

2.7 RESET initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements. This table provides the RESET initialization AC timing specifications. Table 14. EC_GTX_CLK125 AC timing specifications

1. Rise and fall times for EC_GTX_CLK125 are measured from 20% to 80% (rise time) and 80% to 20% (fall time) of LVDD.
2. EC_GTX_CLK125 is used to generate the GTX clock for the dTSEC transmitter with 2% degradation. EC_GTX_CLK125 duty

Table 15. RESET initialization timing specifications

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 This table provides the PLL lock times.

2.8 Power-on ramp rate

This section describes the AC electrical specifications for the power-on ramp rate requirements. Controlling the maximum Power-On Ramp Rate is required to avoid falsely triggering the ESD circuitry. This table provides the power supply ramp rate specifications.

2.9 DDR3 and DDR3L SDRAM controller

This section describes the DC and AC electrical specifications for the DDR3 and DDR3L SDRAM controller interface. Note that the required GVDD(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and GVDD(typ) voltage is 1.35 V when interfacing to DDR3L SDRAM. NOTE When operating at DDR data rates of 1600 MT/s only one dual-ranked module per memory controller is supported. Input hold time for all POR configurations with respect to negation of PORESET 2 — SYSCLKs 1 Maximum valid-to-high impedance time for actively driven POR configurations with respect to negation of PORESET — 5 SYSCLKs 1 Notes: 1. SYSCLK is the primary clock input for the chip. 2. The device asserts HRESET as an output when PORESET is asserted to initiate the power-on reset process. The device releases HRESET sometime after PORESET is negated. The exact sequencing of HRESET negation is documented in Section 4.4.1 “Power-On Reset Sequence,” of the applicable chip reference manual. 3. PORESET must be driven asserted before the core and platform power supplies are powered up , see Section 2.2, “Power-up sequencing.” Table 16. PLL lock times Table 17. Power supply ramp rate

1. Ramp rate is specified as a linear ramp from 10 to 90%. If non-linear (for example, exponential), the maximum rate of change

from 200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry.

1. Over full recommended operating temperature range (see Table 3).

Table 15. RESET initialization timing specifications (continued)

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 67

2.9.1 DDR3 and DDR3L SDRAM interfac e DC electrical characteristics

This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3 SDRAM. This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3L SDRAM. Table 18. DDR3 SDRAM interface DC electrical characteristics (GVDD = 1.5 V)1 For recommended operating conditions, see Table 3.

1. GVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage

supply may or may not be from the same source.

1. MVREF is expected to be equal to 0.5 × GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed the MVREF DC level by more than ±1% of the DC value (that is, ±15 mV).

1. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
2. The voltage regulator for MVREF must meet the specifications stated in Table 21.
3. Input capacitance load for DQ, DQS, and DQS are available in the IBIS models.
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.

Table 19. DDR3L SDRAM interface DC electrical characteristics (GVDD = 1.35 V)1 For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 This table provides the DDR controller interface capacitance for DDR3 and DDR3L. This table provides the current draw characteristics for MVREF. I/O leakage current I OZ –50 50 μA6 Output high current (VOUT = 0.641 V) I OH —– 2 3 . 3 m A 7 , 8 Output low current (VOUT = 0.641 V) I OL 23.3 — mA 7, 8 Notes: 1. GVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage supply may or may not be from the same source. 2. MVREF is expected to be equal to 0.5 × GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed the MVREF DC level by more than ±1% of the DC value (that is, ±13.5 mV). 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be equal to MVREF with a min value of MVREF – 0.04 and a max value of MVREF + 0.04. VTT should track variations in the DC level of MVREF. 4. The voltage regulator for MVREF must meet the specifications stated in Table 21. 5. Input capacitance load for DQ, DQS, and DQS are available in the IBIS models. 6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD. 7. Refer to the IBIS model for the complete output IV curve characteristics. 8. IOH and IOL are measured at GVDD = 1.283 V Table 20. DDR3 and DDR3L SDRAM Capacitance For recommended operating conditions, see Table 3.

1. This parameter is sampled. GVDD = 1.5 V ± 0.075 V (for DDR3), f = 1 MHz, TA =2 5° C , VOUT = GVDD/2,

VOUT (peak-to-peak) = 0.150 V. VOUT (peak-to-peak) = 0.167 V. Table 21. Current Draw Characteristics for MVREF For recommended operating conditions, see Table 3. Table 19. DDR3L SDRAM interface DC electrical characteristics (GVDD = 1.35 V)1 (continued) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 69

2.9.2 DDR3 and DDR3L SDRAM interf ace AC timing specifications

This section provides the AC timing specifications for the DDR SDRAM controller interface. The DDR controller supports DDR3 and DDR3L memories. Note that the required GVDD(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and the required GVDD(typ) voltage is 1.35 V when interfacing to DDR3L SDRAM.

2.9.2.1 DDR3 and DDR3L SDRAM interf ace input AC timing specifications

This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3 SDRAM. This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3L SDRAM. This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3 SDRAM. Table 22. DDR3 SDRAM interface input AC timing specifications For recommended operating conditions, see Table 3. Table 23. DDR3L SDRAM interface input AC timing specifications For recommended operating conditions, see Table 3. Table 24. DDR3 and DDR3L SDRAM interface input AC timing specifications For recommended operating conditions, see Table 3.

1600 MT/s data rate –112 112

1333 MT/s data rate –125 125

1066 MT/s data rate –170 170

800 MT/s data rate –200 200

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 This figure shows the DDR3 and DDR3L SDRAM interface input timing diagram. Figure 9. DDR3 and DDR3L SDRAM interface input timing diagram

1600 MT/s data rate –200 200

1333 MT/s data rate –250 250

1200 MT/s data rate –275 275

1066 MT/s data rate –300 300

800 MT/s data rate –425 425

captured with MDQS[n]. This should be subtracted from the total timing budget.

1. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be

Table 24. DDR3 and DDR3L SDRAM interface input AC timing specifications (continued) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 71

2.9.2.2 DDR3 and DDDR3L SDRAM interface output AC timing specifications

This table contains the output AC timing targets for the DDR3 SDRAM interface. Table 25. DDR3 and DDR3L SDRAM interface output AC timing specifications For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 For the ADDR/CMD setup and hold specifications in Table 25, it is assumed that the clock control register is set to adjust the memory clocks by ½ applied cycle. MDQ/MECC/MDM output setup with respect to MDQS tDDKHDS, tDDKLDS ps 5

1600 MT/s data rate 200 —

1333 MT/s data rate 250 —

1200 MT/s data rate 275 —

1066 MT/s data rate 300 —

800 MT/s data rate 375 —

MDQ/MECC/MDM output hold with respect to MDQS t DDKHDX, tDDKLDX ps 5 DDKHMP 0.9 × tMCK —n s — MDQS post-amble t DDKHME 0.4 × tMCK 0.6 × tMCK ns — Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2. All MCK/MCK and MDQS/MDQS referenced measurements are made from the crossing of the two signals. 3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. 4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the same delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two parameters have been set to the same adjustment value. See the applicable chip reference manual for a description and explanation of the timing modifications enabled by use of these bits. 5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor. Table 25. DDR3 and DDR3L SDRAM interface output AC timing specifications (continued) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 This figure provides the AC test load for the DDR3 and DDR3L controller bus. Figure 12. DDR3 and DDR3L controller bus AC test load This section describes the DC and AC electrical specifications for the eSPI interface. This table provides the DC electrical characteristics for the eSPI interface operating at CVDD = 3.3 V . This table provides the DC electrical characteristics for the eSPI interface operating at CVDD = 2.5 V . Table 26. eSPI DC electrical characteristics (CVDD = 3.3 V)1,2 For recommended operating conditions, see Table 3.

1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3.
2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”

Table 27. eSPI DC electrical characteristics (CVDD = 2.5 V) For recommended operating conditions, see Table 3.

1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3.
2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 75 This table provides the DC electrical characteristics for the eSPI interface operating at CVDD = 1.8 V . 2.10.2 eSPI AC timing specifications This table provides the eSPI input and output AC timing specifications. Table 28. eSPI DC electrical characteristics (CVDD = 1.8 V) For recommended operating conditions, see Table 3.

1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3.
2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”

Table 29. eSPI AC timing specifications For recommended operating conditions, see Table 3.

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are
3. See the applicable chip reference manual for details on the SPMODE register.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 This figure provides the AC test load for the eSPI. Figure 13. eSPI AC test load the clock edge is selectable on eSPI. Figure 14. eSPI AC timing in master mode (Internal Clock) diagram

2.11 DUART

This section describes the DC and AC electrical specifications for the DUART interface.

2.11.1 DUART DC electrical characteristics

This table provides the DC electrical characteristics for the DUART interface. Table 30. DUART DC electrical characteristics (OVDD = 3.3 V) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 77

2.11.2 DUART AC electrical specifications

This table provides the AC timing parameters for the DUART interface. management interface, IEEE Std 1588 This section provides the AC and DC electrical characteristics for the data path three-speed Ethernet controller, the Ethernet management interface, and the IEEE Std 1588 interface.

2.12.1 SGMII timing specifications

See Section 2.20.8, “SGMII interface.”

2.12.2 MII and RGMII timing specifications

This section discusses the electrical characteristics for the MII and RGMII interfaces. Input current (OVIN = 0 V or OVIN = OVDD)I IN — ±40 μA2 Output high voltage (OVDD = min, IOH = –2 mA) V OH 2.4 — V — Output low voltage (OVDD = min, IOL = 2 mA) V OL —0 . 4 V — Notes: 1. The symbol OVIN, in this case, represents the OVIN symbol referenced in Table 3. 2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.” Table 31. DUART AC timing specifications For recommended operating conditions, see Table 3. PLAT refers to the internal platform clock.

1. The actual attainable baud rate is limited by the latency of interrupt processing.
2. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values

Table 30. DUART DC electrical characteristics (OVDD = 3.3 V) (continued) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

2.12.2.1 MII and RGMII DC electrical characteristics

This table shows the MII DC electrical characteristics when operating at LVDD = 3.3 V supply. This table shows the MII and RGMII DC electrical characteristics when operating at LVDD = 2.5 V supply.

2.12.2.2 MII AC timing specifications

This section describes the MII transmit and receive AC timing specifications. Table 32. MII DC electrical characteristics (LVDD = 3.3 V) For recommended operating conditions, see Table 3.

1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
2. The symbol VIN, in this case, represents the LVIN symbols referenced in Table 2 and Table 3.

Table 33. MII and RGMII DC electrical characteristics (LVDD = 2.5 V) For recommended operating conditions, see Table 3.

1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
2. The symbol VIN, in this case, represents the LVIN symbols referenced in Table 2 and Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 79 This table provides the MII transmit AC timing specifications. This figure shows the MII transmit AC timing diagram. Figure 15. MII transmit AC timing diagram This table provides the MII receive AC timing specifications. Table 34. MII transmit AC timing specifications For recommended operating conditions, see Table 3. Table 35. MII Receive AC timing specifications For recommended operating conditions, see Table 3. Note: The frequency of RX_CLK should not exceed frequency of GTX_CLK125 by more than 300ppm.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 This figure provides the AC test load for eTSEC. Figure 16. eTSEC AC test load This figure shows the MII receive AC timing diagram. Figure 17. MII Receive AC timing diagram

2.12.2.3 RGMII AC timing specifications

This table presents the RGMII AC timing specifications. Table 36. RGMII AC timing specifications For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 81 This figure shows the RGMII AC timing and multiplexing diagrams. Figure 18. RGMII AC timing and multiplexing diagrams

2.12.3 Ethernet management interface

controlled by the MDIO controller associated with Frame Manager 1 10GMAC-0.

1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII timing.

representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).

1. The tSKRGT_RX specification implies that PC board design requires clocks to be routed such that an additional trace delay of

inside their chip. If so, additional PCB delay is probably not needed.

1. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
2. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
3. The frequency of RX_CLK should not exceed frequency of GTX_CLK125 by more than 300ppm.

Table 36. RGMII AC timing specifications (continued) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

2.12.3.1 Ethernet management interf ace 1 DC electrical characteristics

The Ethernet management interface 1 is defined to operate at a supply voltage of 3.3 V . The DC electrical characteristics for the Ethernet management interface is provided in this table. The Ethernet management interface 1 is defined to operate at a supply voltage of 3.3 V . The DC electrical characteristics for the Ethernet management interface 1 is provided in Table 37.

2.12.3.2 Ethernet management interf ace 2 DC electrical characteristics

Ethernet management interface 2 pins function as open drain I/Os. The interface conforms to 1.2 V nominal voltage levels. LVDD must be powered to use this interface. The DC electrical characteristics for EMI2_MDIO and EMI2_MDC are provided in this section. Table 37. Ethernet management Interface 1 DC electrical characteristics (LVDD = 3.3 V) For recommended operating conditions, see Table 3.

1. The symbol V IN, in this case, represents the LVIN symbol referenced in Table 2 and Table 3.
2. The min V IL and max VIH values are based on the respective LVIN values found in Table 3.

Table 38. Ethernet management interface 1 DC electrical characteristics (LVDD = 2.5 V) For recommended operating conditions, see Table 3.

1. The min V ILand max VIH values are based on the respective min and max LVIN values found in Table 3.
2. The symbol LV IN, in this case, represents the LVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”

Table 39. Ethernet management interface 2 DC electrical characteristics (1.2 V) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 83

2.12.3.3 Ethernet management in terface 1 AC timing specifications

This table provides the Ethernet management interface 1 AC timing specifications.

2.12.3.4 Ethernet management interface 2 AC electrical characteristics

This table provides the Ethernet management interface 2 AC timing specifications. Output low voltage (IOL = 100 μA) V OL —0 . 2 V — Output low current (VOL = 0.2 V) I OL 4— m A — Input capacitance C IN —1 0 p F — Table 40. Ethernet management interface 1 AC timing specifications For recommended operating conditions, see Table 3.

1. The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

1. This parameter is dependent on the platform clock frequency (MIIMCFG [MgmtClk] field determines the clock frequency of
2. This parameter is dependent on the frame manager clock frequency. The delay is equal to 16 frame manager clock periods

manager clock is 400 MHz, the min/max delay is 40 ns ± 6 ns.

1. t plb_clk is the frame manager clock period.

Table 41. Ethernet management interface 2 AC timing specifications For recommended operating conditions, see Table 3. Table 39. Ethernet management interface 2 DC electrical characteristics (1.2 V) (continued) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 This figure shows the Ethernet management interface timing diagram. Figure 19. Ethernet management interface timing diagram This section discusses the electrical characteristics for the eTSEC IEEE Std 1588 interfaces. This table shows eTSEC IEEE Std 1588 DC electrical characteristics when operating at LVDD = 3.3 V supply.

1. The symbols used for timing specif ications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time.

1. This parameter is dependent on the frame manager cloc k frequency (MIIMCFG [MgmtClk] field determines the clock

frequency of the MgmtClk Clock EC_MDC).

1. This parameter is dependent on the management data clock frequency, fMDC. The delay is equal to 0.5 management data

clock period ±6 ns. For example, with a management data clock of 2.5 MHz, the min/max delay is 200 ns ± 6 ns. Table 42. eTSEC IEEE 1588 DC electrical characteristics (LVDD = 3.3 V) For recommended operating conditions, see Table 3. Table 41. Ethernet management interface 2 AC timing specifications (continued) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 85 2.12.4.2 eTSEC IEEE Std 1588 AC specifications This table provides the IEEE 1588 AC timing specifications. Input low current (LVDD = Max, VIN = 0.5 V) I IL –600 — μA1 Output high voltage (LVDD = Min, IOH = –1.0 mA) V OH 2.4 — V — Output low voltage (LVDD = Min, IOL = 1.0 mA) V OL —0 . 4 V — Note: 1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Table 2 and Table 3. 2. The min VIL and max VIH values are based on the respective LVIN values found in Table 3. Table 43. eTSEC IEEE 1588 AC timing specifications For recommended operating conditions, see Table 3. Processor Reference Manual for a description of TMR_CTRL registers.

1. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For

example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK be 2800, 280, and 56 ns, respectively.

1. It needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the QorIQ Integrated

Processor Reference Manual for a description of TMR_CTRL registers. Table 42. eTSEC IEEE 1588 DC electrical characteristics (LVDD = 3.3 V) (continued) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 This figure shows the data and command output AC timing diagram. Figure 20. eTSEC IEEE 1588 output AC timing This figure shows the data and command input AC timing diagram. Figure 21. eTSEC IEEE 1588 input AC timing

2.13 USB

This section provides the AC and DC electrical specifications for the USB interface. is counted starting at the falling edge.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 87

2.13.1 USB DC electrical characteristics

This table provides the DC electrical characteristics for the USB interface at USB_VDD_3P3 = 3.3 V .

2.13.2 USB AC electrical specifications

This table provides the USB clock input (USBn_CLKIN) AC timing specifications. This figure provides the USB AC test load. Figure 22. USB AC test load

2.14 Enhanced local bus interface (eLBC)

This section describes the DC and AC electrical specifications for the enhanced local bus interface. Table 44. USB DC electrical characteristics (USB_VDD_3P3 = 3.3 V) For recommended operating conditions, see Table 3.

1. The min VILand max VIH values are based on the respective min and max USB_VIN_3P3 values found in Table 3.
2. The symbol USB_VIN_3P3, in this case, represents the USB_VIN_3P3 symbol referenced in Section 2.1.2, “Recommended

Table 45. USBn_CLKIN AC timing specifications For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

2.14.1 Enhanced local bus DC electrical characteristics

This table provides the DC electrical characteristics for the enhanced local bus interface operating at BVDD = 3.3 V . This table provides the DC electrical characteristics for the enhanced local bus interface operating at BVDD = 2.5 V . This table provides the DC electrical characteristics for the enhanced local bus interface operating at BVDD = 1.8 V . Table 46. Enhanced local bus DC electrical characteristics (BVDD = 3.3 V) For recommended operating conditions, see Table 3.

1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”

Table 47. Enhanced local bus DC electrical characteristics (BVDD = 2.5 V) For recommended operating conditions, see Table 3.

1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”

Table 48. Enhanced local bus DC electrical characteristics (BVDD = 1.8 V) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 89

2.14.2 Enhanced local bus AC timing specifications

This section describes the AC timing specifications for the enhanced local bus interface.

2.14.2.1 Test condition

This figure provides the AC test load for the enhanced local bus. Figure 23. Enhanced local bus AC test load

2.14.2.2 Local bus AC timing specification

to the falling edge of LCLKs. This table describes the timing specifications of the local bus interface.

1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”

Table 49. Enhanced local bus timing specifications For recommended operating conditions, see Table 3. Table 48. Enhanced local bus DC electrical characteristics (BVDD = 1.8 V) (continued) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 (for LGTA/LUPWAIT/LFRB) tLBIVKL 6— n s — Input hold (for LGTA/LUPWAIT/LFRB) tLBIXKL 1— n s — Output delay (Except LALE) tLBKLOV —1 . 5 n s — Output hold (Except LALE) tLBKLOX -3.5 — ns 5 Local bus clock to output high impedance for LAD/LDP tLBKLOZ —2 n s 3 LALE output negation to LAD/LDP output transition (LATCH hold time) tLBONOT 2 platform clock cycles—1ns (LBCR[AHD]=1) —n s 4 4 platform clock cycles—1ns (LBCR[AHD]=0) Notes: 1. All signals are measured from BVDD/2 of rising/falling edge of LCLK to BVDD/2 of the signal in question. 2. Skew measured between different LCLKs at BVDD/2. 3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. tLBONOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBONOT is determined by LBCR[AHD]. The unit is the eLBC controller clock cycle, which is the internal clock that runs the local bus controller, not the external LCLK. LCLK cycle = eLBC controller clock cycle X LCRR[CLKDIV]. After power on reset, LBCR[AHD] defaults to 0 and eLBC runs at maximum hold time. 5. Output hold is negative. This means that output transition happens earlier than the falling edge of LCLK. Table 49. Enhanced local bus timing specifications (continued) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 This figure shows how the local bus AC timing diagram applies to GPCM. The same principle applies to UPM and FCM. Figure 25. GPCM Output timing diagram

2.15 Enhanced secure digital host controller (eSDHC)

This section describes the DC and AC electrical specifications for the eSDHC interface. This table provides the DC electrical characteristics for the eSDHC interface. Table 50. eSDHC interface DC electrical characteristics For recommended operating conditions, see Table 3. 1 taddr is programmable and determined by LCRR[EADC] and ORx[EAD]. 2 tarcs, tawcs, taoe, trc, toen, tawe, twc, twen are determined by ORx. See the applicable chip reference manual.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 93 2.15.2 eSDHC AC timing specifications This table provides the eSDHC AC timing specifications as defined in Figure 26 and Figure 27. Output low voltage V OL IOL = 100μA at CVDD min —0 . 1 2 5 × CVDD V— Output high voltage V OH IOH = –100 μA at CVDD min CVDD –0 . 2 — V 2 Output low voltage V OL IOL = 2 mA at CVDD min —0 . 3 V 2 Notes: 1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3. 2. Open drain mode for MMC cards only. Table 51. eSDHC AC timing specifications For recommended operating conditions, see Table 3.

1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state)
2. In full-speed mode, the clock frequency value can be 0–25 MHz for an SD card and 0–20 MHz for an MMC card. In high-speed

mode, the clock frequency value can be 0–50 MHz for an SD card and 0–52 MHz for an MMC card.

1. To satisfy setup timing, one way board routing delay between Host and Card, on SD_CLK, SD_CMD and SD_DATx should not

SD_CLK, SD_CMD and SD_DATx should not exceed 1.5 ns.

1. CCARD ≤ 10 pF , (1 card), and CL = CBUS + CHOST +C CARD ≤ 40 pF
2. The parameter values apply to both full speed and high speed modes.

Table 50. eSDHC interface DC electrical characteristics (continued) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 This figure provides the eSDHC clock input timing diagram. Figure 26. eSDHC clock input timing diagram This figure provides the data and command input/output timing diagram. Figure 27. eSDHC data and command input/output timing diagram referenced to clock This section describes the DC and AC electrical specifications for the multicore programmable interrupt controller.

2.16.1 MPIC DC specifications

This table provides the DC electrical characteristics for the MPIC interface. Table 52. MPIC DC electrical characteristics (OVDD = 3.3 V) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 95

2.16.2 MPIC AC timing specifications

This table provides the MPIC input and output AC timing specifications.

2.17 JTAG controller

This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface.

2.17.1 JTAG DC electrical characteristics

This table provides the JTAG DC electrical characteristics. Output low voltage (OVDD = min, IOL = 2 mA) V OL —0 . 4 V — Notes: 1. The min VILand max VIH values are based on the min and max OVIN respective values found in Table 3 2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Table 3 Table 53. MPIC Input AC timing specifications For recommended operating conditions, see Table 3.

1. MPIC inputs and outputs are asynchronous to any visible clock. MPIC outputs should be synchronized before use by any

Table 54. JTAG DC electrical characteristics (OVDD = 3.3 V) For recommended operating conditions, see Table 3.

1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. The symbol VIN, in this case, represents the OVIN symbol found in Table 3.

Table 52. MPIC DC electrical characteristics (OVDD = 3.3 V) (continued) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

2.17.2 JTAG AC timing specifications

This table provides the JTAG AC timing specifications as defined in Figure 28 through Figure 31. This figure provides the AC test load for TDO and the boundary-scan outputs of the device. Figure 28. AC test load for the JTAG interface Table 55. JTAG AC timing specifications For recommended operating conditions, see Table 3.

1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

1. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
2. All outputs are measured from the midpoint voltage of the falling edge of tTCLK to the midpoint of the signal in question. The

be added for trace lengths, vias, and connectors in the system.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 97 This figure provides the JTAG clock input timing diagram. Figure 29. JTAG clock input timing diagram This figure provides the TRST timing diagram. Figure 30. TRST timing diagram This figure provides the boundary-scan timing diagram. Figure 31. Boundary-scan timing diagram

2.18 I 2C

This section describes the DC and AC electrical characteristics for the I2C interface.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

2.18.1 I 2C DC electrical characteristics

This table provides the DC electrical characteristics for the I2C interfaces.

2.18.2 I 2C AC electrical specifications

This table provides the AC timing parameters for the I2C interfaces. Table 56. I2C DC electrical characteristics (OVDD = 3.3 V) For recommended operating conditions, see Table 3.

1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. Output voltage (open drain or open collector) condition = 3 mA sink current.
3. See the applicable chip reference manual for information about the digital filter used.
4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off.

Table 57. I2C AC timing specifications For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor100

2.19 GPIO

This section describes the DC and AC electrical characteristics for the GPIO interface.

2.19.1 GPIO DC electrical characteristics

This table provides the DC electrical characteristics for GPIO pins operating at 3.3 V . This table provides the DC electrical characteristics for GPIO pins operating at LVDD = 2.5 V . Table 58. GPIO DC electrical characteristics (LVDD or OVDD = 3.3 V) For recommended operating conditions, see Table 3.

1. The min VILand max VIH values are based on the min and max L/OVIN respective values found in Table 3.
2. The symbol VIN, in this case, represents the L/OVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”

Table 59. GPIO DC electrical characteristics (LVDD = 2.5 V) For recommended operating conditions, see Table 3.

1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
2. The symbol VIN, in this case, represents the LVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 101

2.19.2 GPIO AC timing specifications

This table provides the GPIO input and output AC timing specifications. This figure provides the AC test load for the GPIO. Figure 34. GPIO AC test load

2.20 High-speed serial interfaces (HSSI)

SerDes interface can be used for PCI Express, XAUI, Aurora and SGMII data transfers. clocks. The SerDes data lane’s transmitter and receiver reference circuits are also shown.

2.20.1 Signal terms definition

and specification of differential signals. Table 60. GPIO Input AC timing specifications For recommended operating conditions, see Table 3.

1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any

external synchronous logic. GPIO inputs are required to be valid for at least tPIWID to ensure proper operation.

1. Trust inputs are asynchronous to any visible clock. Trust inputs are required to be valid for at least tTIWID to ensure proper

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor102 This figure shows how the signals are defined. For illustration purposes only, one SerDes lane is used in the description. This figure shows the waveform for either a transmitter output (SD_TXn and SD_TXn) or a receiver input (SD_RXn and SD_RXn). Each signal swings between A volts and B volts where A > B. Figure 35. Differential voltage definitions for transmitter or receiver is defined as the differential peak voltage, VDIFFp = |A – B| volts. calculated as VTX-DIFFp-p = 2 × |VOD|.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 103 waveform is not referenced to ground. See Figure 40, “Differential measurement points for rise and fall time,” as an example for differential waveform. Common Mode Voltage, Vcm The common mode voltage is equal to half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. In this example, for SerDes output, V cm_out =( VSD_TXn +V SD_TXn) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two complementary output voltages within a differential pair. In a system, the common mode voltage may often differ from one component’s output to the other’s input. It may be different between the receiver input and driver output circuits within the same component. It is also referred to as the DC offset on some occasions. To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a common mode voltage of 2.25 V and outputs, TD and TD . If these outputs have a swing from 2.0 V to 2.5 V , the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because the differential signaling environment is fully symmetrical in this example, the transmitter output’s differential swing (VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500 mV and –500 mV . In other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV . The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.

2.20.2 SerDes reference clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding SerDes lanes. The SerDes reference clocks inputs are SD_REF_CLK1 and SD_REF_CLK1 for SerDes bank1, SD_REF_CLK2 and SD_REF_CLK2 for SerDes bank2, SD_REF_CLK3 and SD_REF_CLK3 for SerDes bank3, and SD_REF_CLK4 and SD_REF_CLK4 for SerDes bank4. SerDes banks 1–4 may be used for various combinations of the following IP blocks based on the RCW Configuration field SRDS_PRTCL:

• SerDes bank 1: PEX1/2/3, SGMII (1.25 Gbps only) or Aurora.
• SerDes bank 2: SGMII (1.25 or 3.125 GBaud) or XAUI.
• SerDes bank 3: SATA, or XAUI.
• SerDes bank 4: SATA The following sections describe the SerDes reference clock requirements and provide application information.

2.20.2.1 SerDes reference cl ock receiver characteristics

This figure shows a receiver reference diagram of the SerDes reference clocks. Figure 36. Receiver of SerDes reference clocks

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor104 The characteristics of the clock signals are as follows:

• The SerDes transceivers core power supply voltage requirements (SV DD) are as specified in Section 2.1.2, “Recommended operating conditions.”
• The SerDes reference clock receiver refe rence circuit structure is as follows: —T h e SD_REF_CLKn and SD_REF_CLKn are internally AC-coupled differential inputs as shown in Figure 36. Each differential clock input (SD_REF_CLKn or SD_REF_CLKn) has on-chip 50-Ω termination to SGND followed by on-chip AC-coupling. — The external reference clock driver mu st be able to drive this termination. — The SerDes reference clock input can be either differ ential or single-ended. See the differential mode and single-ended mode descriptions below for detailed requirements.
• The maximum average cu rrent requirement also determines the common mode voltage range. — When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input is AC-coupled on-chip. — This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V ÷ 50 = 8 mA) while the minimum common mode input level is 0.1 V above SGND. For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode voltage at 400 mV . — If the device driving the SD_REF_CLK n and SD_REF_CLK n inputs cannot drive 50 Ω to SGND DC or the drive strength of the clock driver chip exceeds the maximum input current limitations, it must be AC-coupled off-chip.
• The input amplitude requirement is described in detail in the following sections.

2.20.2.2 DC-level requirement for SerDes reference clocks

The DC level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs, as described below:

• Differential Mode — The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing of less than 800 mV and greater than 200 mV . This requirement is the same for both external DC-coupled or AC-coupled connection. — For an external DC-coupled connection, as described in Section 2.20.2.1, “SerDes reference clock receiver characteristics,” the maximum average current requirements sets the requirement for average voltage (common mode voltage) as between 100 mV and 400 mV . Figure 37 shows the SerDes reference clock input requirement for DC-coupled connection scheme.

Figure 37. Differential reference clock input DC requirements (external DC-coupled)

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor106

2.20.2.3 AC requirements for SerDes reference clocks

This table lists AC requirements for the PCI Express, SGMII, Serial RapidIO and Aurora SerDes reference clocks to be guaranteed by the customer’s application design. Figure 40. Differential measurement points for rise and fall time Table 61. SD_REF_CLKn and SD_REF_CLKn input clock requirements (SVDD = 1.0 V) For recommended operating conditions, see Table 3.

1. Caution: Only 100 and 125 have been tested. In-between values not work correctly with the rest of the system.
2. Limits from PCI Express CEM Rev 2.0
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLKn minus SD_REF_CLKn). The

centered on the differential zero crossing. See Figure 40.

1. Measurement taken from differential waveform
2. Measurement taken from single-ended waveform
3. Matching applies to rising edge for SD_REF_CLKn and falling edge rate for SD_REF_CLKn. It is measured using a 200 mV

exceed 20% of the slowest edge rate. See Figure 41.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 107 Figure 41. Single-ended measurement points for rise and fall time matching

2.20.2.4 Spread-spectrum clock

results, a source without significant unintended modulation should be used.

2.20.3 SerDes transmitter and receiver reference circuits

This figure shows the reference circuits for SerDes data lane’s transmitter and receiver. Figure 42. SerDes transmitter and receiver reference circuits

• Section 2.20.4, “PCI Express”
• Section 2.20.5, “XAUI”
• Section 2.20.6, “Aurora”
• Section 2.20.7, “Serial ATA (SATA)
• Section 2.20.8, “SGMII interface” Note that external AC-coupling capacitor is required for the above serial transmission protocols per the protocol’s standard requirements. SDn_REF_CLK SDn_REF_CLKSDn_REF_CLK SDn_REF_CLKSDn_REF_CLK VCROSS MEDIAN VCROSS MEDIAN VCROSS MEDIAN + 100 mV VCROSS MEDIAN – 100 mV TFALL TRISE 50 Ω 50 Ω ReceiverTransmitter SD_TXn SD_TXn SD_RXn SD_RXn 50 Ω 50 Ω

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor108

2.20.4 PCI Express

This section describes the clocking dependencies, DC and AC electrical specifications for the PCI Express bus.

2.20.4.1 Clocking dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.

2.20.4.2 PCI Express clocking requirements for SD_REF_CLK n and

SD_REF_CLKn SerDes banks 1–2 (SD_REF_CLK[1:2] and SD_REF_CLK[1:2]) may be used for various SerDes PCI Express configurations based on the RCW Configuration field SRDS_PRTCL. PCI Express is not supported on SerDes bank 3. For more information on these specifications, see Section 2.20.2, “SerDes reference clocks.”

2.20.4.3 PCI Express DC physical layer specifications

This section contains the DC specifications for the physical layer of PCI Express on this device.

2.20.4.3.1 PCI Express DC physica l layer transmitter specifications

This section discusses the PCI Express DC physical layer transmitter specifications for 2.5 GT/s and 5 GT/s. This table defines the PCI Express 2.0 (2.5 GT/s) DC specifications for the differential output at all transmitters. The parameters are specified at the component pins. Table 62. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC specifications For recommended operating conditions, see Table 3. VTX-DIFFp-p 800 — 1200 mV V TX-DIFFp-p = 2 × |VTX-D+ – VTX-D-| See Note 1.

1. Measured at the package pins with a test load of 50Ω to GND on each pin.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 109 This table defines the PCI Express 2.0 (5 GT/s) DC specifications for the differential output at all transmitters. The parameters are specified at the component pins.

2.20.4.4 PCI Express DC physical layer receiver specifications

This section discusses the PCI Express DC physical layer receiver specifications 2.5 GT/s, and 5 GT/s. This table defines the DC specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all receivers. The parameters are specified at the component pins. Table 63. PCI Express 2.0 (5 GT/s) differential transmitter output DC specifications For recommended operating conditions, see Table 3. VTX-DIFFp-p 800 — 1200 mV V TX-DIFFp-p = 2 × |VTX-D+ – VTX-D-| See Note 1. VTX-DIFFp-p_low 400 500 1200 mV V TX-DIFFp-p = 2 × |VTX-D+ – VTX-D-| See Note 1.

1. Measured at the package pins with a test load of 50Ω to GND on each pin.

For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor110 This table defines the DC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers. The parameters are specified at the component pins. Powered down DC input impedance Z RX-HIGH-IMP-DC 50 k — — Ω Required receiver D+ as well as D– DC Impedance when the receiver terminations do not have power. See Note 3. Electrical idle detect threshold V RX-IDLE-DET -DIFFp-p 65 — 175 mV V RX-IDLE-DET -DIFFp-p = Measured at the package pins of the receiver Notes: 1. Measured at the package pins with a test load of 50 Ω to GND on each pin. 2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port. 3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the receiver ground. Table 65. PCI Express 2.0 (5 GT/s) differential receiver input DC specifications (XVDD = 1 . 5V o r 1 . 8V ) For recommended operating conditions, see Table 3. tolerance). See Notes 1 and 2. terminations do not have power.

1. Measured at the package pins with a test load of 50Ω to GND on each pin.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)

there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.

1. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps

measured at 300 mV above the receiver ground.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 111

2.20.4.5 PCI Express AC physical layer specifications

This section contains the DC specifications for the physical layer of PCI Express on this device.

2.20.4.5.1 PCI Express AC physica l layer transmitter specifications

This section discusses the PCI Express AC physical layer transmitter specifications 2.5 GT/s, and 5 GT/s. This table defines the PCI Express 2.0 (2.5 GT/s) AC specifications for the differential output at all transmitters. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter. Table 66. PCI Express 2.0 (2.5 GT/s) differential transmitter Output AC specifications For recommended operating conditions, see Table 3. as TTX-MAX-JITTER = 1 – TTX-EYE = 0.25 UI. jitter. Includes device random jitter at 10-12. used for calculating the transmitter UI. within the transmitting component itself.

1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage test load as shown in Figure 43 and measured over any 250

consecutive transmitter UIs. approximately equal as opposed to the averaged time value.

1. The chip’s SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor112 This table defines the PCI Express 2.0 (5 GT/s) AC specifications for the differential output at all transmitters. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter.

2.20.4.5.2 PCI Express AC physi cal layer receiver specifications

This section discusses the PCI Express AC physical layer receiver specifications 2.5 GT/s, and 5 GT/s. Table 67. PCI Express 2.0 (5 GT/s) differential transmitter Output AC specifications For recommended operating conditions, see Table 3. TX-MAX-JITTER =1–T TX-EYE =0 . 2 5 U I . or within the transmitting component itself.

1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage test load as shown in Figure 43 and measured over any 250

consecutive transmitter UIs. approximately equal as opposed to the averaged time value.

1. The chip’s SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 113 This table defines the AC specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all receivers. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter. Table 68. PCI Express 2.0 (2.5 GT/s) differential receiver Input AC specifications For recommended operating conditions, see Table 3. RX-MAX-JITTER =1 – TRX-EYE= 0.6 UI.

1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 43 should be used

reference clock, the transmitter UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram. UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram.

1. It is recommended that the recovered transmitter UI is calculated using all edges in the 3500 consecutive UI interval with a fit

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor114 This table defines the AC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers (RXs). The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter.

2.20.4.6 Test and measurement load

The AC timing and voltage parameters must be verified at the measurement point. The package pins of the device must be connected to the test/measurement load within 0.2 inches of that load, as shown in Figure 43. NOTE The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from D+ and D– not being exactly matched in length at the package pin boundary. If the vendor does not explicitly state where the measurement point is located, the measurement point is assumed to be the D+ and D– package pins. Figure 43. Test/Measurement load Table 69. PCI Express 2.0 (5 GT/s) differential receiver Input AC specifications For recommended operating conditions, see Table 3.

1. No test load is necessarily associated with this value.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 115

2.20.5 XAUI

This section describes the DC and AC electrical specifications for the XAUI bus.

2.20.5.1 XAUI DC electrical characteristics

This section discusses the XAUI DC electrical characteristics for the clocking signals, transmitter, and receiver.

2.20.5.1.1 DC requirement s for XAUI SD_REF_CLKn and SD_REF_CLKn

Only SerDes banks 2–3 (SD_REF_CLK[2:3] and SD_REF_CLK[2:3]) may be used for various SerDes XAUI configurations based on the RCW Configuration field SRDS_PRTCL. XAUI is not supported on SerDes bank 1. For more information on these specifications, see Section 2.20.2.2, “DC-level requirement for SerDes reference clocks.”

2.20.5.1.2 XAUI transmitter DC electrical characteristics

This table defines the XAUI transmitter DC electrical characteristics.

2.20.5.1.3 XAUI receiver DC electrical characteristics

This table defines the XAUI receiver DC electrical characteristics.

2.20.5.2 XAUI AC timing specifications

This section discusses the XAUI AC timing specifications for the clocking signals, transmitter, and receiver. Table 70. XAUI transmitter DC electrical characteristics (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3.

1. Absolute output voltage limit

Table 71. XAUI receiver DC timing specifications (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3.

1. Measured at the receiver.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor116

2.20.5.2.1 AC requirement s for XAUI SD_REF_CLKn and SD_REF_CLKn

This table specifies AC requirements for SD_REF_CLKn and SD_REF_CLKn, where n = [2:3]. Only SerDes banks 2–3 may be used for various SerDes XAUI configurations based on the RCW Configuration field SRDS_PRTCL. XAUI is not supported on SerDes bank 1.

2.20.5.2.2 XAUI transmitter AC timing specifications

This table defines the XAUI transmitter AC timing specifications. RefClk jitter is not included. Table 72. XAUI AC SD_REF_CLKn and SD_REF_CLKn input clock requirements (SVDD = 1.0 V) For recommended operating conditions, see Table 3.

1. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLKn – SD_REF_CLKn). The

centered on the differential zero crossing. See Figure 40.

1. Measurement taken from differential waveform
2. Measurement taken from single-ended waveform
3. Matching applies to rising edge for SD_REF_CLKn and falling edge rate for SD_REF_CLK

exceed 20% of the slowest edge rate. See Figure 41. Table 73. XAUI transmitter AC timing specifications For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 117

2.20.5.2.3 XAUI receiver AC timing specifications

This table defines the receiver AC specifications for XAUI. RefClk jitter is not included. This figure shows the single-frequency sinusoidal jitter limits. Figure 44. Single-Frequency Sinusoidal Jitter Limits Table 74. XAUI receiver AC timing specifications For recommended operating conditions, see Table 3.

1. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The

is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.

8.5 UI p-p

0.10 UI p-p

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor118

2.20.6 Aurora

This section describes the Aurora clocking requirements and AC and DC electrical characteristics.

2.20.6.1 Aurora DC electrical characteristics

This section describes the DC electrical characteristics for Aurora.

2.20.6.1.1 Aurora DC clocking requirements for SD_REF_CLKn and SD_REF_CLKn

Only SerDes bank 1 (SD_REF_CLK1 and SD_REF_CLK1) may be used for SerDes Aurora configurations based on the RCW Configuration field SRDS_PRTCL. Aurora is not supported on SerDes banks 2-3. For more information on these specifications, see Section 2.20.2, “SerDes reference clocks.”

2.20.6.1.2 Aurora transmitter DC electrical characteristics

This table defines the Aurora transmitter DC electrical characteristics.

2.20.6.1.3 Aurora receiver DC electrical characteristics

This table defines the Aurora receiver DC electrical characteristics for Aurora.

2.20.6.2 Aurora AC timing specifications

This section describes the AC timing specifications for Aurora.

2.20.6.2.1 Aurora AC clocking requirements for SD_REF_CLKn and SD_REF_CLKn

Only SerDes bank 1 (SD_REF_CLK1 and SD_REF_CLK1) may be used for SerDes Aurora configurations based on the RCW Configuration field SRDS_PRTCL. Aurora is not supported on SerDes banks 2–3. Please note that the XAUI clock requirements for SD_REF_CLKn and SD_REF_CLKn are intended to be used within the “AC requirements for SATA REF_CLK.” Table 75. Aurora transmitter DC electrical characteristics (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3. Table 76. Aurora receiver DC electrical characteristics (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 119

2.20.6.2.2 Aurora transmitter AC timing specifications

This table defines the Aurora transmitter AC timing specifications. RefClk jitter is not included.

2.20.6.2.3 Aurora receive r AC timing specifications

This table defines the Aurora receiver AC timing specifications. RefClk jitter is not included.

2.20.7 Serial ATA (SATA)

This section describes the DC and AC electrical specifications for the serial ATA (SATA) interface.

2.20.7.1 SATA DC electrical characteristics

This section describes the DC electrical characteristics for SATA. Table 77. Aurora transmitter AC timing specifications For recommended operating conditions, see Table 3. Table 78. Aurora receiver AC timing specifications For recommended operating conditions, see Table 3.

1. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor120

2.20.7.1.1 SATA DC transmitter Output Characteristics

This table provides the DC differential transmitter output DC characteristics for the transmission. This table provides the differential transmitter output DC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s transmission.

2.20.7.1.2 SATA DC receiver Input Characteristics

This table provides the Gen1i or 1.5 Gbits/s differential receiver input DC characteristics for the SATA interface. Table 79. Gen1i/1.5G transmitter DC specifications (XVDD = 1 . 5V o r 1 . 8V ) For recommended operating conditions, see Table 3. Table 80. Gen 2i/3G transmitter DC specifications (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3. Table 81. Gen1i/1.5 G receiver Input DC specifications (XVDD = 1 . 5V o r 1 . 8V ) For recommended operating conditions, see Table 3.

1. Voltage relative to common of either signal comprising a differential pair

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 121 This table provides the Gen2i or 3 Gbits/s differential receiver input DC characteristics for the SATA interface.

2.20.7.2 SATA AC timing specifications

This section discusses the SATA AC timing specifications.

2.20.7.2.1 AC requirements for SATA REF_CLK

The AC requirements for the SATA reference clock are listed in this table to be guaranteed by the customer’s application design. Table 82. Gen2i/3 G receiver Input DC specifications (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3.

1. Voltage relative to common of either signal comprising a differential pair

Table 83. SATA reference clock input requirements For recommended operating conditions, see Table 3.

1. Caution: Only 100, and 125 MHz have been tested. In-between values do not work correctly with the rest of the system.
2. In a frequency band from 150 kHz to 15 MHz at BER of 10-12
3. Total peak-to-peak deterministic jitter should be less than or equal to 50 ps.
4. Measurement taken from differential waveform

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor122 This figure shows the reference clock timing waveform. Figure 45. Reference clock timing waveform

2.20.7.3 AC transmitter Output Characteristics

transmission. The AC timing specifications do not include RefClk jitter. transmission. The AC timing specifications do not include RefClk jitter. Table 84. Gen1i/1.5 G transmitter AC specifications For recommended operating conditions, see Table 3.

1. Measured at transmitter output pins peak to peak phase variation, random data pattern

Table 85. Gen 2i/3 G transmitter AC specifications For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 123

2.20.7.4 AC differential receiver Input characteristics

This table provides the Gen1i or 1.5 Gbits/s differential receiver input AC characteristics for the SATA interface. The AC timing specifications do not include RefClk jitter. This table provides the differential receiver input AC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s transmission. The AC timing specifications do not include RefClk jitter. Deterministic jitter, fC3dB =f BAUD ÷ 10 USATA_TXDJfB/10 — — 0.17 UI p-p 1 Deterministic jitter, fC3dB =f BAUD ÷ 500 USATA_TXDJfB/500 — — 0.19 UI p-p 1 Deterministic jitter, fC3dB =f BAUD ÷ 1667 USATA_TXDJfB/1667 — — 0.35 UI p-p 1 Note: 1. Measured at transmitter output pins peak-to-peak phase variation, random data pattern Table 86. Gen 1i/1.5G receiver AC specifications For recommended operating conditions, see Table 3. Table 87. Gen 2i/3G receiver AC specifications For recommended operating conditions, see Table 3. Table 85. Gen 2i/3 G transmitter AC specifications (continued) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor124

2.20.8 SGMII interface

Each SGMII port features a 4-wire AC-coupled serial link from the SerDes interface of the chip, as shown in Figure 46, where CTX is the external (on board) AC-coupled capacitor. Each output pin of the SerDes transmitter differential pair features 50-Ω output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to XGND. The reference circuit of the SerDes transmitter and receiver is shown in Figure 42.

2.20.8.0.1 SGMII clocking re quirements for SD_REF_CLKn and SD_REF_CLKn

When operating in SGMII mode, the EC_GTX_CLK125 clock is not required for this port. Instead, a SerDes reference clock is required on SD_REF_CLK[1:3] and SD_REF_CLK[1:3] pins. SerDes banks 1-3 may be used for SerDes SGMII configurations based on the RCW Configuration field SRDS_PRTCL. For more information on these specifications, see Section 2.20.2, “SerDes reference clocks.”

2.20.8.1 SGMII DC elect rical characteristics

This section discusses the electrical characteristics for the SGMII interface.

2.20.8.1.1 SGMII transm it DC timing specifications

This table describe the SGMII SerDes transmitter and receiver AC-coupled DC electrical characteristics for 1.25 GBaud. Transmitter DC characteristics are measured at the transmitter outputs (SD_TXn and SD_TXn) as shown in Figure 47. Deterministic jitter, fC3dB =f BAUD ÷ 10 U SATA_TXDJfB/10 — — 0.35 UI p-p 1 Deterministic jitter, fC3dB =f BAUD ÷ 500 U SATA_TXDJfB/500 — — 0.42 UI p-p 1 Deterministic jitter, fC3dB =f BAUD ÷ 1667 U SATA_TXDJfB/1667 — — 0.35 UI p-p 1 Note: 1. Measured at receiver Table 88. SGMII DC transmitter electrical characteristics (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3. Table 87. Gen 2i/3G receiver AC specifications (continued) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 125 Output differential voltage2, 3, 4 (XVDD-Typ at 1.5 V and 1.8 V) |VOD| 320 500.0 725.0 mV B(1-3)TECR(lane)0[AMP_RED] =0b000000 293.8 459.0 665.6 B(1-3)TECR(lane)0[AMP_RED] =0b000010 266.9 417.0 604.7 B(1-3)TECR(lane)0[AMP_RED] =0b000101 240.6 376.0 545.2 B(1-3)TECR(lane)0[AMP_RED] =0b001000 213.1 333.0 482.9 B(1-3)TECR(lane)0[AMP_RED] =0b001100 186.9 292.0 423.4 B(1-3)TECR(lane)0[AMP_RED] =0b001111 160.0 250.0 362.5 B(1-3)TECR(lane)0[AMP_RED] =0b010011 Output impedance (single-ended) R O 40 50 60 Ω — Notes: 1. This does not align to DC-coupled SGMII. 2. |VOD| = |VSD_TXn– VSD_TXn|. |VOD| is also referred to as output differential peak voltage. VTX-DIFFp-p = 2*|VOD|. 3. Example amplitude reduction setting for SGMII on SerDes bank 1 lane E: B1TECRE0[AMP_RED] = 0b000010 for an output differential voltage of 459 mV typical. 4. The |VOD| value shown in the Typ column is based on the condition of XVDD_SRDSn-Typ = 1.5 V or 1.8 V, no common mode offset variation. SerDes transmitter is terminated with 100-Ω differential load between SD_TXn and SD_TXn. Table 88. SGMII DC transmitter electrical characteristics (XVDD = 1.5 V or 1.8 V) (continued) For recommended operating conditions, see Table 3.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 127 This table defines the SGMII 2.5x transmitter DC electrical characteristics for 3.125 GBaud.

2.20.8.1.2 SGMII DC receiver electrical characteristics

This table lists the SGMII DC receiver electrical characteristics for 1.25 GBaud. Source synchronous clocking is not supported. Clock is recovered from the data. This table defines the SGMII 2.5x receiver DC electrical characteristics for 3.125 GBaud.

2.20.8.2 SGMII AC timing specifications

This section discusses the AC timing specifications for the SGMII interface. Table 89. SGMII 2.5x transmitter DC electrical characteristics (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3.

1. Absolute output voltage limit

Table 90. SGMII DC receiver electrical characteristics (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3.

1. Input must be externally AC coupled.
2. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.
3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. See

layer receiver specifications,” for further explanation.

1. The REIDL_CTL shown in the table refers to the chip’s SerDes control register B(1-3)GCR(lane)1[REIDL_CTL] bit field.

Table 91. SGMII 2.5x receiver DC timing specifications (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3.

1. Measured at the receiver.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor128

2.20.8.2.1 SGMII transm it AC timing specifications

This table provides the SGMII transmit AC timing specifications. A source synchronous clock is not supported. The AC timing specifications do not include RefClk jitter.

2.20.8.2.2 SGMII AC measurement details

Transmitter and receiver AC characteristics are measured at the transmitter outputs (SD_TXn and SD_TXn) or at the receiver inputs (SD_RXn and SD_RXn) respectively, as depicted in this figure. Figure 48. SGMII AC test/measurement load

2.20.8.2.3 SGMII receiver AC timing specification

This table provides the SGMII receiver AC timing specifications. The AC timing specifications do not include RefClk jitter. Source synchronous clocking is not supported. Clock is recovered from the data. Table 92. SGMII transmit AC timing specifications For recommended operating conditions, see Table 3.

1. See Figure 44 for single frequency sinusoidal jitter measurements.
2. The external AC coupling capacitor is required. It is recommended that it be placed near the device transmitter outputs.

Table 93. SGMII receive AC timing specifications For recommended operating conditions, see Table 3.

The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded region of Figure 44.

3 Hardware design considerations

3.1 System clocking

This section describes the PLL configuration of the chip.

• There are two selectable core cluster PLLs which generate a core clock from the externally supplied SYSCLK input. Core complex 0–1 can select from either CC1 PLL or CC2 PLL. The frequency ratio between the core cluster PLLs and SYSCLK is selected using the configuration bits as described in Section 3.1.3, “e5500-64 core complex/ FMan to SYSCLK PLL ratio.” The frequency for each core complex 0–1 is selected using the configuration bits as described in Table 97.
• The platform PLL generates the platfo rm clock from the externally supplied SYSCLK input. The frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in Section 3.1.2, “Platform to SYSCLK PLL ratio.”
• The DDR block PLL generates the DDR clock from the exte rnally supplied SYSCLK input (asynchronous mode) or from the platform clock (synchronous mode). The frequency ratio is selected using the Memory Controller Complex PLL multiplier/ratio configuration bits as described in Section 3.1.5, “DDR controller PLL ratios.”
• The FMan PLL generates the FMan clock from the platfo rm PLL when operating synchronously, or from CC3 PLL when operating asynchronously. Described in Section 3.1.8, “Frame Manager (FMan) clock select.”
• Each of the four SerDes blocks has a PLL which generate a core clock from their respective externally supplied SD_REF_CLKn/SD_REF_CLKn inputs. The frequency ratio is selected using the SerDes PLL ratio configuration bits as described in Section 3.1.6, “Frequency options.” Bit error ratio BER — — 10 -12 —— Unit Interval: 1.25 GBaud UI 800 – 100 ppm 800 800 + 100 ppm ps 1 Unit Interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps 1 Notes: 1. Measured at receiver 2. See the RapidIOTM 1×/4× LP Serial Physical Layer Specification for interpretation of jitter specifications. 3. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 44. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

Table 93. SGMII receive AC timing specifications (continued) For recommended operating conditions, see Table 3.

3.1.1 Clock ranges

This table provides the clocking specifications for the processor core, platform, memory, and local bus. Table 94. Processor clocking specifications

1. Caution: The platform clock to SYSCLK ratio and core to SYSCLK ratio settings must be chosen such that the resulting
2. The memory bus clock speed is half the DDR3/DDR3L data rate. DDR3/DDR3L memory bus clock frequency is limited to min
3. The local bus clock speed on LCLK[0:1] is determined by the platform clock divided by the local bus ratio programmed in

LCRR[CLKDIV]. See the applicable chip reference manual for more information. allowable core frequency of 667MHz for PLL/2.

1. In synchronous mode, the memory bus clock speed is half the platform clock frequency. In other words, the DDR data rate is
2. In asynchronous mode, the memory bus clock speed is dictated by its own PLL.
3. The minimum frequencies for the FMan to support the specified interfaces are: 300 MHz for a 1G interface, 450 MHz for a

frequency range is the same as the Core PLL frequency range.

3.1.2 Platform to SYSCLK PLL ratio

The allowed platform clock to SYSCLK ratios are shown in this table. because the platform frequency must equal the DDR data rate. In asynchronous DDR mode, the memory bus clock frequency is decoupled from the platform bus frequency. CCn_PLL_CFG = 0b10, for setting targeting below 1 GHz CCn_PLL_CFG=0b00. This table lists the supported core complex/ FMan to SYSCLK ratios. Table 95. Platform to SYSCLK PLL ratios Table 96. Core complex/ FMan PLL to SYSCLK ratios

3.1.4 Core complex PLL select

3.1.5 DDR controller PLL ratios

configuration. Both DDR controllers operate at the same frequency configuration. (asynchronous mode) or from the platform clock (synchronous mode). MEM_PLL_CFG[0:1] is listed in Table 99. mode, and b’1 for synchronous mode. mode, and b’1 for synchronous mode. The RCW Configuration field DDR_RSV0 (bit 234) must be set to b’0 for all ratios. Table 97. Core complex [0,1] PLL select

0000 CC1 PLL /1

0001 CC1 PLL /2

0100 CC2 PLL /1

0101 CC2 PLL/2

Table 98. Asynchronous DDR clock ratio

the binary value of the RCW Configuration field MEM_PLL_RAT[10:14].

1. RCW[MEM_PLL_CFG] is set dependant on the DDR clock ratio used. See Table 99 for

valid setttings of DDR clock ratio and MEM_PLL_CFG. Table 99. Supported DDR ratios and RCW MEM_PLL_CFG settings

6 Reserved 800/11 900/11 3

1. For MEM SYSYCLK RATIO = 8, MEM_PLL_CFG changes from 10 to 01 when SYSCLK is
2. For MEM SYSYCLK RATIO = 9, MEM_PLL_CFG changes from 10 to 01 when SYSCLK is
3. Maximum SYSCLK is 161.2MHz when MEM:SYSCLK ratio = 6

Table 98. Asynchronous DDR clock ratio (continued)

3.1.6 Frequency options

This section discusses interface frequency options.

3.1.6.1 SYSCLK and platform frequency options

This table shows the expected frequency options for SYSCLK and platform frequencies.

3.1.6.2 Minimum platform frequency re quirements for high-speed interfaces

The platform clock frequency must be considered for proper operation of high-speed interfaces as described below. Figure 49. Gen 1 PEX minimum platform frequency Figure 50. Gen 2 PEX minimum platform frequency Table 100. Synchronous DDR clock ratio

1. Set RCW field MEM_PLL_CFG=0b01

Table 101. SYSCLK and platform frequency options

1 Platform frequency values are shown rounded down to the nearest whole number (decimal place accuracy

527 MHz PCI Express link width()×

training, which may or may not be the same as the link width POR selection.

3.1.7 SerDes PLL ratio

the binary value of the RCW field SRDS_DIV_Bn as shown in Table 103 and Table 104. This table lists the supported SerDes PLL Bank n to SD_REF_CLKn ratios. This table shows the PLL divider support for each pair of lanes on SerDes Bank 1. This table shows the PLL dividers supported for each 4 lane group for SerDes Banks 2, 3, and 4. Table 102. SerDes PLL bank n to SD_REF_CLKn ratios

001 Reserved 20:1 20:1 Reserved

101 Reserved Reserved 24:1 24:1

110 Reserved Reserved 30:1 30:1

Table 103. SerDes bank 1 PLL dividers

1. 1 bit (of 5 total SRDS_DIV_B1 bits) controls each pair of lanes,

the last bit controls configuration of lanes I/J (or 8/9). Table 104. SerDes banks 2, 3, and 4 PLL dividers

1. One bit controls all 4 lanes of each bank.
2. n = 2 or 3 (SerDes bank 2 or bank 3)

3.1.8 Frame Manager (FMan) clock select

The Frame Managers (FM) can each be synchronous with or asynchronous to the platform, depending on configuration. of the RCW Clocking Configuration fields FM1_CLK_SEL and FM2_CLK_SEL.

3.2 Supply power default setting

Incorrect voltage select settings can lead to irreversible device damage. Table 105. Frame Manager (FMan) clock select

1. For asynchronous mode, max frequency see Table 94.
2. For PLL settings, see Table 96.

3.3 Power supply design

3.3.1 PLL power supply filtering

be derived directly from the SVDD source through a low frequency filter scheme. from one PLL to the other is reduced. This circuit is intended to filter noise in the PLL’s resonant frequency range from a 500-kHz to 10-MHz range. Table 106. I/O voltage selection

footprint, without the inductance of vias. Figure 51 shows the PLL power supply filter circuit. parameters do not change (0402 body, X5R, ESL ≤ 0.5 nH). V oltage for A VDD is defined at the PLL supply filter and not the pin of A VDD. Figure 51. PLL power supply filter circuit Figure 52. SerDes PLL power supply filter circuit

• A V DD_SRDSn should be a filtered version of SVDD.
• Signals on the SerDes interface are fed from the XV DD power plane.
• V oltage for A V DD_SRDSn is defined at the PLL supply filter and not the pin of A VDD_SRDSn.
• An 0805 sized capacitor is recommended for system initial bring-up.

3.3.2 XV DD power supply filtering

options to allow flexibility to address system noise dependencies.

Bulk and decoupling capacitors are added, as needed, per power supply design. Figure 53. XVDD power supply filter circuit

3.3.3 USB_V DD_1P0 power supply filtering

Bulk and decoupling capacitors are added, as needed, per power supply design. Figure 54. USB_VDD_1P0 power supply filter circuit

3.4 Decoupling recommendations

directly under the device using a standard escape pattern. Others may surround the part. used to minimize lead inductance, preferably 0402 or 0603 sizes.

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Hardware design considerations Freescale Semiconductor140 have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (A VX TPS tantalum or Sanyo OSCON). The SerDes block requires a clean, tightly regulated source of power (SVDD and XVDD) to ensure low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below. Only SMT capacitors should be used to minimize inductance. Connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance.

• First, the board should have at least 10 × 10-nF SMT ceramic chip capacitors as close as possible to the supply balls of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the chip as close to the supply and ground connections as possible.
• Second, there should be a 1-µF ceramic chip capacitor on each side of the device. This should be done for all SerDes supplies.
• Third, between the device and any SerDes voltage regulator there should be a 10-µF, low ESR SMT tantalum chip capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all SerDes supplies.

3.6 Connection recommendations

To ensure reliable operation, it is recommended the user consider the following:

• Connect unused inputs to an appropriate signal level. All unused active low inputs should be tied to V DD, BVDD, CVDD, OVDD, GVDD, and LVDD as required. All unused active high inputs should be connected to GND. All NC (no connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, BVDD, CVDD, OVDD, GVDD, LVDD, and GND pins of the chip.
• The Ethernet controllers 1 and/or 2 input pins may be disabled by setting their respective RCW Configuration field EC1 (bits 360–361), and EC2 (bits 363–364), to 0b11 = No parallel mode Ethernet. When disabled, these inputs do not need to be externally pulled to an appropriate signal level.
• E C n_GTX_CLK125 is a 125-MHz input clock on the dTSEC ports. If the dTSEC ports are not used for RGMII, the ECn_GTX_CLK125 input can be tied off to GND.
• If RCW field DMA1=0b1 (RCW bit 384), th e DMA1 external interface is not enabled and this pin should be left as a no connect.
• If RCW field I2C = 0b100 or 0b101 (RCW bits 355–357), the SDHC_WP and SDHC_CD input signals are enabled for external use. If SDHC_WP and SDHC_CD are selected and not used, they must be externally pulled low such that SDHC_WP = 0 (write enabled) and SDHC_CD = 0 (card detected). If RCW field I2C != 0b100 or 0b101, thereby selecting either I2C3 or GPIO functionality, SDHC_WP and SDHC_CD are internally driven such that SDHC_WP = write enabled and SDHC_CD = card detected and the selected I2C3 or GPIO external pin functionality may be used.
• .For P5021 (SVR = 0x8205_00XX) or P5021E (SVR = 0x820D_00XX), TEST_SEL must be connected to GND.
• The TMP_DETECT pin is an active low input to the Security Monitor (see Chapter “Secure Boot and Trust Architecture” in the applicable chip reference manual). When using Trust Architecture functionality, external logic must ramp TMP_DETECT with OVDD. If not using Trust Architecture functionality, TMP_DETECT must be tied to OVDD to prevent the input from going low.

3.6.1 Legacy JTAG configuration signals

Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 56. Care must be taken to ensure that these pins are maintained at a valid negated state under normal operating conditions as most have asynchronous behavior and spurious assertion gives unpredictable results.

Hardware design considerations P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 141 Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE Std 1149.1 specification, but it is provided on all processors built on Power Architecture technology. The device requires TRST to be asserted during power-on reset flow to ensure that the JTAG boundary logic does not interfere with normal device operation. While the TAP controller can be forced to the reset state using only the TCK and TMS signals, generally systems assert TRST during the power-on reset flow. Simply tying TRST to PORESET is not practical because the JTAG interface is also used for accessing the common on-chip processor (COP), which implements the debug interface to the chip. The COP function of these processors allow a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert PORESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 56 allows the COP port to independently assert PORESET or TRST, while ensuring that the target can drive PORESET as well. The COP interface has a standard header, shown in Figure 55, for connection to the target system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed. There is no standardized way to number the COP header; so emulator vendors have issued many different pin numbering schemes. Some COP headers are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom. Still others number the pins counter-clockwise from pin 1 (as with an IC). Regardless of the numbering scheme, the signal placement recommended in Figure 55 is common to all known emulators.

3.6.1.1 Termination of unused signals

If the JTAG interface and COP header is not used, Freescale recommends the following connections:

• T R S T should be tied to PORESET through a 0 kΩ isolation resistor so that it is asserted when the system reset signal (PORESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale recommends that the COP header be designed into the system as shown in Figure 56. If this is not possible, the isolation resistor allows future access to TRST in case a JTAG interface may need to be wired onto the system in future debug situations.
• No pull-up/pull-down is required for TDI, TMS, or TDO.

Figure 55. Legacy COP connector physical pinout

Figure 56. Legacy JTAG interface connection

1. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.

in order to fully control the processor as shown here.

1. The COP port and target board should be able to independently assert PORESET and TRST to the processor
2. Asserting HRESET causes a hard reset on the device.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved

3.6.2 Aurora configuration signals

conditions as most have asynchronous behavior and spurious assertion gives unpredictable results. duplex connector be designed into the system as shown in Figure 60. Figure 57. Aurora 22 pin connector duplex pinout

Figure 58. Aurora 70 pin connector duplex pinout

Figure 59. Aurora 22 pin connector duplex interface connection

1. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.

in order to fully control the processor as shown here.

1. The Aurora port and target board should be able to independently assert PORESET and TRST to the processor
2. Asserting HRESET causes a hard reset on the device. HRESET is not used by the Aurora 22 pin connector.

20 Vendor I/O 3 N/C

18 Vendor I/O 2 (Aurora Event Out)

16 Vendor I/O 1 (Aurora Event In)

14 Vendor I/O 0 (Aurora HALT)

1 TX0_P

3 TX0_N

7 TX1_P

9 TX1_N

13 RX0_P

15 RX0_N

19 RX1_P

21 RX1_N

Figure 60. Aurora 70 pin connector duplex interface connection

1. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.

in order to fully control the processor as shown here.

1. The Aurora port and target board should be able to independently assert PORESET and TRST to the processor
2. Asserting HRESET causes a hard reset on the device.

34 Vendor I/O 5 (Aurora HRESET)

32 Vendor I/O 4 N/C EVT[4]

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Hardware design considerations Freescale Semiconductor148

3.6.3 Guidelines for high-speed interface termination

This section provides the guidelines for high-speed interface termination when the SerDes interface is entirely unused or when it is partly unused.

3.6.3.1 SerDes interface entirely unused

If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in this section. The following pins must be left unconnected:

• SD_TX[19:0]
• S D _ T X [19:0]
• S D _ I M P _ C A L _ R X
• SD_IMP_CAL_TX
• SD1_IMP_CAL_RX
• SD1_IMP_CAL_TX The following pins must be connected to SGND:
• SD_RX[19:0]
• S D _ R X [19:0]
• SD_REF_CLK1, SD_REF_CLK2, SD_REF_CLK3, SD_REF_CLK4
• SD_REF_CLK1 , SD_REF_CLK2, SD_REF_CLK3, SD_REF_CLK4 The RCW configuration fields SRDS_LPD_B1, SRDS_LPD_B2, SRDS_LPD_B3, and SRDS_LPD_B4, all bits must be set to power down all the lanes in each bank. The RCW configuration field SRDS_EN may be cleared to power down the SerDes block for power saving. Setting RCW[SRDS_EN_S1] = 0 powers down the PLLs of banks 1 to 3; RCW[SRDS_EN_S2]=0 powers down the PLL of bank 4. Additionally, software may configure SRDSBnRSTCTL[SDRD] = 1 for the unused banks to power down the SerDes bank PLLs to save power. Note that both SVDD and XVDD must remain powered.

3.6.3.2 SerDes interface partly unused

If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as described in this section. The following pins must be left unconnected:

• S D _ T X [n]
• S D _ T X [n] The following unused pins must be connected to SGND:
• S D _ R X [n]
• S D _ R X [n]
• SD_REF_CLK1, SD_REF_CLK1 (If entire SerDes bank 1 unused)
• SD_REF_CLK2, SD_REF_CLK2 (If entire SerDes bank 2 unused)
• SD_REF_CLK3, SD_REF_CLK3 (If entire SerDes bank 3 unused)
• SD_REF_CLK4, SD_REF_CLK4 (If entire SerDes bank 4 unused)

be set to power down the lane.

3.6.4 USB controller connections

This section details the hardware connections required for the USB controllers.

3.6.4.1 USB divider network

• Both resistors require 0.1% accu racy and a current capability of up to 1 mA. They must both have the same temperature coefficient and accuracy.
• The zener diode must have a value of 5 V −5.25 V .
• The 0.6 V diode requires an I F = 10 mA, IR < 500 nA and VF(Max) = 0.8 V .

Figure 61. Divider network at VBUS

3.6.4.2 USB n_VDD_1P8_DECAP capacitor options

Table 107. Recommended capacitor parts for USBn_VDD_1P8_DECAP

3.7 Recommended thermal model

local Freescale sales office.

3.8 Thermal management information

and thermal interface material. Figure 62. Exploded cross-sectional view—FC-PBGA (with lid) package

3.8.1 Internal package conduction resistance

• The die junction-to-case thermal resistance
• The die junction-to-lid-top thermal resistance
• The die junction-to-board thermal resistance Adhesive or Heat sink FC-PBGA package (small lid) Heat sink clip Printed-circuit board thermal interface material Die Die lid

Package information

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 151 This figure depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. Figure 63. Package with heat sink mounted to a printed-circuit board thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance are the dominant terms.

3.8.2 Thermal interface materials

means of a spring clip attachment to the printed-circuit board (see Figure 62). The system board designer can choose among several types of commercially-available thermal interface materials.

4 Package information

The following section describes the detailed content and mechanical description of the package.

4.1 Package parameters for the FC-PBGA

plastic-ball, grid array (FC-PBGA).

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor152

4.2 Mechanical dimensions of the FC-PBGA

This figure shows the mechanical dimensions and bottom surface nomenclature of the chip. Figure 64. Mechanical dimensions of the FC-PBGA with full lid

1. All dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M-1994.
3. All dimensions are symmetric across the package center lines unless dimensioned otherwise.
4. Maximum solder ball diameter measured parallel to datum A.
5. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
6. Parallelism measurement shall exclude any effect of mark on top surface of package.

5 Security fuse processor

Architecture and SFP can be found in the applicable chip reference manual. should only be powered for the duration of the fuse programming cycle, with a per device limit of two fuse programming cycles. All other times, connect POVDD to GND. The sequencing requirements for raising and lowering POVDD are shown in Figure 8.

6 Ordering information

Please contact your local Freescale sales office or regional marketing team for ordering information.

6.1 Part numbering nomenclature

This table provides the Freescale QorIQ platform part numbering nomenclature. Table 108. Part Numbering Nomenclature

1800 MHz

2000 MHz

2200 MHz

1200 MHz

1333 MHz

1600 MHz

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Revision history

Freescale Semiconductor154

6.2 Orderable part numbers addressed by this document

This table provides the Freescale orderable part numbers addressed by this document for the chip. Contact your Freescale Sales Representative for more information on orderable parts as not all combinations of orderable part numbers are available.

7 Revision history

This table provides a revision history for this document. Table 109. Orderable part numbers addressed by this document

1800 MHz/

2000 MHz/

2200 MHz/

Table 110. Revision history I n Table 1 “Pins listed by bus,” updated footnote 42. I n Table 9 “VDD_LP power dissipation,” updated footnote 2. 0 12/2013  Initial public release.

Document Number: P5021 Rev. 1 How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale, the Freescale logo, and QorIQ are trademarks of Freescale Semiconductor, All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © 2013-2014 Freescale Semiconductor, Inc.