P3041PB

P3041NXN7NNC NXP | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 P3041 Application Use Cases
• 2 P3041 Multicore Processing Options
• 3 P3041 Features
• 4 Developer Environment
• 5 Document Revision History

1.1 Integrated Access Router (IAD)

to SGMII, 2.5-Gb/s Ethernet enables the next step in performance connectivity to switches. Figure 1. P3041 Integrated Access Router Interface

1.2 Base Station Network Interface Card (NIC)

also achieve its intended potential as a highly-efficient, data path. Figure 2. P3041 LTE Wireless Base Station Interface

2.5 Gb/s SGMII,

P3041 Multicore Processing Options P3041 QorIQ Communications Processor Product Brief, Rev. 0 Freescale Semiconductor 3

2 P3041 Multicore Processing Options

The four P3041 cores can run either on an OS or run OS-less using a simple scheduler.

2.1 Running on an OS

There are different multi-processing options with the P3041 cores running on an OS:

• Four-core, asymmetric — Four copies of the same uni-processor operating system or — Up to four different uni-processor operating systems
• Four-core, symmetric
• Mixed symmetric and asymmetric For example, N cores running in SMP mode, while the remainder of the cores operate asymmetrically with up to 4–N different OSes

2.2 Running OS-Less Using a Simple Scheduler

Running one or more cores OS-less using a simple scheduler is a likely use case when cores are performing datapath operations with bounded real-time requirements. This use case is greatly enhanced by the provisioning of a 128-Kbyte private back-side CoreNet platform cache (CPC) for each e500mc core. These caches can operate as a traditional unified cache, or be set to operate as Instruction Only, Data Only, or even locked and used as memory-mapped SRAM. CPU cores operating asymmetrically can be run at asynchronous clock rates. Each processor can source its input clock from one of the multiple PLLs inside the P3041. This allows each core to operate at the minimum frequency required to perform its assigned function, saving power. The cores are also capable of running at half and quarter ratios of their input PLL frequency, and can switch between PLLs and ratios nearly instantaneously. This allows lightly utilized CPUs to be slowed (under software control) for power savings, rather than performing more complex task migration operations.

2.3 DPAA Multicore Processing Use Cases

Figure 3 shows several multicore processing use cases and the potential interaction with the Data Path Acceleration Architecture (DPAA).

by the datapath acceleration hardware. Figure 4. IO Processor Managing PCIe/Serial RapidIO-Based Network Interfaces

3 P3041 Features

3.1 Block Diagram

Figure 5 shows the major functional units within the P3041. Figure 5. P3041 Preliminary Block Diagram

3.2 P3041 Features Summary

• Four e500mc cores built on Powe r Architecture technology, each with a private 128-Kbyte backside cache — Three levels of instructions: –U s e r – Supervisor – Hypervisor — Independent boot and reset — Secure boot capability
• 1-Mbyte shared CoreNet platform cache (CPC)
• Hierarchical interconnect fabric 32-Kbyte I-Cache 18-lane 5-GHz SerDes eOpenPIC Internal Power Mgmt eSDHC eSPI 2x DUART 4x I2C Clocks/Reset GPIO CCSR BootROM USB 2.0 PHY Security Monitor PreBoot Loader 1024-Kbyte Frontside CoreNet Platform Cache 64-bit DDR3/3L Memory Controller CoreNet™ Coherency Fabric P3041 128-Kbyte Backside Cache Power Architecture® e500mc Core 32-Kbyte D-Cache 32-Kbyte I-Cache Perf Monitor CoreNet Trace Watchpoint Cross Trigger Real Time Debug Aurora 1GE 1GE Frame Manager 1GE 1GE DMA Security 4.2 Pattern Match Engine 2.1 eLBC Queue Mgr Buffer Mgr PAMU PAMUPAMU PAMU Peripheral Access Mgmt Unit Buffer Parse, Classify, Distribute SATA 2.0Test Port/ SAP 10GE 1GE PCIe PCIe PCIe PCIeRapidIO Msg Mgr (RMan) DMA sRIO

P3041 QorIQ Communications Processor Product Brief, Rev. 0 Freescale Semiconductor 7 — CoreNet fabric supporting coherent and non-cohe rent transactions with prioritization and bandwidth allocation amongst CoreNet end-points — Queue manager fabric support ing packet-level queue management and quality of service scheduling

• One 64-bit DDR3/3L SDRAM memo ry controller with ECC and chip-select interleaving support
• Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: — Frame management for packet pars ing, classification, and distribution — Queue management for scheduling, pack et sequencing, and congestion management — Hardware buffer management for buf fer allocation and de-allocation — Encryption/decryption (SEC 4.2) — RegEx pattern matching (PME 2.1) — RapidIO™ messaging manager (RMan)
• Ethernet interfaces — One 10 Gbps Ethernet (XAUI) controller — Five 1 Gbps or four 2.5 Gbps Ethernet controllers
• High speed peripheral interfaces — Four PCI Express 2.0 controller s/ports running at up to 5 GHz — Two Serial RapidIO® controllers/ports (versi on 1.3 with features of 2.1) running at up to

5 GHz

– RapidIO message manager (RMan) with Type 5–6 and Type 8–11 support — Dual SATA 2.0 interfaces

• Additional peripheral interfaces — Two USB 2.0 controllers with integrated PHY — SD/MMC controller (eSDHC) — Enhanced SPI controller — Four I 2C controllers — Dual DUARTs — Dual SATA supporting 1.5 and 3.0 Gb/s operation
• 18 SerDes lanes to 5 GHz
• Enhanced local bus controller (eLBC)
• Multicore programmable in terrupt controller (MPIC)
• Two 4-channel DMA engines

3.3 P3041 Benefits

The P3041’s e500mc cores can be combined as a fully-symmetric, multi-processing, system-on-a-chip, or they can be operated with varying degrees of independence to perform asymmetric multi-processing. Full processor independence, including the ability to independently boot and reset each e500mc core, is a

discrete processors onto a single device.

3.4 Data Path Acceleration Architecture (DPAA) Benefits

3.5 P3041 Critical Performance Parameters

Table 1 lists key performance indicators that define a set of values used to measure P3041 operation. Table 1. P3041 Critical Performance Parameters

1.5 GHz

1.3 GHz (DDR3/3L)1

• 1.5-V for DDR3  1.35-V for DDR3L Notes:

1 Conforms to JEDEC standard

P3041 QorIQ Communications Processor Product Brief, Rev. 0 Freescale Semiconductor 9 3.6 e500mc Core and Cache Memory Complex The P3041 offers four high-performance, 32-bite500mc cores based on the Power Architecture® from Power ISA 2.06. Like previous e500 cores, each e500mc is a superscalar dual issue processor, supporting out-of-order execution and in-order completion. 3.6.1 e500mc Features Summary Key features of the e500mc include the following:

• Up to 1.5 GHz core clock speed
• 36 bit physical addressing
• 64 TLB SuperPages
• 512-entry, 4-Kbyt e pages front-end
• 128-Kbyte backside L2 cache suppor ting ECC single-bit error correction
• 3 Integer units —T w o s i m p l e — One complex (integer multiply and divide)
• 64-byte cache line
• L1 caches, running at same frequency as CPU — 32-Kbyte Instruction, 8 way — 32-Kbyte Data, 8 way — Both with data and tag parity protection
• Supports Data Path Acceleration Architecture (DPAA) data and context “stashing” into frontside cache
• User, Supervisor, and Hypervisor instruction level privileges
• New processor facilities — Hardware support for efficient partitioning and virtualization — Double-precision floating-point unit – Complies with IEEE Std. 754™ – Binary-compatible with e300 and e600 – Supports 32 64-bit floating point registers for scalar single- and double-precision floating-point arithmetic. Decorated storage facility to provide additional atomic operations of up to two 64-bit quantities by a single access including a “fire and forget” APU for improved statistics support — Expanded interrupt model – Improved programmable interrupt controll er (PIC) automatically ACKs interrupts – Implements message send and receive f unctions for interprocessor communication, including receive filtering — External PID load and store facility

P3041 QorIQ Communications Processor Product Brief, Rev. 0 P3041 Features Freescale Semiconductor10 – Provides system software with an effici ent means to move data and perform cache operations between two disjoint address spaces – Eliminates the need to copy data from a sour ce context into a kernel context, change to destination address space, then copy the data to the destination address space or alternatively to map the user space into the kernel address space 3.6.2 e500mc 128-Kbyte Pr ivate Backside Cache Each e500mc core features a 128-Kbyte private backside cache running at the same frequency of the CPU, which supports the following:

• Write-back, pseudo LRU replacement algorithm
• Tag parity and ECC data protection
• 8-way, with arbitrary partitioni ng between instruction and data. For example, 3-ways instruction, 5-ways data, and so on
• Supports direct stashing of Da ta Path Acceleration Architecture (DPAA) data into cache

3.6.3 CoreNet Platform Cache (CPC)

The P3041 contains 1-Mbyte of shared CoreNet platform cache (CPC). The key features of the CPC include the following:

• Configurable as write-back or write-through
• Pseudo LRU replacement algorithm
• ECC protection
• 64-byte coherency granule
• 1 cache line read 64 bytes per cycle at 750 MHz, 0.4 terabits/sec read bandwidth
• 32-way cache array configurable to any of several modes on a per-way basis. — Unified cache, I-only, D-only — I/O stash (configurable portion of each pack et copied to CPC on write to main memory) – stashing of all transactions and sizes supported – explicit (CoreNet si gnalled) and implicit (address range based) stash allocation — Addressable SRAM ( 32-Kbyte granularity)

3.7 CoreNet Fabric and Address Map

The CoreNet fabric is Freescale’s next generation Front-side Interconnect Standard for multicore products, and provides the following:

• A highly concurrent, fully cach e coherent, multi-ported fabric
• Point-to-point connectivity with fl exible protocol architecture allows for pipelined interconnection between CPUs, platform caches, memory controllers, and I/O and accelerators at up to 750 MHz
• The CoreNet fabric has been designed to ove rcome bottlenecks associated with shared bus architectures, particularly address issue and data bandwidth limitations. The P3041’s multiple,

P3041 QorIQ Communications Processor Product Brief, Rev. 0 Freescale Semiconductor 11 parallel address paths allow for high address bandwidth, which is a key performance indicator for large coherent multicore processors

• Eliminates address retries, triggered by CPUs being unable to snoop within the narrow snooping window of a shared bus. This results in the P3041 having lower average memory latency The flexible P3041’s 36-bit, physical address map consists of local space and external address space. For the local address map, 32 local access windows (LAWs) define mapping within the local 36-bit (64-Gbyte) address space. Inbound and outbound translation windows can map the P3041 into a larger system address space such as the RapidIO or PCIe 64-bit address environment. This functionality is included in the address translation and mapping units (ATMUs).

3.8 Memory Complex

The P3041 memory complex consists of one DDR controller for main memory, and the memory controllers associated with the Enhanced Local Bus Controller (eLBC).

3.8.1 DDR Memory Controller

The P3041 DDR memory controllers have the following functionalities:

• Supports DDR3/3L SDRAM. The P3041 also supports chip-select interleaving within a controller.
• The P3041 can be configured to retain the cu rrently active SDRAM page for pipelined burst accesses. Page mode support of up to 32 simultaneously open pages can dramatically reduce access latencies for page hits. Depending on the memory system design and timing parameters, page mode can save up to 10 memory clock cycles for subsequent burst accesses that hit in an active page.
• Using ECC, the P3041 detects and co rrects all single-bit errors and detects all double-bit errors and all errors within a nibble.
• Upon detection of a loss of power signal from external logic, the DDR controllers can put compliant DDR SDRAM DIMMs into self-refresh mode, allowing systems to implement battery-backed main memory protection.
• Supports initialization bypass feature for use by syst em designers to prevent re-initialization of main memory during system power-on after an abnormal shutdown
• Supports active zeroization of system memory upon detection of a user-defined security violation

3.8.2 PreBoot Loader (PBL) and Nonvolatile Memory Interfaces

The PreBoot Loader (PBL) is a new logic module that operates similarly to an I2C boot sequencer but on behalf of a larger number of interfaces. The PBL’s functions include the following:

• Simplifies boot operations, replacing pin strapping re sistors with configuration data loaded from nonvolatile memory
• Uses the configuration data to initialize other system logic and to copy data from low speed memory interfaces (I2C, eLBC, SPI, and SD/MMC) into fully initialized DDR or the 1-Mbyte front-side cache.

P3041 QorIQ Communications Processor Product Brief, Rev. 0 P3041 Features Freescale Semiconductor12

• Releases CPU 0 from reset, allowing the boot pr ocesses to begin from fast system memory. The nonvolatile memory interfaces accessible by the PBL are as follows:
• The eLBC may be accessed by so ftware running on the CPUs following boot; it is not dedicated to the PBL. It also can be used for both volatile (SRAM) and nonvolatile memory as well as a control and low-performance data port for external memory-mapped devices. See Section 3.8.2.1, “Enhanced Local Bus Controllers (eLBC).”
• The serial memory controllers may be accessed by software running on the CPUs following boot;

3.8.2.1 Enhanced Local Bus Controllers (eLBC)

The enhanced local bus controller (eLBC) port connects to a variety of external memories, DSPs, and ASICs. Key features of the eLBC include the following:

• Multiplexed 32-bit addr ess and 32-bit data bus operating at up to 93 MHz
• Eight chip selects for eight external slaves
• Up to eight-beat burst transfers
• 8-, 16-, or 32-bit port sizes controll ed by an internal memory controller
• Three protocol engines on a per-chip-select basis
• Parity support
• Default boot ROM chip select with conf igurable bus width (8-, 16-, or 32-bit)
• Support for parallel NAND and NOR flash Three separate state machines share the same external pins and can be programmed separately to access different types of devices. Some examples are as follows:
• The general-purpose chip-select machine (GPC M) controls accesses to asynchronous devices using a simple handshake protocol.
• The user-programmable machine (UPM) can be pr ogrammed to interface to synchronous devices or custom ASIC interfaces.
• The NAND flash control machine (FCM ) further extends interface options.
• Each chip select can be configured so that the associated chip interface is controlled by the GPCM, UPM, or FCM controller. All controllers can be enabled simultaneously. The eLBC internally arbitrates among the controllers, allowing each to read or write a limited amount of data before allowing another controller to use the bus.

3.8.2.2 Serial Memory Controllers

In addition to the parallel NAND and NOR flash supported by means of the eLBC, the P3041 supports serial flash using SPI and SD/MMC card interfaces. The SD/MMC controller includes a DMA engine, allowing it to move data from serial flash to external or internal memory following straightforward initiation by software.

P3041 QorIQ Communications Processor Product Brief, Rev. 0 Freescale Semiconductor 13 3.9 Universal Serial Bus (USB) 2.0 The two USB 2.0 controllers with integrated PHY provide point-to-point connectivity complying with the USB specification, Rev. 2.0. Each USB controller can be configured to operate as a stand-alone host, and USB #2 can be configured as a stand-alone device, or with both host and device functions operating simultaneously. Key features of the USB 2.0 controller include the following:

• Complies with USB specification, Rev. 2.0
• Supports high-speed (480 Mbps), full-speed ( 12 Mbps), and low-speed (1.5 Mbps) operations
• Supports the required signaling for the USB tran sceiver macrocell interface (UTMI).The PHY interfacing to the UTMI is an internal PHY .
• Both controllers support operation as a stand-alone USB host controller — Support USB root hub with one downstream-facing port — Enhanced host controller interface (EHCI)-compatible
• One controller supports operatio n as a stand-alone USB device — Supports one upstream-facing port — Supports six programmable USB endpoints The host and device functions are both configured to support all four USB transfer types:
• Bulk
• Control
• Interrupt
• Isochronous

3.10 High-Speed Peripheral Interface Complex

All high-speed peripheral interfaces connect via 18 lanes of 5-GHz SerDes to a common crossbar switch referred to as OCeaN. Two high-speed I/O interface standards are supported: PCI Express (PCIe), and Serial RapidIO (sRIO). The P3041 integrates the following:

• Four PCIe controllers
• Two Serial RapidIO controllers
• RapidIO message manager (RMan).

3.10.1 PCI Express Controllers

Each of the four PCIe interfaces is compliant with the PCI Express Base Specification Revision 2.0. Key features of the PCIe interface include the following:

• Power-on reset configuratio n options allow root complex or endpoint functionality.
• The physical layer operates at 2.5 or 5 Gbaud data rate per lane.
• Receive and transmit ports operate independently, with an aggregate theoretical bandwidth of 32 Gbps.

P3041 QorIQ Communications Processor Product Brief, Rev. 0 P3041 Features Freescale Semiconductor14

• x8, x4, x2, and x1 link widths supported
• Both 32- and 64-bit addressing and 256-byte maximum payload size
• Full 64-bit decode with 36-bit wide windows
• Inbound INTx transactions
• Message Signaled Interrupt (MSI) transactions

3.10.2 Serial RapidIO Interfaces

3.10.2.1 Serial RapidIO Interface

The Serial RapidIO interface is based on the RapidIO Interconnect Specification, Revision 1.3 with features from 2.1. RapidIO is a high-performance, point-to-point, low-pin-count, packet-switched system-level interconnect that can be used in a variety of applications as an open standard. The rich feature set includes high data bandwidth, low-latency capability, and support for high-performance I/O devices as well as message-passing and software-managed programming models. Receive and transmit ports operate independently, and with 2 x 4 Serial RapidIO controllers, the aggregate theoretical bandwidth is 32 Gbps. Key features of the Serial RapidIO interface unit include the following:

• Support for RapidIO Interconnect Specification, Revision 1.3 (all transaction flows and priorities)
• 1x, 2x, and 4x LP-serial link interfaces, with tr ansmission rates of 2.5, 3.125, or 5.0 Gbaud (data rates of 2.0, 2.5, or 4.0 Gbps) per lane.
• Auto-detection of 1x, 2x, or 4x mode operation during port initialization
• 34-bit addressing and up to 256-byte data payload
• Receiver-controlle d flow control
• RapidIO error injection
• Internal LP-serial and applicati on interface-level loopback modes

3.10.2.2 RapidIO Message Manager (RMan)

The key features of the RapidIO message manager (RMan) include the following:

• Manages two inbox/outbox mailboxe s (queues) for data and one doorbell message structure
• Can multi-cast a single-segm ent 256-byte message to up to 32 different destination DevIDs
• Has four outbound segmentation units s upporting RapidIO Type 5–6 and Type 8–11 3.10.3 Serial ATA (SATA) 2.0 Controllers The key features of each of the two SATA include the following:
• Designed to comply with Serial ATA 2.6 Specification
• Supports host SATA I per spec Rev 1.0a — OOB — Port multipliers

P3041 QorIQ Communications Processor Product Brief, Rev. 0 Freescale Semiconductor 15 — ATAPI 6+ — Spread spectrum clocking on receive

• Support for SATA II extensions — Asynchronous notification — Hot plug including asynchronous signal recovery — Link power management — Native command queuing — Staggered spin-up and port multiplier support
• Support for SATA I and II data rates (1.5 and 3.0 Gbaud)
• Standard ATA master-only emulation
• Includes ATA shadow registers
• Implements SATA superset regist ers (SError, SControl, SStatus)
• Interrupt driven
• Power management support
• Error handling and diagnostic features — Far end/near end loopback — Failed CRC error reporting — Increased ALIGN insertion rates — Scrambling and CONT override

3.11 Data Path Acceleration Architecture (DPAA)

The DPAA provides the infrastructure to support simplified sharing of networking interfaces and accelerators by multiple CPU cores. These resources are abstracted into enqueue/dequeue operations by means of a common DPAA Queue Manager (QMan) driver. Beyond enabling multicore resource sharing, the DPAA significantly reduces software overheads associated with high-touch packet-forwarding operations. Examples of the types of packet-processing services this architecture is optimized to support are as follows:

• Traditional routing and bridging
• Firewall
• VPN termination for both IPsec and SSL VPNs
• Intrusion detection/prevention (IDS/IPS)
• Network anti-virus (A V) The DPAA generally leaves software in control of protocol processing, while reducing CPU overheads through off-load functions, which fall into two, broad categories:
• Section 3.11.1, “Packet Distribution and Queue/Congestion Management”
• Section 3.11.2, “Accelerating Content Processing”

3.11.1 Packet Distribution and Queue/Congestion Management

Table 2 lists some packet distribution and queue/congestion management offload functions.

3.11.2 Accelerating Content Processing

content-processing accelerators on the P3041. Table 2. P3041 Offload Functions configurable depletion thresholds. Implemented in a module called the Buffer Manager (BMan). functions such as RED/WRED, congestion notifications and tail discards. called the Frame Manager (FMan). profiles are supported. This function is also implemented in the FMan. Table 3. P3041 Content-Processing Accelerators these engines have been enhanced to work within the DPAA, and also upgraded in both features and performance.

3.11.3 DPAA Terms and Definitions

3.11.4 Major DPAA Components

• Section 3.11.4.1, “Frame Manager (FMan)
• Section 3.11.4.2, “Queue Manager (QMan)
• Section 3.11.4.3, “Buffer Manager (BMan)
• Section 3.10.2.2, “RapidIO Message Manager (RMan)
• Section 3.11.4.4, “Security Engine (SEC 4.2)

Table 4. DPAA Terms and Definitions any of the end points may dequeue frames.

• Section 3.11.4.5, “Pattern Matching Engine (PME 2.1)

Figure 6. QorIQ Data Path Acceleration Architecture (DPAA)

3.11.4.1 Frame Manager (FMan)

3.11.4.1.1 FMan Network Interfaces

• Programmable CRC ge neration and checking
• RMON statistics
• Jumbo frames of up to 9.6 Kbytes They are designed to comply with IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab, and additionally the 1Gbps MACs support IEEE-1588 v2 (clock synchronization over Ethernet). The dTSECS are capable of full- and half-duplex Ethernet support (1000 Mbps supports only full duplex); the 10-Gbit MAC is a single-speed full duplex. It supports IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or software-programmed PAUSE frame generation and recognition). QMan BMan 1GE 1GE 1GE 1GE Parse SEC 4.2 PME 2.1 and Classify Buffer Buffer Frame Manager DMA BMan RMan 10GE 1GE

however, the FMan can support line rate parsing and classification on an aggregate of 12 Gbps.

3.11.4.1.2 FMan Parse Function

There are several types of parser headers, shown in Table 5. parsing of the frame can proper treatment be determined. Parse results can (optionally) be passed to software.

3.11.4.1.3 FMan Distribution and Policing

After parsing is complete, there are two options for treatment (see Table 6). Table 5. Parser Header Types Self-describing Announced by proprietary values of Ethertype, protocol identifier, next header, and other standard fields. Non-self-describing Does not contain any information that indicates the presence of the header. Table 6. Post-Parsing Treatment Options  The result is a specific frame queue identifier. such as TOS or p-bits, or any other desired field(s).  The FMan contains internal memory that holds small tables for this purpose. which one of those sets to use.

P3041 QorIQ Communications Processor Product Brief, Rev. 0 P3041 Features Freescale Semiconductor20

• Because the FMan has up to 256 policing profiles , any frame queue or group of frame queues can be policed to either drop or mark packets if the flow exceeds a preconfigured rate.
• Policing and classification can be used in conjunction for mitigating Distributed Denial of Service Attack (DDOS).
• The policing is based on two-ra te-three-color marking algorithm (RFC2698). The sustained and peak rates as well as the burst sizes are user-configurable. Hence, the policing function can rate-limit traffic to conform to the rate the flow is mapped to at flow set-up time. By prioritizing and policing traffic prior to software processing, CPU cycles can be focused on the important and urgent traffic ahead of other traffic.

3.11.4.2 Queue Manager (QMan)

The Queue Manager (QMan) is the main component in the DPAA that allows for simplified sharing of network interfaces and hardware accelerators by multiple CPU cores. It also provides a simple and consistent message and data passing mechanism for dividing processing tasks amongst multiple CPU cores. The QMan features are as follows:

• Common interface between software and all hardware — Controls the prioritized queuing of data between multiple processor cores, network interfaces, and hardware accelerators — Supports both dedicated and pool channels, allowing both push and pull models of multicore load spreading
• Atomic access to common queues wi thout software locking overhead
• Mechanisms to guarantee order preservation with atomicity and order restoration following parallel processing on multiple CPUs
• Two-level queuing hierarchy with one or more Channels per Endpoint, eight work queues per Channel, and numerous frame queues per work queue
• Priority and work conserving fair scheduling between the work queues and the frame queues
• Loss-less flow control for ingress network interfaces
• Congestion avoidance (RED/WRED) and congestion management with tail discard and up to 256 congestion groups with each group composed of a user-configured number of frame queues.

3.11.4.3 Buffer Manager (BMan)

The buffer manager (BMan) manages pools of buffers on behalf of software for both hardware (accelerators and network interfaces) and software use. The BMan features are as follows:

• Common interface for software and hardware
• Guarantees atomic access to shared buffer pools
• Supports 32 buffer pools. Software and hardware buffer consumers can request both different size buffers and buffers in different memory partitions.
• Supports depletion thresholds with congestion notifications
• On-chip per pool buffer stockpile to minimi ze access to memory for buffer pool management
• LIFO (last in first out) buffer allocation polic y that optimizes cache usage and allocation

P3041 QorIQ Communications Processor Product Brief, Rev. 0 Freescale Semiconductor 21 3.11.4.4 Security Engine (SEC 4.2) The SEC 4.2 is QorIQ’s fourth generation crypto-acceleration engine. In addition to off-loading cryptographic algorithms, the SEC 4.2 offers header and trailer processing for several established security protocols. The SEC 4.2 includes several Descriptor Controllers (DECOs), which are updated versions of the previous SEC crypto-channels. DECOs are responsible for header and trailer processing, and managing context and data flow into the CHAs assigned to it for the length of an operation. The DECOs can perform header and trailer processing, as well as single pass encryption/integrity checking for the following security protocols:

• I P s e c
• SSL/TLS
• S R T P
• IEEE Std 802.1AE™ MACSec
• IEEE 802.16e WiMax MAC layer
• 3GPP RLC encryption/decryption In prior versions of the SEC, the individual algorithm accelerators were referred to as Execution Units (EUs). In the SEC 4.2, these are referred to as Crypto Hardware Accelerators (CHAs) to distinguish them from prior implementations. Specific CHAs available to the DECOs are listed below.
• Advanced encryption standard unit (AESA)
• ARC four execution unit (AFHA)
• Cyclic redundancy check accelerator (CRCA)
• Data encryption standard execution unit (DESA)
• Kasumi execution unit (KFHA)
• SNOW 3 G hardware accelerator (STHA)
• Message digest execution unit (MDHA)
• Public key execution unit (PKHA)
• Random number generator (RNGB) Depending on the security protocol and specific algorithms, the SEC 4.2’s aggregate symmetric encryption/integrity performance is 5 Gbps, while asymmetric encryption (RSA public key) performance is ~5,000 1024b RSA operations per second. The SEC 4.2 is also part of the QorIQ Trust Architecture, which gives the P3041 the ability to perform secure boot, runtime code integrity protection, and session key protection. The Trust Architecture is described in Section 3.12, “Avoiding Resource Contentions Using the QorIQ Trust Architecture.”

Figure 7. SEC 4.2 Block Diagram

• QMan interface supporting the DPAA Queue Interface Driver
• 2x increase in the number of patter ns supported (16 Kbytes to 32 Kbytes)
• Increase in number of stateful rule s supported (8 Kbytes to 16 Kbytes)
• Raw scanning performance is ~ 5 Gbps. Patterns that can be recognized, or “matched,” by the PME are of two general forms:
• Byte patterns are simple matches such as “abcd123” existing in both the data being scanned and in the pattern specification database.
• Event patterns are a sequence of multiple byte patterns. In the PME, event patterns are defined by stateful rules.

3.11.4.5.1 PME Regular Expressions (Regex)

regexes with stateful rules.

3.11.4.5.2 PME Match Detection

Figure 8. PME 2.1 Block Diagram

3.12 Avoiding Resource Contentions Using

Trust Architecture can reduce the risk of these issues.

3.12.1 QorIQ Trust Architecture Benefits

creates opportunities for malicious code to enter a system. presence of malicious software.

P3041 QorIQ Communications Processor Product Brief, Rev. 0 P3041 Features Freescale Semiconductor24 3.12.2 e500mc MMU and Embedded Hypervisor The P3041’s first line of defense against unintended interactions amongst the multiple CPUs/OSes is each e500mc core’s MMU, which are configured to determine which addresses in the global address map the CPU is able to read or write. If a particular resource (such as a portion of memory or a peripheral device) is dedicated to a single CPU, that CPU’s MMU is configured to allow access to those addresses (on 4-Kbyte granularity); other CPU MMUs are not configured for access to the other CPU’s private memory range. When two CPUs need to share resources, both of their MMUs are configured to have access to the shared address range. This level of hardware support for partitioning is common today; however, it is not sufficient for many core systems running diverse software. When the functions of multiple discrete CPUs are consolidated onto a single multicore SoC, achieving strong partitioning shouldn’t require the developer to map functions onto cores that are the exclusive owners of specific platform resources. The alternative, a fully open system with no private resources, is also unacceptable. For this reason, the e500mc MMU also includes embedded Hypervisor extensions. Each e500mc MMU supports three levels of instructions:

• U s e r
• Supervisor (OS)
• Hypervisor: An embedded Hypervis or micro-kernel (provided by Freescale as source code) runs unobtrusively beneath the various OSes running on the CPUs, consuming CPU cycles only when an access attempt is made to an embedded Hypervisor-managed shared resource.The embedded Hypervisor determines whether the access should be allowed, and if so, proxies the access on behalf of the original requestor. If malicious or poorly tested software on any core attempts to overwrite important device configuration registers (including CPU MMUs), the embedded Hypervisor blocks the write. Other examples of embedded Hypervisor managed resources are high- and low-speed peripheral interfaces (PCIe, UART) if those resources are not dedicated to a single CPU/partition.

3.12.3 Peripheral Access Management Unit (PAMU)

The P3041 includes a distributed function collectively referred to as the peripheral access management unit (PAMU), which provides address translation and access control for all bus masters in the system (PME, SEC, FMan, and so on). The PAMU access control can be one of the following:

• Absolute—The FMan, PME, SEC, and other bus masters can never access memory range XYZ.
• Conditional—Based on the Part ition ID of the CPU that programmed the bus master Being MMU-based, the embedded Hypervisor is only able to stop unauthorized software access attempts. Internal components with bus mastering capability also need to be prevented from reading and writing to specific memory regions. These devices do not spontaneously generate access attempts, but, if programmed to do so by buggy or malicious software, any of them could overwrite sensitive configuration registers and crash the system.

P3041 QorIQ Communications Processor Product Brief, Rev. 0 Freescale Semiconductor 25

3.12.4 Secure Boot and Sensitive Data Protection

The e500mc MMUs and PAMU allow the P3041 to enforce a consistent set of memory access permissions on a per-partition basis. When combined with embedded Hypervisor for safe sharing of resources, the P3041 becomes highly resilient when poorly tested or malicious code is run. For system developers building high reliability/high security platforms, rigorous testing of code of known origin is the norm.

3.12.4.1 Secure Boot Option

The system developer digitally signs the code to be executed by the CPU coming out of reset, and the P3041 ensures that only an unaltered version of that code runs on the platform. The P3041 offers both boot time and run time code authenticity checking and configurable consequences when the authenticity check fails.

3.12.4.2 Sensitive Data Protection Option

The P3041 supports protected internal and external storage of developer-provisioned sensitive instructions and data. For example, a system developer may provision each system with a number of RSA private keys to be used in mutual authentication and key exchange. These values would initially be stored in external non-volatile memory, but following secure boot, these values can be decrypted into on-chip protected memory (portion of platform cache dedicated as SRAM). Session keys, which may number in the thousands to tens of thousands, are not good candidates for on-chip storage, so the P3041 offers session key encryption. Session keys are stored in main memory, and are decrypted (transparently to software and without impacting SEC throughput) as they are brought into the SEC 4.2 for decryption of session traffic.

3.13 Advanced Power Management

The P3041’s advanced power management capabilities are based around fine-grained static clock control and software-controlled dynamic frequency management.

3.13.1 Saving Power by Managing Internal Clocks

Dynamic voltage and frequency scaling (DVFS) are useful techniques for reducing typical/average power and maximizing battery life in laptop environments, but embedded applications must be designed for rapid response to bursts of traffic and max power under worst-case environmental conditions. While the P3041 does not implement DVFS in the PC sense, it does actively manage internal clocks to avoid wasting energy. Clock signals are disabled to idle components, reducing dynamic power. These blocks can return to full operating frequency on the clock cycle after work is dispatched to them. The P3041 also supports (under software control) dynamic changes to CPU operating frequencies and voltages. Each CPU sources its input clock from one of two independent PLLs inside the P3041. Each CPU can also source its input clock from an integer frequency divider from two of the three independent PLLs. CPUs can switch their source PLL, and their frequency divider glitchlessly and nearly instantaneously. This allows each core to operate at the minimum frequency required to perform its assigned function, saving power.

P3041 QorIQ Communications Processor Product Brief, Rev. 0 P3041 Features Freescale Semiconductor26

3.13.2 Turning Off Unneeded Clocks

Fine-grained static control allows developers to turn off the clocks to individual logic blocks within the SoC that the system has no need for. Based on a finite number of SerDes, it is expected that any given application will have some Ethernet MACs, PCIe, or Serial RapidIO controllers inactive. These blocks can be disabled by means of the DEVDIS register. Re-enabling clocks to a logic block requires an SoC reset, which makes this type of power management operation infrequent (effectively static).

3.13.3 Avoiding Full System Failure Due to Thermal Overload

Changing PLL frequency dividers (/2, /4) can be used to achieve large and rapid reductions in dynamic power consumptions, and with the help of external temperature detection circuitry, can serve as a thermal overload protection scheme. If the junction temperature or system ambient temperature of the P3041 achieves some critical level, external temperature detection circuitry can drive a high-priority interrupt into the P3041, causing it to reduce selected CPU frequencies by half or more. This allows the system to continue to function in a degraded mode, rather than failing entirely. This technique is much simpler than turning off selected CPUs, which can involve complex task migration in an AMP system. When system temperatures have been restored to safe ranges, all CPUs can be returned to normal frequency within a few clock cycles. When less drastic frequency changes are desired, software can switch the CPU to a slower speed PLL, such as 1 G Hz versus 1.5 GHz. Many cores could be switched to a slower PLL during periods of light traffic, with the ability to immediately return those cores to the full rate PLL should traffic suddenly increase. The more traditional Power Architecture single-core power management modes (such as Core Doze, Core Nap, and Core Sleep) are also available in the e500mc.

3.14 Debug Support

The reduced number of external buses enabled by the move to multicore SoCs greatly simplifies board level lay-out and eliminates many concerns over signal integrity. While the board designer may embrace multicore CPUs, software engineers have real concerns over the potential to lose debug visibility. Despite the problems external buses can cause for the hardware engineer, they provide software developers with the ultimate confirmation that the proper instructions and data are passing between processing elements. Processing on a multicore SoC with shared caches and peripherals also leads to greater concurrency and an increased potential for unintended CPU interactions. To ensure that software developers have the same or better visibility into the P3041 as they would with multiple discrete devices, the P3041 implements the debug architecture shown in Figure 9.

Figure 9. P3041 Debug Architecture Block Diagram

• Debug and performance monitoring regi sters in both the e500mc and platform — Accessible by target resident debug so ftware and non-resident debug tools — Capable of generating debug interrupts and trace event messages
• Run control with enhancements — Classic — Cross-core and SoC watchpoint triggering
• High speed trace port (Aurora-based) — Supports Nexus class 2 instruct ion trace including timestamps – Process ID trace, watchpoint trace — Supports “light” subset of Nexus class 3 data trace – Enabled by cores, by event triggers, by In struction Address Compare/Data Address Compare events — Data Acquisition Trace – Compatible with Nexus class 3 – Instrumented code can generate data trace messages for values of interest – Performed by writing values to cont rol registers within each e500mc core — Watchpoint Trace – Can generate cross-core correlated breakpoints – Breakpoint on any core can halt execution of selected additional cores with minimal skid
• CoreNet transaction analyzer — Provides visibility to transactions across CoreNet (CoreNet fabric is otherwise transparent to software) e500mcG n l e Events Events Events Trace Scan Trace SerDes to Trace Probe Trace Trace Transactions Trace TransactionsTLM TAP/SAP SoC Peripherals e500mc Performance Monitor TAP Nexus Event Processing Unit Performance Nexus Port Controller Trace Buffers CoreNet Trace Analyzer PCIe/sRIO Memory Controller Aurora Trace Watchpoints Monitor CoreNet Fabric

4 Developer Environment

Architecture-based products, including the P3041. and boards at the base of the pyramid, and increasingly application-specific enablement items at the top.

• Section 4.1, “Base of the Pyramid: Broadly-Used Tools and Boards”
• Section 4.2, “First Level of the Pyramid: Debug and Performance Analysis”
• Section 4.3, “Second Level of the Pyramid: Simulation, Hypervisor, and DPAA Reference “Stacklets”
• Section 4.4, “Top Level of the Pyramid: Application-Specific Enablement”

Figure 10. Levels of Developer Environment

P3041 QorIQ Communications Processor Product Brief, Rev. 0 Freescale Semiconductor 29

4.1 Base of the Pyramid: Broadly-Used Tools and Boards

4.1.1 Hardware Platforms

This category includes both development systems and the reference designs. Development systems are available from both Freescale and our partners, with some partner systems being offered with form factors and BOMs to support use as reference designs. Freescale development systems are supported by the open source GNU tool set including compilers, linkers, and debuggers.

4.1.2 Compilers, Debuggers, Bootloaders, LSPs, Drivers

In active partnership with the open source community and Linux distribution and support suppliers, these tools will be updated to fully and efficiently support the P3041.

4.1.3 SMP/AMP Capable OS’s

Open source tools will be part of an overall P3041 development board Linux support package, which will include AMP and SMP versions of the Linux OS, and device drivers for the accelerators and networking and peripheral interfaces featured in the P3041. AMP Linux support will include the ability to boot multiple instances of Linux on different cores. Power Architecture ecosystem partners are committed to providing board support packages for the P3041.

4.2 First Level of the Pyramid: Debug and Performance Analysis

4.2.1 Advanced Debug

Advanced debug supports real-time trace analysis. It allows the developer to perform initial system bring-up and development, and is required to deal with the special challenges of software debugging and performance analysis in multicore systems.

4.2.2 Profiling and Performance Analysis

Freescale will bring tools support for profiling and performance analysis (such as enhanced statistics gathering) to the market both by means of our CodeWarrior line of tools and in partnership with industry standard tools suppliers.

4.3 Second Level of the Pyramid:

Simulation, Hypervisor, and DPAA Reference “Stacklets”

4.3.1 Hybrid Simulator

In conjunction with Virtutech, Freescale will provide a hybrid simulator that combines both functional and performance measurement models of the P3041. The hybrid simulator allows the user to switch between “fast functional mode” and “detailed performance mode” with capabilities that include the following:

• Global visibility
• Determinism
• Bug reproducibility
• Reverse execution
• Special abilities to detect race conditions
• Ability to detect race conditions

4.3.2 Hypervisor Micro-Kernel

developer can modify to match unique system requirements.

4.3.3 DPAA Reference “Stacklets ”

It is expected that some CPUs will be dedicated as datapath processors, working closely with the DPAA. processing and their interaction with the DPAA hardware.

4.4 Top Level of the Pyramid: Application-Specific Enablement

This category includes 3rd-party stacks optimized for DPAA, RegEx, A V TCP, IPv4/6, IPsec/SSL. “time-to-performance” advantages.

5 Document Revision History

Table 7 provides a revision history for this product brief. Table 7. Revision History

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