P25Q05LA-UWH-IR

P25Q40L PUYA | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 75

Technical content

Datasheet sections

• 1 Overview
• 2 Description
• 3 Pin Definition
• 3.1 Pin Configurations
• 3.2 Pin Descriptions
• 4 Block Diagram
• 5 Electrical Specifications
• 5.1 Absolute Maximum Ratings
• 5.2 DC Characteristics
• 5.3 AC Characteristics
• 5.4 AC Characteristics for Program and Erase
• 5.5 Operation Conditions
• 6 Data Protection
• 7 Memory Address Mapping
• 8 Device Operation
• 9 Hold Feature
• 10 Commands
• 10.1 Commands listing
• 10.2 Write Enable (WREN)
• 10.3 Write Disable (WRDI)
• 10.4 Write Enable for Volatile Status Register
• 10.5 Read Status Register (RDSR)
• 10.6 Active Status Interrupt (ASI)
• 10.7 Write Status Register (WRSR)
• 10.8 Read Data Bytes (READ)
• 10.9 Read Data Bytes at Higher Speed (FAST_READ)
• 10.10 Dual Read Mode (DREAD)
• 10.13 Quad Read Mode (QREAD)
• 10.16 Burst Read
• 10.17 Page Erase (PE)
• 10.18 Sector Erase (SE)
• 10.19 Block Erase (BE32K)
• 10.20 Block Erase (BE)
• 10.21 Chip Erase (CE)
• 10.22 Page Program (PP)
• 10.23 Dual Input Page Program (DPP)
• 10.24 Quad Page Program (QPP)
• 10.25 Erase Security Registers (ERSCUR)
• 10.26 Program Security Registers (PRSCUR)
• 10.27 Read Security Registers (RDSCUR)
• 10.28 Deep Power-down (DP)
• 10.29 Release form Deep Power-Down (RDP), Read Electronic Signature (RES)
• 10.30 Read Electronic Manufacturer ID & Device ID (REMS)
• 10.31 Dual I/O Read Electronic Manufacturer ID & Device ID (DREMS)
• 10.32 Quad I/O Read Electronic Manufacturer ID & Device ID (QREMS)
• 10.33 Read Identification (RDID)

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 1 of 75 版本号 密级 Ver1.3 机密 P25Q40L/20L/10L/05L Ultra Low Power, 4M/2M/1M/512K-bit Serial Multi I/O Flash Memory Datasheet Nov. 03, 2020 Puya Semiconductor (Shanghai) Co., Ltd Performance Highlight  Supply Range from 1.65V to 2.0V for Read, Erase and Program  Ultra Low Power consumption for Read, Erase and Program  X1, X2 and X4 Multi I/O Support  High reliability with 100K cycling and 20 Year-retention

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 3 of 75

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 4 of 75

1 Overview

 Single 1.65V to 2.0V supply  Industrial Temperature Range -40C to 85C  Serial Peripheral Interface (SPI) Compatible: Mode 0 and Mode 3  Single, Dual and Quad IO mode - 4M/2M/1M/512K x 1 bit - 2M/1M/512K/256K x 2 bits - 1M/512K/256K/128K x 4 bits  Flexible Architecture for Code and Data Storage - Uniform 256-byte Page Program - Uniform 256-byte Page Erase - Uniform 4K-byte Sector Erase - Uniform 32K/64K-byte Block Erase - Full Chip Erase  Hardware Controlled Locking of Protected Sectors by WP Pin  One Time Programmable (OTP) Security Register - 3*512-Byte Security Registers With OTP Lock  128 bit unique ID for each device  Fast Program and Erase Speed - 2ms Page program time - 8ms Page erase time - 8ms 4K-byte sector erase time - 8ms 32K-byte block erase time - 8ms 64K-byte block erase time  JEDEC Standard Manufacturer and Device ID Read Methodology  Ultra Low Power Consumption - 0.1uA Deep Power Down current - 9uA Standby current - 1.0mA Active Read current at 33MHz - 1.5mA Active Program or Erase current  High Reliability - 100,000 Program / Erase Cycles - 20-year Data Retention  Industry Standard Green Package Options - 8-pin SOP (150mil/208mil) - 8-land USON (3x2x0.55mm), (3x2x0.45mm), (3x4x0.55mm) - 8-land WSON (6x5x0.75mm) - 8-pin TSSOP - KGD for SiP

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 5 of 75

2 Description

The P25Q40L/20L/10L/05L is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the device, with its page erase granularity it is ideal for data storage as well, eliminating the need for additional data storage devices. The erase block sizes of the device have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density. The device also contains an additional 3*512-byte security registers with OTP lock (One-Time Programmable), can be used for purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. Specifically designed for use in many different systems, the device supports read, program, and erase operations with a wide supply voltage range of 1.65V to 2.0V. No separate voltage is required for programming and erasing.

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 6 of 75

3 Pin Definition

3.1 Pin Configurations

CS# SO WP# HOLD# SLCK SI VCC GND CS# SO WP# HOLD# SLCK SI VCC GND 8-PIN SOP (150mil/208mil) and TSSOP 8-Land UDFN (2x3mm/6x5mm)

3.2 Pin Descriptions

No. Symbol Extension Remarks

1 CS# Chip select

2 SO SIO1 Serial data output for 1 x I/O

Serial data input and output for 4 x I/O read mode

3 WP# SIO2 Write protection active low

Serial data input and output for 4 x I/O read mode

4 GND - Ground of the device

5 SI SIO0 Serial data input for 1x I/O

Serial data input and output for 4 x I/O read mode

6 SCLK - Serial interface clock input

7 HOLD# SIO3 To pause the device without deselecting the device

Serial data input and output for 4 x I/O read mode

8 Vcc - Power supply of the device

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 7 of 75

4 Block Diagram

Serial MUX & I/O buffers High Voltage Generator Control and Protection logic WP# HOLD# SO CS# SCK VCC GND Interface Control & Logic SI

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 8 of 75

5 Electrical Specifications

5.1 Absolute Maximum Ratings

 Voltage on Any Pin with Table 5-1 Pin Capacitance [1] Symbol Parameter Max. Units Test Condition COUT Output Capacitance 8 pF VOUT=GND CIN Input Capacitance 6 pF VIN=GND Note: 1. Test Conditions: TA = 25° C, F = 1MHz, Vcc = 1.8V. Figure 5-1 Maximum Overshoot Waveform -0.6V 20ns 20ns VCC+0.5V VCC Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform Figure 5-2 Input Test Waveforms and Measurement Level 0.8VCC 0.2VCC 0.7VCC 0.3VCC 0.5VCC AC Measurement Level Input timing reference level Output timing reference level Note:Input pulse rise and fall time ara < 5ns Figure 5-3 Output Loading VCC DEVICE UNDER TEST 25K ohm 25K ohmCL CL = 15/30pF Including jig capacitance NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 9 of 75

5.2 DC Characteristics

CS#=Vcc, all other inputs at 0V or Vcc 0.1 0.6 uA ISB Standby current CS#, HOLD#, WP#=VIH all inputs at CMOS levels 9 uA ICC1 Low power read current (03h) f=1MHz; SO=Open 0.5 1.0 mA f=33MHz; SO=Open 1.0 2.0 mA ICC2 Read current (0Bh) f=50MHz; SO=Open 1.0 2.0 mA f=85MHz; SO=Open 1.0 2.0 mA ICC3 Program current CS#=Vcc 1.5 3.0 mA ICC4 Erase current CS#=Vcc 1.5 3.0 mA ILI Input load current All inputs at CMOS level 1.0 uA ILO Output leakage All inputs at CMOS level 1.0 uA VIL Input low voltage 0.2Vcc V VIH Input high voltage 0.8Vcc V VOL Output low voltage IOL=100uA 0.2 V VOH Output high voltage IOH=-100uA Vcc-0.2 V Note: 1. Typical values measured at 1.8V @ 25° C.

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 10 of 75

5.3 AC Characteristics

Symbol Alt. Parameter 1.65V to 2.0V min typ max Unit fSCLK fC Clock Frequency for the following instructions: FAST_READ, RDSFDP, PP, SE, BE32K, BE, CE, DP, RES, WREN, WRDI, RDID, RDSR, WRSR(7) D.C. 85 MHz fRSCLK fR Clock Frequency for READ instructions 33 MHz fTSCLK fT Clock Frequency for 2READ,DREAD instructions 70 MHz fQ Clock Frequency for 4READ,QREAD instructions 70 MHz fQPP Clock Frequency for QPP (Quad page program) 85 MHz tCH(1) tCLH Clock High Time 5.5 ns tCL(1) tCLL Clock Low Time (fSCLK) 45% x (1fSCLK) 5.5 ns tCLCH(7) Clock Rise Time (peak to peak) 0.1 v/ns tCHCL(7) Clock Fall Time (peak to peak) 0.1 v/ns tSLCH tCSS CS# Active Setup Time (relative to SCLK) 5 ns tCHSL CS# Not Active Hold Time (relative to SCLK) 5 ns tDVCH tDS U Data In Setup Time 2 ns tCHDX tDH Data In Hold Time 3 ns tCHSH CS# Active Hold Time (relative to SCLK) 5 ns tSHCH CS# Not Active Setup Time (relative to SCLK) 5 ns tSHSL tCSH CS# Deselect Time From Read to next Read 15 ns CS# Deselect Time From Write,Erase,Program to Read Status Register 30 ns tSHQZ(7) tDIS Output Disable Time 6 ns tCLQV tV Clock Low to Output Valid Loading 30pF 7 ns Clock Low to Output Valid Loading 15pF 6 ns tCLQX tHO Output Hold Time 0 ns tHLCH HOLD# Active Setup Time (relative to SCLK) 5 ns tCHHH HOLD# Active Hold Time (relative to SCLK) 5 ns tHHCH HOLD# Not Active Setup Time (relative to SCLK) 5 ns tCHHL HOLD# Not Active Hold Time (relative to SCLK) 5 ns tHHQX tLZ HOLD# to Output Low-Z 6 ns tHLQZ tHZ HOLD# to Output High-Z 6 ns tWHSL(3) Write Protect Setup Time 20 ns tSHWL(3) Write Protect Hold Time 100 ns tDP CS# High to Deep Power-down Mode 3 us tRES1 CS# High To Standby Mode Without Electronic Signature Read 8 us tRES2 CS# High To Standby Mode With Electronic Signature Read 8 us tW Write Status Register Cycle Time 8 12 ms tReady Reset recovery time(for erase/program operation except WRSR) 30 us Reset recovery time(for WRSR operation) 8 12 ms

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 11 of 75

5.4 AC Characteristics for Program and Erase

Table 5-4 AC parameters fro program and erase TESL(6) Erase Suspend Latency 30 us TPSL(6) Program Suspend Latency 30 us TPRS(4) Latency between Program Resume and next Suspend 20 us TERS(5) Latency between Erase Resume and next Suspend 20 us tPP Page program time (up to 256 bytes) 2 3 ms tPE Page erase time 8 12 ms tSE Sector erase time 8 12 ms tBE1 Block erase time for 32K bytes 8 12 ms tBE2 Block erase time for 64K bytes 8 12 ms tCE Chip erase time 8 12 ms Note: 1. tCH + tCL must be greater than or equal to 1/ Frequency. 2. Typical values given for TA=25° C. Not 100% tested. 3. Only applicable as a constraint for a WRSR instruction. 4. Program operation may be interrupted as often as system request. The minimum timing of tPRS must be observed before issuing the next program suspend command. However, in order for an Program operation to make progress, tPRS ≥ 100us must be included in resume-to-suspend loop(s). Not 100% tested. 5. Erase operation may be interrupted as often as system request. The minimum timing of tERS must be observed before issuing the next erase suspend command. However, in order for an Erase operation to make progress, tERS ≥ 200us must be included in resume-to-suspend loop(s). Notes. Not 100% tested. 6. Latency time is required to complete Erase/Program Suspend operation. 7. The value guaranteed by characterization, not 100% tested in production. Figure 5-4 Serial Input Timing SCLK CS# SI MSB SO High-Z LSB tCHSL tSLCH tDVCH tCHDX tSHCH tCHSH tCHCL tCLCH tSHSL tCLH tCLL Figure 5-5 Output Timing

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 12 of 75 CS# SCLK SO SI Least significant address bit (LIB) in tCLQV tCLQX tCLQX tCLQV tCLH tCLL tSHQZ LSB tQLQH tQHQL Figure 5-6 Hold Timing CS# SCLK SO HOLD# tCHHL tHLQZ tHLCH tCHHH tHHCH tHHQX SI do not care during HOLD operation. Figure 5-7 WP Timing WP# SI SCLK tWHSL tSHWL CS# Write status register is allowed Write status register is not allowed

5.5 Operation Conditions

At Device Power-Up and Power-Down AC timing illustrated in "Figure AC Timing at Device Power-Up" and "Figure Power-Down Sequence" are for

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 14 of 75 Power Up/Down and Voltage Drop For Power-down to Power-up operation, the VCC of flash device must below VPWD for at least tPWD timing. Please check the table below for more detail. Figure 5-10 Power down-up Timing Vcc(max) Vcc(min) VPWD(max) tVSL Chip Selection is not allowed Device is fully accessible Time tPWD Symbol Parameter min max unit VPWD VCC voltage needed to below VPWD for ensuring initialization will occur 1 V tPWD The minimum duration for ensuring initialization will occur 300 us tVSL VCC(min.) to device operation 70 us tVR VCC Rise Time 1 500000 us/V VWI Write Inhibit Voltage 1.45 1.55 V Initial Delivery State The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0).

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 15 of 75

6 Data Protection

During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC power-up and power-down or from system noise.

• Power-on reset: to avoid sudden power switch by system power supply transition, the power-on reset may protect the Flash.
• Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before issuing other commands to change data.
• Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the memory array that can be read but not change.
• Hardware Protection Mode: WP# going low to protected the BP0~BP4bits and SRP0~1bits
• Deep Power-Down Mode: By entering deep power down mode, the flash device is under protected from writing all commands except the Release form Deep Power-Down Mode command.

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 16 of 75 Table 6-1. Protected Area Sizes P25Q40L Protected Area Sizes (CMP bit = 0) Status bit Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion x x 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 7 070000H-07FFFFH 64KB Upper 1/8 0 0 0 1 0 6 and 7 060000H-07FFFFH 128KB Upper 1/4 0 0 0 1 1 4 to 7 040000H-07FFFFH 256KB Upper 1/2 0 1 0 0 1 0 000000H-00FFFFH 64KB Lower 1/8 0 1 0 1 0 0 and 1 000000H-01FFFFH 128KB Lower 1/4 0 1 0 1 1 0 to 3 000000H-03FFFFH 256KB Lower 1/2 0 x 1 x x 0 to 7 000000H-07FFFFH 512KB ALL 1 0 0 0 1 7 07F000H-07FFFFH 4KB Upper 1/128 1 0 0 1 0 7 07E000H-07FFFFH 8KB Upper 1/64 1 0 0 1 1 7 07C000H-07FFFFH 16KB Upper 1/32 1 0 1 0 x 7 078000H- 07FFFFH 32KB Upper 1/16 1 0 1 1 0 7 078000H-07FFFFH 32KB Upper 1/16 1 1 0 0 1 0 000000H-000FFFH 4KB Lower 1/128 1 1 0 1 0 0 000000H-001FFFH 8KB Lower 1/64 1 1 0 1 1 0 000000H-003FFFH 16KB Lower 1/32 1 1 1 0 x 0 000000H-007FFFH 32KB Lower 1/16 1 1 1 1 0 0 000000H-007FFFH 32KB Lower 1/16 1 x 1 1 1 0 to 7 000000H-07FFFFH 512KB ALL P25Q40L Protected Area Sizes (CMP bit = 1) Status bit Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion x x 0 0 0 0 to 7 000000H-07FFFFH 512KB ALL 0 0 0 0 1 0 to 6 000000H-06FFFFH 448KB Lower 7/8 0 0 0 1 0 0 to 5 000000H-05FFFFH 384KB Lower 3/4 0 0 0 1 1 0 to 3 000000H-03FFFFH 256KB Lower 1/2 0 1 0 0 1 1 to 7 010000H-07FFFFH 448KB Upper 7/8 0 1 0 1 0 2 to 7 020000H-07FFFFH 384KB Upper 3/4 0 1 0 1 1 4 to 7 040000H-07FFFFH 256KB Upper 1/2 0 x 1 x x NONE NONE NONE NONE 1 0 0 0 1 0 to 7 000000H-07EFFFH 508KB Lower 127/128 1 0 0 1 0 0 to 7 000000H-07DFFFH 504KB Lower 63/64 1 0 0 1 1 0 to 7 000000H-07BFFFH 496KB Lower 31/32 1 0 1 0 x 0 to 7 000000H-077FFFH 480KB Lower 15/16 1 0 1 1 0 0 to 7 000000H-077FFFH 480KB Lower 15/16 1 1 0 0 1 0 to 7 001000-07FFFFH 508KB Upper 127/128 1 1 0 1 0 0 to 7 002000-07FFFFH 504KB Upper 63/64 1 1 0 1 1 0 to 7 004000-07FFFFH 496KB Upper 31/32 1 1 1 0 x 0 to 7 008000-07FFFFH 480KB Upper 15/16 1 1 1 1 0 0 to 7 008000-07FFFFH 480KB Upper 15/16 1 x 1 1 1 NONE NONE NONE NONE

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 17 of 75 P25Q20L Protected Area Sizes (CMP bit = 0) Status bit Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion 0 x x 0 0 NONE NONE NONE NONE 0 0 x 0 1 3 030000H-03FFFFH 64KB Upper 1/4 0 0 x 1 0 2 and 3 020000H-03FFFFH 128KB Upper 1/2 0 1 x 0 1 0 000000H-00FFFFH 64KB Lower 1/4 0 1 x 1 0 0 and 1 000000H-01FFFFH 128KB Lower 1/2 0 x x 1 1 0 to 3 000000H-03FFFFH 256KB ALL 1 x 0 0 0 NONE NONE NONE NONE 1 0 0 0 1 3 03F000H-03FFFFH 4KB Upper 1/64 1 0 0 1 0 3 03E000H-03FFFFH 8KB Upper 1/32 1 0 0 1 1 3 03C000H-03FFFFH 16KB Upper 1/16 1 0 1 0 x 3 038000H-03FFFFH 32KB Upper 1/8 1 0 1 1 0 3 038000H-03FFFFH 32KB Upper 1/8 1 1 0 0 1 0 000000H-000FFFH 4KB Lower 1/64 1 1 0 1 0 0 000000H-001FFFH 8KB Lower 1/32 1 1 0 1 1 0 000000H-003FFFH 16KB Lower 1/16 1 1 1 0 x 0 000000H-007FFFH 32KB Lower 1/8 1 1 1 1 0 0 000000H-007FFFH 32KB Lower 1/8 1 x 1 1 1 0 to 3 000000H-03FFFFH 256KB ALL P25Q20L Protected Area Sizes (CMP bit = 1) Status bit Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion 0 x x 0 0 0 to 3 000000H-03FFFFH 256KB ALL 0 0 x 0 1 0 to 2 000000H-02FFFFH 192KB Lower 3/4 0 0 x 1 0 0 and 1 000000H-01FFFFH 128KB Lower 1/2 0 1 x 0 1 1 to 3 010000H-03FFFFH 192KB Upper 3/4 0 1 x 1 0 2 and 3 020000H-03FFFFH 128KB Upper 1/2 0 x x 1 1 NONE NONE NONE NONE 1 x 0 0 0 0 to 3 000000H-03FFFFH 256KB ALL 1 0 0 0 1 0 to 3 000000H-03EFFFH 252KB Lower 63/64 1 0 0 1 0 0 to 3 000000H-03DFFFH 248KB Lower 31/32 1 0 0 1 1 0 to 3 000000H-03BFFFH 240KB Lower 15/16 1 0 1 0 x 0 to 3 000000H-037FFFH 224KB Lower 7/8 1 0 1 1 0 0 to 3 000000H-037FFFH 224KB Lower 7/8 1 1 0 0 1 0 to 3 001000-03FFFFH 252KB Upper 63/64 1 1 0 1 0 0 to 3 002000-03FFFFH 248KB Upper 31/32 1 1 0 1 1 0 to 3 004000-03FFFFH 240KB Upper 15/16 1 1 1 0 x 0 to 3 008000-03FFFFH 224KB Upper 7/8 1 1 1 1 0 0 to 3 008000-03FFFFH 224KB Upper 7/8 1 x 1 1 1 NONE NONE NONE NONE

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 18 of 75 P25Q10L Protected Area Sizes (CMP bit = 0) Status bit Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion 0 x x 0 0 NONE NONE NONE NONE 0 0 x 0 1 1 010000H-01FFFFH 64KB Upper 1/2 0 1 x 0 1 0 000000H-00FFFFH 64KB Lower 1/2 0 x x 1 x 0 to 1 000000H-01FFFFH 128KB ALL 1 x 0 0 0 NONE NONE NONE NONE 1 0 0 0 1 1 01F000H-01FFFFH 4KB Upper 1/32 1 0 0 1 0 1 01E000H-01FFFFH 8KB Upper 1/16 1 0 0 1 1 1 01C000H-01FFFFH 16KB Upper 1/8 1 0 1 0 x 1 018000H-01FFFFH 32KB Upper 1/4 1 0 1 1 0 1 018000H-01FFFFH 32KB Upper 1/4 1 1 0 0 1 0 000000H-000FFFH 4KB Lower 1/32 1 1 0 1 0 0 000000H-001FFFH 8KB Lower 1/16 1 1 0 1 1 0 000000H-003FFFH 16KB Lower 1/8 1 1 1 0 x 0 000000H-007FFFH 32KB Lower 1/4 1 1 1 1 0 0 000000H-007FFFH 32KB Lower 1/4 1 x 1 1 1 0 to 1 000000H-01FFFFH 128KB ALL P25Q10L Protected Area Sizes (CMP bit = 1) Status bit Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion 0 x x 0 0 0 to 1 000000H-01FFFFH 128KB ALL 0 0 x 0 1 0 000000H-00FFFFH 64KB Lower 1/2 0 1 x 0 1 1 010000H-01FFFFH 64KB Upper 1/2 0 x x 1 x NONE NONE NONE NONE 1 x 0 0 0 0 to 1 000000H-01FFFFH 128KB ALL 1 0 0 0 1 0 to 1 000000H-01EFFFH 124KB Lower 31/32 1 0 0 1 0 0 to 1 000000H-01DFFFH 120KB Lower 15/16 1 0 0 1 1 0 to 1 000000H-01BFFFH 112KB Lower 7/8 1 0 1 0 x 0 to 1 000000H-017FFFH 96KB Lower 3/4 1 0 1 1 0 0 to 1 000000H-017FFFH 96KB Lower 3/4 1 1 0 0 1 0 to 1 001000H-01FFFFH 124KB Upper 31/32 1 1 0 1 0 0 to 1 002000H-01FFFFH 120KB Upper 15/16 1 1 0 1 1 0 to 1 004000H-01FFFFH 112KB Upper 7/8 1 1 1 0 x 0 to 1 008000H-01FFFFH 96KB Upper 3/4 1 1 1 1 0 0 to 1 008000H-01FFFFH 96KB Upper 3/4 1 x 1 1 1 NONE NONE NONE NONE

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 19 of 75 P25Q05L Protected Area Sizes (CMP bit = 0) Status bit Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion 0 x x x 0 NONE NONE NONE NONE 0 x x x 1 0 000000H-00FFFFH 64KB ALL 1 x 0 0 0 NONE NONE NONE NONE 1 0 0 0 1 0 00F000H-00FFFFH 4KB Upper 1/16 1 0 0 1 0 0 00E000H-00FFFFH 8KB Upper 1/8 1 0 0 1 1 0 00C000H-00FFFFH 16KB Upper 1/4 1 0 1 0 x 0 008000H-00FFFFH 32KB Upper 1/2 1 0 1 1 0 0 008000H-00FFFFH 32KB Upper 1/2 1 1 0 0 1 0 000000H-000FFFH 4KB Lower 1/16 1 1 0 1 0 0 000000H-001FFFH 8KB Lower 1/8 1 1 0 1 1 0 000000H-003FFFH 16KB Lower 1/4 1 1 1 0 x 0 000000H-007FFFH 32KB Lower 1/2 1 1 1 1 0 0 000000H-007FFFH 32KB Lower 1/2 1 x 1 1 1 0 000000H-00FFFFH 64KB ALL P25Q05L Protected Area Sizes (CMP bit = 1) Status bit Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion 0 x x x 0 0 000000H-00FFFFH 64KB ALL 0 x x x 1 NONE NONE NONE NONE 1 x 0 0 0 0 000000H-00FFFFH 64KB ALL 1 0 0 0 1 0 000000H-00EFFFH 60KB Lower 15/16 1 0 0 1 0 0 000000H-00DFFFH 56KB Lower 7/8 1 0 0 1 1 0 000000H-00BFFFH 48KB Lower 3/4 1 0 1 0 x 0 000000H-007FFFH 32KB Lower 1/2 1 0 1 1 0 0 000000H-007FFFH 32KB Lower 1/2 1 1 0 0 1 0 001000H-00FFFFH 60KB Upper 15/16 1 1 0 1 0 0 002000H-00FFFFH 56KB Upper 7/8 1 1 0 1 1 0 004000H-00FFFFH 48KB Upper 3/4 1 1 1 0 x 0 008000H-00FFFFH 32KB Upper 1/2 1 1 1 1 0 0 008000H-00FFFFH 32KB Upper 1/2 1 x 1 1 1 NONE NONE NONE NONE Note: 1. X=don’t care 2. If any erase or program command specifies a memory that contains protected data portion, this command will be ignored.

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 20 of 75

7 Memory Address Mapping

The memory array can be erased in three levels of granularity including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing both code and data segments to reside in their own erase regions. P25Q40L Memory Organization Block64K Sector Address Range 127 07F000H 07FFFFH 112 070000H 070FFFH 111 06F000H 06FFFFH 96 060000H 060FFFH 47 02F000H 02FFFFH 32 020000H 020FFFH 31 01F000H 01FFFFH 16 010000H 010FFFH 15 00F000H 00FFFFH 0 000000H 000FFFH Block32K 1 - 0 3 - 2 5 - 4 13 - 12 15 - 14 P25Q20L Memory Organization Block64K Sector Address Range 63 03F000H 03FFFFH 48 030000H 030FFFH 47 02F000H 02FFFFH 32 020000H 020FFFH 31 01F000H 01FFFFH 16 010000H 010FFFH 15 00F000H 00FFFFH 0 000000H 000FFFH Block32K 1 - 0 3 - 2 5 - 4 7 - 63

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 21 of 75 P25Q10L Memory Organization Block64K Sector Address Range 31 01F000H 01FFFFH 16 010000H 010FFFH 15 00F000H 00FFFFH 0 000000H 000FFFH Block32K 1 - 0 3 - 2 P25Q05L Memory Organization Block64K Sector Address Range 15 00F000H 00FFFFH 8 008000H 008FFFH 7 007000H 007FFFH 0 000000H 000FFFH Block32K

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 22 of 75

8 Device Operation

Before a command is issued, status register should be checked to ensure device is ready for the intended operation. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK. The difference of serial peripheral interface mode 0 and mode 3 is shown as Figure 8-1. For the following instructions: RDID, RDSR, RDSR1, RDSCUR, READ, FAST_READ, DREAD, 2READ, 4READ, QREAD, RDSFDP , RES, REMS, DREMS, QREMS, the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, PE, SE, BE32K, BE, CE, PP, DPP , QPP , DP , ERSCUR, PRSCUR, SUSPEND, RESUME, RSTEN, RST, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase. Figure 8-1 Serial Peripheral Interface Modes Supported SCLK MSB CPHA shift in shift out SI CPOL 0 (Serial mode 0) (Serial mode 3) 1 SO SCLK MSB Note: CPOL indicates clock polarity of serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which serial mode is supported. Standard SPI The P25Q40L/20L/10L/05L features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. Dual SPI The P25Q40L/20L/10L/05L supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read”(3BHand BBH) commands. These commands allow data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 23 of 75 Quad SPI The P25Q40L/20L/10L/05L supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast Read”(6BH,EBH) commands. These commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 andIO3. Quad SPI commands require the non-volatile Quad Enable bit(QE) in Status Register to be set.

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 24 of 75

9 Hold Feature

HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low). Figure 9-1 Hold Condition Operation HOLD HOLD CS# SCLK HOLD# During the HOLD operation, the Serial Data Output (SO) is high impedance when Hold# pin goes low and will keep high impedance until Hold# pin goes high. The Serial Data Input (SI) is don't care if both Serial Clock (SCLK) and Hold# pin goes low and will keep the state until SCLK goes low and Hold# pin goes high. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the devi ce. To re-start communication with chip, the HOLD# must be at high and CS# must be at low. Note: The HOLD feature is disabled during Quad I/O mode.

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 25 of 75

10 Commands

10.1 Commands listing

Commands Abbr. Code ADR Bytes DMY Bytes Data Bytes Function description Read Read Array (fast) FREAD 0Bh 3 1 1+ n bytes read out until CS# goes high Read Array (low power) READ 03h 3 0 1+ n bytes read out until CS# goes high Read Dual Output DREAD 3Bh 3 1 1+ n bytes read out by Dual output Read 2x I/O 2READ BBh 3 1 1+ n bytes read out by 2 x I/O Read Quad Output QREAD 6Bh 3 1 1+ n bytes read out by Quad output Read 4x I/O 4READ EBh 3 1 1+ n bytes read out by 4 x I/O Program and Erase Page Erase PE 81h 3 0 0 erase selected page Sector Erase (4K bytes) SE 20h 3 0 0 erase selected sector Block Erase (32K bytes) BE32 52h 3 0 0 erase selected 32K block Block Erase (64K bytes) BE64 D8h 3 0 0 erase selected 64K block Chip Erase CE 60h 0 0 0 erase whole chip C7h 0 0 0 erase whole chip Page Program PP 02h 3 0 1+ program selected page Dual-IN Page Program 2PP A2h 3 0 1+ program selected page by Dual input Quad page program QPP 32h 3 0 1+ quad input to program selected page Program/Erase Suspend PES 75h 0 0 0 suspend program/erase operation B0h 0 0 0 suspend program/erase operation Program/Erase Resume PER 7Ah 0 0 0 continue program/erase operation 30h 0 0 0 continue program/erase operation Protection Write Enable WREN 06h 0 0 0 sets the (WEL) write enable latch bit Write Disable WRDI 04h 0 0 0 resets the (WEL) write enable latch bit Volatile SR Write Enable VWREN 50h 0 0 0 Write enable for volatile status register Security Erase Security Registers ERSCUR 44h 3 0 0 Erase security registers Program Security Registers PRSCUR 42h 3 0 1+ Program security registers Read Security Registers RDSCUR 48h 3 1 1+ Read value of security register Status Register Read Status Register RDSR 05h 0 0 1 read out status register RDSR2 35h 0 0 1 Read out status register-1 Active Status Interrupt ASI 25h 0 1 0 Enable the active status interrupt Write Status Register WRSR 01h 0 0 2 Write data to status/configuration registers

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 26 of 75 Command set (Cont’d) Commands Abbr. Code ADR Bytes DMY Bytes Data Bytes Function Other Commands Reset Enable RSTEN 66h 0 0 0 Enable reset Reset RST 99h 0 0 0 Reset Read Manufacturer/device ID RDID 9Fh 0 0 1 to 3 output JEDEC ID: 1-byte manufacturer ID & 2-byte device ID Read Manufacture ID REMS 90h 3 1+ Read manufacturer ID/device ID data Dual Read Manufacture ID DREMS 92h 3 1 1+ Dual output read manufacture/device ID Quad Read Manufacture ID QREMS 94h 3 1 1+ Quad output read manufacture/device ID Deep Power-down DP B9h 0 0 0 enters deep power-down mode Release Deep Power- down/Read Electronic ID RDP/RES ABh 3 0 1 Read electronic ID data Set burst length SBL 77h 0 0 0 Set burst length Read SFDP RDSFDP 5Ah Read SFDP parameter Release read enhanced FFh Release from read enhanced Read unique ID RUID 4Bh 4 1+ Read unique ID NOTE: 1. Dual Output data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 2. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 3. Quad Output Data IO3 = (D7, D3,…..) 4. Quad Input Address IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 5. Fast Read Quad I/O Data IO0 = (x, x, x, x, D4, D0,…) IO1 = (x, x, x, x, D5, D1,…) IO2 = (x, x, x, x, D6, D2,…) IO3 = (x, x, x, x, D7, D3,…) 6. Security Registers Address: Security Register1: A23-A16=00H, A15-A9=0001000, A8-A0= Byte Address; Security Register2: A23-A16=00H, A15-A9=0010000, A8-A0= Byte Address; Security Register3: A23-A16=00H, A15-A9=0011000, A8-A0= Byte Address;

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 27 of 75

10.2 Write Enable (WREN)

The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP,DPP,QPP, PE,SE, BE32K,BE, CE, and WRSR,ERSCUR, PRSCUR which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high. Figure 10-2 Write Enable (WREN) Sequence (Command 06) Command 0 1 2 3 4 5 6 7 06H CS# SCLK SI SO High-Z

10.3 Write Disable (WRDI)

The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. The WEL bit is reset by following situations: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Dual Input Page Program (DPP) instruction completion - Quod Page Program (QPP) instruction completion - Page Erase (PE) instruction completion - Sector Erase (SE) instruction completion - Block Erase (BE32K,BE) instruction completion - Chip Erase (CE) instruction completion - Erase Security Register (ERSCUR) instruction completion - Program Security Register (PRSCUR) instruction completion - Reset (RST) instruction completion Figure 10-3 Write Disable (WRDI) Sequence (Command 04) Command 0 1 2 3 4 5 6 7 04H CS# SCLK SI SO High-Z

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 28 of 75

10.4 Write Enable for Volatile Status Register

The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non -volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command must be issued prior to a Write Status Register command. The Write Enable for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status Register bit values. The sequence of issuing Write Enable for Volatile Status Register instruction is: CS# goes low→ sending Write Enable for Volatile Status Register instruction code→ CS# goes high. Figure 10-4 Write Enable for Volatile Status Register Sequence (Command 50) CS# SCLK SI SO 0 1 2 3 4 5 6 7 High-Z Command(50H )

10.5 Read Status Register (RDSR)

The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. For command code “05H”, the SO will output Status Register bits S7~S0. T he command code “35H”, the SO will output Status Register bits S15~S8 The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out on SO. The SIO[3:1] are "don't care". Figure 10-5 Read Status Register (RDSR) Sequence (Command 05 or 35) Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 05Hor35H CS# SCLK SI SO High-Z 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 MSB S7~S0 or S15~S8 out S7~S0 or S15~S8 out MSB Status Register S15 S14 S13 S12 S11 S10 S9 S8 SUS1 CMP LB3 LB2 LB1 SUS2 QE SRP1 S7 S6 S5 S4 S3 S2 S1 S0 SRP0 BP4 BP3 BP2 BP1 BP0 WEL WIP The definition of the status register bits is as below:

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 29 of 75 WIP bit. The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means the device is not in program/erase/write status register progress. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase command is accepted. BP4, BP3, BP2, BP1, BP0 bits. The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table “Protected Area Sizes”).becomes protected against Page Program (PP), Page Erase (PE), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed, only if the Block Protect (BP4, BP3, BP2, BP1and BP0) are set to “None protected”. SRP1, SRP0 bits. The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits control the method of write protection: software protection, hardware protection, power supply lock- down or one time programmable protection. SRP1 SRP0 WP# Status Register Description 0 0 x Software Protected The Status Register can be written to after a Write Enable command, WEL=1.(Default) 0 1 0 Hardware Protected WP#=0, the Status Register locked and can not be written to. 0 1 1 Hardware Unprotected WP#=1, the Status Register is unlocked and can be written to after a Write Enable command, WEL=1. 1 0 x Power Supply Lock- Down(1) Status Register is protected and can not be written to again until the next Power-Down, Power-Up cycle. 1 1 x One Time Program(2) Status Register is permanently protected and can not be written to. NOTE: 1. When SRP1, SRP0=(1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state. 2. This feature is available on special order. Please contact PUYA for details. QE bit. The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or ground) LB3, LB2, LB1, bits. The LB3, LB2, LB1, bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide the write protect control and status to the Security Registers. The default state of LB 3-LB1are0, the security registers are unlocked. The LB3-LB1bitscan be set to 1 individually using the Write Register instruction. The LB3-LB1bits are One Time Programmable, once its set to 1, the Security Registers will become read-only permanently.

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 30 of 75 CMP bit The CMP bit is a non-volatile Read/Write bit in the Status Register(S14). It is used in conjunction the BP4 -BP0 bits to provide more flexibility for the array protection. Please see the table “Protected Area Size” for details. The default setting is CMP=0. SUS1, SUS2bit The SUS1 and SUS2bit are read only bit in the status register (S15and S10) that are set to 1 after executing an Program/Erase Suspend (75H or B0H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set the SUS2 to 1). The SUS1 and SUS2 bit are cleared to 0 by Program/Erase Resume (7AH or 30H) command as well as a power-down, power-up cycle.

10.6 Active Status Interrupt (ASI)

To simplify the readout of the WIP bit, the Active Status Interrupt command (25h) may be used. It is then not necessary to continuously read the status register, it is sufficient to monitor the value of the SO line. If the SO line is connected to an interrupt line on the host controller, the host controller may be in sleep mode until the SO line indicates that the device is ready for the next command. The WIP bit can be read at any time, including during an internally self-timed program or erase operation. To enable the Active Status Interrupt command, the CS pin must first be asserted and the opcode of 25h must be clocked into the device. For SPI Mode3, at least one dummy bit has to be clocked into the device after the last bit of the opcode has been clocked in. (In most cases, this is most easily done by sending a dummy byte to the device.) The value of the SI line after the opcode is clocked in is of no significance to the operation. For SPI Mode 0, this dummy bit (dummy byte) is not required. The value of WIP is then output on the SO line, and is continuously updated by the device for as long as the CS pin remains asserted. Additional clocks on the SCK pin are not required. If the WIP bit changes from 1 to 0 while the CS pin is asserted, the SO line will change from 1 to 0. (The WIP bit cannot change from 0 to 1 during an operation, so if the SO line already is 0, it will not change.) Deasserting the CS pin will terminate the Active Status Interrupt operation and put the SO pin into a high - impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. The sequence of issuing ASI instruction is: CS# goes low→ sending ASI instruction code→ WIP data out on SO Figure 10-6 Active Status Interrupt (ASI) Sequence (Command 25) Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 25H CS# SCLK SI SO High - Z RDY/BSY High - Z

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 31 of 75

10.7 Write Status Register (WRSR)

The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) command must previousl y have been executed. After the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) command has no effect on S15, S10, S1 and S0 of the Status Register. CS# must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register (WRSR) command is not executed. If CS# is driven high after eighth bit of the data byte, the CMP and QE and SRP1 bits will be cleared to 0. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. Th e Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read -only, as defined in Table1. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is entered. The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→CS# goes high. The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Write Status Regis ter cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Figure 10-7 Write Status Register (WRSR) Sequence (Command 01) Command 0 1 2 3 4 5 6 7 01H CS# SCLK SI SO High-Z 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 MSB 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 Status Register in

10.8 Read Data Bytes (READ)

The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte address on SI→ data out on SO→ to end READ operation can use CS# to high at any time during data out.

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 32 of 75 Figure 10-8 Read Data Bytes (READ) Sequence (Command 03) Command 0 1 2 3 4 5 6 7 03H CS# SCLK SI SO High - Z 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 MSB 3 2 1 0 23 22 21 MSB 7 6 5 4 3 2 1 0 24-bit address Data Out1 Data Out2

10.9 Read Data Bytes at Higher Speed (FAST_READ)

The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→3-byte address on SI→ 1-dummy byte address on SI→data out on SO→ to end FAST_READ operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Figure 10-9 Read at Higher Speed (FAST_READ) Sequence (Command 0B) Command 0 1 2 3 4 5 6 7 0BH CS# SCLK SI SO High - Z 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24-bit address MSB 6 5 4 3 2 1 0 Data Out1 6 5 4 3 2 1 0 7 6 5 7 Data Out2 CS# SCLK SI SO MSB DummyByte 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 33 of 75

10.10 Dual Read Mode (DREAD)

The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte address on SI → 8-bit dummy cycle → data out interleave on SIO1 & SIO0 → to end DREAD operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Figure 10-10 Dual Read Mode Sequence (Command 3B) Command 0 1 2 3 4 5 6 7 3BH CS# SCLK SI SO High - Z 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24- bit address MSB 5 3 1 7 5 3 1 Data Out1 Data Out2 CS# SCLK SI SO MSB Dummy Clocks 4 2 0 6 4 2 0 6 6 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 35 of 75 0 1 2 3 4 5 6 7 CS# SCLK 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 A23-16 A15-8 A7-0 M7-0 SI(IO0) SO(IO1) Command 0 1 2 3 4 5 6 7 BBH CS# SCLK SI(IO0) SO(IO1) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 A23-16 A15-8 A7-0 M7-0 CS# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SI(IO0) SO(IO1) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 SCLK Byte1 Byte2 Byte3 Byte4 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 Byte1 Byte2 Note: 2 X IO Read Performance Enhance Mode, if M5-4 = 1, 0. If not using performance enhance recommend to set M5-4 ≠ 1, 0.

10.13 Quad Read Mode (QREAD)

The QREAD instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before sending the QREAD instruction. The address is l atched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address on SI → 8-bit dummy cycle → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 36 of 75 Figure 10-13 Quad Read Mode Sequence (Command 6B) Command 0 1 2 3 4 5 6 7 6BH CS# SCLK SI(IO0) SO(IO1) High-Z 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24-Bit address 32 33 34 35 36 37 38 39 40 1 5 1 5 1 5 1 Byte1 Byte2 Byte3 Byte4 41 42 43 44 45 46 47 Dummy Clocks 0 4 0 4 0 4 0 4 4 WP#(IO2) High-Z HOLD#(IO3) High-Z CS# SCLK SI(IO0) SO(IO1) WP#(IO2) HOLD#(IO3) 2 6 2 6 2 6 2 6 6 3 7 3 7 3 7 3 7 7

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 37 of 75 10.14 4 X IO Read Mode (4READ) The 4READ instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memo ry can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4 -bit instead of previous 1- bit. The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→2+4 dummy cycles→data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out. Another sequence of issuing 4READ instruction especially useful in random access is: CS# goes low → sending 4READ instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 → “Continuous Read Mode” byte M[7:0]→ 4 dummy cycles →data out still CS# goes high → CS# goes low (reduce 4 Read instruction) →24-bit random access address. In the performance-enhancing mode, the “Continuous Read Mode” bits M[5:4] = (1,0) can make this mode continue and reduce the next 4READ instruction. Once M[5:4 ] ≠ (1,0) and afterwards CS# is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing normal command While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Figure 10-14 4 X IO Read Mode Sequence (Command EB M5-4 ≠ (1,0)) Command 0 1 2 3 4 5 6 7 EBH CS# SCLK SI(IO0) SO(IO1) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 A23-16 A15-8 A7-0 M7-0 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 WP#(IO2) HOLD#(IO3) Dummy Byte1 Byte2 Note: 1. Hi-impedance is inhibited for the two clock cycles. 2. M[5-4] = (1,0) is inhibited.

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 38 of 75 10.15 4 X IO Read Performance Enhance Mode “EBh” command supports 4 X IO Performance Enhance Mode which can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next 4 X IO Read command (after CS# is raised and then lowered) does not require the EBH command code. If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command requires the first EBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing normal command. Figure 10-15 4 x I/O Read Performance Enhance Mode Sequence ( M5-4 = (1,0) ) Command 0 1 2 3 4 5 6 7 EBH CS# SCLK SI(IO0) SO(IO1) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 A23-16 A15-8 A7-0 M7-0 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 WP#(IO2) HOLD#(IO3) Dummy Byte1 Byte2 0 1 2 3 4 5 6 7 CS# SCLK 8 9 10 11 12 13 14 15 SI(IO0) SO(IO1) WP#(IO2) HOLD#(IO3) 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 M7-0 Dummy Byte1 Byte2 A23-16 A15-8 A7-0 Note: 1. 4 X IO Read Performance Enhance Mode, if M5-4 = 1, 0. If not using performance enhance recommend to set M5-4 ≠ 1, 0.

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 39 of 75

10.16 Burst Read

The Set Burst with Wrap command is used in conjunction with “4 X IO Read” command to access a fixed length of 8/16/32/64-byte section within a 256-byte page, in standard SPI mode. The Set Burst with Wrap command sequence: CS# goes low → Send Set Burst with Wrap command → Send 24 dummy bits→ Send 8 bits “Wrap bits” → CS# goes high. W6,W5 W4=0 W4=1 (default) Wrap Aroud Wrap Length Wrap Aroud Wrap Length 0,0 Yes 8-byte No N/A 0,1 Yes 16-byte No N/A 1,0 Yes 32-byte No N/A 1,1 Yes 64-byte No N/A If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “4 X IO Read” command will use the W6-W4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap command should be issued to set W4=1. Figure 10-16 Burst Read (SBL) Sequence (Command 77) Command 0 1 2 3 4 5 6 7 77H CS# SCLK SI(IO0) SO(IO1) 8 9 10 11 12 13 14 15 X X X X X X 4 X X X X X X X 5 X W6-W4 X X X X X X 6 X X X X X X X X X WP#(IO2) HOLD#(IO3)

10.17 Page Erase (PE)

The Page Erase (PE) instruction is for erasing the data of the chosen Page to be "1". A Write Enable (WREN)

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 40 of 75 instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Erase (PE). To perform a Page Erase with the standard page size (256 bytes), an opcode of 81h must be clocked into the device followed by three address bytes comprised of 2 page address bytes that specify the page in the main memory to be erased, and 1 dummy byte. The sequence of issuing PE instruction is: CS# goes low → sending PE instruction code→ 3-byte address on SI → CS# goes high. Figure 10-17 Page Erase Sequence (Command 81) Command 0 1 2 3 4 5 6 7 81H CS# SCLK SI 8 9 29 30 31 MSB 2 1 0 24-bit address 23 22

10.18 Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI → CS# goes high. The SIO[3:1] are don't care. Figure 10-18 Sector Erase (SE) Sequence (Command 20) Command 0 1 2 3 4 5 6 7 20H CS# SCLK SI 8 9 29 30 31 MSB 2 1 0 24-bit address 23 22 The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the sector is protected by BP4, BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the sector.

10.19 Block Erase (BE32K)

The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1 ". The instruction is used for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block is a valid

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 41 of 75 address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte has been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE32K instruction is: CS# goes low → sending BE32K instruction code → 3-byte address on SI → CS# goes high. The SIO[3:1] are don't care. The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the block is protected by BP4, BP3, BP2, BP1,BP0 bits, the array data will be protected (no change) and the WEL bit still be reset. Figure 10-19 Block Erase 32K(BE32K) Sequence (Command 52 ) Command 0 1 2 3 4 5 6 7 52H CS# SCLK SI 8 9 29 30 31 MSB 2 1 0 24-bit address 23 22

10.20 Block Erase (BE)

The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3 -byte address on SI→CS# goes high. The SIO[3:1] are "don't care". The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Block Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block is protected by BP4, BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the block. Figure 10-20 Block Erase (BE) Sequence (Command D8) Command 0 1 2 3 4 5 6 7 D8H CS# SCLK SI 8 9 29 30 31 MSB 2 1 0 24-bit address 23 22

10.21 Chip Erase (CE)

The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 42 of 75 otherwise, the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low→ sending CE instruction code→ CS# goes high. The SIO[3:1] are "don't care". The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enabl e Latch (WEL) bit is reset. If the chip is protected by BP4,BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when all Block Protect(BP4, BP3, BP2, BP1, BP0) are set to “None protected”. Figure 10-21 Chip Erase (CE) Sequence (Command 60 or C7) Command 0 1 2 3 4 5 6 7 60H or C7H CS# SCLK SI

10.22 Page Program (PP)

The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0 (The eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the requested address of the page. For the very best performance, programming should be done in full pages of 256 bytes aligned on 256 byte boundaries with each Page being programmed only once. Using the Page Program (PP) command to load an entire page, within the page boundary, will save overall programming time versus loading less than a page into the program buffer. It is possible to program from one byte up to a page size in each Page programming operation. Please refer to the P25Q serial flash application note for multiple byte program operation within one page. The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at least 1-byte on data on SI→ CS# goes high. The CS# must be kept low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. T he Write in Progress (WIP) bit still can be checked during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP4, BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 43 of 75 The SIO[3:1] are "don't care". Figure 10-22 Page Program (PP) Sequence (Command 02) Command 0 1 2 3 4 5 6 7 02H CS# SCLK SI 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 3 2 1 0 7 23 22 21 24- bit address 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 6 5 4 3 2 1 0 7 CS# SCLK SI MSB Data Byte 2 6 5 4 3 2 1 0 MSB 6 5 4 3 2 1 0 6 5 4 3 2 1 0 7 Data Byte 1 Data Byte 3 Data Byte 256 MSB MSB MSB 2072 2073 2074 2075 2076 2077 2078 2079

10.23 Dual Input Page Program (DPP)

The Dual Input Page Program (DPP) instruction is similar to the standard Page Program command and can be used to program anywhere from a single byte of data up to 256 bytes of data into previously erased memory locations. The Dual-Input Page Program command allows two bits of data to be clocked into the device on every clock cycle rather than just one. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Dual Input Page Program (DPP). The Dual Input Page Programming takes tw o pins: SIO0, SIO1 as data input, which can improve programmer performance and the effectiveness of application. The other function descriptions are as same as standard page program. The sequence of issuing DPP instruction is: CS# goes low→ sending DPP instruction code→ 3-byte address on SI→at least 1-byte on data on SIO[1:0]→ CS# goes high. Figure 10-23 Page Program (DPP) Sequence (Command A2)

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 44 of 75 Command 0 1 2 3 4 5 6 7 A2H CS# SCLK 8 9 10 3 2 1 0 23 22 21 24- bitaddress 6 4 MSB SI(IO0) SO(IO1) 7 5 2 0 3 1 6 4 7 5 2 0 3 1 Byte1 Byte2 CS# SCLK SI(IO0) SO(IO1) 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 6 4 7 5 2 0 3 1 6 4 7 5 2 0 3 1 6 4 7 5 2 0 3 1 6 4 7 5 Byte5 Byte6 2 0 3 1 6 4 7 5 Byte255 2 0 3 1 6 4 7 5 2 0 3 1 Byte256 28 29 30 31 32 33 34 35 36 37 38 39 1048 1049 1050 1051 1052 1053 1054 1055

10.24 Quad Page Program (QPP)

The Quad Page Program (QPP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (QPP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3 as data input, which can improve programmer performance and the effectiveness of application. The QPP operation frequency supports as fast as fQPP. The other function descriptions are as same as standard page program. The sequence of issuing QPP instruction is: CS# goes low→ sending QPP instruction code→ 3 -byte address on SIO0 → at least 1-byte on data on SIO[3:0]→CS# goes high. Figure 10-24 Quad Page Program (QPP) Sequence (Command 32)

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 45 of 75 Command 0 1 2 3 4 5 6 7 32H CS# SCLK 8 9 10 3 2 1 0 23 22 21 24- bit address 4 0 MSB SI(IO0) SO(IO1) WP#(IO2) HOLD#(IO3) 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 Byte1 Byte2 CS# SCLK SI(IO0) SO(IO1) WP#(IO2) HOLD#(IO3) 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 Byte11 Byte12 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 Byte253 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 Byte256 28 29 30 31 32 33 34 35 36 37 38 39 536 537 538 539 540 541 542 543

10.25 Erase Security Registers (ERSCUR)

The product provides three512-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Erase Security Registers command sequence: CS# goes low → sending ERSCUR instruction CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Erase Security Registers command is not executed. As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. The Security Registers Lock Bit (LB3-1) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security Registers command will be ignored. Address A23-16 A15-12 A11-9 A8-0

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 46 of 75 Security Register 00H 0001 000 Don’t care Security Register 00H 0010 000 Don’t care Security Register 00H 0011 000 Don’t care Figure 10-25 Erase Security Registers (ERSCUR) Sequence (Command 44) Command 0 1 2 3 4 5 6 7 44H CS# SCLK SI 8 9 29 30 31 MSB 2 1 0 24 bit address 23 22

10.26 Program Security Registers (PRSCUR)

The Program Security Registers command is similar to the Page Program command. It allows from 1 to 512bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The Program Security Registers command sequence: CS# goes low → sending PRSCUR instruction As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked. Program Security Registers command will be ignored. Address A23-16 A15-12 A11-9 A8-0 Security Register 00H 0001 000 Byte Address Security Register 00H 0010 000 Byte Address Security Register 00H 0011 000 Byte Address

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 47 of 75 Figure 10-26 Program Security Registers (PRSCUR) Sequence (Command 42) Command 0 1 2 3 4 5 6 7 42H CS# SCLK SI 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 3 2 1 7 23 22 21 24- bit address 6 5 4 3 2 1 0 7 CS# SCLK SI MSB Data Byte 2 6 5 4 3 2 1 0 MSB 6 5 4 3 2 1 0 6 5 4 3 2 1 0 7 Data Byte 1 Data Byte 3 Data Byte 256 MSB MSB MSB 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 2073 2074 2075 2076 2077 2078 2079

10.27 Read Security Registers (RDSCUR)

The Read Security Registers command is similar to Fast Read command. The command is followed by a 3 - byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Once the A8-A0 address reaches the last byte of the register (Byte 1FFH), it will reset to 000H, the command is completed by driving CS# high. The sequence of issuing RDSCUR instruction is : CS# goes low → sending RDSCUR instruction → sending 24 bit address → 8 bit dummy byte → Security Register data out on SO → CS# goes high. Address A23-16 A15-12 A11-9 A8-0 Security Register 00H 0001 000 Byte Address Security Register 00H 0010 000 Byte Address Security Register 00H 0011 000 Byte Address Figure 10-27 Read Security Registers (RDSCUR) Sequence (Command 48)

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 48 of 75 Command 0 1 2 3 4 5 6 7 48H CS# SCLK SI SO High-Z 8 9 10 28 29 30 31 3 2 1 0 24- bitaddress MSB 6 5 4 3 2 1 0 Data Out1 6 5 4 3 2 1 0 7 6 5 7 Data Out2 CS# SCLK SI SO MSB DummyByte 23 22 21 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

10.28 Deep Power-down (DP)

The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power- down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out). When Power- down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not be executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2. Figure 10-28 Deep Power-down (DP) Sequence (Command B9) Command 0 1 2 3 4 5 6 7 B9H CS# SCLK SI tDP Standby mode Deep power-down mode

10.29 Release form Deep Power-Down (RDP), Read Electronic Signature (RES)

The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven high, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max). Once in the

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 49 of 75 Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power -down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/ write cycle in progress. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2 (max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power-Down Mode. Figure 10-29 Read Electronic Signature (RES) Sequence (Command AB) Command 0 1 2 3 4 5 6 7 ABH CS# SCLK SI 8 9 29 30 31 32 33 34 35 36 37 38 MSB 2 1 0

3 Dummy Bytes

Standby Mode Deep Power-down mode High-Z Electronic Signature Out Figure 10-30 Release from Deep Power-down (RDP) Sequence (Command AB) Command 0 1 2 3 4 5 6 7 ABH CS# SCLK SI tRES1 Stand-by mode Deep Power- down mode

10.30 Read Electronic Manufacturer ID & Device ID (REMS)

The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID values are listed in "Table ID Definitions". The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by two du mmy bytes and one address byte (A7~A0). After which the manufacturer ID for PUYA (85h) and the device ID are shifted out on the falling edge of SCLK with the most significant bit (MSB) first. If the address byte is 00h, the manufacturer ID will be output f irst, followed by the device ID. If the address byte is 01h, then the device ID will be output first, followed by the manufacturer ID. While CS# is low, the manufacturer and device IDs can be read continuously, alternating from one to the other. The instru ction is completed by driving CS# high .

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 50 of 75 Figure 10-31 Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90) Command 90H CS# SCLK SI SO High-Z 3 2 1 0 23 22 21 2 dummy byte and 1 address byte MSB 6 5 4 3 2 1 0 Device ID CS# SCLK SI SO MSB Manufacturer ID 6 5 4 3 2 1 0 7 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

10.31 Dual I/O Read Electronic Manufacturer ID & Device ID (DREMS)

The DREMS instruction is similar to the REMS command and returns the JEDEC assigned manufacturer ID which takes two pins: SIO0, SIO1 as address input and ID output I/O The instruction is initiated by driving the CS# pin low and shift the instruction code "92h" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for PUYA (85h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Figure 10-32 DUAL I/O Read Electronic Manufacturer & Device ID (DREMS) Sequence (Command 92)

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 51 of 75 Command 92H CS# SCLK SI(IO0) SO(IO1) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 Dummy byte ADD byte M7-0 CS# SI(IO0) SO(IO1) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 SCLK MFRID DeviceID 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 MFRID (Repeat) DeviceID (Repeat) MFRID (Repeat) DeviceID (Repeat) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Dummy byte

10.32 Quad I/O Read Electronic Manufacturer ID & Device ID (QREMS)

The QREMS instruction is similar to the REMS command and returns the JEDEC assigned manufacturer ID which takes four pins: SIO0, SIO1,SIO2,SIO3 as address input and ID output I/O The instruction is initiated by driving the CS# pin low and shift the instruction code "94h" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for PUYA (85h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Figure 10-33 QUAD I/O Read Electronic Manufacturer & Device ID (QREMS) Sequence (Command 94)

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 52 of 75 Command 94H CS# SCLK SI(IO0) SO(IO1) 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 A23-16 A15-8 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 WP#(IO2) HOLD#(IO3) Dummy MFRID DID CS# SCLK SI(IO0) SO(IO1) WP#(IO2) HOLD#(IO3) 7 24 25 26 27 28 29 30 31 4 0 4 0 5 1 5 1 6 2 6 2 3 7 3 MFRID Repeat Repeat Repeat Repeat DID 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 MFRID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 DID A7-0 M7-0

10.33 Read Identification (RDID)

The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The PUYA Manufacturer ID and Device ID are list as “as "Table . ID Definitionsi”. The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data out on SO→ to end RDID operation can use CS# to high at any time during data out. While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. Figure 10-34 Read Identification (RDID) Sequence (Command 9F)

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 53 of 75 0 1 2 3 4 5 6 7 CS# SCLK SI SO 8 9 10 11 12 13 14 15 MSB 6 5 4 3 2 1 0 Capacity ID CS# SCLK SI SO MSB Memory Type ID 6 5 4 3 2 1 0 7 9FH 6 5 4 3 2 1 0 7 Manufacturer ID MSB 22 23 24 25 26 27 28 29 30 31 16 17 18 19 20 21 Table ID Definitions P25Q40L RDID command manufacturer ID memory type memory density 85 60 13 RES command electronic ID REMS command manufacturer ID device ID 85 12 P25Q20L RDID command manufacturer ID memory type memory density 85 60 12 RES command electronic ID REMS command manufacturer ID device ID 85 11 P25Q10L RDID command manufacturer ID memory type memory density 85 60 11 RES command electronic ID REMS command manufacturer ID device ID 85 10 P25Q05L RDID command manufacturer ID memory type memory density 85 60 10 RES command electronic ID REMS command manufacturer ID device ID 85 09

10.34 Program/Erase Suspend/Resume

The Suspend instruction interrupts a Page Program, Sector Erase, or Block Erase operation to allow access to the memory array. After the program or erase operation has entered the suspended state, the memory array can be read except for the page being programmed or the sector or block being erased.

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 54 of 75 Readable Area of Memory While a Program or Erase Operation is Suspended Suspended Operation Readable Region of Memory Array Page Program All but the Page being programmed Page Erase All but the Page being erased Sector Erase(4KB) All but the 4KB Sector being erased Block Erase(32KB) All but the 32KB Block being erased Block Erase(64KB) All but the 64KB Block being erased When the Serial NOR Flash receives the Suspend instruction, there is a latency of tPSL or tESL before the Write Enable Latch (WEL) bit clears to “0” and the SUS2 or SUS1 sets to “1”, after which the device is ready to accept one of the commands listed in "Table Acceptable Commands During Program/Erase Suspend after tPSL/tESL" (e.g. FAST READ). Refer to " AC Characteristics" for tPSL and tESL timings. "Table Acceptable Commands During Suspend (tPSL/tESL not required)" lists the commands for which the tPSL and tESL latencies do not apply. For example, RDSR, RDSCUR, RSTEN, and RST can be issued at any time after the Suspend instruction. Status Register bit 15 (SUS2) and bit 10 (SUS1) can be read to check the suspend status. The SUS2 (Program Suspend Bit) sets to “1” when a program operation is suspended. The SUS1 (Erase Suspend Bit) sets to “1” when an erase operation is suspended. The SUS2 or SUS1 clears to “0” when the program or erase operation is resumed. Acceptable Commands During Program/Erase Suspend after tPSL/tESL Command name Command Code Suspend Type Program Suspend Erase Suspend READ 03H • • FAST READ 0BH • • DREAD 3BH • • QREAD 6BH • • 2READ BBH • • 4READ EBH • • RDSFDP 5AH • • RDID 9FH • • REMS 90H • • DREMS 92H • • QREMS 94H • • RDSCUR 48H • • SBL 77H • • WREN 06H • RESUME 7AH OR 30H • • PP 02H • DPP A2H • QPP 32H • Acceptable Commands During Suspend（tPSL/tESL not required） Command name Command Code Suspend Type Program Suspend Erase Suspend WRDI 04H • • RDSR 05H • •

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 55 of 75 RDSR2 35H • • ASI 25H • • RES ABH • • RSTEN 66H • • RST 99H • • NOP 00H • • Figure 10-35 Resume to Suspend Latency Resume CommandCS# Suspend Command tPRS / tERS tPRS: Program Resume to another Suspend tERS: Erase Resume to another Suspend

10.35 Erase Suspend to Program

The “Erase Suspend to Program” feature allows Page Programming while an erase operation is suspended. Page Programming is permitted in any unprotected memory except within the sector of a suspended Sector Erase operation or within the block of a suspended Block Erase operation. The Write Enable (WREN) instruction must be issued before any Page Program instruction. A Page Program operation initiated within a suspended erase cannot itself be suspended and must be allowed to finish before the suspended erase can be resumed. The Status Register can be polled to determine the status of the Page Program operation. The WEL and WIP bits of the Status Register will remain “1” while the Page Program operation is in progress and will both clear to “0” when the Page Program operation completes. Figure 10-36 Suspend to Read/Program Latency Suspend CommandCS# Read/Program command tPSL / tESL tPSL: Program latency tESL: Erase latency Notes: 1. Please note that Program only available after the Erase-Suspend operation 2. To check suspend ready information, please read status register bit15 (SUS2) and bit10(SUS1)

10.36 Program Resume and Erase Resume

The Resume instruction resumes a suspended Page Program, Sector Erase, or Block Erase operation. Before issuing the Resume instruction to restart a suspended erase operation, make sure that there is no Page Program operation in progress. Immediately after the Serial NOR Flash receives the Resume instruction, the WEL and WIP bits are set to “1” and the SUS2 or SUS1 is cleared to “0”. The program or erase operation will continue until finished ("Resume to Read Latency") or until another Suspend instruction is received. A resume -to-suspend latency

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 56 of 75 of tPRS or tERS must be observed before issuing another Suspend instruction ("Resume to Suspend Latency"). Figure 10-37 Resume to Read Latency Resume CommandCS# Read Command tSE /tBE / tPP

10.37 No Operation (NOP)

The "No Operation" command is only able to terminate the Reset Enable (RSTEN) command and will not affect any other command. The SIO[3:1] are don't care.

10.38 Software Reset (RSTEN/RST)

The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST) command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which makes the device return to the default status as power on. To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the Reset operation. If there is any other command to interrupt after the Reset -Enable command, the Reset- Enable will be invalid. The SIO[3:1] are "don't care". If the Reset command is executed during program or erase operation, the operation will be disabled, the data under processing could be damaged or lost. Figure 10-38 Software Reset Recovery CS# Mode tReady 66H 99H Stand-by Mode Figure 10-39 Reset Sequence Command 0 1 2 3 4 5 6 7 66H CS# SCLK SI SO High-Z Command 0 1 2 3 4 5 6 7 99H

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 57 of 75

10.39 Read Unique ID (RUID)

The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each P25Qxx device. The Unique ID can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID command sequence: CS# goes low → sending Read Unique ID command →Dummy Byte1 →Dummy Byte2 →Dummy Byte3 → Dummy Byte4 → 128bit Unique ID Out → CS# goes high. The command sequence is show below. Figure 10-40 Read Unique ID (RUID) Sequence (Command 4B) Command 0 1 2 3 4 5 6 7 4BH CS# SCLK SI SO High-Z 8 9 10 28 29 30 31 3 bytes dummy MSB 128 bit unique serial number 127 1 0 2 CS# SCLK SI SO DummyByte 32 33 34 35 36 37 38 39 40 41 42 43 164 165 166 126 125 124

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 58 of 75

10.40 Read SFDP Mode (RDSFDP)

The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. The sequence of issuing RDSFDP instruction is same as FAST_READ: CS# goes low→ send RDSFDP instruction (5Ah)→send 3 address bytes on SI pin→ send 1 dummy byte on SI pin→ read SFDP code on SO→ to end RDSFDP operation can use CS# to high at any time during data out. SFDP is a JEDEC Standard, JESD216B. Figure 10-41 Read Serial Flash Discoverable Parameter (RDSFDP) Sequence Command 0 1 2 3 4 5 6 7 5AH CS# SCLK SI SO High - Z 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24-bit address MSB 6 5 4 3 2 1 0 Data Out1 6 5 4 3 2 1 0 7 6 5 7 Data Out2 CS# SCLK SI SO MSB DummyByte 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 59 of 75 Figure 10-42 Serial Flash Discoverable Parameter (SFDP) Table Table Signature and Parameter Identification Data Values Description Comment Add(H) (Byte) DW Add (Bit) Data Data SFDP Signature Fixed:50444653H 00H 07:00 53H 53H 01H 15:08 46H 46H 02H 23:16 44H 44H 03H 31:24 50H 50H SFDP Minor Revision Number Start from 00H 04H 07:00 00H 00H SFDP Major Revision Number Start from 01H 05H 15:08 01H 01H Number of Parameters Headers Start from 00H 06H 23:16 01H 01H Unused Contains 0xFFH and can never be changed 07H 31:24 FFH FFH ID number (JEDEC) 00H: It indicates a JEDEC specified header 08H 07:00 00H 00H Parameter Table Minor Revision Number Start from 0x00H 09H 15:08 00H 00H Parameter Table Major Revision Number Start from 0x01H 0AH 23:16 01H 01H Parameter Table Length (in double word) How many DWORDs in the Parameter table 0BH 31:24 09H 09H Parameter Table Pointer (PTP) First address of JEDEC Flash Parameter table 0CH 07:00 30H 30H 0DH 15:08 00H 00H 0EH 23:16 00H 00H Unused Contains 0xFFH and can never be changed 0FH 31:24 FFH FFH ID Number (PUYADevice Manufacturer ID) It is indicates PUYA manufacturer ID 10H 07:00 85H 85H Parameter Table Minor Revision Number Start from 0x00H 11H 15:08 00H 00H Parameter Table Major Revision Number Start from 0x01H 12H 23:16 01H 01H Parameter Table Length (in double word) How many DWORDs in the Parameter table 13H 31:24 03H 03H Parameter Table Pointer (PTP) First address of PUYA Flash Parameter table 14H 07:00 60H 60H 15H 15:08 00H 00H 16H 23:16 00H 00H Unused Contains 0xFFH and can never be changed 17H 31:24 FFH FFH

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 60 of 75 Table Parameter Table (0): JEDEC Flash Parameter Tables Description Comment Add(H) (Byte) DW Add (Bit Data Data Block/Sector Erase Size 00: Reserved; 01: 4KB erase; 10: Reserved; 11: not support 4KB erase 30H 01:00 01b E5H Write Granularity 0: 1Byte, 1: 64Byte or larger 02 1b Write Enable Instruction Requested for Writing to Volatile Status Registers 0: Nonvolatile status bit 1: Volatile status bit (BP status register bit) 03 0b Write Enable Opcode Select for Writing to Volatile Status Registers 0: Use 50H Opcode, 1: Use 06H Opcode, Note: If target flash status register is Nonvolatile, then bits 3 and 4 must be set to 00b. 04 0b Unused Contains 111b and can never be changed 07:05 111b 4KB Erase Opcode 31H 15:08 20H 20H (1-1- 2) Fast Read 0=Not support, 1=Support 32H 16 1b F1H Address Bytes Number used in addressing flash array 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte only, 11: Reserved 18:17 00b Double Transfer Rate (DTR) clocking 0=Not support, 1=Support 19 0b (1-2- 2) Fast Read 0=Not support, 1=Support 20 1b (1-4- 4) Fast Read 0=Not support, 1=Support 21 1b (1-1- 4) Fast Read 0=Not support, 1=Support 22 1b Unused 23 1b Unused 33H 31:24 FFH FFH Flash Memory Density 37H:34H 31:00 003FFFFFH (1-4- 4) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 38H 04:00 00100b 44H (1-4- 4) Fast Read Number of Mode Bits 000b:Mode Bits not support 07:05 010b (1-4- 4) Fast Read Opcode 39H 15:08 EBH EBH (1-1- 4) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 3AH 20:16 01000b 08H (1-1- 4) Fast Read Number of Mode Bits 000b:Mode Bits not support 23:21 000b (1-1- 4) Fast Read Opcode 3BH 31:24 6BH 6BH

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 61 of 75 Description Comment Add(H) (Byte) DW Add (Bit) Data Data (1-1- 2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support 3CH 04:00 01000b 08H (1-1- 2) Fast Read Number of Mode Bits 000b: Mode Bits not support 07:05 000b (1-1- 2) Fast Read Opcode 3DH 15:08 3BH 3BH (1-2- 2) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 3EH 20:16 00000b 80H (1-2- 2) Fast Read Number of Mode Bits 000b: Mode Bits not support 23:21 100b (1-2- 2) Fast Read Opcode 3FH 31:24 BBH BBH (2-2- 2) Fast Read 0=not support 1=support 40H 00 0b EEH Unused 03:01 111b (4-4- 4) Fast Read 0=not support 1=support 04 0b Unused 07:05 111b Unused 43H:41H 31:08 0xFFH 0xFFH Unused 45H:44H 15:00 0xFFH 0xFFH (2-2- 2) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 46H 20:16 00000b 00H (2-2- 2) Fast Read Number of Mode Bits 000b: Mode Bits not support 23:21 000b (2-2- 2) Fast Read Opcode 47H 31:24 FFH FFH Unused 49H:48H 15:00 0xFFH 0xFFH (4-4- 4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support 4AH 20:16 00000b 00H (4-4- 4) Fast Read Number of Mode Bits 000b: Mode Bits not support 23:21 000b (4-4- 4) Fast Read Opcode 4BH 31:24 FFH FFH Sector Type 1 Size Sector/block size=2^N bytes 0x00b: this sector type don’t exist 4CH 07:00 0CH 0CH Sector Type 1 erase Opcode 4DH 15:08 20H 20H Sector Type 2 Size Sector/block size=2^N bytes 0x00b: this sector type don’t exist 4EH 23:16 0FH 0FH Sector Type 2 erase Opcode 4FH 31:24 52H 52H Sector Type 3 Size Sector/block size=2^N bytes 0x00b: this sector type don’t exist 50H 07:00 10H 10H Sector Type 3 erase Opcode 51H 15:08 D8H D8H Sector Type 4 Size Sector/block size=2^N bytes 0x00b: this sector type don’t exist 52H 23:16 08H 08H Sector Type 4 erase Opcode 53H 31:24 81H 81H

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 62 of 75 Table Parameter Table (1): PUYA Flash Parameter Tables Description Comment Add(H) (Byte) DW Add (Bit) Data Data Vcc Supply Maximum Voltage 2000H=2.000V 2700H=2.700V 3600H=3.600V 61H:60H 15:00 2000 2000H Vcc Supply Minimum Voltage 1650H=1.650V 2250H=2.250V 2350H=2.350V 2700H=2.700V 63H:62H 31:16 1650 1650H HW Reset# pin 0=not support 1=support 65H:64H 00 0b F99EH HW Hold# pin 0=not support 1=support 01 1b Deep Power Down Mode 0=not support 1=support 02 1b SW Reset 0=not support 1=support 03 1b SW Reset Opcode Should be issue Reset Enable(66H) before Reset cmd. 11:04 1001 1001b (99H) Program Suspend/Resume 0=not support 1=support 12 1b Erase Suspend/Resume 0=not support 1=support 13 1b Unused 14 1b Wrap Around Read mode 0=not support 1=support 15 1b Wrap - Around Read mode Opcode 66H 23:16 77H 77H Wrap - Around Read data length 08H:support 8B wrap- around read 16H:8B&16B 32H:8B&16B&32B 64H:8B&16B&32B&64B 67H 31:24 64H 64H Individual block lock 0=not support 1=support 6BH:68H 00 0b CBFCH Individual block lock bit (Volatile/Nonvolatile) 0=Volatile 1=Nonvolatile 01 0b Individual block lock Opcode 09:02 FFH Individual block lock Volatile protect bit default protect status 0=protect 1=unprotect 10 0b Secured OTP 0=not support 1=support 11 1b Read Lock 0=not support 1=support 12 0b Permanent Lock 0=not support 1=support 13 0b Unused 15:14 11b Unused 31:16 FFFFH FFFFH

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 63 of 75 P = Puya Semiconductor P 25 Q 40 A – SS H – I T Company Designator 25 = SPI interface flash Product Family Q = Q serial Product Serial 40 = 4 M bit Memory Density A = A Version Generation 20 = 2 M bit 10 = 1 M bit 05 = 512 K bit SS = SOP8 150mil Package Type H: RoHS Compliant, Halogen-free, Antimony- free Plating Technology I = - 40 ~ 85C Device Grade K = - 40 ~ 105C T = TUBE Packing Type R = TAPE & REEL W = WAFER L Operation Voltage L=1.65V~2.0V Default = blank SU = SOP8 208mil UX = USON8 3x2x0.55mm UW = USON8 3x2x0.45mm NX = USON8 4x3x0.55mm WX = WSON8 6x5x0.75mm TS = TSSOP8 WF = WAFER Note：For UV=USON 3x2x0.45 (max) package, please consult PUYA sales for details.

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 64 of 75

12 Valid Part Numbers and Top Marking

The following table provides the valid part numbers for the P25Q40L/20L/10L/05L Flash Memory. Please contact PUYA for specific availability by density and package type. PUYA Flash memories use a 14-digit Product Number for ordering. 4M bit Flash Valid Part Number Package Type Product Number Density Top Side Marking Temp. Packing Type SS SOP8 150mil P25Q40L-SSH-IT 4M-bit P25Q40L xxxxxxx 85C Tube SS SOP8 150mil P25Q40L-SSH-IR 4M-bit P25Q40L xxxxxxx 85C Reel SU SOP8 208mil P25Q40L-SUH-IT 4M-bit P25Q40L xxxxxxx 85C Tube SU SOP8 208mil P25Q40L-SUH-IR 4M-bit P25Q40L xxxxxxx 85C Reel TS TSSOP8 P25Q40L-TSH-IT 4M-bit P25Q40L xxxxxxx 85C Tube TS TSSOP8 P25Q40L-TSH-IR 4M-bit P25Q40L xxxxxxx 85C Reel UX USON8 3x2x0.55mm P25Q40L-UXH-IR 4M-bit PQ40 xxxx 85C Reel WX WSON8 6x5mm P25Q40L-WXH-IR 4M-bit P25Q40L xxxxxxx 85C Reel

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 65 of 75 2M bit Flash Valid Part Number Package Type Product Number Density Top Side Marking Temp. Packing Type SS SOP8 150mil P25Q20L-SSH-IT 2M-bit P25Q20L xxxxxxx 85C Tube SS SOP8 150mil P25Q20L-SSH-IR 2M-bit P25Q20L xxxxxxx 85C Reel SU SOP8 208mil P25Q20L-SUH-IT 2M-bit P25Q20L xxxxxxx 85C Tube SU SOP8 208mil P25Q20L-SUH-IR 2M-bit P25Q20L xxxxxxx 85C Reel TS TSSOP8 P25Q20L-TSH-IT 2M-bit P25Q20L xxxxxxx 85C Tube TS TSSOP8 P25Q20L-TSH-IR 2M-bit P25Q20L xxxxxxx 85C Reel UX USON8 3x2x0.55mm P25Q20L-UXH-IR 2M-bit PQ20 xxxx 85C Reel WX WSON8 6x5mm P25Q20L-WXH-IR 2M-bit P25Q20L xxxxxxx 85C Reel UW WSON8 3x2x0.45mm P25Q20L-UWH-IR 2M-bit P25Q20L xxxxxxx 85C Reel 1M bit Flash Valid Part Number Package Type Product Number Density Top Side Marking Temp. Packing Type SS SOP8 150mil P25Q10L-SSH-IT 1M-bit P25Q10L xxxxxxx 85C Tube SS SOP8 150mil P25Q10L-SSH-IR 1M-bit P25Q10L xxxxxxx 85C Reel SU SOP8 208mil P25Q10L-SUH-IT 1M-bit P25Q10L xxxxxxx 85C Tube SU SOP8 208mil P25Q10L-SUH-IR 1M-bit P25Q10L xxxxxxx 85C Reel TS TSSOP8 P25Q10L-TSH-IT 1M-bit P25Q10L xxxxxxx 85C Tube TS TSSOP8 P25Q10L-TSH-IR 1M-bit P25Q10L xxxxxxx 85C Reel UX USON8 3x2x0.55mm P25Q10L-UXH-IR 1M-bit PQ10 xxxx 85C Reel WX WSON8 6x5mm P25Q10L-WXH-IR 1M-bit P25Q10L xxxxxxx 85C Reel

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 66 of 75 512K bit Flash Valid Part Number Package Type Product Number Density Top Side Marking Temp. Packing Type SS SOP8 150mil P25Q05L-SSH-IT 512K-bit P25Q05L xxxxxxx 85C Tube SS SOP8 150mil P25Q05L-SSH-IR 512K-bit P25Q05L xxxxxxx 85C Reel SU SOP8 208mil P25Q05L-SUH-IT 512K-bit P25Q05L xxxxxxx 85C Tube SU SOP8 208mil P25Q05L-SUH-IR 512K-bit P25Q05L xxxxxxx 85C Reel TS TSSOP8 P25Q05L-TSH-IT 512K-bit P25Q05L xxxxxxx 85C Tube TS TSSOP8 P25Q05L-TSH-IR 512K-bit P25Q05L xxxxxxx 85C Reel UX USON8 3x2x0.55mm P25Q05L-UXH-IR 512K-bit PQ05 xxxx 85C Reel WX WSON8 6x5mm P25Q05L-WXH-IR 512K-bit P25Q05L xxxxxxx 85C Reel

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 67 of 75 13.1 8-Lead SOP(150mil) REV A Symbol Min Typ Max A b c D e E L h 1.250 0.280 0.170 4.800 3.800 0.400 4.900 6.000 3.900 1.270 1.750 0.480 0.230 5.000 4.000 0.500 1.270 0.100 5.800 6.200 Note：1. Dimensions are not to scale k 8° 0.250 b e A D E h x45° C L k GAUGE PLANE 0.25mm 0.250 1.040 Common Dimensions (Unit of Measure=millimeters) TITLE 8-lead SOP DRAWING NO. SP-8

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 68 of 75 13.2 8-Lead SOP(208mil) REV A Symbol Min Typ Max A b c D e E L 1.700 0.350 0.100 5.130 5.180 0.500 1.270 2.150 0.500 0.250 5.330 5.380 0.850 0.050 7.700 8.100 Note：1. Dimensions are not to scale k 8°0° b e A D E C L k GAUGE PLANE 0.25mm 0.250- 1.900 Common Dimensions (Unit of Measure=millimeters) TITLE 8-lead SOP(208mil) DRAWING NO. SP-8

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 69 of 75 13.3 8-Lead TSSOP REV A TITLE 8-lead TSSOP DRAWING NO. TS-8 1 4 E E1 D C L α A A2 b CP Symbol Min Typ Max A b c CP D e E L α 0.050 0.800 0.190 0.090 2.900 6.200 4.300 0.450 1.000 3.000 0.650 6.400 4.400 0.600 1.000 1.200 0.150 1.050 0.300 0.200 0.100 3.100 6.600 4.500 0.750 - - Note：1. Dimensions are not to scale e Common Dimensions (Unit of Measure=millimeters)

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 70 of 75 13.4 8-Land USON(3x2x0.55mm)

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 71 of 75 13.5 8-Land USON(3x4x0.55mm)

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 72 of 75 13.6 8-Land USON (3x2x0.45mm)

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 73 of 75 13.7 8-Land WSON(6x5mm)

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 74 of 75 Rev. Date Description Note V1.0 2016-12-29 V1.0 datasheet - V1.1 2017-02-19 Change 12.4 UDFN package to USON package Change 12.5 UDFN 6*5 package to WSON package - V1.2 2017-09-06 Add 1 USON 3x2x0.45mm, 4x3x0.55mm Change 5.1 operation temperature to -40C~85C Add 11 package type UV,NX Add 12.5 USON 3x2x0.45 package Add 12.6 USON 3x4x0.55 package V1.3 2017-11-23 Page6 3.1 corrected to SOP(150mil/208mil) - 1.4 2018-01-10 Page 10 update AC parameter fTSCLK to 70MHz - 1.5 2018-05-31 P72~P75 Update Package POD - V1.6 2019-03-26 P42 PP command "For the very best performance, programming should be done in full pages of 256 bytes aligned on 256 byte boundaries with each Page being programmed only once. Using the Page Program (PP) command to load an entire page, within the page boundary, will save overall programming time versus loading less than a page into the program buffer. It is possible to program from one byte up to a page size in each Page programming operation. Please refer to the P25Q serial flash application note for multiple byte program operation within one page." P62 add Valid Part Number V1.7 2019-06-20 DC Data Update - V1.8 2019-08-02 2M Add UW=USON 3x2x0.45 package(Typ) - V1.9 2020-11-03 Update AC data and Cancel UV=USON 3x2x0.45(Max) Package -

P25Q40L/20L/10L/05L Datasheet Puya Semiconductor Page 75 of 75 IMPORTANT NOTICE Puya Semiconductor reserves the right to make changes without further notice to any products or specifications herein. Puya Semiconductor does not assume any responsibility for use of any its products for any particular purpose, nor does Puya Semiconductor assume any liability arising out of the application or use of any its products or circuits. Puya Semiconductor does not convey any license under its patent rights or other rights nor the rights of others. Puya Semiconductor Co., Ltd.