P24FJ128GL305

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 2019-2020 Microchip Technology Inc. DS30010198B-page 1 PIC24FJ128GL306 FAMILY High-Performance CPU

• Modified Harvard Architecture
• 128 Kbytes Flash Memory
• 8 Kbytes SRAM
• Up to 16 MIPS Operation @ 32 MHz
• 17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16-Bit x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture
• Two Address Generation Units (AGUs) for Separate Read and Write Addressing of Data Memory LCD Display Controller
• 32x8 with Up to 256 Pixels
• LCD Charge Pump
• Core-Independent LCD Animation
• Operation in Sleep mode Analog Features
• Up to 17-Channel, Software-Selectable, 10/12-Bit Analog-to-Digital Converter: - 12-bit, 350K samples/second conversion rate (single Sample-and-Hold) - 10-bit, 400K samples/second conversion rate (single Sample-and-Hold) - Sleep mode operation - Low-voltage boost for input - Band gap reference input feature - Core-independent windowed threshold compare feature - Auto-scan feature
• Three Analog Comparators with Input Multiplexing: - Programmable reference voltage for comparators eXtreme Low-Power Features
• Sleep and Idle modes Selectively Shut Down Peripherals and/or Core for Substantial Power Reduction and Fast Wake-up
• Doze mode Allows CPU to Run at a Lower Clock Speed than Peripherals
• Alternate Clock modes Allow On-the-Fly Switching to a Lower Clock Speed for Selective Power Reduction
• Retention Sleep with On-Chip Ultra Low-Power Retention Regulator Functional Safety and Security Peripherals
• Fail-Safe Clock Monitor Operation: - Detects clock failure and switches to on-chip, low-power RC oscillator
• Power-on Reset (POR), Brown-out Reset (BOR)
• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Programmable High/Low-Voltage Detect (HLVD)
• Flexible Watchdog Timer (WDT) with RC Oscillator for Reliable Operation
• Deadman Timer (DMT) for Monitoring Health of Software
• Programmable 32-Bit Cyclic Redundancy Check (CRC) Generator
• Flash OTP by ICSP™ Write Inhibit
• CodeGuard™ Security
• ECC Flash Memory (128 Kbytes) with Fault Injection: - Single Error Correction (SEC) - Double Error Detection (DED)
• Customer OTP Memory
• Unique Device Identifier (UDID) Special Microcontroller Features
• Supply Voltage Range of 2.0V to 3.6V
• Operating Ambient Temperature Range of -40°C to +125°C
• On-Chip Voltage Regulators (1.8V) for Low-Power Operation
• Flash Memory: - 10,000 erase/write cycle endurance, typical - Data retention: 20 years minimum - Self-programmable under software control - Flash OTP emulation
• 8 MHz Fast RC Internal Oscillator: - Multiple clock divide options - Fast start-up
• 9 6 M H z P L L O p t i o n
• Programmable Reference Clock Output
• In-Circuit Serial Programming™ (ICSP™) and In-Circuit Emulation (ICE) via Two Pins
• JTAG Boundary Scan Support 16-Bit eXtreme Low-Power Microcontrollers with LCD Controller in Low Pin Count Packages

DS30010198B-page 2  2019-2020 Microchip Technology Inc. Peripheral Features

• Independent, Low-Power 32 kHz Timer Oscillator
• Six-Channel DMA Controller: - Minimizes CPU overhead and increases data throughput
• Timer1: 16-Bit Timer/Counter with External Crystal Oscillator; Timer1 can Provide an A/D Trigger
• Timer2,3,4,5: 16-Bit Timer/Counter can Create 32-Bit Timer; Timer3 and Timer5 can Provide an A/D Trigger
• Five MCCP modules, Each with a Dedicated 16/32-Bit Timer: - One 6-output MCCP module - Four 2-output MCCP modules
• Two Variable Width, Serial Peripheral Interface (SPI) Ports on All Devices; Three Operation modes: - 3-wire SPI (supports all four SPI modes) - Up to 32-byte deep FIFO buffer -I 2S mode - Speed up to 25 MHz
• T w o I2C Master and Slave w/Address Masking, PMBus™ and IPMI Support
• Four UART modules: - LIN/J2602 bus support (auto-wake-up, Auto-Baud Detect, Break character support) - RS-232 and RS-485 support -I r D A® mode (hardware encoder/decoder functions)
• Five External Interrupt Pins
• Hardware Real-Time Clock and Calendar (RTCC)
• Peripheral Pin Select (PPS) allows Independent I/O Mapping of Many Peripherals
• Configurable Interrupt-on-Change on All I/O Pins: - Each pin is independently configurable for rising edge or falling edge change detection
• Reference Clock Output with Programmable Divider
• Four Configurable Logic Cell (CLC) Blocks: - Two inputs and one output, all mappable to peripherals or I/O pins - AND/OR/XOR logic and D/JK flip-flop functions Qualification
• AEC-Q100 REVG (Grade 1: -40°C to +125°C) Compliant TABLE 1: PIC24FJ128GL306 FAMILY DEVICES Device Memory Pins GPIO Remappable I/O (PPS) (Output/Input) DMA Channels Peripherals JTAG LCD Pixels Program (bytes) SRAM (bytes) 10/12-Bit A/D Channels Comparators CRC MCCP 6-Output/2-Output 16-Bit Timers I2C Variable Width SPI UART w/IrDA® CLC RTCC PIC24FJ128GL306 128K 8K 64 54 32/33 6 17 3 Yes 1/4 5 2 2 4 4 Yes Yes 256 PIC24FJ128GL305 128K 8K 48 39 24/25 6 12 3 Yes 1/4 5 2 2 4 4 Yes Yes 152 PIC24FJ128GL303 128K 8K 36 29 15/16 6 11 3 Yes 1/4 5 2 2 4 4 Yes Yes 80 PIC24FJ128GL302 128K 8K 28 21 13/14 6 9 3 Yes 1/4 5 2 2 4 4 Yes Yes 42 PIC24FJ64GL306 64K 8K 64 54 32/33 6 17 3 Yes 1/4 5 2 2 4 4 Yes Yes 256 PIC24FJ64GL305 64K 8K 48 39 24/25 6 12 3 Yes 1/4 5 2 2 4 4 Yes Yes 152 PIC24FJ64GL303 64K 8K 36 29 15/16 6 11 3 Yes 1/4 5 2 2 4 4 Yes Yes 80 PIC24FJ64GL302 64K 8K 28 21 13/14 6 9 3 Yes 1/4 5 2 2 4 4 Yes Yes 42

 2019-2020 Microchip Technology Inc. DS30010198B-page 3 PIC24FJ128GL306 FAMILY Pin Diagrams Note 1: See Table 2 for a complete description of pin functions. 2: Shaded pins are up to 5.5 VDC tolerant. 3: There is an internal pull-up resistor connected to the TMS pin during POR and programming. 4: RC15/OSCO will toggle during programming or debugging time. 28-Pin QFN/UQFN 10 11 12 13 14 232425262728 PIC24FJXXXGL302 RE1 RE0 RF1 RB4 AVDD/VDD VDD RC12 RC1320 RG7 RG8 MCLR RB5 RB1 RB0 RB6 RB7 AVss/Vss RB14 RB15 RG3 VSS RC14 VCAP VSS RE2 RE3 RB10(3) RC15(4) TABLE 2: 28-PIN QFN/UQFN COMPLE TE PIN FUNCTION DESCRIPTIONS P i nF u n c t i o nP i n F u n c t i o n 1V LCAP1/C1INC/C2INC/C3INC/RP26/RG7 15 TDO/SEG47/RP31/SDA1/OCM1F/INT0/RG3 2V LCAP2/C2IND/RP19/RG8 16 V DD 3M C L R 17 OSCI/CLKI/RC12

4 PGC3/SEG2/AN5/C1INA/ RP18/ASCL1(1)/OCM1A/RB5 18 OSCO/CLKO/RC15

5 PGD3/SEG3/AN4/C1INB/ RP28/ASDA1(1)/OCM1B/RB4 19 V SS

6 PGC1/SEG6/CV REF-/AN1/AN1-/C2INA/RP1/RB1 20 SOSCI/RC13

7 PGD1/SEG7/V REF+/CVREF+/AN0/C2INB/RP0/RB0 21 SOSCO/SCLKI/ RPI37/PWRLCLK/RC14

8 PGC2/LCDBIAS3/AN6/ RP6/RB6 22 V CAP

9P G D 2 / A N 7 /RP7/T1CK/RB7 23 V SS

10 AV DD/VDD 24 COM4/SEG48/ RP2/SCL1/OCM1E/RF1

11 AV SS/VSS 25 COM3/RE0

12 TMS/COM5/SEG29/CV REF/AN10/RP15/RB10 26 COM2/C3INA/RE1

13 TCK/SEG8/AN14/ RP14/SDA2/OCM1C/RB14 27 COM1/C3IND/RE2

14 TDI/SEG9/AN15/ RP29/SCL2/OCM1D/RB15 28 COM0/HLVDIN/RE3

Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions. Note 1: Alternate pin assignments for I2C1 as determined by the ALTI2C1 Configuration bit.

DS30010198B-page 4  2019-2020 Microchip Technology Inc. Pin Diagrams (Continued) Note 1: See Table 3 for a complete description of pin functions. 2: Shaded pins are up to 5.5 VDC tolerant. 3: There is an internal pull-up resistor conne cted to the TMS pin during POR and programming. 4: RC15/OSCO will toggle during programming or debugging time. 28-Pin SOIC/SSOP RF1 MCLR RB6 RE0 RE1 VSS VCAP RE2 AVDD/VDD RB0 RB1 RB15RB4 RB5 RG3 AVSS/VSS RB14 RG8 RG7 RE3 RC14 RC13 V SS VDD RC12 RB7 PIC24FJXXXGL302 RB10(3) RC15(4) TABLE 3: 28-PIN SOIC/SSOP COMPLE TE PIN FUNCTION DESCRIPTIONS Pin Function Pin Function

1 COM4/SEG48/ RP2/SCL1/OCM1E/RF1 15 AV DD/VDD

2 COM3/RE0 16 AV SS/VSS

3 COM2/C3INA/RE1 17 TMS/COM5/SEG29/CV REF/AN10/RP15/RB10

4 COM1/C3IND/RE2 18 TCK/SEG8/AN14/ RP14/SDA2/OCM1C/RB14

5 COM0/HLVDIN/RE3 19 TDI/SEG9/AN15/ RP29/SCL2/OCM1D/RB15

6V LCAP1/C1INC/C2INC/C3INC/RP26/RG7 20 TDO/SEG47/ RP31/SDA1/OCM1F/INT0/RG3 7V LCAP2/C2IND/RP19/RG8 21 V DD 8M C L R 22 OSCI/CLKI/RC12

9 PGC3/SEG2/AN5/C1INA/ RP18/ASCL1(1)/OCM1A/RB5 23 OSCO/CLKO/RC15

10 PGD3/SEG3/AN4/C1INB/ RP28/ASDA1(1)/OCM1B/RB4 24 V SS

11 PGC1/SEG6/CV REF-/AN1/AN1-/C2INA/RP1/RB1 25 SOSCI/RC13

12 PGD1/SEG7/V REF+/CVREF+/AN0/C2INB/RP0/RB0 26 SOSCO/SCLKI/ RPI37/PWRLCLK/RC14

13 PGC2/LCDBIAS3/AN6/ RP6/RB6 27 V CAP

14 PGD2/AN7/ RP7/T1CK/RB7 28 V SS

Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions. Note 1: Alternate pin assignments for I2C1 as determined by the ALTI2C1 Configuration bit.

 2019-2020 Microchip Technology Inc. DS30010198B-page 5 PIC24FJ128GL306 FAMILY Pin Diagrams (Continued) RC14 RC13 Vss RC12 VDD RG2 RG3 RB15 RC15 (4) 36-Pin UQFN 3214 PIC24FJXXXGL303 RE5 RE6 RE7 RG7 RG8 MCLR RB5 RB4 RB1 RB0 RB6 RB7 AVDD/VDD AVSS/VSS RB8 RB9 RB14 RE3 RE2 RE1 RE0 RF1 V SS VCAP RD7 RD6 RB10(3) Note 1: See Table 4 for a complete description of pin functions. 2: Shaded pins are up to 5.5 VDC tolerant. 3: There is an internal pull-up resistor connect ed to the TMS pin during POR and programming. 4: RC15/OSCO will toggle during programming or debugging time.

DS30010198B-page 6  2019-2020 Microchip Technology Inc. TABLE 4: 36-PIN UQFN COMPLETE PIN FUNCTION DESCRIPTIONS Pin Function Pin Function

1 LCDBIAS2/RE5 19 TDI/SEG9/AN15/ RP29/SCL2/OCM1D/RB15

2 LCDBIAS1/RE6 20 TDO/SEG47/ RP31/SDA1/OCM1F/INT0/RG3

3 LCDBIAS0/RE7 21 SEG28/SCL1/RG2

LCAP1/C1INC/C2INC/C3INC/RP26/RG7 22 V DD 5V LCAP2/C2IND/RP19/RG8 23 OSCI/CLKI/RC12 6M C L R 24 OSCO/CLKO/RC15

7 PGC3/SEG2/AN5/C1INA/ RP18/ASCL1(1)/OCM1A/RB5 25 V SS

8 PGD3/SEG3/AN4/C1INB/ RP28/ASDA1(1)/OCM1B/RB4 26 SOSCI/RC13

9 PGC1/SEG6/CV REF-/AN1/AN1-/C2INA/RP1/RB1 27 SOSCO/SCLKI/ RPI37/PWRLCLK/RC14

10 PGD1/SEG7/V REF+//CVREF+/AN0/C2INB/RP0/RB0 28 SEG25/C3INB/RD6

11 PGC2/LCDBIAS3/AN6/ RP6/RB6 29 SEG26/C3INA/RD7

12 PGD2/AN7/ RP7/T1CK/RB7 30 V CAP

13 AV DD/VDD 31 V SS

14 AV SS/VSS 32 COM4/SEG48/ RP2/OCM1E/RF1

15 COM7/SEG31/AN8/ RP8/RB8 33 COM3/RE0

16 COM6/SEG30/AN9/ RP9/RB9 34 COM2/RE1

17 TMS/COM5/SEG29/CVREF/AN10/ RP15/RB10 35 COM1/C3IND/RE2

18 TCK/SEG8/AN14/ RP14/SDA2/OCM1C/RB14 36 COM0/HLVDIN/RE3

Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions. Note 1: Alternate pin assignments for I2C1 as determined by the ALTI2C1 Configuration bit.

 2019-2020 Microchip Technology Inc. DS30010198B-page 7 PIC24FJ128GL306 FAMILY Pin Diagrams (Continued) 48-Pin TQFP/UQFN 48 47 46 45 43 42 41 40 39 38 13 14 15 16 17 18 19 21 22 23 2 35 VSS RC13 RC14 VSS VCAP RB0 RB1 RB4 RB5 VSS MCLR RG8 RG7 RE7 RE6 RB6 RB7 AVDD RB8 RB9 PIC24FJXXXGL305 8VDD RB11

32 RD10

RB10(3) RC15(4) Note 1: See Table 5 for a complete description of pin functions. 2: Shaded pins are up to 5.5 VDC tolerant. 3: There is an internal pull-up resistor connect ed to the TMS pin during POR and programming. 4: RC15/OSCO will toggle during programming or debugging time.

DS30010198B-page 8  2019-2020 Microchip Technology Inc. TABLE 5: 48-PIN TQFP/UQFN COMPLE TE PIN FUNCTION DESCRIPTIONS Pin Function Pin Function

1 LCDBIAS2/RE5 25 SEG12/ RP16/RF3

2 LCDBIAS1/RE6 26 SEG47/ RP31/SDA1/OCM1F/INT0/RG3

3 LCDBIAS0/RE7 27 SEG28/SCL1/RG2

LCAP1/C1INC/C2INC/C3INC(2)/RP26/RG7 28 V DD 5V LCAP2/AN19/C2IND/RP19/RG8 29 OSCI/CLKI/RC12 6M C L R 30 OSCO/CLKO/RC15 7V SS 31 V SS 8V DD 32 SEG15/C3IND/ RP3/RD10

9 PGC3/SEG2/AN5/C1INA/ RP18/SCL1(1)/OCM1A/RB5 33 SEG16/C3INC/ RP12/RD11

10 PGD3/SEG3/AN4/C1INB/ RP28/SDA1(1)/OCM1B/RB4 34 SEG17/ RP11/RD0

11 PGC1/SEG6/CV REF-/AN1/AN1-/C2INA/RP1/RB1 35 SOSCI/RC13

12 PGD1/SEG7/V REF+/CVREF+/AN0/C2INB/RP0/RB0 36 SOSCO/SCLKI/ RPI37/PWRLCLK/RC14

13 PGC2/LCDBIAS3/AN6/C1IND/ RP6/RB6 37 SEG22/ RP22/RD3

14 PGD2/AN7/ RP7/T1CK/RB7 38 SEG23/ RP25/RD4

15 AV DD 39 SEG24/ RP20/RD5

16 AV SS 40 SEG25/C3INB/RD6

17 COM7/SEG31/AN8/ RP8/RB8 41 SEG26/C3INA/RD7

18 COM6/SEG30/AN9/ RP9/RB9 42 V CAP

19 TMS/COM5/SEG29/CV REF/AN10/RP15/RB10 43 V SS

20 TDO/AN11/RB11 44 COM4/SEG48/ RP2/OCM1E/RF1

21 TCK/SEG8/AN14/ RP14/OCM1C/RB14 45 COM3/RE0

22 TDI/SEG9/AN15/ RP29/OCM1D/RB15 46 COM2/RE1

23 SEG10/ RP10/SDA2/RF4 47 COM1/RE2

24 SEG11/ RP17/SCL2/RF5 48 COM0/HLVDIN/RE3

Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions. Note 1: Alternate pin assignments for I2C1 as determined by the ALTI2C1 Configuration bit. 2: Alternate pin assignments for C3INC as determined by the ALTCMPI Configuration bit.

 2019-2020 Microchip Technology Inc. DS30010198B-page 9 PIC24FJ128GL306 FAMILY Pin Diagrams (Continued) 64-Pin TQFP/QFN Note 1: See Table 6 for a complete description of pin functions. 2: Shaded pins are up to 5.5 VDC tolerant. 3: There is an internal pull-up resistor connect ed to the TMS pin during POR and programming. 4: RC15/OSCO will toggle during programming or debugging time. MCLR RE5 RE6 RE7 RG6 RG7 RG8 RG9 VSS VDD RB5 RB4 RB3 RB2 RB1 RB0 RD8 RC14 RC13 RD0 RD11 RD10 RD9 V SS RC12 VDD RG2 RG3 RF6 RF2 RF3 RB6 RB7 AVDD AVSS RB8 RB9 RB11 VSS VDD RB12 RB13 RB14 RB15 RF4 RF5 RA0 RE4 RE3 RE2 RE1 RF1 RF0 VCAP RD7 RD6 RD5 RD4 RD3 RD2 RD1 RE0 PIC24FJXXXGL306 RB10(3) RC15(4)

DS30010198B-page 10  2019-2020 Microchip Technology Inc. TABLE 6: 64-PIN TQFP/QFN COMPLE TE PIN FUNCTION DESCRIPTIONS Pin Function Pin Function

1 LCDBIAS2/RE5 33 SEG12/ RP16/RF3

2 LCDBIAS1/RE6 34 SEG40/ RP30/RF2

3 LCDBIAS0/RE7 35 RP5/INT0/RF6

4 SEG0/C1IND/ RP21/RG6 36 SEG47/ RP31/SDA1/OCM1F/RG3

5V LCAP1/C1INC/C2INC(2)/C3INC(2)/RP26/RG7 37 SEG28/SCL1/RG2 6V LCAP2/C2IND/RP19/RG8 38 V DD 7M C L R 39 OSCI/CLKI/RC12

8 SEG1/C2INC/ RP27/RG9 40 OSCO/CLKO/RC15

10 V DD 42 SEG13/ RP2/RD8

11 PGC3/SEG2/AN5/C1INA/ RP18/ASCL1(1)/OCM1A/RB5 43 SEG14/ RP4/RD9

12 PGD3/SEG3/AN4/C1INB/ RP28/ASDA1(1)/OCM1B/RB4 44 SEG15/C3IND/ RP3/RD10

13 SEG4/AN3/C2INA/RB3 45 SEG16/C3INC/ RP12/RD11

14 SEG5/AN2/C2INB/ RP13/RB2 46 SEG17/ RP11/RD0

15 PGC1/SEG6/CV REF-/AN1/AN1-/RP1/RB1 47 SOSCI/RC13

16 PGD1/SEG7/V REF+/CVREF+/AN0/RP0/RB0 48 SOSCO/SCLKI/ RPI37/PWRLCLK/RC14

17 PGC2/LCDBIAS3/AN6/ RP6/RB6 49 SEG20/ RP24/RD1

18 PGD2/AN7/ RP7/T1CK/RB7 50 SEG21/ RP23/RD2

19 AV DD 51 SEG22/ RP22/RD3

20 AV SS 52 SEG23/ RP25/RD4

21 COM7/SEG31/AN8/ RP8/RB8 53 SEG24/ RP20/RD5

22 COM6/SEG30/AN9/ RP9/RB9 54 SEG25/C3INB/RD6

23 TMS/COM5/SEG29/CV REF/AN10/RP15/RB10 55 SEG26/C3INA/RD7

24 TDO/AN11/RB11 56 V CAP

25 V SS 57 AN16/RA0

26 V DD 58 SEG27/RF0

27 TCK/SEG18/AN12/RB12 59 COM4/SEG48/OCM1E/RF1

28 TDI/SEG19/AN13/RB13 60 COM3/RE0

29 SEG8/AN14/ RP14/OCM1C/RB14 61 COM2/RE1

30 SEG9/AN15/ RP29/OCM1D/RB15 62 COM1/RE2

31 SEG10/ RP10/SDA2/RF4 63 COM0/RE3

32 SEG11/ RP17/SCL2/RF5 64 SEG63/HLVDIN/RE4

Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions. Note 1: Alternate pin assignments for I2C1 as determined by the ALTI2C1 Configuration bit. 2: Alternate pin assignments for C2INC and C3INC as determined by the ALTCMPI Configuration bit.

 2019-2020 Microchip Technology Inc. DS30010198B-page 11 PIC24FJ128GL306 FAMILY Table of Contents

DS30010198B-page 12  2019-2020 Microchip Technology Inc. TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regardi ng this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . The last character of the literature number is the versio n number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisi on of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Website; http://www.microchip.com
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 2019-2020 Microchip Technology Inc. DS30010198B-page 13 PIC24FJ128GL306 FAMILY Referenced Sources This device data sheet is based on the following individual chapters of the “dsPIC33/PIC24 Family Reference Manual” . These documents should be considered as the general reference for the operation of a particular module or device feature.

• “CPU with Extended Data Space (EDS)” (www.microchip.com/DS39732)
• “Direct Memory Access Controller (DMA)” (www.microchip.com/DS30009742)
• “PIC24F Flash Program Memory” (www.microchip.com/DS30009715)
• “Data Memory with Extended Data Space (EDS)” (www.microchip.com/DS39733)
• “Reset” (www.microchip.com/DS39712)
• “Interrupts” (www.microchip.com/DS70000600)
• “Oscillator” (www.microchip.com/DS39700)
• “Power-Saving Features with Deep Sleep” (www.microchip.com/DS39727)
• “I/O Ports with Peripheral Pin Select (PPS)” (www.microchip.com/DS30009711)
• “Timers” (www.microchip.com/DS39704)
• “Capture/Compare/PWM/Timer (MCCP and SCCP)” (www.microchip.com/DS30003035)
• “Serial Peripheral Interface (SPI) with Audio Codec Support” (www.microchip.com/DS70005136)
• “Inter-Integrated Circuit (I2C)” (www.microchip.com/DS70000195)
• “Universal Asynchronous Receiver Transmitter (UART)” (www.microchip.com/DS70000582)
• “RTCC with Timestamp” (www.microchip.com/DS70005193)
• “32-Bit Programmable Cyclic Redundancy Check (CRC)” (www.microchip.com/DS30009729)
• “Configurable Logic Cell (CLC)” (www.microchip.com/DS70005298)
• “12-Bit A/D Converter with Threshold Detect” (www.microchip.com/DS39739)
• “Scalable Comparator Module” (www.microchip.com/DS39734)
• “Dual Comparator Module” (www.microchip.com/DS39710)
• “High-Level Integration with Programmable High/Low-Voltage Detect (HLVD)” (www.microchip.com/DS39725)
• “Watchdog Timer (WDT)” (www.microchip.com/DS39697)
• “CodeGuard™ Intermediate Security” (www.microchip.com/DS70005182)
• “High-Level Device Integration” (www.microchip.com/DS39719)
• “Programming and Diagnostics” (www.microchip.com/DS39716)
• “Comparator Voltage Reference Module” (www.microchip.com/DS39709)
• “Deadman Timer” (www.microchip.com/DS70005155)
• “Liquid Crystal Display (LCD)” (www.microchip.com/DS30009740) Note 1: To access the documents listed below, browse to the documentation section of the PIC24FJ128GL306 product page of the Microchip website (www.microchip.com) or select a family reference manual section from the following list. In addition to parameters, features and other documentation, the resulting page provides links to the related family reference manual sections.

DS30010198B-page 14  2019-2020 Microchip Technology Inc. NOTES:

 2020 Microchip Technology Inc. DS30010198B-page 15 PIC24FJ128GL306 FAMILY

1.0 DEVICE OVERVIEW

This document contains device-specific information for the following devices: The PIC24FJ128GL306 family introduces eXtreme low-power microcontrollers with LCD controller in low pin count packages. This is a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance. This family also offers a new migration option for those high-performance applications which may be outgrowing their 8-bit platforms, but do not require the numerical processing power of a Digital Signal Processor (DSP). Table 1-1 lists the functions of the various pins shown in the pinout diagrams.

1.1 Core Features

1.1.1 16-BIT ARCHITECTURE Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip’s dsPIC® Digital Signal Controllers (DSCs). The PIC24F CPU core offers a wide range of enhancements, such as:

• 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces
• Linear addressing of up to 12 Mbytes (program space) and 32 Kbytes (data)
• A 16-element Working register array with built-in software stack support
• A 17 x 17 hardware multiplier with support for integer math
• Hardware support for 32 by 16-bit division
• An instruction set that supports multiple addressing modes and is optimized for high-level languages, such as ‘C’
• Operational performance up to 16 MIPS

1.1.2 POWER-SAVING TECHNOLOGY

The PIC24FJ128GL306 family of devices includes Retention Sleep, a low-power mode with essential circuits being powered from a separate low-voltage regulator. This new low-power mode also supports the continuous operation of the low-power, on-chip Real-Time Clock/ Calendar (RTCC), making it possible for an application to keep time while the device is otherwise asleep. Aside from this new feature, PIC24FJ128GL306 family devices also include all of the legacy power-saving features of previous PIC24F microcontrollers, such as:

• On-the-Fly Clock Switching, allowing the selection of a lower power clock during run time
• Doze Mode Operation, for maintaining peripheral clock speed while slowing the CPU clock
• Instruction-Based Power-Saving Modes, for quick invocation of the Idle and Sleep modes

1.1.3 OSCILLATOR OPTIONS AND

FEATURES

All of the devices in the PIC24FJ128GL306 family offer six different oscillator options, allowing users a range of choices in developing application hardware. These include:

• Two Crystal modes
• External Clock (EC) mode
• A Phase-Locked Loop (PLL) frequency multiplier, which allows processor speeds up to 32 MHz
• An internal Fast RC Oscillator (FRC), a nominal

8 MHz output with multiple frequency divider options

• A separate internal Low-Power RC Oscillator (LPRC), 32 kHz nominal for low-power, timing-insensitive applications. The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor (FSCM). This option constantly monitors the main clock source against a reference signal provided by the internal oscil- lator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown.

1.1.4 EASY MIGRATION

Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating from one device to the next larger device.

• PIC24FJ128GL306 • PIC24FJ64GL306
• PIC24FJ128GL305 • PIC24FJ64GL305
• PIC24FJ128GL303 • PIC24FJ64GL303
• PIC24FJ128GL302 • PIC24FJ64GL302

DS30010198B-page 16  2020 Microchip Technology Inc.

1.2 DMA Controller

PIC24FJ128GL306 family devices have a Direct Memory Access (DMA) Controller. This module acts in concert with the CPU, allowing data to move between data memory and peripherals without the intervention of the CPU, increasing data throughput and decreasing execu- tion time overhead. Six independently programmable channels make it possible to service multiple peripherals at virtually the same time, with each channel peripheral performing a different operation. Many types of data transfer operations are supported.

1.3 LCD Controller

The versatile on-chip LCD controller includes many features that make the integration of displays in low- power applications easier. These include an integrated voltage regulator with charge pump and an integrated internal resistor ladder that allows contrast control in software, and display operation above the device V DD. Core-independent automatic display features:

• Dual display memory
• Blink mode of individual pixels or the complete pixels
• Blank of individual pixels or the complete pixels
• Timing schedule can be changed without core intervention, based on user configurations

1.4 Other Special Features

• Peripheral Pin Select: The Peripheral Pin Select (PPS) feature allows most digital peripherals to be mapped over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many digital peripherals to any one of the I/O pins.
• Configurable Logic Cell: The Configurable Logic Cell (CLC) module allows the user to specify combinations of signals as inputs to a logic function and to use the logic output to control other peripherals or I/O pins.
• Timing Modules: The PIC24FJ128GL306 family provides five independent, general purpose, 16-bit timers (four of which can be combined into two 32-bit timers). The devices also include five multiple output advanced Capture/Compare/PWM/Timer peripherals.
• Communications: The PIC24FJ128GL306 family incorporates a range of serial communication peripherals to handle a range of application requirements. There are two independent I modules that support both Master and Slave modes of operation. Devices also have, through the PPS feature, four independent UARTs with built-in IrDA ® encoders/decoders, LIN support and two SPI modules.
• Analog Features: All members of the PIC24FJ128GL306 family include a 12-bit A/D Converter (A/D) module and a triple comparator module. The A/D module incorporates a range of new features that allow the converter to assess and make decisions on incoming data, reducing CPU overhead for routine A/D conversions. The comparator module includes three analog comparators that are configurable for a wide range of operations.
• Real-Time Clock and Calendar (RTCC): This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application.
• Deadman Timer (DMT): This module is provided to interrupt the processor in the event of a software malfunction.

1.5 Details of Individual Family

Devices in the PIC24FJ128GL306 family are available in 28-pin, 36-pin, 48-pin and 64-pin packages. The general block diagram for all devices is shown in Figure 1-1. A list of the pin features available on the PIC24FJ128GL306 family devices, sorted by function, is shown in Table 1-1. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the “Pin Diagrams” section in the begin- ning of this data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first.

 2020 Microchip Technology Inc. DS30010198B-page 17 PIC24FJ128GL306 FAMILY FIGURE 1-1: PIC24FJ128GL306 FA MILY GENERAL BLOCK DIAGRAM Instruction Decode and Control PCH Program Counter 16-Bit ALU Data Bus Inst Register Divide Support Inst Latch EA MUX Interrupt Controller EDS and Stack Control Logic Repeat Control Logic Data Latch Data RAM Address Latch Address Latch Extended Data Data Latch Address Bus Literal Control Signals 16 x 16 W Reg Array Multiplier 17x17 OSCI/CLKI OSCO/CLKO VDD, VSS Timing Generation MCLR Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer HLVD and Precision Reference Band Gap FRC/LPRC Oscillators Regulators Voltage VCAP PORTA(1) (1 I/O) PORTB(1) (16 I/Os) Note 1: Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-1 for specific implementations by pin count. 2: Some peripheral I/Os are only accessible through remappable pins. 3: These peripheral I/Os are only accessible through remappable pins. Comparators(3)Timer2/3(3) Timer1 RTCC A/D 12-Bit DMT SPI I2C1-2IOCs(1) UART REFO 1-2(3) 1-4(3) LCD Space Program Memory/ CLC1-4(1) DMA Controller Data DMA Data Bus Table Data Access Control MCCP PCL BOR(2) Read AGU Write AGU PORTC(1) (4 I/Os) PORTD(1) (12 I/Os) PORTE(1) (8 I/Os) PORTF(1) (7 I/Os) PORTG(1) (6 I/Os) and 4/51/4 SOSCO/SOSCI

DS30010198B-page 18  2020 Microchip Technology Inc. TABLE 1-1: PIC24FJ128GL306 FA MILY PINOUT DESCRIPTION Pin Name Pin Type Buffer Type PPS Description AN0-AN16 I Analog No A/D Analog Inputs AVDD P — No Positive Supply for Analog Modules AVSS P — No Ground Reference for Analog Modules C1INA-C1IND C1OUT I O Analog DIG No Yes Comparator 1 Inputs A through D Comparator 1 Output C2INA-C2IND C2OUT I O Analog DIG No Yes Comparator 2 Inputs A through D Comparator 2 Output C3INA-C3IND C3OUT I O Analog DIG No Yes Comparator 3 Inputs A through D Comparator 3 Output CLKI CLKO O DIG No No Main Clock Input Connection System Clock Output COM0-COM7 LCDBIAS0-LCDBIAS3 V LCAP1 VLCAP2 SEG0-SEG31 SEG40 SEG47 SEG48 SEG63 O O O O O O O O O Analog Analog Analog Analog Analog Analog Analog Analog Analog No No No No No No No No No LCD Driver Common Outputs 0 through 7 Bias Inputs 0 through 3 for LCD Driver Charge Pump LCD Drive Charge Pump Capacitor Input 1 LCD Drive Charge Pump Capacitor Input 2 LCD Driver Segment Outputs 0 through 31 LCD Driver Segment Output 40 LCD Driver Segment Output 47 LCD Driver Segment Output 48 LCD Driver Segment Output 63 CV REF O Analog No Comparator Voltage Reference Output CVREF+ I Analog No Comparator Voltage Reference (high) Input CVREF- I Analog No Comparator Voltage Reference (low) Input INT0 INT1-INT4 I I ST ST No Yes External Interrupt Input 0 External Interrupt Inputs 1 through 4 HLVDIN I Analog No High/Low-Voltage Detect Input MCLR I ST No Master Clear (device Reset) Input This line is brought low to cause a Reset. ICM1-ICM5 TCKIA-TCKIB OCFA-OCFB OCM1A-OCM1F OCM2A-OCM2B OCM3A-OCM3B OCM4A-OCM4B OCM5A-OCM5B I I I O O O O O ST ST ST DIG DIG DIG DIG DIG Yes Yes Yes No Yes Yes Yes Yes MCCP Capture Inputs 1 through 5 MCCP Timer Clock Inputs A through B MCCP Fault Inputs A through B MCCP1 Outputs A through F MCCP2 Outputs A through B MCCP3 Outputs A through B MCCP4 Outputs A through B MCCP5 Outputs A through B CLCINA-CLCIND CLC1OUT-CLC4OUT I O ST DIG Yes Yes CLC Inputs A through D CLC Outputs 1 through 4 OSCI OSCO I O Analog/ST No Main Oscillator Input Connection Main Oscillator Output Connection REFO REFI O I ST Yes Yes Reference Clock Output Reference Clock Input Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer DIG = Digital input/output I 2C = I2C/SMBus input buffer Analog = Analog level input/output SMB3 = SMBus Version 3

 2020 Microchip Technology Inc. DS30010198B-page 19 PIC24FJ128GL306 FAMILY PGC1 PGD1 PGC2 PGD2 PGC3 PGD3 I I/O I I/O I I/O ST DIG/ST ST DIG/ST ST DIG/ST No No No No No No ICSP ™ Programming Clock 1 ICSP Programming Data 1 ICSP Programming Clock 2 ICSP Programming Data 2 ICSP Programming Clock 3 ICSP Programming Data 3 PWRLCLK TMPRN PWRGT RTCC I I O O ST ST DIG DIG No Yes Yes Yes Real-Time Clock 50/60 Hz Clock Input Tamper Detect RTCC Power Control RTCC Clock Output RA0 I/O DIG/ST No PORTA Digital I/O RB0-RB15 I/O DIG/ST No PORTB Digital I/Os RC12-RC15 I/O DIG/ST No PORTC Digital I/Os RD0-RD11 I/O DIG/ST No PORTD Digital I/Os RE0-RE7 I/O DIG/ST No PORTE Digital I/Os RF0-RF6 I/O DIG/ST No PORTF Digital I/Os RG2-RG3, RG6-RG9 I/O DIG/ST No PORTG Digital I/Os RP0-RP31 I/O DIG/ST No Remappable Peripherals (input or output) RPI37 I ST No Remappable Peripheral (input only) SCK1 SDI1 SDO1 SS1 I/O I O I/O ST ST DIG ST Yes Yes Yes Yes Synchronous Serial Clock Input/Output for SPI1 SPI1 Data In SPI1 Data Out SPI1 Slave Synchronization or Frame Pulse I/O SCK2 SDI2 SDO2 SS2 I/O I O I/O ST ST DIG ST Yes Yes Yes Yes Synchronous Serial Clock Input/Output for SPI2 SPI2 Data In SPI2 Data Out SPI2 Slave Synchronization or Frame Pulse I/O SCL1 SDA1 ASCL1 ASDA1 I/O DIG/I 2C/SMB3 No I2C1 Synchronous Serial Clock Input/Output I2C1 Data Input/Output Alternate I2C1 Synchronous Serial Clock Input/Output Alternate I2C1 Data Input/Output SCL2 SDA2 I/O DIG/I 2C/SMB3 No I2C2 Synchronous Serial Clock Input/Output I2C2 Data Input/Output U1CTS U1RTS U1RX U1TX I O I O ST DIG ST DIG Yes Yes Yes Yes UART1 Clear-to-Send UART1 Request-to-Send UART1 Receive UART1 Transmit U2CTS U2RTS U2RX U2TX I O I O ST DIG ST DIG Yes Yes Yes Yes UART2 Clear-to-Send UART2 Request-to-Send UART2 Receive UART2 Transmit U3CTS U3RTS U3RX U3TX I O I O ST DIG ST DIG Yes Yes Yes Yes UART3 Clear-to-Send UART3 Request-to-Send UART3 Receive UART3 Transmit TABLE 1-1: PIC24FJ128GL306 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Name Pin Type Buffer Type PPS Description Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer DIG = Digital input/output I2C = I2C/SMBus input buffer Analog = Analog level input/output SMB3 = SMBus Version 3

DS30010198B-page 20  2020 Microchip Technology Inc. U4CTS U4RTS U4RX U4TX I O I O ST DIG ST DIG Yes Yes Yes Yes UART4 Clear-to-Send UART4 Request-to-Send UART4 Receive UART4 Transmit SOSCI SOSCO SCLKI I ST No No Secondary Oscillator/Timer1 Clock Input Secondary Oscillator/Timer1 Clock Output Secondary Clock Digital Input T1CK T2CK-T5CK TxCK I I I ST ST ST No Yes Yes Timer1 Clock Timer2 through Timer5 Clock Timer External Clock TCK TDI TDO TMS I I O I ST ST DIG ST No No No No JTAG Test Clock/Programming Clock Input JTAG Test Data/Programming Data Input JTAG Test Data Output JTAG Test Mode Select Input V CAP P — No External Filter Capacitor Connection (regulator enabled) VDD P — No Positive Supply for Peripheral Digital Logic and I/O Pins VREF+ I Analog No Comparator and A/D Reference Voltage (high) Input VSS P — No Ground Reference for Peripheral Digital Logic and I/O Pins TABLE 1-1: PIC24FJ128GL306 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Name Pin Type Buffer Type PPS Description Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer DIG = Digital input/output I2C = I2C/SMBus input buffer Analog = Analog level input/output SMB3 = SMBus Version 3

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2.0 GUIDELINES FOR GETTING

2.1 Basic Connection Requirements

Getting started with the PIC24FJ128GL306 family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected:

• A l l V DD and VSS pins (see Section 2.2 “Power Supply Pins”)
• A l l A VDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”)
• M C L R pin (see Section 2.3 “Master Clear (MCLR) Pin”)
• V CAP pin (see Section 2.4 “Voltage Regulator Pin (VCAP)”) These pins must also be connected if they are being used in the end application:
• PGCx/PGDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.4.2 “ICSP Pins”)
• OSCI and OSCO pins when an external oscillator source is used (see Section 2.5 “External Oscillator Pins”) Additionally, the following pins may be required: REF+ pin used when external voltage reference for analog modules is implemented The minimum mandatory connections are shown in Figure 2-1. FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. PIC24FJXXX VDD VSS VDD VSS VSS VDD AVDD AVSS VDD VSS VDD MCLR VCAP(1)R2 C2(2) C3(2) C4(2)C5(2) C6(2) Key (all values are recommendations): C1 through C6: 0.1 µF, 50V ceramic C7: 10 µF, 16V or greater, ceramic R1: 10 kΩ R2: 100Ω to 470Ω Note 1: See Section 2.4 “Voltage Regulator Pin CAP)” for an explanation of voltage regulator pin connections. 2: The example shown is for a PIC24F device with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately.

DS30010198B-page 22  2019-2020 Microchip Technology Inc.

2.2 Power Supply Pins

2.2.1 DECOUPLING CAPACITORS

The use of decoupling capacitors on every pair of power supply pins, such as V DD, V SS, AV DD and AVSS, is required. Consider the following criteria when using decoupling capacitors:

• Value and type of capacitor: A 0.1 µF (100 nF), 25V-50V capacitor is recommended. The capacitor should be a low-ESR device with a self-resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
• Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm).
• Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic-type capaci- tor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible
• Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance.

2.2.2 BULK CAPACITORS

On boards with power traces running longer than six inches in length, it is suggested to use a bulk capacitance of 10 µF or greater located near the MCU. The value of the capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. Typical values range from 10 µF to 47 µF. The capacitor should be ceramic and have a voltage rating of 25V or more to reduce DC bias effects (see Section 2.4.1 “Considerations for Ceramic Capacitors”).

2.3 Master Clear (MCLR ) Pin

The MCLR pin provides two specific device functions: device Reset, and device programming and debug- ging. If programming and debugging are not required in the end application, a direct connection to V DD may be all that is required. The addition of other components, to help increase the application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented depending on the application’s requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (V IH and V IL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debug- ging operations by using a jumper ( Figure 2-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin. FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS Note 1: R1  10 k  is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. 2: R2  470 will limit any current flowing into MCLR from the external capacitor, C, in the event of a MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. VDD MCLR PIC24FJXXXJP

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2.4 Voltage Regulator Pin (V CAP)

Refer to Section 27.3 “On-Chip Voltage Regulator” for details on connecting and using the on-chip regulator. A low-ESR (< 5Ω) capacitor is required on the VCAP pin to stabilize the voltage regulator output voltage. The V CAP pin must not be connected to VDD and must use a capacitor of 10 µF connected to ground. The type can be ceramic or tantalum. Suitable examples of capacitors are shown in Table 2-1. Capacitors with equivalent specifications can be used. Designers may use Figure 2-3 to evaluate the ESR equivalence of candidate devices. The placement of this capacitor should be close to V CAP. It is recommended that the trace length not exceed 0.25 inch (6 mm). Refer to Section 30.0 “Electrical Characteristics” for additional information. FIGURE 2-3: FREQUENCY vs. ESR PERFORMANCE FOR SUGGESTED V CAP Note: This section applies only to PIC24FJ devices with an on-chip voltage regulator. 0.1 0.01 0.001 0.01 0.1 1 10 100 1000 10,000 Frequency (MHz) ESR () Note: Typical data measurement at +25°C, 0V DC bias. TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS (0805 CASE SIZE) Make Part # Nominal Capacitance Base Tolerance Rated Voltage TDK C2012X5R1E106K085AC 10 µF ±10% 25V TDK C2012X5R1C106K085AC 10 µF ±10% 16V Kemet C0805C106M4PACTU 10 µF ±10% 16V Murata GRM21BR61E106KA3L 10 µF ±10% 25V Murata GRM21BR61C106KE15 10 µF ±10% 16V

DS30010198B-page 24  2019-2020 Microchip Technology Inc.

2.4.1 CONSIDERATIONS FOR CERAMIC

In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the inter- nal voltage regulator of this microcontroller. However, some care is needed in selecting the capacitor to ensure that it maintains sufficient capacitance over the intended operating range of the application. Typical low-cost, 10 µF ceramic capacitors are available in X5R, X7R and Y5V dielectric ratings (other types are also available, but are less common). The initial tolerance specifications for these types of capacitors are often specified as ±10% to ±20% (X5R and X7R) or -20%/+80% (Y5V). However, the effective capacitance that these capacitors provide in an application circuit will also vary based on additional factors, such as the applied DC bias voltage and the temperature. The total in-circuit tolerance is, therefore, much wider than the initial tolerance specification. The X5R and X7R capacitors typically exhibit satisfac- tory temperature stability (ex: ±15% over a wide temperature range, but consult the manufacturer’s data sheets for exact specifications). However, Y5V capaci- tors typically have extreme temperature tolerance specifications of +22%/-82%. Due to the extreme temperature tolerance, a 10 µF nominal rated Y5V type capacitor may not deliver enough total capacitance to meet minimum internal voltage regulator stability and transient response requirements. Therefore, Y5V capacitors are not recommended for use with the internal regulator if the application must operate over a wide temperature range. In addition to temperature tolerance, the effective capacitance of large value ceramic capacitors can vary substantially, based on the amount of DC voltage applied to the capacitor. This effect can be very signifi- cant, but is often overlooked or is not always documented. A typical DC bias voltage vs. capacitance graph for X7R type capacitors is shown in Figure 2-4. FIGURE 2-4: DC BIAS VOLTAGE vs. CAPACITANCE CHARACTERISTICS When selecting a ceramic capacitor to be used with the internal voltage regulator, it is suggested to select a high-voltage rating so that the operating voltage is a small percentage of the maximum rated capacitor volt- age. For example, choose a ceramic capacitor rated at a minimum of 16V for the 1.8V core voltage. Suggested capacitors are shown in Table 2-1.

2.4.2 ICSP PINS

The PGCx and PGDx pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recom- mended, with the value in the range of a few tens of ohms, not to exceed 100Ω. Pull-up resistors, series diodes and capacitors on the PGCx and PGDx pins are not recommended as they will interfere with the programmer/debugger communi- cations to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits, and pin Voltage Input High IH) and Voltage Input Low (VIL) requirements. For device emulation, ensure that the “Communication Channel Select” pins (i.e., PGCx/PGDx) programmed into the device match the physical connections for the ICSP to the Microchip debugger/emulator tool. For more information on available Microchip development tools connection requirements, refer to Section 29.0 “Development Support”. -80 -70 -60 -50 -40 -30 -20 -10 5 1 01 11 21 31 41 51 61 7 DC Bias Voltage (VDC) Capacitance Change (%)01234 6789 6.3V Capacitor 10V Capacitor 16V Capacitor

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2.5 External Oscillator Pins

Many microcontrollers have options for at least two oscillators: a high-frequency Primary Oscillator and a low-frequency Secondary Oscillator (refer to Section 9.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit com- ponents and the pins. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. Layout suggestions are shown in Figure 2-5. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With fine-pitch packages, it is not always possible to com- pletely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored ground layer. In all cases, the guard trace(s) must be returned to ground. In planning the application’s routing and I/O assign- ments, ensure that adjacent port pins, and other signals in close proximity to the oscillator, are benign (i.e., free of high frequencies, short rise and fall times, and other similar noise). For additional information and design guidance on oscillator circuits, please refer to these Microchip Application Notes, available at the corporate website (www.microchip.com):

• AN943, “Practical PICmicro ® Oscillator Analysis and Design”
• AN949, “Making Your Oscillator Work”
• AN1798, “Crystal Selection for Low-Power Secondary Oscillator” FIGURE 2-5: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT GND OSCI OSCO SOSCO SOSCI Copper Pour Primary Oscillator Crystal Secondary Crystal DEVICE PINS Primary Oscillator Sec Oscillator: C1 Sec Oscillator: C2 (tied to ground) GND OSCO OSCI Bottom Layer Copper Pour Oscillator Crystal Top Layer Copper Pour DEVICE PINS (tied to ground) (tied to ground) Single-Sided and In-Line Layouts: Fine-Pitch (Dual-Sided) Layouts: Oscillator

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2.6 Configuration of Analog and

If an ICSP compliant emulator is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as “digital” pins. This is done by clearing all bits in the ANSELx registers. Refer to Section 11.2 “Configur- ing Analog Port Pins (ANSELx)” for more specific information. The bits in these registers that correspond to the A/D pins that initialized the emulator must not be changed by the user application firmware; otherwise, commu- nication errors will result between the debugger and the device. If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must modify the appropriate bits during initialization of the A/D module, as follows:

• Set the bits corresponding to the pin(s) to be configured as analog. Do not change any other bits, particularly those corresponding to the PGCx/PGDx pair, at any time. When a Microchip debugger/emulator is used as a pro- grammer, the user application firmware must correctly configure the ANSELx registers. Automatic initializa- tion of these registers is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality.

2.7 Unused I/Os

Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ to 10 kΩ resistor to VSS on unused pins and drive the output to logic low.

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3.0 CPU

The PIC24F CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M instructions of user program memory space. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the REPEAT instructions, which are interruptible at any point. PIC24F devices have sixteen, 16-bit Working registers in the programmer’s model. Each of the Working registers can act as a Data, Address or Address Offset register. The 16 th Working register (W15) operates as a Software Stack Pointer (SSP) for interrupts and calls. The lower 32 Kbytes of the Data Space (DS) can be accessed linearly. The upper 32 Kbytes of the Data Space are referred to as Extended Data Space (EDS), to which the extended data RAM, EPMP memory space or program memory can be mapped. The Instruction Set Architecture (ISA) has been significantly enhanced beyond that of the PIC18, but maintains an acceptable level of backward compatibility. All PIC18 instructions and addressing modes are supported, either directly, or through simple macros. Many of the ISA enhancements have been driven by compiler efficiency needs. The core supports Inherent (no operand), Relative, Literal, Memory Direct Addressing modes along with three groups of addressing modes. All modes support Register Direct and various Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements. For most instructions, the core is capable of executing a data (or program data) memory read, a Working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing trinary operations (for example, A + B = C) to be executed in a single cycle. A high-speed, 17-bit x 17-bit multiplier has been included to significantly enhance the core arithmetic capability and throughput. The multiplier supports Signed, Unsigned and Mixed mode, 16-bit x 16-bit or 8-bit x 8-bit, integer multiplication. All multiply instructions execute in a single cycle. The 16-bit ALU has been enhanced with integer divide assist hardware that supports an iterative non-restoring divide algorithm. It operates in conjunction with the REPEAT instruction looping mechanism and a selection of iterative divide instructions to support 32-bit (or 16-bit), divided by 16-bit, integer signed and unsigned division. All divide operations require 19 cycles to complete but are interruptible at any cycle boundary. The PIC24F has a vectored exception scheme with up to eight sources of non-maskable traps and up to 118 interrupt sources. Each interrupt source can be assigned to one of seven priority levels. A block diagram of the CPU is shown in Figure 3-1.

3.1 Programmer’s Model

The programmer’s model for the PIC24F is shown in Figure 3-2. All registers in the programmer’s model are memory-mapped and can be manipulated directly by instructions. A description of each register is provided in Table 3-1. All registers associated with the programmer’s model are memory-mapped. Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive reference source. For more information, refer to “CPU with Extended Data Space (EDS)” ( www.microchip.com/ DS39732) in the “dsPIC33/PIC24 Family Reference Manual” . The information in this data sheet supersedes the information in the FRM.

DS30010198B-page 28  2019-2020 Microchip Technology Inc. FIGURE 3-1: PIC24F CP U CORE BLOCK DIAGRAM TABLE 3-1: CPU CORE REGISTERS Register(s) Name Description W0 through W15 Working Register Array PC 23-Bit Program Counter SR ALU STATUS Register SPLIM Stack Pointer Limit Value Register TBLPAG Table Memory Page Address Register RCOUNT REPEAT Loop Counter Register CORCON CPU Control Register DISICNT Disable Interrupt Count Register DSRPAG Data Space Read Page Register DSWPAG Data Space Write Page Register Instruction Decode and Control PCH Program Counter 16-Bit ALU Data Bus Instruction Reg Divide Support EA MUX RAGU WAGU Interrupt Controller Stack Control Logic Loop Control Logic Data Latch Data RAM Address Latch Control Signals to Various Blocks Program Memory/ Data Latch Address Bus Literal Data 16 16 Hardware Multiplier To Peripheral Modules Address Latch Up to 0x7FFF Extended Data Space PCL 16 x 16 W Register Array EDS and Table Data Access Control Block ROM Latch

 2019-2020 Microchip Technology Inc. DS30010198B-page 29 PIC24FJ128GL306 FAMILY FIGURE 3-2: PROGRAMMER’S MODEL NO VZ C TBLPAG 22 0 7 0 015 Program Counter Table Memory Page ALU STATUS Register (SR) Working/Address Registers W0 (WREG) W10 W11 W12 W13 Frame Pointer Stack Pointer RA RCOUNT 15 0 REPEAT Loop Counter SPLIM Stack Pointer Limit SRL 15 0 CPU Control Register (CORCON) SRH W14 W15 DC IPL2 1 0 PC Divider Working Registers Multiplier Registers 15 0 Value Register Address Register Register Data Space Read Page Register Data Space Write Page Register Disable Interrupt Count Register 13 0 DISICNT DSRPAG DSWPAG IPL3 ——— Registers or bits are shadowed for PUSH.S and POP.S instructions.

DS30010198B-page 30  2019-2020 Microchip Technology Inc.

3.2 CPU Control Registers

REGISTER 3-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 bit 15 bit 8 R/W-0(1) R/W-0(1) R/W-0(1) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL2(2) IPL1(2) IPL0(2) RA N OV Z C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 DC: ALU Half Carry/Borrow bit 1 = A carry out from the 4 th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry out from the 4 th or 8th low-order bit of the result has occurred bit 7-5 IPL[2:0]: CPU Interrupt Priority Level Status bits(1,2) 111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop is in progress 0 = REPEAT loop is not in progress bit 3 N: ALU Negative bit 1 = Result was negative 0 = Result was not negative (zero or positive) bit 2 OV: ALU Overflow bit 1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation 0 = No overflow has occurred bit 1 Z: ALU Zero bit 1 = An operation, which affects the Z bit, has set it at some time in the past 0 = The most recent operation, which affects the Z bit, has cleared it (i.e., a non-zero result) bit 0 C: ALU Carry/Borrow bit 1 = A carry out from the Most Significant bit (MSb) of the result occurred 0 = No carry out from the Most Significant bit of the result occurred Note 1: The IPLx Status bits are read-only when NSTDIS (INTCON1[15]) = 1. 2: The IPLx Status bits are concatenated with the IPL3 Status bit (CORCON[3]) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.

 2019-2020 Microchip Technology Inc. DS30010198B-page 31 PIC24FJ128GL306 FAMILY REGISTER 3-2: CORCON: CP U CORE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0 R/W-1 U-0 U-0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less bit 2 PSV: Program Space Visibility (PSV) in Data Space Enable bit(2) 1 = Program space is visible in Data Space 0 = Program space is not visible in Data Space bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL[2:0] bits (SR[7:5]) to form the CPU Interrupt Priority Level; see Register 3-1 for bit description. 2: If PSV = 0, any reads from data memory at 0x8000 and above will cause an address trap error instead of reading from the PSV section of program memory. This bit is not individually addressable.

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3.3 Arithmetic Logic Unit (ALU)

The PIC24F ALU is 16 bits wide and is capable of addi- tion, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. The PIC24F CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit divisor division.

3.3.1 MULTIPLIER

The ALU contains a high-speed, 17-bit x 17-bit multiplier. It supports unsigned, signed or mixed sign operation in several multiplication modes:

• 16-bit x 16-bit signed
• 16-bit x 16-bit unsigned
• 16-bit signed x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit unsigned
• 16-bit unsigned x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit signed
• 8-bit unsigned x 8-bit unsigned

3.3.2 DIVIDER

The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes:

• 32-bit signed/16-bit signed divide
• 32-bit unsigned/16-bit unsigned divide
• 16-bit signed/16-bit signed divide
• 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. The 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn), and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute.

3.3.3 MULTIBIT SHIFT SUPPORT

The PIC24F ALU supports both single-bit and single- cycle, multibit arithmetic and logic shifts. Multibit shifts are implemented using a shifter block, capable of performing up to a 15-bit arithmetic right shift, or up to a 15-bit left shift, in a single cycle. All multibit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided in Table 3-2. TABLE 3-2: INSTRUCTIONS THAT USE THE SI NGLE-BIT AND MULTIBIT SHIFT OPERATION Instruction Description ASR Arithmetic Shift Right Source register by one or more bits. SL Shift Left Source register by one or more bits. LSR Logical Shift Right Source register by one or more bits.

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4.0 MEMORY ORGANIZATION

As Harvard architecture devices, PIC24F micro- controllers feature separate program and data memory spaces and buses. This architecture also allows direct access of program memory from the Data Space (DS) during code execution.

4.1 Program Memory Space

The program address memory space of the PIC24FJ128GL306 family devices is 4M instructions. The space is addressable by a 24-bit value derived from either the 23-bit Program Counter (PC) during pro- gram execution, or from table operation or Data Space remapping, as described in Section 4.3 “Interfacing Program and Data Memory Spaces”. User access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG[7] to permit access to the Configuration bits and customer OTP sections of the configuration memory space. The memory map for the PIC24FJ128GL306 family of devices is shown in Figure 4-1. Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive ref- erence source. For more information, refer to “PIC24F Flash Program Memory” (www.microchip.com/DS30009715) in the “dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM.

DS30010198B-page 34  2019-2020 Microchip Technology Inc. FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ128GL306 DEVICES TABLE 4-1: PROGRAM MEMORY SIZES AND BOUNDARIES (2) Device Program Memory Upper Boundary (Instruction Words) Write Blocks(1) Erase Blocks(1) PIC24FJ128GL30X 015FFEh (45,056 x 24) 352 44 PIC24FJ64GL30X 00AFFEh (22,528 x 24) 176 22 Note 1: One Write Block = 128 Instruction Words; One Erase Block (Page) = 1024 Instruction Words. 2: To maintain integer page sizes, the memory sizes are not exactly half of each other. Configuration Memory Space User Memory Space Legend: Memory areas are not shown to scale. Note: Exact boundary addresses are determined by the size of the implemented program memory ( Table 4-1). 000000h FEFFFEh FF0000h FFFFFFh Flash Write Latches DEVID (2) FF0004h FA00FEh FA0100h 800000h 7FFFFFh Reserved Interrupt Vector Table 00B000h 00AFFEh Unimplemented Read ‘0’ 801800h Reserved Executive Code Memory 800FFEh 800100h OTP Memory 8017FEh 801700h Reserved 801000h 8016FEh GOTO Instruction Reset Address User Flash Program Memory (44K Instructions) Flash Config Words DEVID (2) Interrupt Vector Table Unimplemented Read ‘0’ Reserved Executive Code Memory OTP Memory Reserved GOTO Instruction Reset Address User Flash Program Memory (22K Instructions) Flash Config Words 000002h 000004h 0000FEh 000100h 016000h 015FFEh PIC24FJ64GL30X PIC24FJ128GL30X Reserved Reserved Reserved Flash Write Latches Reserved Reserved F9FFFEh FA0000h

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4.1.1 PROGRAM MEMORY

The program memory space is organized in word- addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 4-2). Program memory addresses are always word-aligned on the lower word and addresses are incremented or decremented by two during code execution. This arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space.

4.1.2 HARD MEMORY VECTORS

All PIC24F devices reserve the addresses between 000000h and 000200h for hard-coded program execu- tion vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on a device Reset to the actual start of code. A GOTO instruction is programmed by the user at 000000h, with the actual address for the start of code at 000002h. The PIC24FJ128GL306 devices can have up to two Interrupt Vector Tables (IVT). The first is located from addresses, 000004h to 0000FFh. The Alternate Inter- rupt Vector Table (AIVT) can be enabled by the AIVTDIS Configuration bit if the Boot Segment (BS) is present. If the user has configured a Boot Segment, the AIVT will be located at the address: (BSLIM[12:0] – 1) x 0x800. These vector tables allow each of the many device interrupt sources to be handled by separate ISRs. A more detailed discussion of the Interrupt Vector Tables is provided in Section 8.1 “Interrupt Vector Table”.

4.1.3 CONFIGURATION BITS OVERVIEW

The Configuration bits are stored in the last page loca- tion of implemented program memory. These bits can be set or cleared to select various device configurations. There are two types of Configuration bits: system oper- ation bits and code-protect bits. The system operation bits determine the power-on settings for system-level components, such as the oscillator and the Watchdog Timer. The code-protect bits prevent program memory from being read and written. Refer to Section 27.0 “Special Features” for the full Configuration register description for each specific device.

4.1.4 CODE-PROTECT CONFIGURATION

The device implements intermediate security features defined by the FSEC register. The Boot Segment (BS) is the higher privileged segment and the General Seg- ment (GS) is the lower privileged segment. The total user code memory can be split into BS or GS. The size of the segments is determined by the BSLIM[12:0] bits. The relative location of the segments within user space does not change, such that BS (if present) occupies the memory area just after the Interrupt Vector Table (IVT) and the GS occupies the space just after the BS (or if the Alternate IVT is enabled, just after it). The Configuration Segment (CS) is a small segment (less than a page, typically just one row) within user Flash address space. It contains all user configuration data that are loaded by the NVM Controller during the Reset sequence.

DS30010198B-page 36  2019-2020 Microchip Technology Inc.

4.2 Data Memory Space

The PIC24F core has a 16-bit wide data memory space, addressable as a single linear range. The Data Space is accessed using two Address Generation Units (AGUs), one each for read and write operations. The Data Space memory map is shown in Figure 4-2. The 16-bit wide data addresses in the data memory space point to bytes within the Data Space (DS). This gives a DS address range of 64 Kbytes or 32K words. The lower half (0000h to 7FFFh) is used for implemented (on-chip) memory addresses. The upper half of data memory address space (8000h to FFFFh) is used as a window into the Extended Data Space (EDS). This allows the microcontroller to directly access a greater range of data beyond the standard 16-bit address range. EDS is discussed in detail in Section 4.2.5 “Extended Data Space (EDS)” .

4.2.1 DATA SPACE WIDTH

The data memory space is organized in byte- addressable, 16-bit wide blocks. Data are aligned in data memory and registers as 16-bit words, but all Data Space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses. FIGURE 4-2: DATA SPACE MEMORY MAP FOR PIC24FJ128GL306 DEVICES Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive refer- ence source. For more information, refer to “Data Memory with Extended Data Space (EDS) ” ( www.microchip.com/ DS39733) in the “dsPIC33/PIC24 Family Reference Manual”, . The information in this data sheet supersedes the information in the FRM. Note: Memory areas are not shown to scale. 0000h 07FEh FFFEh LSB AddressLSBMSB MSB Address 0001h 07FFh 1FFFh FFFFh 8001h 8000h 7FFFh 0801h 0800h 2001h Near 1FFEh SFR 2000h 7FFEh EDS Window Space Data Space Upper 32 Kbytes Data Space Lower 32 Kbytes Data Space SFR Space 27FFh 2801h 27FEh 2800h Unimplemented

8 Kbytes Data RAM

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4.2.2 DATA MEMORY ORGANIZATION

To maintain backward compatibility with PIC® MCUs and improve Data Space memory usage efficiency, the PIC24F instruction set supports both word and byte operations. As a consequence of byte accessibility, all EA calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode, [Ws++], will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Data byte reads will read the complete word, which contains the byte, using the LSB of any EA to deter- mine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel, byte-wide entities with shared (word) address decode, but separate write lines. Data byte writes only write to the corresponding side of the array or register which matches the byte address. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap will be generated. If the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed but the write will not occur. In either case, a trap is then executed, allow- ing the system and/or user to examine the machine state prior to execution of the address Fault. All byte loads into any W register are loaded into the LSB. The Most Significant Byte (MSB) is not modified. A Sign-Extend (SE) instruction is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a Zero-Extend (ZE) instruction on the appropriate address. Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words.

4.2.3 NEAR DATA SPACE

The 8-Kbyte area between 0000h and 1FFFh is referred to as the Near Data Space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. The remainder of the Data Space is addressable indirectly. Additionally, the whole Data Space is addressable using MOV instructions, which support Memory Direct Addressing with a 16-bit address field.

4.2.4 SPECIAL FUNCTION REGISTER

(SFR) SPACE The first 2 Kbytes of the Near Data Space, from 0000h to 07FFh, are primarily occupied with Special Function Registers (SFRs). These are used by the PIC24F core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as ‘0’. Each implemented area indicates a 32-byte region where at least one address is implemented as an SFR. A complete list of imple- mented SFRs, including their addresses, is shown in Table 4-2 through Table 4-9. These tables contain all registers applicable to the PIC24FJ128GL306 family. Not all registers are present on all device variants. Refer to Table 1 for peripheral availability. Refer to Table 11-3 through Table 11-9 for detailed port availability for the different package options.

DS30010198B-page 38  2019-2020 Microchip Technology Inc. TABLE 4-2: SFR MAP: 0000h BLOCK Register Address (1) All Resets(2) Register Address (1) All Resets(2) CPU Core Interrupt Controller (Continued) WREG0 0000h 0000000000000000 IFS3 008Eh 000-00---00--00- WREG2 0004h 0000000000000000 IFS5 0092h 00----000-00000- WREG3 0006h 0000000000000000 IFS6 0094h -0-000----000000 WREG5 000Ah 0000000000000000 IEC0 0098h 000000000--00000 WREG6 000Ch 0000000000000000 IEC1 009Ah 00000--0-0-00000 WREG8 0010h 0000000000000000 IEC3 009Eh 000-00---00--00- WREG10 0014h 0000000000000000 IEC5 00A2h 00----000-00000- WREG11 0016h 0000000000000000 IEC6 00A4h -0-000----000000 WREG13 001Ah 0000000000000000 IPC0 00A8h -100-100-100-100 WREG15 001Eh 0000100000000000 IPC2 00ACh -100-100-100-100 SPLIM 0020h xxxxxxxxxxxxxxxx IPC3 00AEh -100-100-100-100 PCL 002Eh 0000000000000000 IPC4 00B0h -100-100-100-100 DISICNT 0052h --xxxxxxxxxxxxxx IPC11 00BEh -100-100-----100 Deadman Timer IPC13 00C2h -----100-100---- DMTCLR 0064h 0000000000000000 IPC16 00C8h -100-100-100-100 DMTHOLDREG 0070h 0000000000000000 IPC20 00D0h -100-100-100---- DMTPSCNTL 0074h 0000000000000000 IPC21 00D2h -100-----100-100 DMTPSINTVH 007Ah 0000000000000000 IPC24 00D8h -100-100-100-100 IFS0 0088h 000000000--00000 INTTREG 00E4h 0-0-000000000000 IFS1 008Ah 00000--0-0-00000 Legend: x = unknown or indeterminate value; - = unimplemented bits. Note 1: Address values are in hexadecimal. 2: Reset values are in binary.

 2019-2020 Microchip Technology Inc. DS30010198B-page 39 PIC24FJ128GL306 FAMILY TABLE 4-3: SFR MAP: 0100h BLOCK Register Address (1) All Resets(2) Register Address (1) All Resets(2) Oscillator and Reset Timers (Continued) OSCCON 0100h -qqq-qqq00q00000 TMR2 0196h 0000000000000000 CLKDIV 0102h 0011000000q----- TMR3HLD 0198h 0000000000000000 OSCTUN 0106h 0000000000000000 TMR3 019Ah 0000000000000000 OSCDIV 010Ch -000000000000001 PR2 019Ch 1111111111111111 RCON 0110h 0010--0000000011 T2CON 01A0h 0-0---xx-0000-0- HLVD T3CON 01A2h 0-0---xx-000--0- HLVDCON 0114h 0-0-xxxx----0000 TMR4 01A4h 0000000000000000 CRC TMR5HLD 01A6h 0000000000000000 CRCCON1 0158h 0-00000001x00--- TMR5 01A8h 0000000000000000 CRCCON2 015Ah ---00000---00000 PR4 01AAh 1111111111111111 CRCXORL 015Ch 000000000000000- PR5 01ACh 1111111111111111 CRCXORH 015Eh 0000000000000000 T4CON 01AEh 0-0---xx-0000-0- CRCDATL 0160h xxxxxxxxxxxxxxxx T5CON 01B0h 0-0---xx-000--0- CRCDATH 0162h xxxxxxxxxxxxxxxx Real-Time Clock and Calendar (RTCC) CRCWDATL 0164h xxxxxxxxxxxxxxxx RTCCON1L 01CCh 0---00000000---0 CRCWDATH 0166h xxxxxxxxxxxxxxxx RTCCON1H 01CEh 00--000000000000 REFO RTCCON2L 01D0h 10000---0000--00 REFOCONL 0168h 0-000-00----0000 RTCCON2H 01D2h 0011111111111111 REFOCONH 016Ah -000000000000000 RTCCON3L 01D4h 0000000000000000 TMR1 0190h 0000000000000000 TSATIMEH 01EEh --000000-0000000 PR1 0192h 1111111111111111 TSADATEL 01F0h --000000-----000 T1CON 0194h 0-0---00-000-00- TSADATEH 01F2h 00000000---00000 Legend: x = unknown or indeterminate value; - = unimplemented bits; q = value set by Configuration bits. Note 1: Address values are in hexadecimal. 2: Reset values are in binary.

DS30010198B-page 40  2019-2020 Microchip Technology Inc. TABLE 4-4: SFR MAP: 0200h BLOCK Register Address (1) All Resets(2) Register Address (1) All Resets(2) Multiple Output Capture/Compare/PWM Multiple Output Capture/Compare/PWM (Continued) CCP1CON1L 026Ch 0000000000000000 CCP2RBL 02ACh 0000000000000000 CCP1CON1H 026Eh 0000000000000000 CCP2BUFL 02B0h 0000000000000000 CCP1CON2L 0270h 0000000000000000 CCP2BUFH 02B2h 0000000000000000 CCP1CON2H 0272h 0000000100000000 CCP3CON1L 02B4h 0000000000000000 CCP1CON3H 0276h 0000000000000000 CCP3CON2L 02B8h 0000000000000000 CCP1STATL 0278h 0000000000000000 CCP3CON2H 02BAh 0000000100000000 CCP1TMRH 027Eh 0000000000000000 CCP3CON3H 02BEh 0000000000000000 CCP1PRL 0280h 1111111111111111 CCP3STATL 02C0h 0000000000000000 CCP1PRH 0282h 1111111111111111 CCP3TMRL 02C4h 0000000000000000 CCP1RAL 0284h 0000000000000000 CCP3TMRH 02C6h 0000000000000000 CCP1RBL 0288h 0000000000000000 CCP3PRL 02C8h 0000000000000000 CCP1BUFL 028Ch 0000000000000000 CCP3PRH 02CAh 0000000000000000 CCP1BUFH 028Eh 0000000000000000 CCP3RAL 02CCh 0000000000000000 CCP2CON1L 0290h 0000000000000000 CCP3RBL 02D0h 0000000000000000 CCP2CON1H 0292h 0000000000000000 CCP3BUFL 02D4h 0000000000000000 CCP2CON2L 0294h 0000000000000000 CCP3BUFH 02D6h 0000000000000000 CCP2CON2H 0296h 0000000100000000 Comparator CCP2CON3H 029Ah 0000000000000000 CVRCON 02E8h -----00000000000 CCP2STATL 029Ch 0000000000000000 CM1CON 02EAh 000---0000-0--00 CCP2TMRL 02A0h 0000000000000000 CM2CON 02ECh 000---0000-0--00 CCP2TMRH 02A2h 0000000000000000 CM3CON 02EEh 000---0000-0--00 CCP2PRH 02A6h 0000000000000000 CCP2RAL 02A8h 0000000000000000 Legend: x = unknown or indeterminate value; - = unimplemented bits. Note 1: Address values are in hexadecimal. 2: Reset values are in binary.

 2019-2020 Microchip Technology Inc. DS30010198B-page 41 PIC24FJ128GL306 FAMILY TABLE 4-5: SFR MAP: 0300h BLOCK Register Address (1) All Resets(2) Register Address (1) All Resets(2) Multiple Output Capture/Compare/PWM UART CCP4CON1L 0300h 0000000000000000 U1MODE 0398h 0-000-0000000000 CCP4CON1H 0302h 0000000000000000 U1STA 039Ah 0000000100010000 CCP4CON3H 030Ah 0000000000000000 U1ADMD 03A2h 0000000000000000 CCP4STATL 030Ch 0000000000000000 U2MODE 03AEh 0-000-0000000000 CCP4TMRL 0310h 0000000000000000 U2STA 03B0h 0000000100010000 CCP4PRH 0316h 0000000000000000 U2BRG 03B6h 0000000000000000 CCP4RAL 0318h 0000000000000000 U2ADMD 03B8h 0000000000000000 CCP4RBL 031Ch 0000000000000000 U3MODE 03C4h 0-000-0000000000 CCP4BUFL 0320h 0000000000000000 U3STA 03C6h 0000000100010000 CCP5CON1H 0326h 0000000000000000 U3BRG 03CCh 0000000000000000 CCP5CON2L 0328h 0000000000000000 U3ADMD 03CEh 0000000000000000 CCP5CON2H 032Ah 0000000100000000 U4MODE 03D0h 0-000-0000000000 CCP5TMRL 0334h 0000000000000000 U4BRG 03D8h 0000000000000000 CCP5TMRH 0336h 0000000000000000 U4ADMD 03DAh 0000000000000000 CCP5PRL 0338h 0000000000000000 SPI CCP5PRH 033Ah 0000000000000000 SPI1CON1L 03F4h 0-00000000000000 CCP5RAL 033Ch 0000000000000000 SPI1CON1H 03F6h 0000000000000000 CCP5BUFL 0344h 0000000000000000 SPI1STATL 03FCh ---00--0001-1-00 CCP5BUFH 0346h 0000000000000000 SPI1STATH 03FEh --000000--000000 Legend: x = unknown or indeterminate value; - = unimplemented bits. Note 1: Address values are in hexadecimal. 2: Reset values are in binary.

DS30010198B-page 42  2019-2020 Microchip Technology Inc. TABLE 4-6: SFR MAP: 0400h BLOCK Register Address (1) All Resets(2) Register Address (1) All Resets(2) SPI (Continued) I 2C (Continued) SPI1BUFL 0400h 0000000000000000 I2C1CONL 049Ah 0-01000000000000 SPI1BRGL 0404h ---xxxxxxxxxxxxx I2C1STAT 049Eh 000--00000000000 SPI2CON1L 0410h 0-00000000000000 I2C2BRG 04A8h 0000000000000000 SPI2CON1H 0412h 0000000000000000 I2C2CONL 04AAh 0-01000000000000 SPI2STATL 0418h ---00--0001-1-00 I2C2STAT 04AEh 000--00000000000 SPI2BUFH 041Eh 0000000000000000 DMA SPI2IMSKL 0424h ---00--0000-0-00 DMABUF 04C6h 0000000000000000 SPI2IMSKH 0426h 0-0000000-000000 DMAL 04C8h 0000000000000000 SPI2URDTL 0428h 0000000000000000 DMAH 04CAh 0000000000000000 SPI2URDTH 042Ah 0000000000000000 DMACH0 04CCh ---0-00000000000 Configurable Logic Cell (CLC) DMAINT0 04CEh 0000000000000--0 CLC1CONL 0464h 0---00--000--000 DMASRC0 04D0h 0000000000000000 CLC1SEL 0468h -000-000-000-000 DMACNT0 04D4h 0000000000000001 CLC1GLSL 046Ch 0000000000000000 DMACH1 04D6h ---0-00000000000 CLC1GLSH 046Eh 0000000000000000 DMAINT1 04D8h 0000000000000--0 CLC2CONL 0470h 0---00--000--000 DMASRC1 04DAh 0000000000000000 CLC2SELL 0474h -000-000-000-000 DMACNT1 04DEh 0000000000000001 CLC2GLSL 0478h 0000000000000000 DMACH2 04E0h ---0-00000000000 CLC2GLSH 047Ah 0000000000000000 DMAINT2 04E2h 0000000000000--0 CLC3CONL 047Ch 0---00--000--000 DMASRC2 04E4h 0000000000000000 CLC3SELL 0480h -000-000-000-000 DMACNT2 04E8h 0000000000000001 CLC3GLSL 0484h 0000000000000000 DMACH3 04EAh ---0-00000000000 CLC3GLSH 0486h 0000000000000000 DMAINT3 04ECh 0000000000000--0 CLC4CONL 0488h 0---00--000--000 DMASRC3 04EEh 0000000000000000 CLC4SELL 048Ch -000-000-000-000 DMACNT3 04F2h 0000000000000001 CLC4GLSL 0490h 0000000000000000 DMACH4 04F4h ---0-00000000000 CLC4GLSH 0492h 0000000000000000 DMAINT4 04F6h 0000000000000--0 I2C DMASRC4 04F8h 0000000000000000 I2C1BRG 0498h 0000000000000000 DMACH5 04FEh ---0-00000000000 Legend: x = unknown or indeterminate value; - = unimplemented bits. Note 1: Address values are in hexadecimal. 2: Reset values are in binary.

 2019-2020 Microchip Technology Inc. DS30010198B-page 43 PIC24FJ128GL306 FAMILY TABLE 4-7: SFR MAP: 0500h BLOCK Register Address (1) All Resets(2) Register Address (1) All Resets(2) DMA (Continued) LCD (Continued) DMAINT5 0500h 0000000000000--0 LCDSE2 058Ah xxxxxxxxxxxxxxxx DMASRC5 0502h 0000000000000000 LCDSE3 058Ch xxxxxxxxxxxxxxxx DMACNT5 0506h 0000000000000001 LCDACTRL 0590h 0000000000000000 LCD LCDASTAT 0592h 0000000000000000 LCDCON 0540h 0000000000000000 LCDFC0 0594h 0000000000000001 LCDREF 0542h 0000000000000000 LCDFC1 0596h 0000000000000001 LCDPS 0544h 0000000000000000 LCDFC2 0598h 0000000000000001 LCDDATA0 0546h xxxxxxxxxxxxxxxx LCDTEVNT 059Ah 0000000000000001 LCDDATA1 0548h xxxxxxxxxxxxxxxx LCDSDATA0 059Ch xxxxxxxxxxxxxxxx LCDDATA2 054Ah xxxxxxxxxxxxxxxx LCDSDATA1 059Eh xxxxxxxxxxxxxxxx LCDDATA3 054Ch xxxxxxxxxxxxxxxx LCDSDATA2 05A0h xxxxxxxxxxxxxxxx LCDDATA4 054Eh xxxxxxxxxxxxxxxx LCDSDATA3 05A2h xxxxxxxxxxxxxxxx LCDDATA5 0550h xxxxxxxxxxxxxxxx LCDSDATA4 05A4h xxxxxxxxxxxxxxxx LCDDATA6 0552h xxxxxxxxxxxxxxxx LCDSDATA5 05A6h xxxxxxxxxxxxxxxx LCDDATA7 0554h xxxxxxxxxxxxxxxx LCDSDATA6 05A8h xxxxxxxxxxxxxxxx LCDDATA8 0556h xxxxxxxxxxxxxxxx LCDSDATA7 05AAh xxxxxxxxxxxxxxxx LCDDATA9 0558h xxxxxxxxxxxxxxxx LCDSDATA8 05ACh xxxxxxxxxxxxxxxx LCDDATA10 055Ah xxxxxxxxxxxxxxxx LCDSDATA9 05AEh xxxxxxxxxxxxxxxx LCDDATA11 055Ch xxxxxxxxxxxxxxxx LCDSDATA10 05B0h xxxxxxxxxxxxxxxx LCDDATA12 055Eh xxxxxxxxxxxxxxxx LCDSDATA11 05B2h xxxxxxxxxxxxxxxx LCDDATA13 0560h xxxxxxxxxxxxxxxx LCDSDATA12 05B4h xxxxxxxxxxxxxxxx LCDDATA14 0562h xxxxxxxxxxxxxxxx LCDSDATA13 05B6h xxxxxxxxxxxxxxxx LCDDATA15 0564h xxxxxxxxxxxxxxxx LCDSDATA14 05B8h xxxxxxxxxxxxxxxx LCDDATA16 0566h xxxxxxxxxxxxxxxx LCDSDATA15 05BAh xxxxxxxxxxxxxxxx LCDDATA17 0568h xxxxxxxxxxxxxxxx LCDSDATA16 05BCh xxxxxxxxxxxxxxxx LCDDATA18 056Ah xxxxxxxxxxxxxxxx LCDSDATA17 05BEh xxxxxxxxxxxxxxxx LCDDATA19 056Ch xxxxxxxxxxxxxxxx LCDSDATA18 05C0h xxxxxxxxxxxxxxxx LCDDATA20 056Eh xxxxxxxxxxxxxxxx LCDSDATA19 05C2h xxxxxxxxxxxxxxxx LCDDATA21 0570h xxxxxxxxxxxxxxxx LCDSDATA20 05C4h xxxxxxxxxxxxxxxx LCDDATA22 0572h xxxxxxxxxxxxxxxx LCDSDATA21 05C6h xxxxxxxxxxxxxxxx LCDDATA23 0574h xxxxxxxxxxxxxxxx LCDSDATA22 05C8h xxxxxxxxxxxxxxxx LCDDATA24 0576h xxxxxxxxxxxxxxxx LCDSDATA23 05CAh xxxxxxxxxxxxxxxx LCDDATA25 0578h xxxxxxxxxxxxxxxx LCDSDATA24 05CCh xxxxxxxxxxxxxxxx LCDDATA26 057Ah xxxxxxxxxxxxxxxx LCDSDATA25 05CEh xxxxxxxxxxxxxxxx LCDDATA27 057Ch xxxxxxxxxxxxxxxx LCDSDATA26 05D0h xxxxxxxxxxxxxxxx LCDDATA28 057Eh xxxxxxxxxxxxxxxx LCDSDATA27 05D2h xxxxxxxxxxxxxxxx LCDDATA29 0580h xxxxxxxxxxxxxxxx LCDSDATA28 05D4h xxxxxxxxxxxxxxxx LCDDATA30 0582h xxxxxxxxxxxxxxxx LCDSDATA29 05D6h xxxxxxxxxxxxxxxx LCDDATA31 0584h xxxxxxxxxxxxxxxx LCDSDATA30 05D8h xxxxxxxxxxxxxxxx LCDSE0 0586h xxxxxxxxxxxxxxxx LCDSDATA31 05DAh xxxxxxxxxxxxxxxx LCDSE1 0588h xxxxxxxxxxxxxxxx Legend: x = unknown or indeterminate value; - = unimplemented bits. Note 1: Address values are in hexadecimal. 2: Reset values are in binary.

DS30010198B-page 44  2019-2020 Microchip Technology Inc. TABLE 4-8: SFR MAP: 0600h BLOCK Register Address (1) All Resets(2) Register Address (1) All Resets(2) I/O ODCD 06A2h ----000000000000 PORTA IOCND 06A8h ----000000000000 ODCB 067Ah 0000000000000000 PORTF Legend: x = unknown or indeterminate value; - = unimplemented bits. Note 1: Address values are in hexadecimal. 2: Reset values are in binary.

 2019-2020 Microchip Technology Inc. DS30010198B-page 45 PIC24FJ128GL306 FAMILY TABLE 4-9: SFR MAP: 0700h BLOCK Register Address (1) All Resets(2) Register Address (1) All Resets(2) ADC Peripheral Pin Select (PPS) ADC1BUF1 0702h xxxxxxxxxxxxxxxx RPINR1 0792h --111111--111111 ADC1BUF3 0706h xxxxxxxxxxxxxxxx RPINR3 0796h --xxxxxx--111111 ADC1BUF4 0708h xxxxxxxxxxxxxxxx RPINR4 0798h --111111--111111 ADC1BUF5 070Ah xxxxxxxxxxxxxxxx RPINR5 079Ah --111111--111111 ADC1BUF6 070Ch xxxxxxxxxxxxxxxx RPINR6 079Ch --111111--111111 ADC1BUF7 070Eh xxxxxxxxxxxxxxxx RPINR11 07A6h --111111--111111 ADC1BUF8 0710h xxxxxxxxxxxxxxxx RPINR12 07A8h --111111--111111 ADC1BUF9 0712h xxxxxxxxxxxxxxxx RPINR13 07AAh --111111--111111 ADC1BUF12 0718h xxxxxxxxxxxxxxxx RPINR18 07B4h --111111--111111 ADC1BUF13 071Ah xxxxxxxxxxxxxxxx RPINR19 07B6h --111111--111111 ADC1BUF14 071Ch xxxxxxxxxxxxxxxx RPINR20 07B8h --111111--111111 ADC1BUF15 071Eh xxxxxxxxxxxxxxxx RPINR21 07BAh --111111--111111 ADC1BUF16 0720h xxxxxxxxxxxxxxxx RPINR22 07BCh --111111--111111 AD1CON1 0734h 0-0000000000-000 RPINR23 07BEh --111111--111111 AD1CON2 0736h 000000--00000000 RPINR25 07C2h --111111--111111 AD1CON3 0738h 0000000000000000 RPINR26 07C4h --111111--111111 AD1CHS 073Ah 0000000000000000 RPINR27 07C6h --111111--111111 AD1CSSL 073Eh 0000000000000000 RPOR1 07D6h -0000000-0000000 AD1CON5 0742h 0000--00----0000 RPOR3 07DAh -0000000-0000000 AD1CHITH 0744h 0000000000000000 RPOR4 07DCh -0000000-0000000 AD1CHITL 0746h 0000000000000000 RPOR5 07DEh -0000000-0000000 AD1RESDMA 074Ch xxxxxxxxxxxxxxxx RPOR6 07E0h -0000000-0000000 NVM RPOR7 07E2h -0000000-0000000 NVMADR 0762h 0000000000000000 RPOR9 07E6h -0000000-0000000 ECC RPOR12 07ECh -0000000-0000000 ECCCONL 076Ch 0000000000000000 RPOR13 07EEh -0000000-0000000 ECCCONH 076Eh 0000000000000000 RPOR14 07F0h -0000000-0000000 ECCADDRL 0770h 0000000000000000 RPOR15 07F2h -0000000-0000000 ECCADDRH 0772h 0000000000000000 ECCSTATL 0774h 0000000000000000 ECCSTATH 0776h 0000000000000000 Legend: x = unknown or indeterminate value; - = unimplemented bits. Note 1: Address values are in hexadecimal. 2: Reset values are in binary.

DS30010198B-page 46  2019-2020 Microchip Technology Inc.

4.2.5 EXTENDED DATA SPACE (EDS)

The Extended Data Space (EDS) allows PIC24F devices to address a much larger range of data than would otherwise be possible with a 16-bit address range. EDS allows read access to the program memory space. This feature is called Program Space Visibility (PSV) and is discussed in detail in Section 4.3.3 “Reading Data from Program Memory Using EDS”. Figure 4-3 displays the entire EDS space. The EDS is organized as pages, called EDS pages, with one page equal to the size of the EDS window (32 Kbytes). A particular EDS page is selected through the Data Space Read Page register (DSRPAG) or the Data Space Write Page register (DSWPAG). For PSV, only the DSRPAG register is used. The combination of the DSRPAG register value and the 16-bit wide data address forms a 24-bit Effective Address (EA). FIGURE 4-3: EXTENDED DATA SPACE Note: Accessing Page 0 in the EDS window will generate an address error trap as Page 0 is the base data memory (data locations, 0800h to 7FFFh, in the lower Data Space). 0000hSpecial Registers 32-Kbyte EDS 8000h Program Memory DSRPAG = 200h DSRPAG = 3FFh Function 000000h 7F8001h 007FFEh 7FFFFFh Program Space 0800h FFFEh EDS Pages DSRPAG = 2FFh 7F8000h 7FFFFEh Access Program Space Access Program Space Access DSRPAG = 300h 000001h 007FFFh Program Space Access Internal Data Memory Space (Lower Word) (Lower Word) (Upper Word) (Upper Word) Window 047FEh 04800h Unimplemented

 2019-2020 Microchip Technology Inc. DS30010198B-page 47 PIC24FJ128GL306 FAMILY

4.2.6 SOFTWARE STACK

Apart from its use as a Working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer (SSP). The pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post- increments for stack pushes, as shown in Figure 4-4. Note that for a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear. The Stack Pointer Limit Value register (SPLIM), associ- ated with the Stack Pointer, sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM[0] is forced to ‘0’ as all stack operations must be word-aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is com- pared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal, and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a stack error trap when the stack grows beyond address 2000h in RAM, initialize the SPLIM with the value, 1FFEh. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0800h. This prevents the stack from interfering with the SFR space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. FIGURE 4-4: CALL STACK FRAME

4.3 Interfacing Program and Data

The PIC24F architecture uses a 24-bit wide program space and 16-bit wide Data Space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use these data successfully, they must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the PIC24F architecture provides two methods by which program space can be accessed during operation:

• Using table instructions to access individual bytes or words anywhere in the program space
• Remapping a portion of the program space into the Data Space (Program Space Visibility) Table instructions allow an application to read or write to small areas of the program memory. This makes the method ideal for accessing data tables that need to be updated from time to time. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look-ups from a large table of static data. It can only access the least significant word of the program word.

4.3.1 ADDRESSING PROGRAM SPACE

Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Memory Page Address register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the MSBs of TBLPAG are used to determine if the operation occurs in the user memory (TBLPAG[7] = 0) or the configuration memory (TBLPAG[7] = 1). For remapping operations, the 10-bit Extended Data Space Read register (DSRPAG) is used to define a 16K word page in the program space. When the Most Significant bit (MSb) of the EA is ‘1’, and the MSb (bit 9) of DSRPAG is ‘ 1’, the lower 8 bits of DSRPAG are concatenated with the lower 15 bits of the EA to form a 23-bit program space address. The DSRPAG[8] bit decides whether the lower word (when the bit is ‘0’) or the higher word (when the bit is ‘1’) of program memory is mapped. Unlike table operations, this strictly limits remapping operations to the user memory area. Table 4-10 and Figure 4-5 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P[23:0] refers to a program space word, whereas D[15:0] refers to a Data Space word. Note: A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. [Free Word] PC[15:0] 000000000 015 W15 (before CALL) W15 (after CALL) Stack Grows Towards Higher Address 0000h PC[22:16] POP : [--W15] PUSH: [W15++]

DS30010198B-page 48  2019-2020 Microchip Technology Inc. TABLE 4-10: PROGRAM SP ACE ADDRESS CONSTRUCTION FIGURE 4-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Access Type Access Space Program Space Address Instruction Access (Code Execution) User 0 PC[22:1] 0 0xx xxxx xxxx xxxx xxxx xxx0 TBLRD/TBLWT (Byte/Word Read/Write) User TBLPAG[7:0] Data EA[15:0] 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG[7:0] Data EA[15:0] 1xxx xxxx xxxx xxxx xxxx xxxx Program Space Visibility (Block Remap/Read) User 0 DSRPAG7:0 Data EA14:0 0 xxxx xxxx xxx xxxx xxxx xxxx Note 1: Data EA[15] is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is DSRPAG[0]. 2: DSRPAG[9] is always ‘1’ in this case. DSRPAG[8] decides whether the lower word or higher word of program memory is read. When DSRPAG[8] is ‘0’, the lower word is read, and when it is ‘1’, the higher word is read. 0Program Counter

23 Bits

DSRPAG[7:0]

8 Bits

15 Bits

16 Bits

Table Operations(2) Program Space Visibility(1) Space Select

24 Bits

(Remapping) Note 1: DSRPAG[8] acts as word select. DSRPAG[9] should always be ‘1’ to map program memory to data memory. 2: The instructions, TBLRDH/TBLWTH/TBLRDL/TBLWTL, decide if the higher or lower word of program memory is accessed. TBLRDH/TBLWTH instructions access the higher word and TBLRDL/TBLWTL instructions access the lower word. Table Read operations are permitted in the configuration memory space. 1-Bit

 2019-2020 Microchip Technology Inc. DS30010198B-page 49 PIC24FJ128GL306 FAMILY

4.3.2 DATA ACCESS FROM PROGRAM

The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through Data Space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper eight bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to Data Space addresses. Program memory can thus be regarded as two, 16-bit word-wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space which contains the least significant data word, and TBLRDH and TBLWTH access the space which contains the upper data byte. Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations. 1. TBLRDL (Table Read Low): In Word mode, it maps the lower word of the program space location (P[15:0]) to a data address (D[15:0]). In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when byte select is ‘1’; the lower byte is selected when it is ‘0’. 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P[23:16]) to a data address. Note that D[15:8], the ‘phantom’ byte, will always be ‘0’. In Byte mode, it maps the upper or lower byte of the program word to D[7:0] of the data address, as above. Note that the data will always be ‘ 0’ when the upper ‘phantom’ byte is selected (byte select = 1). In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are described in Section 6.0 “Flash Program Memory”. For all table operations, the area of program memory space to be accessed is determined by the Table Memory Page Address (TBLPAG) register. TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG[7] = 0, the table page is located in the user memory space. When TBLPAG[7] = 1, the page is located in configuration space. FIGURE 4-6: ACCESS PROGRAM ME MORY WITH TABLE INSTRUCTIONS Note: Only Table Read operations will execute in the configuration memory space where Device IDs are located. Table Write operations are not allowed. 081623 00000000 00000000 00000000 00000000 ‘Phantom’ Byte TBLRDH.B (Wn[0] = 0) TBLRDL.W TBLRDL.B (Wn[0] = 1) TBLRDL.B (Wn[0] = 0) 23 15 0 TBLPAG 000000h 800000h 020000h 030000h Program Space Data EA[15:0] The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area.

DS30010198B-page 50  2019-2020 Microchip Technology Inc.

4.3.3 READING DATA FROM PROGRAM

The upper 32 Kbytes of Data Space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the Data Space without the need to use special instructions (i.e., TBLRDL/H). Program space access through the Data Space occurs when the MSb of EA is ‘ 1’ and the DSRPAG[9] bit is also ‘1’. The lower eight bits of DSRPAG are concate- nated to the Wn[14:0] bits to form a 23-bit EA to access program memory. The DSRPAG[8] decides which word should be addressed; when the bit is ‘ 0’, the lower word, and when ‘ 1’, the upper word of the program memory is accessed. The entire program memory is divided into 512 EDS pages, from 200h to 3FFh, each consisting of 16K words of data. Pages, 200h to 2FFh, correspond to the lower words of the program memory, while 300h to 3FFh correspond to the upper words of the program memory. Using this EDS technique, the entire program memory can be accessed. Previously, the access to the upper word of the program memory was not supported. Table 4-11 provides the corresponding 23-bit EDS address for program memory with EDS page and source addresses. For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions will require one instruction cycle in addition to the specified execution time. All other instructions will require two instruction cycles in addition to the specified execution time. For operations that use PSV, which are executed inside a REPEAT loop, there will be some instances that require two instruction cycles in addition to the specified execution time of the instruction:

• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an interrupt
• Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle. TABLE 4-11: EDS PROGRAM ADDRESS WITH DIFFERENT PAGES AND ADDRESSES EXAMPLE 4-1: EDS READ CODE FROM PROGRAM MEMORY IN ASSEMBLY DSRPAG (Data Space Read Register) Source Address while Indirect Addressing 23-Bit EA Pointing to EDS Comment 200h 2FFh 8000h to FFFFh 000000h to 007FFEh 7F8000h to 7FFFFEh Lower words of 4M program instructions (8 Mbytes) for read operations only. 300h 3FFh 000001h to 007FFFh 7F8001h to 7FFFFFh Upper words of 4M program instructions (4 Mbytes remaining;

4 Mbytes are phantom bytes) for

read operations only. 000h Invalid Address Address error trap. (1) Note 1: When the source/destination address is above 8000h and DSRPAG/DSWPAG is ‘0’, an address error trap will occur. ; Set the EDS page from where the data to be read mov #0x0202, w0 mov w0, DSRPAG ;page 0x202, consisting lower words, is selected for read mov #0x000A, w1 ;select the location (0x0A) to be read bset w1, #15 ;set the MSB of the base address, enable EDS mode ;Read a byte from the selected location mov.b [w1++], w2 ;read Low byte mov.b [w1++], w3 ;read High byte ;Read a word from the selected location mov [w1], w2 ; ;Read Double - word from the selected location mov.d [w1], w2 ;two word read, stored in w2 and w3

DS30010198B-page 52  2019-2020 Microchip Technology Inc. NOTES:

 2019-2020 Microchip Technology Inc. DS30010198B-page 53 PIC24FJ128GL306 FAMILY

5.0 DIRECT MEMORY ACCESS

CONTROLLER (DMA) The Direct Memory Access (DMA) Controller is designed to service high throughput data peripherals operating on the SFR bus, allowing them to access data memory directly and alleviating the need for CPU-intensive man- agement. By allowing these data-intensive peripherals to share their own data path, the main data bus is also deloaded, resulting in additional power savings. The DMA Controller functions both as a peripheral and a direct extension of the CPU. It is located on the micro- controller data bus, between the CPU and DMA-enabled peripherals, with direct access to SRAM. This partitions the SFR bus into two buses, allowing the DMA Controller access to the DMA-capable peripherals located on the new DMA SFR bus. The controller serves as a Master device on the DMA SFR bus, controlling data flow from DMA-capable peripherals. The controller also monitors CPU instruction process- ing directly, allowing it to be aware of when the CPU requires access to peripherals on the DMA bus and automatically relinquishing control to the CPU as needed. This increases the effective bandwidth for handling data without DMA operations causing a processor Stall. This makes the controller essentially transparent to the user. The DMA Controller has these features:

• Six Independent and Independently Programmable Channels
• Concurrent Operation with the CPU (no DMA caused Wait states)
• DMA Bus Arbitration
• Five Programmable Address modes
• Four Programmable Transfer modes
• Four Flexible Internal Data Transfer modes
• Byte or Word Support for Data Transfer
• 16-Bit Source and Destination Address Register for Each Channel, Dynamically Updated and Reloadable
• 16-Bit Transaction Count Register, Dynamically Updated and Reloadable
• Upper and Lower Address Limit Registers
• Counter Half-Full Level Interrupt
• Software Triggered Transfer
• Null Write mode for Symmetric Buffer Operations A simplified block diagram of the DMA Controller is shown in Figure 5-1. FIGURE 5-1: DMA FUNCTIONAL BLOCK DIAGRAM Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive reference source. To complement the infor- mation in this data sheet, refer to “Direct Memory Access Controller (DMA)” (www.microchip.com/DS30009742) in the “dsPIC33/PIC24 Family Reference Man- ual”. The information in this data sheet supersedes the information in the FRM. To I/O Ports To DMA-Enabled Peripheralsand Peripherals DMACH0 DMAINT0 DMASRC0 DMADST0 DMACNT0 DMACH1 DMAINT1 DMASRC1 DMADST1 DMACNT1 DMACH4 DMAINT4 DMASRC4 DMADST4 DMACNT4 DMACH5 DMAINT5 DMASRC5 DMADST5 DMACNT5 DMACON DMAH DMAL DMABUF Channel 0 Channel 1 Channel 4 Channel 5 Data RAM Address Generation Data RAM Control Logic Data Bus CPU Execution Monitoring

DS30010198B-page 54  2019-2020 Microchip Technology Inc.

5.1 Summary of DMA Operations

The DMA Controller is capable of moving data between addresses according to a number of different parameters. Each of these parameters can be independently configured for any transaction; in addition, any or all of the DMA channels can independently perform a differ- ent transaction at the same time. Transactions are classified by these parameters:

• Source and destination (SFRs and data RAM)
• Data size (byte or word)
• Trigger source
• Transfer mode (One-Shot, Repeated or Continuous)
• Addressing modes (Fixed Address or Address Blocks, with or without Address Increment/ Decrement) In addition, the DMA Controller provides channel priority arbitration for all channels.

5.1.1 SOURCE AND DESTINATION

Using the DMA Controller, data may be moved between any two addresses in the Data Space. The SFR space (0000h to 07FFh), or the data RAM space (0800h to FFFFh), can serve as either the source or the destina- tion. Data can be moved between these areas in either direction or between addresses in either area. The four different combinations are shown in Figure 5-2. If it is necessary to protect areas of data RAM, the DMA Controller allows the user to set upper and lower address boundaries for operations in the Data Space above the SFR space. The boundaries are set by the DMAH and DMAL Limit registers. If a DMA channel attempts an operation outside of the address boundaries, the transaction is terminated and an interrupt is generated.

5.1.2 DATA SIZE

The DMA Controller can handle both 8-bit and 16-bit transactions. Size is user-selectable using the SIZE bit (DMACHn[1]). By default, each channel is configured for word-sized transactions. When byte-sized transac- tions are chosen, the LSb of the source and/or destination address determines if the data represent the upper or lower byte of the data RAM location.

5.1.3 TRIGGER SOURCE

The DMA Controller can use any one of the device’s interrupt sources to initiate a transaction. The DMA trigger sources are listed in reverse order of their natural interrupt priority and are shown in Table 5-1. Since the source and destination addresses for any transaction can be programmed independently of the trigger source, the DMA Controller can use any trigger to perform an operation on any peripheral. This also allows DMA channels to be cascaded to perform more complex transfer operations.

5.1.4 TRANSFER MODE

The DMA Controller supports four types of data transfers, based on the volume of data to be moved for each trigger.

• One-Shot: A single transaction occurs for each trigger.
• Continuous: A series of back-to-back transactions occur for each trigger; the number of transactions is determined by the DMACNTn transaction counter.
• Repeated One-Shot: A single transaction is performed repeatedly, once per trigger, until the DMA channel is disabled.
• Repeated Continuous: A series of transactions are performed repeatedly, one cycle per trigger, until the DMA channel is disabled. All transfer modes allow the option to have the source and destination addresses, and counter value, auto- matically reloaded after the completion of a transaction. Repeated mode transfers do this automatically.

5.1.5 ADDRESSING MODES

The DMA Controller also supports transfers between single addresses or address ranges. The four basic options are:

• Fixed-to-Fixed: Between two constant addresses
• Fixed-to-Block: From a constant source address to a range of destination addresses
• Block-to-Fixed: From a range of source addresses to a single, constant destination address
• Block-to-Block: From a range of source addresses to a range of destination addresses The option to select auto-increment or auto-decrement of source and/or destination addresses is available for Block Addressing modes. In addition to the four basic modes, the DMA Controller also supports Peripheral Indirect Addressing (PIA) mode, where the source or destination address is gen- erated jointly by the DMA Controller and a PIA-capable peripheral. When enabled, the DMA channel provides a base source and/or destination address, while the peripheral provides a fixed range offset address. For PIC24FJ128GL306 family devices, the 12-bit A/D Converter module is the only PIA-capable peripheral. Details for its use in PIA mode are provided in Section 22.0 “12-Bit A/D Converter with Threshold Detect”.

 2019-2020 Microchip Technology Inc. DS30010198B-page 55 PIC24FJ128GL306 FAMILY FIGURE 5-2: TYPES OF DMA DATA TRANSFERS SFR Area Data RAM DMA RAM Area SFR Area Data RAM DMA RAM Area SFR Area Data RAM SFR Area Data RAM 07FFh 0800h DMASRCn DMADSTn DMA RAM Area DMAL DMAH 07FFh 0800h DMASRCn DMADSTn DMAL DMAH 07FFh 0800h DMASRCn DMADSTn DMAL DMAH 07FFh 0800h DMASRCn DMADSTn DMAL DMAH DMA RAM Area Peripheral to Memory Memory to Peripheral Peripheral to Peripheral Memory to Memory Note: Relative sizes of memory areas are not shown to scale.

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5.1.6 CHANNEL PRIORITY

Each DMA channel functions independently of the others, but also competes with the others for access to the data and DMA buses. When access collisions occur, the DMA Controller arbitrates between the channels using a user-selectable priority scheme. Two schemes are available:

• Round-Robin: When two or more channels collide, the lower numbered channel receives priority on the first collision. On subsequent colli- sions, the higher numbered channels each receive priority, based on their channel number.
• Fixed: When two or more channels collide, the lowest numbered channel always receives priority, regardless of past history; however, any channel being actively processed is not available for an immediate retrigger. If a higher priority channel is continually requesting service, it will be scheduled for service after the next lower priority channel with a pending request.

5.2 Typical Setup

To set up a DMA channel for a basic data transfer: 1. Enable the DMA Controller (DMAEN = 1) and select an appropriate channel priority scheme by setting or clearing PRSSEL. 2. Program DMAH and DMAL with the appropriate upper and lower address boundaries for data RAM operations. 3. Select the DMA channel to be used and disable its operation (CHEN = 0). 4. Program the appropriate source and destination addresses for the transaction into the channel’s DMASRCn and DMADSTn registers. For PIA mode addressing, use the base address value. 5. Program the DMACNTn register for the number of triggers per transfer (One-Shot or Continuous modes) or the number of words (bytes) to be transferred (Repeated modes). 6. Set or clear the SIZE bit to select the data size. 7. Program the TRMODE[1:0] bits to select the Data Transfer mode. 8. Program the SAMODE[1:0] and DAMODE[1:0] bits to select the addressing mode. 9. Enable the DMA channel by setting CHEN. 10. Enable the trigger source interrupt.

5.3 Peripheral Module Disable

Unlike other peripheral modules, the channels of the DMA Controller cannot be individually powered down using the Peripheral Module Disable (PMD) registers. Instead, the channels are controlled as two groups. The DMA0MD bit (PMD7[4]) selectively controls DMACH0 through DMACH3. The DMA1MD bit (PMD7[5]) controls DMACH4 and DMACH5. Setting both bits effectively disables the DMA Controller.

5.4 DMA Registers

The DMA Controller uses a number of registers to con- trol its operation. The number of registers depends on the number of channels implemented for a particular device. There are always four module-level registers (one control and three buffer/address):

• DMACON: DMA Engine Control Register (Register 5-1)
• DMAH and DMAL: DMA High and Low Address Limit Registers
• DMABUF: DMA Data Buffer Each of the DMA channels implements five registers (two control and three buffer/address):
• DMACHn: DMA Channel n Control Register (Register 5-2)
• DMAINTn: DMA Channel n Interrupt Register (Register 5-3)
• DMASRCn: DMA Data Source Address Pointer for Channel n
• DMADSTn: DMA Data Destination Address Pointer for Channel n
• DMACNTn: DMA Transaction Counter for Channel n For PIC24FJ128GL306 family devices, there are a total of 34 registers.

 2019-2020 Microchip Technology Inc. DS30010198B-page 57 PIC24FJ128GL306 FAMILY REGISTER 5-1: DMACON: DMA ENGINE CONTROL REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DMAEN: DMA Module Enable bit 1 = Enables module 0 = Disables module and terminates all active DMA operation(s) bit 14-1 Unimplemented: Read as ‘0’ bit 0 PRSSEL: Channel Priority Scheme Selection bit 1 = Round-robin scheme 0 = Fixed priority scheme

DS30010198B-page 58  2019-2020 Microchip Technology Inc. REGISTER 5-2: DMACHn: DMA CHANNEL n CONTROL REGISTER U-0 U-0 U-0 r-0 U-0 R/W-0 R/W-0 R/W-0 — — — — —N U L L W R E L O A D (1) CHREQ(3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 SIZE CHEN bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 Reserved: Maintain as ‘0’ bit 11 Unimplemented: Read as ‘0’ bit 10 NULLW: Null Write Mode bit 1 = A dummy write is initiated to DMASRCn for every write to DMADSTn 0 = No dummy write is initiated bit 9 RELOAD: Address and Count Reload bit(1) 1 = DMASRCn, DMADSTn and DMACNTn registers are reloaded to their previous values upon the start of the next operation 0 = DMASRCn, DMADSTn and DMACNTn are not reloaded on the start of the next operation (2) bit 8 CHREQ: DMA Channel Software Request bit(3) 1 = A DMA request is initiated by software; automatically cleared upon completion of a DMA transfer 0 = No DMA request is pending bit 7-6 SAMODE[1:0]: Source Address Mode Selection bits 11 = DMASRCn is used in Peripheral Indirect Addressing and remains unchanged 10 = DMASRCn is decremented based on the SIZE bit after a transfer completion 01 = DMASRCn is incremented based on the SIZE bit after a transfer completion 00 = DMASRCn remains unchanged after a transfer completion bit 5-4 DAMODE[1:0]: Destination Address Mode Selection bits 11 = DMADSTn is used in Peripheral Indirect Addressing and remains unchanged 10 = DMADSTn is decremented based on the SIZE bit after a transfer completion 01 = DMADSTn is incremented based on the SIZE bit after a transfer completion 00 = DMADSTn remains unchanged after a transfer completion bit 3-2 TRMODE[1:0]: Transfer Mode Selection bits 11 = Repeated Continuous mode 10 = Continuous mode 01 = Repeated One-Shot mode 00 = One-Shot mode bit 1 SIZE: Data Size Selection bit 1 = Byte (8-bit) 0 = Word (16-bit) bit 0 CHEN: DMA Channel Enable bit 1 = The corresponding channel is enabled 0 = The corresponding channel is disabled Note 1: Only the original DMACNTn is required to be stored to recover the original DMASRCn and DMADSTn. 2: DMASRCn, DMADSTn and DMACNTn are always reloaded in Repeated mode transfers (DMACHn[2] = 1), regardless of the state of the RELOAD bit. 3: The number of transfers executed while CHREQ is set depends on the configuration of TRMODE[1:0].

 2019-2020 Microchip Technology Inc. DS30010198B-page 59 PIC24FJ128GL306 FAMILY REGISTER 5-3: DMAINTn: DMA CHANNEL n INTERRUPT REGISTER R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DBUFWF(1) CHSEL6 CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 HIGHIF(1,2) LOWIF(1,2) DONEIF(1) HALFIF(1) OVRUNIF(1) — —H A L F E N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DBUFWF: DMA Buffered Data Write Flag bit(1) 1 = The content of the DMA buffer has not been written to the location specified in DMADSTn or DMASRCn in Null Write mode 0 = The content of the DMA buffer has been written to the location specified in DMADSTn or DMASRCn in Null Write mode bit 14-8 CHSEL[6:0]: DMA Channel Trigger Selection bits See Table 5-1 for a complete list. bit 7 HIGHIF: DMA High Address Limit Interrupt Flag bit(1,2) 1 = The DMA channel has attempted to access an address higher than DMAH or the upper limit of the data RAM space 0 = The DMA channel has not invoked the high address limit interrupt bit 6 LOWIF: DMA Low Address Limit Interrupt Flag bit(1,2) 1 = The DMA channel has attempted to access the DMA SFR address lower than DMAL, but above the SFR range (07FFh) 0 = The DMA channel has not invoked the low address limit interrupt bit 5 DONEIF: DMA Complete Operation Interrupt Flag bit(1) If CHEN = 1: 1 = The previous DMA session has ended with completion 0 = The current DMA session has not yet completed If CHEN = 0: 1 = The previous DMA session has ended with completion 0 = The previous DMA session has ended without completion bit 4 HALFIF: DMA 50% Watermark Level Interrupt Flag bit(1) 1 = DMACNTn has reached the halfway point to 0000h 0 = DMACNTn has not reached the halfway point bit 3 OVRUNIF: DMA Channel Overrun Flag bit(1) 1 = The DMA channel is triggered while it is still completing the operation based on the previous trigger 0 = The overrun condition has not occurred bit 2-1 Unimplemented: Read as ‘0’ bit 0 HALFEN: Halfway Completion Watermark bit 1 = Interrupts are invoked when DMACNTn has reached its halfway point and at completion 0 = An interrupt is invoked only at the completion of the transfer Note 1: Setting these flags in software does not generate an interrupt. 2: Testing for address limit violations (DMASRCn or DMADSTn is either greater than DMAH or less than DMAL) is NOT done before the actual access.

DS30010198B-page 60  2019-2020 Microchip Technology Inc. TABLE 5-1: DMA TRIGGER SOURCES CHSEL[6:0] Trigger (Interrupt) CHSEL[6:0] Trigger (Interrupt) 0000000 0h Off 1000101 45h UART1 RX Interrupt 0000001 1h Reserved 1000110 46h UART1 Error Interrupt 0000111 7h MCCP5 IC/OC Interrupt 1001010 4Ah 0001000 8h MCCP5 Timer Interrupt 1001011 4Bh DMACHA5 Interrupt 0001001 9h MCCP4 IC/OC Interrupt 1001100 4Ch DMACHA4 Interrupt

0001010 Ah MCCP4 Timer Interrupt 1001101 4Dh DMACHA3 Interrupt

0001011 Bh MCCP3 IC/OC Interrupt 1001110 4Eh DMACHA2 Interrupt

0001100 Ch MCCP3 Timer Interrupt 1001111 4Fh DMACHA1 Interrupt

0001101 Dh MCCP2 IC/OC Interrupt 1010000 50h DMACHA0 Interrupt

0001110 Eh MCCP2 Timer Interrupt 1010001 51h ADC Interrupt

0001111 Fh MCCP1 IC/OC Interrupt 1010010 52h

0100010 22h 1010101 55h CRC Interrupt 0100011 23h SPI2 Receive Interrupt 1010110 56h LCD Interrupt 0100100 24h SPI2 Transmit Interrupt 1010111 57h LCD Automation Interrupt 0100101 25h SPI2 General Interrupt 1011000 58h Reserved 0100110 26h SPI1 Receive Interrupt 1011001 59h CLC4 Out 0100111 27h SPI1 Transmit Interrupt 1011010 5Ah CLC3 Out 0101000 28h SPI1 General Interrupt 1011011 5Bh CLC2 Out 0101001 29h Reserved 1011100 5Ch CLC1 Out 0101110 2Eh 1011110 5Eh RTCC Alarm Interrupt 0101111 2Fh I2C2 Slave Interrupt 1011111 5Fh TMR5 Interrupt 0110000 30h I2C2 Master Interrupt 1100000 60h TMR4 Interrupt 0110001 31h I2C2 Collision Interrupt 1100001 61h TMR3 Interrupt 0110010 32h I2C1 Slave Interrupt 1100010 62h TMR2 Interrupt 0110011 33h I2C1 Master Interrupt 1100011 63h TMR1 Interrupt 0110100 34h I2C1 Collision Interrupt 1100100 64h Reserved0110101 35h Reserved 0111010 3Ah 1100111 67h Comparator Interrupt 0111011 3Bh UART4 TX Interrupt 1101000 68h INT4 Interrupt 0111100 3Ch UART4 RX Interrupt 1101001 69h INT3 Interrupt 0111101 3Dh UART4 Error Interrupt 1101010 6Ah INT2 Interrupt 0111110 3Eh UART3 TX Interrupt 1101011 6Bh INT1 Interrupt 0111111 3Fh UART3 RX Interrupt 1101100 6Ch INT0 Interrupt 1000000 40h UART3 Error Interrupt 1101101 6Dh Interrupt-on-Change (IOC) Interrupt 1000001 41h UART2 TX Interrupt 1101110 6Eh 1000011 43h UART2 Error Interrupt 1111111 7Fh 1000100 44h UART1 TX Interrupt

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6.0 FLASH PROGRAM MEMORY

The PIC24FJ128GL306 family of devices contains internal Flash program memory for storing and execut- ing application code. The program memory is readable, writable and erasable. The Flash memory can be programmed in four ways:

• In-Circuit Serial Programming™ (ICSP™)
• Run-Time Self-Programming (RTSP)
• J T A G
• Enhanced In-Circuit Serial Programming (Enhanced ICSP) ICSP allows a PIC24FJ128GL306 family device to be serially programmed while in the end application circuit. This is simply done with two lines for the programming clock and programming data (named PGCx and PGDx, respectively), and three other lines for power (V DD), ground (V SS) and Master Clear (MCLR ). This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. RTSP is accomplished using TBLRD (Table Read) and TBLWT (Table Write) instructions. With RTSP , the user may write program memory data in blocks of 128 instructions (384 bytes) at a time and erase program memory in blocks of 1024 instructions (3072 bytes) at a time. The device implements a 7-bit Error Correcting Code (ECC). The NVM block contains a logic to write and read ECC bits to and from the Flash memory. The Flash is programmed at the same time as the corresponding ECC parity bits. The ECC provides improved resistance to Flash errors. ECC single-bit errors can be transparently corrected; ECC double-bit errors generate an interrupt.

6.1 Table Instructions and Flash

Regardless of the method used, all programming of Flash memory is done with the Table Read and Table Write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using the TBLPAG[7:0] bits and the Effective Address (EA) from a W register, specified in the table instruction, as shown in Figure 6-1. The TBLRDL and the TBLWTL instructions are used to read or write to bits[15:0] of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits[23:16] of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode. FIGURE 6-1: ADDRESSING FOR TABLE REGISTERS Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive refer- ence source. For more information, refer to “PIC24F Flash Program Memory” (www.microchip.com/DS30009715) in the “dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. 0Program Counter

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6.2 RTSP Operation

The PIC24F Flash program memory array is organized into rows of 128 instructions or 384 bytes. RTSP allows the user to erase blocks of eight rows (1024 instruc- tions) at a time and to program one row at a time. It is also possible to program two instruction word blocks. The 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 3072 bytes and 384 bytes, respectively. When data are written to program memory using TBLWT instructions, the data are not written directly to memory. Instead, data written using Table Writes are stored in holding latches until the programming sequence is executed. Any number of TBLWT instructions can be executed and a write will be successfully performed. However,

128 TBLWT instructions are required to write the full row

of memory. To ensure that no data are corrupted during a write, any unused address should be programmed with FFFFFFh. This is because the holding latches reset to an unknown state, so if the addresses are left in the Reset state, they may overwrite the locations on rows which were not rewritten. The basic sequence for RTSP programming is to set the Table Pointer to point to the programming latches, do a series of TBLWT instructions to load the buffers and set the NVMADRU/NVMADR registers to point to the destination. Programming is performed by setting the control bits in the NVMCON register. Data can be loaded in any order and the holding registers can be written to multiple times before perform- ing a write operation. Subsequent writes, however, will wipe out any previous writes. All of the Table Write operations are single-word writes (two instruction cycles), because only the buffers are written. A programmi ng cycle is required for programming each row.

6.2.1 PROGRAMMING OPERATIONS

A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. During a programming or erase operation, the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON[15]) starts the operation and the WR bit is automatically cleared when the operation is finished.

6.2.2 PROGRAMMING ALGORITHM FOR

The user can program one row of Flash program memory at a time. To do this, it is necessary to erase the 8-row erase block containing the desired row. The general process is: 1. Read eight rows of program memory (1024 instructions) and store in data RAM. 2. Update the program data in RAM with the desired new data. 3. Erase the block (see Example 6-1): a) Set the NVMOP[3:0] bits (NVMCON[3:0]) to ‘0011’ to configure for block erase. Set the WREN (NVMCON[14]) bit. b) Write the starting address of the block to be erased into the NVMADRU/NVMADR registers. c) Write 55h to NVMKEY. d) Write AAh to NVMKEY . e) Set the WR bit (NVMCON[15]). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. 4. Update the TBLPAG register to point to the programming latches on the device. Update the NVMADRU/NVMADR registers to point to the destination in the program memory. 5. Write the first 128 instructions from data RAM into the program memory buffers (see Table 6-1). 6. Write the program block to Flash memory: a) Set the NVMOPx bits to ‘ 0010’ to configure for row programming. Set the WREN bit. b) Write 55h to NVMKEY. c) Write AAh to NVMKEY . d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. 7. Repeat Steps 4 through 6, using the next available 128 instructions from the block in data RAM, by incrementing the value in NVMADRU/ NVMADR until all 1024 instructions are written back to Flash memory. For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 6-2. Note: Writing to a location multiple times without erasing is not recommended.

 2019-2020 Microchip Technology Inc. DS30010198B-page 63 PIC24FJ128GL306 FAMILY TABLE 6-1: EXAMPLE PAGE ERASE EXAMPLE 6-1: ERASING A PROGRAM ME MORY BLOCK (‘C’ LANGUAGE CODE) Step 1: Set the NVMCON register to erase a page. MOV #0x4003, W0 MOV W0, NVMCON Step 2: Load the address of the page to be erased into the NVMADRU/NVMADR register pair. MOV #PAGE_ADDR_LO, W0 MOV W0, NVMADR MOV #PAGE_ADDR_HI, W0 MOV W0, NVMADRU Step 3: Set the WR bit. MOV #0x55, W0 MOV W0, NVMKEY MOV #0xAA, W0 MOV W0, NVMKEY BSET NVMCON, #WR NOP NOP NOP // C example using MPLAB XC16 unsigned long progAddr = 0xXXXXXX; // Address of row to write unsigned int offset; //Set up pointer to the first memory location to be written NVMADRU = progAddr>>16; // Initialize PM Page Boundary SFR NVMADR = progAddr & 0xFFFF; // Initialize lower word of address NVMCON = 0x4003; // Initialize NVMCON asm("DISI #5"); // Block all interrupts with priority <7 // for next 5 instructions __builtin_write_NVM(); // check function to perform unlock // sequence and set WR

DS30010198B-page 64  2019-2020 Microchip Technology Inc. EXAMPLE 6-2: ROW PR OGRAMMING (‘C’ LANGUAGE CODE) TABLE 6-2: CODE MEMORY PROG RAMMING EXAMPLE: ROW WRITES Step 1: Set the NVMCON register to program 128 instruction words. MOV #0x4002, W0 MOV W0, NVMCON Step 2: Initialize the TBLPAG register for writing to the latches. MOV #0xFA, W12 MOV W12, TBLPAG Step 3: Load W0:W5 with the next four instruction words to program. MOV #<LSW0>, W0 MOV #<MSB1:MSB0>, W1 MOV #<LSW1>, W2 MOV #<LSW2>, W3 MOV #<MSB3:MSB2>, W4 MOV #<LSW3>, W5 Step 4: Set the Read Pointer (W6) and load the (next set of) write latches. CLR W6 CLR W7 TBLWTL [W6++], [W7] TBLWTH.B [W6++], [W7++] TBLWTH.B [W6++], [++W7] TBLWTL [W6++], [W7++] TBLWTL [W6++], [W7] TBLWTH.B [W6++], [W7++] TBLWTH.B [W6++], [++W7] TBLWTL [W6++], [W7++] Step 5: Repeat Steps 4 and 5, for a total of 32 times, to load the write latches with 128 instructions. Step 6: Set the NVMADRU/NVMADR register pair to point to the correct address. MOV #DestinationAddress[15:0], W3 MOV #DestinationAddress[23:16], W4 MOV W3, NVMADR MOV W4, NVMADRU Step 7: Execute the WR bit unlock sequence and initiate the write cycle. MOV #0x55, W0 MOV W0, NVMKEY MOV #0xAA, W0 MOV W0, NVMKEY BSET NVMCON, #WR NOP NOP NOP int varWord1L[128]; int varWord1H[128]; int targetWriteAddressL; // bits<15:0> int targetWriteAddressH; // bits<22:16> int i; NVMCON = 0x4002; // Set WREN and row program mode TBLPAG = 0xFA; NVMADRL = targetWriteAddressL; // set target write address NVMADRH = targetWriteAddressH; for(i=0; i<128; i++) // load write latches with data { // to be written __builtin_tblwtl( (i*2), varWord1L[i]); __builtin_tblwth( (i*2), varWord1H[i]); __builtin_disi(5); //Disable interrupts for NVM unlock sequence __builtin_write_NVM(); // initiate write

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6.2.3 PROGRAMMING A DOUBLE WORD

If a Flash location has been erased, it can be programmed using Table Write instructions to write two instruction words (2 x 24-bit) into the write latch. The TBLPAG register is loaded with the address of the write latches and the NVMADRU/NVMADR registers are loaded with the address of the first of the two instruction words to be programmed. The TBLWTL and TBLWTH instructions write the desired data into the write latches. To configure the NVMCON register for a two-word write, set the NVMOPx bits (NVMCON[3:0]) to ‘ 0001’. The write is performed by executing the unlock sequence and setting the WR bit. An equivalent procedure in ‘C’, using the MPLAB ® XC16 compiler and built-in hardware functions, is shown in Example 6-3. TABLE 6-3: PROGRAMMING A DOUBLE WORD OF FLASH PROGRAM MEMORY Step 1: Initialize the TBLPAG register for writing to the latches. MOV #0xFA, W12 MOV W12, TBLPAG Step 2: Load W0:W2 with the next two packed instruction words to program. MOV #<LSW0>, W0 MOV #<MSB1:MSB0>, W1 MOV #<LSW1>, W2 Step 3: Set the Read Pointer (W6) and Write Pointer (W7), and load the (next set of) write latches. CLR W6 CLR W7 TBLWTL [W6++], [W7] TBLWTH.B [W6++], [W7++] TBLWTH.B [W6++], [++W7] TBLWTL.W [W6++], [W7++] Step 4: Set the NVMADRU/NVMADR register pair to point to the correct address. MOV #DestinationAddress[15:0], W3 MOV #DestinationAddress[23:16], W4 MOV W3, NVMADR MOV W4, NVMADRU Step 5: Set the NVMCON register to program two instruction words. MOV #0x4001, W10 MOV W10, NVMCON NOP Step 6: Initiate the write cycle. MOV #0x55, W1 MOV W1, NVMKEY MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP NOP

DS30010198B-page 66  2019-2020 Microchip Technology Inc. EXAMPLE 6-3: PROGRAMMING A DOUBLE WORD OF FLASH PROGRAM MEMORY (‘C’ LANGUAGE CODE) // C example using MPLAB XC16 unsigned long progAddr = 0xXXXXXX; // Address of word to program unsigned int progData1L = 0xXXXX; // Data to program lower word of word 1 unsigned char progData1H = 0xXX; // Data to program upper byte of word 1 unsigned int progData2L = 0xXXXX; // Data to program lower word of word 2 unsigned char progData2H = 0xXX; // Data to program upper byte of word 2 //Set up NVMCON for word programming NVMCON = 0x4001; // Initialize NVMCON TBLPAG = 0xFA; // Point TBLPAG to the write latches //Set up pointer to the first memory location to be written NVMADRU = progAddr>>16; // Initialize PM Page Boundary SFR NVMADR = progAddr & 0xFFFF; // Initialize lower word of address //Perform TBLWT instructions to write latches __builtin_tblwtl(0, progData1L); // Write word 1 to address low word __builtin_tblwth(0, progData2H); // Write word 1 to upper byte __builtin_tblwtl(1, progData2L); // Write word 2 to address low word __builtin_tblwth(1, progData2H); // Write word 2 to upper byte asm(“DISI #5”); // Block interrupts with priority <7 for next 5 // instructions __builtin_write_NVM(); // XC16 function to perform unlock sequence and set WR

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6.3 Control Registers

There are four SFRs used to read and write the Program Flash Memory (PFM): NVMCON, NVMADRU, NVMADR and NVMKEY. The NVMCON register ( Register 6-1) controls which blocks are to be erased, which memory type is to be programmed and when the programming cycle starts. NVMKEY (Register 6-4) is a write-only register that is used for write protection. To start a programming or erase sequence, the user must consecutively write 55h and AAh to the NVMKEY register. Refer to Section 6.2.1 “Programming Operations” for further details. The NVMADRU/NVMADR registers contain the upper byte and lower word of the destination of the NVM write or erase operation. Some operations (chip erase) operate on fixed locations and do not require an address value. REGISTER 6-1: NVMCON: NONVOLATIL E FLASH MEMORY CONTROL REGISTER HC/R/S-0(1,3) R/W-0(1) HSC/R-0(1) R/W-0 r-0 r-0 U-0 U-0 WR WREN WRERR NVMSIDL — — — — bit 15 bit 8 — — — —N V M O P 3 (2) NVMOP2(2) NVMOP1(2) NVMOP0(2) bit 7 bit 0 Legend: S = Settable bit HC = Hardware Clearable bit r = Reserved bit R = Readable bit W = Writable bit ‘0’ = Bit is cleared x = Bit is unknown -n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ HSC = Hardware Settable/Clearable bit bit 15 WR: Write Control bit (1,3) 1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is cleared by hardware once the operation is complete 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit(1) 1 = Enables Flash program/erase operations 0 = Inhibits Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit(1) 1 = An improper program or erase sequence attempt, or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12 NVMSIDL: NVM Stop in Idle bit 1 = Removes power from the program memory when device enters Idle mode 0 = Powers program memory in Standby mode when the device enters Idle mode bit 11-10 Reserved: Maintain as ‘0’ bit 9-4 Unimplemented: Read as ‘0’ bit 3-0 NVMOP[3:0]: NVM Operation Select bits(1,2) 1110 = Chip erases user memory (does not erase Device ID, customer OTP or executive memory) 0100 = Unused 0011 = Erases a page of program or executive memory 0010 = Row programming operation 0001 = Double-word programming operation Note 1: These bits can only be reset on a Power-on Reset. 2: All other combinations of NVMOP[3:0] are unimplemented. 3: Unlock sequence must be executed before writing to this bit.

DS30010198B-page 68  2019-2020 Microchip Technology Inc. REGISTER 6-2: NVMADR: NONVOLATIL E MEMORY LOWER ADDRESS REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x NVMADR[15:8] bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x NVMADR[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 NVMADR[15:0]: Nonvolatile Memory Lower Write Address bits Selects the lower 16 bits of the location to program or erase in Program Flash Memory. This register may be read or written to by the user application. REGISTER 6-3: NVMADRU: NONVOLATIL E MEMORY UPPER ADDRESS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x NVMADRU[23:16] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMADRU[23:16]: Nonvolatile Memory Upper Write Address bits Selects the upper eight bits of the location to program or erase in Program Flash Memory. This register may be read or written to by the user application.

 2019-2020 Microchip Technology Inc. DS30010198B-page 69 PIC24FJ128GL306 FAMILY Register 6-4: NVMKEY: NONVOL ATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY[7:0]: NVM Key Register bits (write-only)

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6.4 Error Correcting Code (ECC)

In order to improve program memory performance and durability, these devices include Error Correcting Code (ECC) functionality as an integral part of the Flash memory controller. ECC can determine the presence of single-bit errors in program data, including which bit is in error, and correct the data automatically without user intervention. ECC cannot be disabled. When data are written to program memory, ECC generates a 7-bit Hamming code parity value for every two (24-bit) instruction words. The data are stored in blocks of 48 data bits and seven parity bits; parity data are not memory-mapped and are inaccessible. When the data are read back, the ECC calculates the parity on them and compares it to the previously stored parity value. If a parity mismatch occurs, there are two possible outcomes:

• Single-bit error has occurred and has been automatically corrected on read-back
• Double-bit error has occurred and the read data are not changed Single-bit error occurrence can be identified by the state of the ECCSBEIF (IFS6[12]) bit. An interrupt can be generated when the corresponding interrupt enable bit is set, ECCSBEIE (IEC6[12]). The ECCSTATL register contains the parity information for single-bit errors. The SECOUT[7:0] bits field contains the expected calculated SEC parity and the SECIN[7:0] bits contain the actual value from a Flash read opera- tion. The SECSYNDx bits (ECCSTATH[7:0]) indicate the bit position of the single-bit error within the 48-bit pair of instruction words. When no error is present, SECINx equals SECOUTx and SECSYNDx is zero. Double-bit error occurrences generate a generic hard trap and set the ECCDBE (INTCON4[1]) bit. If no Inter- rupt Service Routine is implemented for the hard trap, a device Reset will also occur. The ECCSTATH register contains double-bit error status information. The DEDOUT bit is the expected calculated Dual Bit Error Detection (DED) parity and DEDIN is the actual value from a Flash read operation. When no error is present, DEDIN equals DEDOUT.

6.4.1 ECC FAULT INJECTION

To test Fault handling, an ECC error can be generated. Both single and double-bit errors can be generated in both the read and write data paths. Read path Fault injection first reads the Flash data and then modifies them prior to entering the ECC logic. Write path Fault injection modifies the actual data prior to them being written into the target Flash and will cause an ECC error on a subsequent Flash read. The following procedure is used to inject a Fault: 1. Load the Flash target address into the ECCADDR register. 2. Select 1st Fault bit determined by the FLT1PTRx (ECCCONH[7:0]) bits. The target bit is inverted to create the Fault. 3. If a double Fault is desired, select the 2nd Fault bit determined by the FLT2PTRx (ECCCONH[15:8]) bits; otherwise, set to all ‘1’s. 4. Write the NVMKEY unlock sequence (see Section 6.3 “Control Registers”). 5. Enable the ECC Fault injection logic by setting the FLTINJ bit (ECCCONL[0]). 6. Perform a read or write to the Flash target address.

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6.4.2 ECC CONTROL REGISTERS

REGISTER 6-5: ECCCONL: ECC FAULT IN JECTION CONFIGURATION REGISTER LOW U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 Unimplemented: Read as ‘0’ bit 0 FLTINJ: Fault Injection Sequence Enable bit 1 = Enabled 0 =D i s a b l e d REGISTER 6-6: ECCCONH: ECC FAULT IN JECTION CONFIGURATION REGISTER HIGH R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLT2PTR[7:0] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLT1PTR[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 FLT2PTR[7:0]: ECC Fault Injection Bit Pointer 2 bits 11111111-00111000 = No Fault injection occurs 00110111 = Fault injection (bit inversion) occurs on bit 55 of ECC bit order 00000001 = Fault injection (bit inversion) occurs on bit 1 of ECC bit order 00000000 = Fault injection (bit inversion) occurs on bit 0 of ECC bit order bit 7-0 FLT1PTR[7:0]: ECC Fault Injection Bit Pointer 1 bits 11111111-00111000 = No Fault injection occurs 00110111 = Fault injection occurs on bit 55 of ECC bit order 00000001 = Fault injection occurs on bit 1 of ECC bit order 00000000 = Fault injection occurs on bit 0 of ECC bit order

DS30010198B-page 72  2019-2020 Microchip Technology Inc. REGISTER 6-7: ECCADDRL: ECC FAULT INJECT ADDRESS COMPARE REGISTER LOW R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCADDR[15:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCADDR[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 ECCADDR[15:0]: ECC Fault Injection NVM Address Match Compare bits REGISTER 6-8: ECCADDRH: ECC FAULT INJECT ADDRESS COMPARE REGISTER HIGH U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCADDR[23:16] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 ECCADDR[23:16]: ECC Fault Injection NVM Address Match Compare bits

 2019-2020 Microchip Technology Inc. DS30010198B-page 73 PIC24FJ128GL306 FAMILY REGISTER 6-9: ECCSTATL: ECC SYSTEM STATUS DISPLAY REGISTER LOW R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 SECOUT[7:0] bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 SECIN[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 SECOUT[7:0]: Calculated Single Error Correction Parity Value bits bit 7-0 SECIN[7:0]: Read Single Error Correction Parity Value bits SECIN[7:0] bits are the actual parity value of a Flash read operation. REGISTER 6-10: ECCSTATH: ECC SYSTEM STATUS DISPLAY REGISTER HIGH U-0 U-0 U-0 U-0 U-0 U-0 R-0 R-0 bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 SECSYND[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9 DEDOUT: Calculated Dual Bit Error Detection Parity bit bit 8 DEDIN: Read Dual Bit Error Detection Parity bit DEDIN is the actual parity value of a Flash read operation. bit 7-0 SECSYND[7:0]: Calculated ECC Syndrome Value bits Indicates the bit location that contains the error.

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6.5 Flash OTP by ICSP™ Write Inhibit

ICSP Write Inhibit is an access restriction feature, that when activated, restricts all of Flash memory. Once acti- vated, ICSP Write Inhibit permanently prevents ICSP Flash programming and erase operations, and cannot be deactivated. This feature is intended to prevent alter- ation of Flash memory contents, with behavior similar to One-Time-Programmable (OTP) devices. RTSP, including erase and programming operations, is not restricted when ICSP Write Inhibit is activated; however, code to perform these actions must be pro- grammed into the device before ICSP Write Inhibit is activated. This allows for a bootloader-type application to alter Flash contents with ICSP Write Inhibit activated. Entry into ICSP and Enhanced ICSP modes is not affected by ICSP Write Inhibit. In these modes, it will con- tinue to be possible to read configuration memory space and any user memory space regions which are not code protected. With ICSP writes inhibited, an attempt to set WR (NVMCON[15]) = 1 will maintain WR = 0, and instead, set WRERR (NVMCON[13]) = 1. All Enhanced ICSP erase and programming commands will have no effect with self-checked programming commands return- ing a FAIL response opcode (PASS if the destination already exactly matched the requested programming data). Once ICSP Write Inhibit is activated, it is not possible for a device executing in Debug mode to erase/write Flash, nor can a debug tool switch the device to Production mode. ICSP Write Inhibit should therefore, only be activated on devices programmed for production.

6.5.1 ACTIVATING FLASH OTP BY ICSP

ICSP Write Inhibit is activated by executing a pair of NVMCON double-word programming commands to save two 16-bit activation values in the configuration memory space. The target NVM addresses and values required for activation are shown in Table 6-4. Once both addresses contain their activation values, ICSP Write Inhibit will take permanent effect on the next device Reset. Only the lower 16 data bits stored at the activation addresses are evaluated; the upper eight bits and second 24-bit word, written by the double-word pro- gramming (NVMOP[3:0]), should be written as ‘0’s. The addresses can be programmed in any order and also during separate ICSP/Enhanced ICSP/RTSP sessions, but any attempt to program an incorrect 16-bit value or use a row programming operation to program the values will be aborted without altering the existing data. TABLE 6-4: ICSP™ WRITE INHIBIT ACTIVATION ADDRESSES AND DATA

6.6 JTAG Operation

The PIC24F family supports JTAG boundary scan. Boundary scan can improve the manufacturing process by verifying pin to PCB connectivity.

6.7 Enhanced In-Circuit Serial

Enhanced In-Circuit Serial Programming uses an on- board bootloader, known as the Program Executive (PE), to manage the programming process. Using an SPI data frame format, the Program Executive can erase, program and verify program memory. For more information on Enhanced ICSP , refer to the “PIC24FJ128GL306 Family Flash Programming Specification” (www.microchip.com/ DS30010189).Note: It is not possible to deactivate ICSP Write Inhibit. Configuration Memory Address ICSP Write Inhibit Activation Value Write Lock 1 0x801024 0x006D63 Write Lock 2 0x801028 0x006870

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7.0 RESETS

The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources:

• POR: Power-on Reset
• M C L R: Master Clear Pin Reset
• S W R : RESET Instruction
• WDT: Watchdog Timer Reset
• BOR: Brown-out Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Opcode Reset
• UWR: Uninitialized W Register Reset A simplified block diagram of the Reset module is shown in Figure 7-1. Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets. All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 7-1). A POR will clear all bits, except for the BOR and POR (RCON[1:0]) bits, which are set. The user may set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software will not cause a device Reset to occur. The RCON register also has other bits associated with the Watchdog Timer and device Power-Saving states. The function of these bits is discussed in other sections of this data sheet. FIGURE 7-1: RESET SY STEM BLOCK DIAGRAM Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive reference source. For more information, refer to “Reset” ( www.microchip.com/ DS39712) in the “dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. Note: Refer to the specific peripheral or CPU section of this data sheet for register Reset states. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register values after a device Reset will be meaningful. MCLR VDD VDD Rise Detect POR Sleep or Idle Brown-out Reset Enable Voltage Regulator RESET Instruction WDT Module Glitch Filter BOR Trap Conflict Illegal Opcode Uninitialized W Register SYSRST Configuration Mismatch

DS30010198B-page 76  2019-2020 Microchip Technology Inc. REGISTER 7-1: RCON: RE SET CONTROL REGISTER(6) R/W-0 R/W-0 R/W-1 R/W-0 U-0 U-0 R/W-0 R/W-0 TRAPR(1) IOPUWR(1) SBOREN(5) RETEN(2) — —C M (1) VREGS(3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR(1) SWR(1) SWDTEN(4) WDTO(1) SLEEP(1) IDLE(1) BOR(1) POR(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit (1) 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred bit 14 IOPUWR: Illegal Opcode or Uninitialized W Register Access Reset Flag bit(1) 1 = An illegal opcode detection, an illegal address mode or Uninitialized W register is used as an Address Pointer and caused a Reset 0 = An illegal opcode or Uninitialized W register Reset has not occurred bit 13 SBOREN: Software Control Over the BOR Function bit(5) 1 = BOR is enabled 0 = BOR is disabled bit 12 RETEN: Retention Mode Enable bit(2) 1 = Retention mode is enabled while device is in Sleep mode (1.2V regulator supplies to the core) 0 = Retention mode is disabled; normal voltage levels are present bit 11-10 Unimplemented: Read as ‘0’ bit 9 CM: Configuration Word Mismatch Reset Flag bit(1) 1 = A Configuration Word Mismatch Reset has occurred 0 = A Configuration Word Mismatch Reset has not occurred bit 8 VREGS: Fast Wake-up from Sleep bit(3) 1 = Regulator Standby mode is disabled (fast wake-up, uses more power) 0 = Regulator Standby mode is enabled (slow wake-up, uses less power) bit 7 EXTR: External Reset (MCLR) Pin bit(1) 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 SWR: Software RESET (Instruction) Flag bit(1) 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the LPCFG Configuration bit is ‘1’ (unprogrammed), the retention regulator is disabled and the RETEN bit has no effect. 3: Re-enabling the regulator after it enters Standby mode will add a delay, TVREG, when waking up from Sleep. Applications that do not use the voltage regulator should set this bit to prevent this delay from occurring. 4: If the FWDTEN[1:0] Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. 5: The BOREN[1:0] (FPOR[1:0]) Configuration bits must be set to ‘01’ in order for SBOREN to have an effect. 6: On wake-up from Retention Sleep, RCON will have same value as a POR event.

 2019-2020 Microchip Technology Inc. DS30010198B-page 77 PIC24FJ128GL306 FAMILY TABLE 7-1: RESET FLAG BIT OPERATION bit 5 SWDTEN: Software Enable/Disable of WDT bit(4) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit(1) 1 = WDT time-out has occurred 0 = WDT time-out has not occurred bit 3 SLEEP: Wake from Sleep Flag bit(1) 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit(1) 1 = Device has been in Idle mode 0 = Device has not been in Idle mode bit 1 BOR: Brown-out Reset Flag bit(1) 1 = A Brown-out Reset has occurred (also set after a Power-on Reset) 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit(1) 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Flag Bit Setting Event Clearing Event TRAPR (RCON[15]) Trap Conflict Event POR IOPUWR (RCON[14]) Illegal Opcode or Uninitialized W Register Access POR CM (RCON[9]) Configuration Mismatch Reset POR EXTR (RCON[7]) MCLR Reset POR SWR (RCON[6]) RESET Instruction POR WDTO (RCON[4]) WDT Time-out CLRWDT, PWRSAV Instruction, POR SLEEP (RCON[3]) PWRSAV #0 Instruction POR IDLE (RCON[2]) PWRSAV #1 Instruction POR BOR (RCON[1]) POR, BOR — POR (RCON[0]) POR — Note: All Reset flag bits may be set or cleared by the user software. REGISTER 7-1: RCON: RE SET CONTROL REGISTER(6) (CONTINUED) Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the LPCFG Configuration bit is ‘1’ (unprogrammed), the retention regulator is disabled and the RETEN bit has no effect. 3: Re-enabling the regulator after it enters Standby mode will add a delay, TVREG, when waking up from Sleep. Applications that do not use the voltage regulator should set this bit to prevent this delay from occurring. 4: If the FWDTEN[1:0] Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. 5: The BOREN[1:0] (FPOR[1:0]) Configuration bits must be set to ‘01’ in order for SBOREN to have an effect. 6: On wake-up from Retention Sleep, RCON will have same value as a POR event.

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7.1 Special Function Register Reset

Most of the Special Function Registers (SFRs) associated with the PIC24F CPU and peripherals are reset to a par- ticular value at a device Reset. The SFRs are grouped by their peripheral or CPU function and their Reset values are specified in each section of this data sheet. The Reset value for each SFR does not depend on the type of Reset, with the exception of four registers. The Reset value for the Reset Control register, RCON, will depend on the type of device Reset. The Reset value for the Oscillator Control register, OSCCON, will depend on the type of Reset and the programmed values of the FNOSC[2:0] bits in the FOSCSEL Configuration register (see Table 7-2). The NVMCON register is only affected by a POR.

7.2 Device Reset Times

The Reset times for various types of device Reset are summarized in Table 7-3. Note that the Master Reset Signal, SYSRST , is released after the POR delay time expires. The time at which the device actually begins to execute code will also depend on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and the PLL lock time. The OST and PLL lock times occur in parallel with the applicable SYSRST delay times. The Fail-Safe Clock Monitor (FSCM) delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released.

7.3 Brown-out Reset (BOR)

PIC24FJ128GL306 family devices implement a BOR circuit that provides the user with several configuration and power-saving options. The BOR is controlled by the BOREN[1:0] (FPOR[1:0]) Configuration bits. When BOR is enabled, any drop of VDD below the BOR threshold results in a device BOR. Threshold levels are described in Section 30.1 “DC Characteristics”.

7.4 Low-Power BOR (LPBOR)

Low-Power BOR is implemented to provide downside protection when BOR is disabled.

• LPBOR re-arms the POR to ensure that the device will reset if VDD drops below the POR threshold. The LPBOR trip point is around 2.0V.
• LPBOR is selected in the configuration through the DNVPEN bit in the FPOR Configuration register. Because it is designed for very low-current consumption, accuracy may vary slightly.

7.5 Clock Source Selection at Reset

If clock switching is enabled, the system clock source at device Reset is chosen, as shown in Table 7-2. If clock switching is disabled, the system clock source is always selected according to the Oscillator Configura- tion bits. For more information, refer to “Oscillator” (www.microchip.com/DS39700) in the “dsPIC33/PIC24 Family Reference Manual”. TABLE 7-2: OSCILLATOR SELECTION vs. TYPE OF RESET (CLOCK SWITCHING ENABLED) Reset Type Clock Source Determinant POR FNOSC[2:0] Configuration bits (FOSCSEL[2:0])BOR MCLR COSC[2:0] Control bits (OSCCON[14:12])WDTO SWR

 2019-2020 Microchip Technology Inc. DS30010198B-page 79 PIC24FJ128GL306 FAMILY TABLE 7-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Reset Type Clock Source SYSRST Delay System Clock Delay Notes POR EC T POR + TSTARTUP + TRST — 1, 2, 3 ECPLL T POR + TSTARTUP + TRST TLOCK 1, 2, 3, 5 XT, HS, SOSC T POR + TSTARTUP + TRST TOST 1, 2, 3, 4 XTPLL, HSPLL T POR + TSTARTUP + TRST TOST + TLOCK 1, 2, 3, 4, 5 FRC, OSCFDIV T POR + TSTARTUP + TRST TFRC 1, 2, 3, 6, 7 FRCPLL T POR + TSTARTUP + TRST TFRC + TLOCK 1, 2, 3, 5, 6 LPRC T POR + TSTARTUP + TRST TLPRC 1, 2, 3, 6 BOR EC T STARTUP + TRST — 2, 3 ECPLL T STARTUP + TRST TLOCK 2, 3, 5 XT, HS, SOSC T STARTUP + TRST TOST 2, 3, 4 XTPLL, HSPLL T STARTUP + TRST TOST + TLOCK 2, 3, 4, 5 FRC, OSCFDIV T STARTUP + TRST TFRC 2, 3, 6, 7 FRCPLL T STARTUP + TRST TFRC + TLOCK 2, 3, 5, 6 LPRC T STARTUP + TRST TLPRC 2, 3, 6 MCLR Any Clock T RST — 3 WDT Any Clock T RST — 3 Software Any clock T RST — 3 Illegal Opcode Any Clock T RST — 3 Uninitialized W Any Clock T RST — 3 Trap Conflict Any Clock T RST — 3 Note 1: TPOR = Power-on Reset delay (10 µs nominal). 2: TSTARTUP = TVREG. 3: TRST = Internal State Reset Time (2 µs nominal). 4: TOST = Oscillator Start-up Timer (OST). A 10-bit counter counts 1024 oscillator periods before releasing the oscillator clock to the system. 5: TLOCK = PLL Lock Time. 6: TFRC and TLPRC = RC Oscillator Start-up Times. 7: If Two-Speed Start-up is enabled, regardless of the Primary Oscillator selected, the device starts with FRC so the system clock delay is just TFRC, and in such cases, FRC start-up time is valid; it switches to the Primary Oscillator after its respective clock delay.

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7.5.1 POR AND LONG OSCILLATOR

The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low- frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released:

• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a crystal oscillator is used).
• The PLL has not achieved a lock (if PLL is used). The device will not begin to execute code until a valid clock source has been released to the system. There- fore, the oscillator and PLL start-up delays must be considered when the Reset delay time must be known.

7.5.2 FAIL-SAFE CLOCK MONITOR

(FSCM) AND DEVICE RESETS If the FSCM is enabled, it will begin to monitor the system clock source when SYSRST is released. If a valid clock source is not available at this time, the device will automatically switch to the FRC Oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine (TSR).

 2019-2020 Microchip Technology Inc. DS30010198B-page 81 PIC24FJ128GL306 FAMILY

8.0 INTERRUPT CONTROLLER

The PIC24FJ128GL306 family interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the PIC24FJ128GL306 family CPU. The interrupt controller has the following features:

• Up to Eight Processor Exceptions and Software Traps
• Seven User-Selectable Priority Levels
• Interrupt Vector Table (IVT) with a Unique Vector for Each Interrupt or Exception Source
• Fixed Priority within a Specified User Priority Level
• Fixed Interrupt Entry and Return Latencies

8.1 Interrupt Vector Table

The PIC24FJ128GL306 family IVT, shown in Figure 8-1, resides in program memory starting at location, 000004h. The IVT contains six non-maskable trap vectors and up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). Interrupt vectors are prioritized in terms of their natural priority. This priority is linked to their position in the vector table. Lower addresses generally have a higher natural priority. For example, the interrupt associated with Vector 0 takes priority over interrupts at any other vector address.

8.1.1 ALTERNATE INTERRUPT VECTOR

The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 8-1. The AIVTEN (INTCON2[8]) control bit provides access to the AIVT. If the AIVTEN bit is set, all interrupt and exception processes will use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT is available only if the Boot Segment has been defined and the AIVT has been enabled. To enable the AIVT, both the Configuration bit, AIVTDIS (FSEC[15]), and the AIVTEN bit (INTCON2[8] in the SFR), have to be set. When the AIVT is enabled, all interrupts and exception processes use the alternate vectors instead of the default vectors. The AIVT begins at the start of the last page of the Boot Segment (BS) defined by the BSLIM[12:0] bits. The AIVT address is: (BSLIM[12:0] – 1) x 0x800.

8.2 Reset Sequence

A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The PIC24FJ128GL306 family devices clear their registers in response to a Reset, which forces the PC to zero. The device then begins program execution at location, 0x000000. A GOTO instruction at the Reset address can redirect program execution to the appropriate start-up routine. Note 1: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Interrupts” (www.microchip.com/DS70000600 ) in the “dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. Note: Any unimplemented or unused vector locations in the IVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction.

DS30010198B-page 82  2019-2020 Microchip Technology Inc. FIGURE 8-1: PIC24F INTERRUPT VECTOR TABLES TABLE 8-1: TRAP VECTOR DETAILS Vector Number IVT Addres s AIVT Address Trap Source MPLAB® XC16 ISR Name 0 000004h BOA+04h Oscillator Failure _Oscillator Fail 1 000006h BOA+06h Address Error _AddressError 2 000008h BOA+08h General Hardware Error _NVMError 3 00000Ah BOA+0Ah Stack Error _StackError 4 00000Ch BOA+0Ch Math Error _MathError 5 00000Eh BOA+0Eh Reserved Reserved 6 000010h BOA+10h General Software Error _GeneralError 7 000012h BOA+12h Reserved Reserved Legend: BOA = Base Offset Address for AIVT segment, which is the starting address of the last page of the Boot Segment. Legend: BOA: Base Offset Address for AIVT, which is the starting address of the last page of the Boot Segment. All addresses are in hexadecimal. Note 1: See Table 8-2 for the interrupt vector list. 2: AIVT is only available when a Boot Segment is implemented. Reset – GOTO Instruction 000000h Reset – GOTO Address 000002h Oscillator Fail Trap Vector 000004h Address Error Trap Vector General Hard Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved General Soft Trap Vector Reserved Interrupt Vector 0 000014h Interrupt Vector 1 Interrupt Vector 52 00007Ch Interrupt Vector 53 00007Eh Interrupt Vector 54 000080h Interrupt Vector 116 0000FCh Interrupt Vector 117 0000FEh Decreasing Natural Order Priority Interrupt Vector Table (IVT)(1) Alternate Interrupt Vector Table (AIVT)(1,2) Reserved BOA+00h Reserved BOA+02h Oscillator Fail Trap Vector BOA+04h Address Error Trap Vector General Hard Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved General Soft Trap Vector Reserved Interrupt Vector 0 BOA+14h Interrupt Vector 1 Interrupt Vector 52 BOA+7Ch Interrupt Vector 53 BOA+7Eh Interrupt Vector 54 BOA+80h Interrupt Vector 116 Interrupt Vector 117 BOA+FEh (Start of Code) (BOA+100h)

 2019-2020 Microchip Technology Inc. DS30010198B-page 83 PIC24FJ128GL306 FAMILY TABLE 8-2: INTERRUPT VECTOR DETAILS Interrupt Description MPLAB® XC16 ISR Name Vector IRQ # IVT Address Interrupt Bit Location Flag Enable Priority Highest Natural Order Priority External Interrupt 0 _INT0Interrupt 8 0 000014h IFS0[0] IEC0[0] IPC0[2:0] Capture/Compare/Timer1 _CCT1Interrupt 9 1 000016h IFS0[1] IEC0[1] IPC0[6:4] Capture/Compare/Timer2 _CCT2Interrupt 10 2 000018h IFS0[2] IEC0[2] IPC0[10:8] Timer1 _T1Interrupt 11 3 00001Ah IFS0[3] IEC0[3] IPC0[14:12] Direct Memory Access 0 _DMA0Interrupt 12 4 00001Ch IFS0[4] IEC0[4] IPC1[2:0] Reserved Reserved 13-14 5-6 00001Eh-000020h — — — Timer2 _T2Interrupt 15 7 000022h IFS0[7] IEC0[7] IPC1[14:12] Timer3 _T3Interrupt 16 8 000024h IFS0[8] IEC0[8] IPC2[2:0] SPI1 General _SPI1Interrupt 17 9 000026h IFS0[9] IEC0[9] IPC2[6:4] SPI1 Transfer Done _SPI1TXInterrupt 18 10 000028h IFS0[10] IEC0[10] IPC2[10:8] UART1 Receiver _U1RXInterrupt 19 11 00002Ah IFS0[11] IEC0[11] IPC2[14:12] UART1 Transmitter _U1TXInterrupt 20 12 00002Ch IFS0[12] IEC0[12] IPC3[2:0] A/D Converter 1 _ADC1Interrupt 21 13 00002Eh IFS0[13] IEC0[13] IPC3[6:4] Direct Memory Access 1 _DMA1Interrupt 22 14 000030h IFS0[14] IEC0[14] IPC3[10:8] NVM Program/Erase Complete _NVMInterrupt 23 15 000032h IFS0[15] IEC0[15] IPC3[14:12] I2C1 Slave Events _SI2C1Interrupt 24 16 000034h IFS1[0] IEC1[0] IPC4[2:0] I2C1 Master Events _MI2C1Interrupt 25 17 000036h IFS1[1] IEC1[1] IPC4[6:4] Comparator _CompInterrupt 26 18 000038h IFS1[2] IEC1[2] IPC4[10:8] Interrupt-on-Change Interrupt _IOCInterrupt 27 19 00003Ah IFS1[3] IEC1[3] IPC4[14:12] External Interrupt 1 _INT1Interrupt 28 20 00003Ch IFS1[4] IEC1[4] IPC5[2:0] Reserved Reserved 29 21 00003Eh — — — Capture/Compare 5 _CCP5Interrupt 30 22 000040h IFS1[6] IEC1[6] IPC5[10:8] Reserved Reserved 31 23 000042h — — — Direct Memory Access 2 _DMA2Interrupt 32 24 000044h IFS1[8] IEC1[8] IPC6[2:0] Reserved Reserved 33-34 25-26 000046h-000048h — — — Timer4 _T4Interrupt 35 27 00004Ah IFS1[11] IEC1[11] IPC6[14:12] Timer5 _T5Interrupt 36 28 00004Ch IFS1[12] IEC1[12] IPC7[4:2] External Interrupt 2 _INT2Interrupt 37 29 00004Eh IFS1[13] IEC1[13] IPC7[6:4] UART2 Receiver _U2RXInterrupt 38 30 000050h IFS1[14] IEC1[14] IPC7[10:8] UART2 Transmitter _U2TXInterrupt 39 31 000052h IFS1[15] IEC1[15] IPC7[14:12] SPI2 General _SPI2Interrupt 40 32 000054h IFS2[0] IEC2[0] IPC8[2:0] SPI2 Transfer Done _SPI2TXInterrupt 41 33 000056h IFS2[1] IEC2[1] IPC8[6:4] Reserved Reserved 42-43 34-35 000058h-00005Ah — — — Direct Memory Access 3 _DMA3Interrupt 44 36 00005Ch IFS2[4] IEC2[4] IPC9[2:0] Reserved Reserved 45-50 37-42 00005Eh-000068h — — — Capture/Compare/Timer3 _CCT3Interrupt 51 43 00006Ah IFS2[11] IEC2[11] IPC10[14:12] Capture/Compare/Timer4 _CCT4Interrupt 52 44 00006Ch IFS2[12] IEC2[12] IPC11[2:0] Reserved Reserved 53 45 00006Eh — — — Direct Memory Access 4 _DMA4Interrupt 54 46 000070h IFS2[14] IEC2[14] IPC11[10:8] Capture/Compare/Timer5 _CCT5Interrupt 55 47 000072h IFS2[15] IEC2[15] IPC11[14:12] Reserved Reserved 56 48 000074h — — — I2C2 Slave Events _SI2C2Interrupt 57 49 000076h IFS3[1] IEC3[1] IPC12[6:4] I2C2 Master Events _MI2C2Interrupt 58 50 000078h IFS3[2] IEC3[2] IPC12[10:8] Reserved Reserved 59-60 51-52 00007Ah-00007Ch — — —

DS30010198B-page 84  2019-2020 Microchip Technology Inc. External Interrupt 3 _INT3Interrupt 61 53 00007Eh IFS3[5] IEC3[5] IPC13[6:4] External Interrupt 4 _INT4Interrupt 62 54 000080h IFS3[6] IEC3[6] IPC13[10:8] Reserved Reserved 63-65 55-57 000082h-000086h — — — SPI1 Receive Done _SPI1RXInterrupt 66 58 000088h IFS3[10] IEC3[10] IPC14[10:8] SPI2 Receive Done _SPI2RXInterrupt 67 59 00008Ah IFS3[11] IEC3[11] IPC14[14:12] Reserved Reserved 68 60 00008Ch — — — Direct Memory Access 5 _DMA5Interrupt 69 61 00008Eh IFS3[13] IEC3[13] IPC15[6:4] Real-Time Clock and Calendar _RTCCInterrupt 70 62 000090h IFS3[14] IEC3[14] IPC15[10:8] Capture/Compare 1 _CCP1Interrupt 71 63 000092h IFS3[15] IEC3[15] IPC15[14:12] Capture/Compare 2 _CCP2Interrupt 72 64 000094h IFS4[0] IEC4[0] IPC16[2:0] UART1 Error _U1EInterrupt 73 65 000096h IFS4[1] IEC4[1] IPC16[6:4] UART2 Error _U2EInterrupt 74 66 000098h IFS4[2] IEC4[2] IPC16[10:8] Cyclic Redundancy Check _CRCInterrupt 75 67 00009Ah IFS4[3] IEC4[3] IPC16[14:12] Reserved Reserved 76-79 68-71 00009Ch-0000A2h — — — High/Low-Voltage Detect _HLVDInterrupt 80 72 0000A4h IFS4[8] IEC4[8] IPC18[2:0] Reserved Reserved 81-88 73-80 0000A6h-0000B4h — — — UART3 Error _U3EInterrupt 89 81 0000B6h IFS5[1] IEC5[1] IPC20[6:4] UART3 Receiver _U3RXInterrupt 90 82 0000B8h IFS5[2] IEC5[2] IPC20[10:8] UART3 Transmitter _U3TXInterrupt 91 83 0000BAh IFS5[3] IEC5[3] IPC20[14:12] I2C1 Bus Collision _I2C1BCInterrupt 92 84 0000BCh IFS5[4] IEC5[4] IPC21[2:0] I2C2 Bus Collision _I2C2BCInterrupt 93 85 0000BEh IFS5[5] IEC5[5] IPC21[6:4] Reserved Reserved 94 86 0000C0h — — — UART4 Error _U4EInterrupt 95 87 0000C2h IFS5[7] IEC5[7] IPC21[14:12] UART4 Receiver _U4RXInterrupt 96 88 0000C4h IFS5[8] IEC5[8] IPC22[2:0] UART4 Transmitter _U4TXInterrupt 97 89 0000C6h IFS5[9] IEC5[9] IPC20[6:4] Reserved Reserved 98-101 90-93 0000C8h-0000CEh — — — Capture/Compare 3 _CCP3Interrupt 102 94 0000D0h IFS5[14] IEC5[14] IPC23[10:8] Capture/Compare 4 _CCP4Interrupt 103 95 0000D2h IFS5[15] IEC5[15] IPC23[14:12] Configurable Logic Cell 1 _CLC1Interrupt 104 96 0000D4h IFS6[0] IEC6[0] IPC24[2:0] Configurable Logic Cell 2 _CLC2Interrupt 105 97 0000D6h IFS6[1] IEC6[1] IPC24[6:4] Configurable Logic Cell 3 _CLC3Interrupt 106 98 0000D8h IFS6[2] IEC6[2] IPC24[10:8] Configurable Logic Cell 4 _CLC4Interrupt 107 99 0000DAh IFS6[3] IEC6[3] IPC24[14:12] LCD – Liquid Crystal Display _LCDInterrupt 108 100 0000DCh IFS6[4] IEC6[4] IPC25[2:0] LCD Automation Timer _LCDATInterrupt 109 101 0000DEh IFS6[5] IEC6[5] IPC25[6:4] Reserved Reserved 110-113 102-105 0000E0h-0000E6h — — — FRC Self-Tuning Interrupt _FSTInterrupt 114 106 0000E8h IFS6[10] IEC6[10] IPC26[10:8] Reserved Reserved 115 107 0000EAh — — — ECC Single-Bit Error _ECCSBEInterrupt 116 108 0000ECh IFS6[12] IEC6[12] IPC27[2:0] Reserved Reserved 117 109 0000EEh — — — Real-Time Clock Timestamp _RTCCTSInterrupt 118 110 0000F0h IFS6[14] IEC6[14] IPC27[10:8] Reserved Reserved 119-124 111-116 0000F2h-0000FCh — — — JTAG _JTAGInterrupt 125 117 0000FEh IFS7[5] IEC7[5] IPC29[6:4] TABLE 8-2: INTERRUPT VECTOR DETAILS (CONTINUED) Interrupt Description MPLAB® XC16 ISR Name Vector IRQ # IVT Address Interrupt Bit Location Flag Enable Priority

 2019-2020 Microchip Technology Inc. DS30010198B-page 85 PIC24FJ128GL306 FAMILY TABLE 8-3: INTERRUPT FLAG REGISTERS Register Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IFS0 0088h NVMIF DMA1IF AD1IF U1TXIF U1RXIF SPI1TXIF SPI1IF T3IF T2IF — — DMA0IF T1IF CCT2IF CCT1IF INT0IF IFS1 008Ah U2TXIF U2RXIF INT2IF T5IF T4IF — —D M A 2 I F — CCP5IF — INT1IF IOCIF CMIF MI2C1IF SI2C1IF IFS2 008Ch CCT5IF DMA4IF — CCT4IF CCT3IF — — — — — —D M A 3 I F — — SPI2TXIF SPI2IF IFS3 008Eh CCP1IF RTCIF DMA5IF — SPI2RXIF SPI1RXIF — — — INT4IF INT3IF — — MI2C2IF SI2C2IF — IFS4 0090h — — — — — — —H L V D I F — — — — CRCIF U2ERIF U1ERIF CCP2IF IFS5 0092h CCP4IF CCP3IF — — — — U4TXIF U4RXIF U4ERIF — I2C2BCIF I2C1BCIF U3TXIF U3RXIF U3ERIF — IFS6 0094h — RTCCTSIF — ECCSBEIF —F S T I F — — — — LCDATIF LCDIF CLC4IF CLC3IF CLC2IF CLC1IF TABLE 8-4: INTERRUPT ENABLE REGISTERS Register Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IEC0 0098h NVMIE DMA1IE AD1IE U1TXIE U1RXIE SPI1TXIE SPI1IE T3IE T2IE — — DMA0IE T1IE CCT2IE CCT1IE INT0IE IEC1 009Ah U2TXIE U2RXIE INT2IE T5IE T4IE — —D M A 2 I E — CCP5IE — INT1IE IOCIE CMIE MI2C1IE SI2C1IE IEC2 009Ch CCT5IE DMA4IE — CCT4IE CCT3IE — — — — — —D M A 3 I E — — SPI2TXIE SPI2IE IEC3 009Eh CCP1IE RTCIE DMA5IE — SPI2RXIE SPI1RXIE — — — INT4IE INT3IE — — MI2C2IE SI2C2IE — IEC4 00A0h — — — — — — —H L V D I E — — — — CRCIE U2ERIE U1ERIE CCP2IE IEC5 00A2h CCP4IE CCP3IE — — — — U4TXIE U4RXIE U4ERIE — I2C2BCIE I2C1BCIE U3TXIE U3RXIE U3ERIE — IEC6 00A4h — RTCCTSIE — ECCSBEIE —F S T I E — — — — LCDATIE LCDIE CLC4IE CLC3IE CLC2IE CLC1IE

DS30010198B-page 86  2019-2020 Microchip Technology Inc. TABLE 8-5: INTERRUPT PRIORITY REGISTERS Register Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IPC0 00A8h — T1IP[2:0] — CCT2IP[2:0] — CCT1IP[2:0] — INT0IP[2:0] IPC1 00AAh — T2IP[2:0] — — — — — — — — — DMA0IP[2:0] IPC2 00ACh — U1RXIP[2:0] — SPI1TXIP[2:0] — SPI1IP[2:0] — T3IP[2:0] IPC3 00AEh — NVMIP[2:0] — DMA1IP[2:0] — AD1IP[2:0] — U1TXIP[2:0] IPC4 00B0h — IOCIP[2:0] —C M I P [ 2 : 0 ] — MI2C1IP[2:0] — SI2C1IP[2:0] IPC5 00B2h — — — — — CCP5IP[2:0] — — — — — INT1IP[2:0] IPC6 00B4h — T4IP[2:0] — — — — — — — — — DMA2IP[2:0] IPC7 00B6h — U2TXIP[2:0] — U2RXIP[2:0] — INT2IP[2:0] — T5IP[2:0] IPC8 00B8h — — — — — — — — — SPI2TXIP[2:0] — SPI2IP[2:0] IPC11 00BEh — CCT5IP[2:0] — DMA4IP[2:0] — — — — — CCT4IP[2:0] IPC12 00C0h — — — — — MI2C2IP[2:0] — SI2C2IP[2:0] — — — — IPC13 00C2h — — — — — INT4IP[2:0] — INT3IP[2:0] — — — — IPC14 00C4h — SPI2RXIP[2:0] — SPI1RXIP[2:0] — — — — — — — — IPC15 00C6h — CCP1IP[2:0] — RTCIP[2:0] — DMA5IP[2:0] — — — — IPC16 00C8h — CRCIP[2:0] — U2ERIP[2:0] — U1ERIP[2:0] — CCP2IP[2:0] IPC20 00D0h — U3TXIP[2:0] — U3RXIP[2:0] — U3ERIP[2:0] — — — — IPC21 00D2h — U4TXIP[2:0] — — — — — I2C2BCIP[2:0] — I2C1BCIP[2:0] IPC22 00D4h — — — — — — — — — U4TXIP[2:0] — U4RXIP[2:0] IPC23 00D6h — CCP4IP[2:0] — CCP3IP[2:0] — — — — — — — — IPC24 00D8h — CLC4IP[2:0] — CLC3IP[2:0] — CLC2IP[2:0] — CLC1IP[2:0] IPC25 00DAh — — — — — — — — — LCDATIP[2:0] — LCDIP[2:0] IPC27 00DEh — — — — — RTCCTSIP[2:0] — — — — — ECCSBEIP[2:0]

 2019-2020 Microchip Technology Inc. DS30010198B-page 87 PIC24FJ128GL306 FAMILY

8.3 Interrupt Resources

Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet.

8.3.1 KEY RESOURCES

• “Interrupts” (www.microchip.com/DS70000600) in the “dsPIC33/PIC24 Family Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• W e b i n a r s
• All Related “dsPIC33/PIC24 Family Reference Manual” Sections
• Development Tools

8.4 Interrupt Control and Status

PIC24FJ128GL306 family devices implement the following registers for the interrupt controller:

• INTCON1
• INTCON2
• INTCON4
• IFS0 through IFS7
• IEC0 through IEC7
• IPC0 through ICP29
• INTTREG

8.4.1 INTCON1-INTCON4

Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the processor trap sources. The INTCON2 register controls global interrupt gener- ation, the external interrupt request signal behavior and the use of the Alternate Interrupt Vector Table (AIVT). The INTCON3 register contains the Deadman Timer (DMT) trap bit. The INTCON4 register contains the Software Generated Hard Trap (SGHT) bit and the ECC Double-Bit Error (ECCDBE) trap bit.

8.4.2 IFSx

The IFSx registers maintain all of the interrupt request flags. Each source of interrupt has a status bit, which is set by the respective peripherals or external signal, and is cleared via software.

8.4.3 IECx

The IECx registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals.

8.4.4 IPCx

The IPCx registers are used to set the Interrupt Priority Level (IPL) for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels.

8.4.5 INTTREG

The INTTREG register contains the associated interrupt vector number and the new CPU Interrupt Pri- ority Level, which are latched into the Vector Number bits (VECNUM[7:0]) and Interrupt Priority Level bits (ILR[3:0]) fields in the INTTREG register. The new Interrupt Priority Level is the priority of the pending interrupt. The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence as they are listed in Table 8-2. For example, the INT0 (External Interrupt 0) is shown as having Vector Number 8 and a natural order priority of 0. Thus, the INT0IF bit is found in IFS0[0], the INT0IE bit in IEC0[0] and the INT0IPx bits in the first position of IPC0 (IPC0[2:0]).

8.4.6 STATUS/CONTROL REGISTERS

Although these registers are not specifically part of the interrupt control hardware, two of the CPU Control registers contain bits that control interrupt functionality. For more information on these registers, refer to “CPU with Extended Data Space (EDS)” (www.microchip.com/DS39732) in the “dsPIC33/PIC24 Family Reference Manual”.

• The CPU STATUS Register, SR, contains the IPL[2:0] bits (SR[7:5]). These bits indicate the current CPU Interrupt Priority Level. The user software can change the current CPU Interrupt Priority Level by writing to the IPLx bits.
• The CORCON register contains the IPL3 bit, which together with the IPL[2:0] bits, also indi- cates the current CPU Interrupt Priority Level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. All Interrupt registers are described in Register 8-3 through Register 8-7 in the following pages.

DS30010198B-page 88  2019-2020 Microchip Technology Inc. REGISTER 8-1: SR: ALU STATUS REGISTER (1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL2(2) IPL1(2) IPL0(2) RA N OV Z C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’= Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 IPL[2:0]: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) Note 1: For complete register details, see Register 3-1. 2: The IPL[2:0] Status bits are concatenated with the IPL3 Status bit (CORCON[3]) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. User interrupts are disabled when IPL3 = 1. 3: The IPL[2:0] Status bits are read-only when the NSTDIS bit (INTCON1[15]) = 1.

 2019-2020 Microchip Technology Inc. DS30010198B-page 89 PIC24FJ128GL306 FAMILY REGISTER 8-2: CORCON: CP U CORE CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0 R/W-1 U-0 U-0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’= Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less bit 2 PSV: Not used as part of the interrupt module bit 1-0 Unimplemented: Read as ‘0’ Note 1: For complete register details, see Register 3-2. 2: The IPL[2:0] Status bits are concatenated with the IPL3 Status bit (CORCON[3]) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. User interrupts are disabled when IPL3 = 1.

DS30010198B-page 90  2019-2020 Microchip Technology Inc. REGISTER 8-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14-5 Unimplemented: Read as ‘0’ bit 4 MATHERR: Math Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’

 2019-2020 Microchip Technology Inc. DS30010198B-page 91 PIC24FJ128GL306 FAMILY REGISTER 8-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 GIE DISI SWTRAP — — — —A I V T E N bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 GIE: Global Interrupt Enable bit 1 = Interrupts and associated interrupt enable bits are enabled 0 = Interrupts are disabled, but traps are still enabled bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13 SWTRAP: Software Trap Status bit 1 = Software trap is enabled 0 = Software trap is disabled bit 12-9 Unimplemented: Read as ‘0’ bit 8 AIVTEN: Alternate Interrupt Vector Table Enable bit 1 = Uses Alternate Interrupt Vector Table (if enabled in Configuration bits) 0 = Uses standard Interrupt Vector Table (default) bit 7-5 Unimplemented: Read as ‘0’ bit 4 INT4EP: External Interrupt 4 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 3 INT3EP: External Interrupt 3 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge

DS30010198B-page 92  2019-2020 Microchip Technology Inc. REGISTER 8-5: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DMT: Deadman Timer (soft) Trap Status bit 1 = Deadman Timer trap has occurred 0 = Trap has not occurred bit 14-0 Unimplemented: Read as ‘0’ REGISTER 8-6: INTCON4: INTERRUPT CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/C-0 R/C-0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-2 Unimplemented: Read as ‘0’ bit 1 ECCDBE: ECC Double-Bit Error Trap bit 1 = ECC double-bit error trap has occurred 0 = ECC double-bit error trap has not occurred bit 0 SGHT: Software Generated Hard Trap Status bit 1 = Software generated hard trap has occurred 0 = Software generated hard trap has not occurred

 2019-2020 Microchip Technology Inc. DS30010198B-page 93 PIC24FJ128GL306 FAMILY REGISTER 8-7: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER R-0 U-0 R/W-0 U-0 R-0 R-0 R-0 R-0 CPUIRQ —V H O L D — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VECNUM[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CPUIRQ: Interrupt Request from Interrupt Controller to CPU bit 1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU; this happens when the CPU priority is higher than the interrupt priority 0 = No interrupt request is unacknowledged bit 14 Unimplemented: Read as ‘0’ bit 13 VHOLD: Vector Number Capture Configuration bit 1 = The VECNUMx bits contain the value of the highest priority pending interrupt 0 = The VECNUMx bits contain the value of the last Acknowledged interrupt (i.e., the last interrupt that has occurred with higher priority than the CPU, even if other interrupts are pending) bit 12 Unimplemented: Read as ‘0’ bit 11-8 ILR[3:0]: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7-0 VECNUM[7:0]: Vector Number of Pending Interrupt bits 11111111 = 255, Reserved; do not use 00001001 = 9, CCT1, MCCP1 timer 00001000 = 8, INT0 – External Interrupt 0 00000111 = 7, Reserved; do not use 00000110 = 6, Generic soft error trap 00000101 = 5, Reserved; do not use 00000100 = 4, Math error trap 00000011 = 3, Stack error trap 00000010 = 2, Generic hard trap 00000001 = 1, Address error trap 00000000 = 0, Oscillator fail trap

DS30010198B-page 94  2019-2020 Microchip Technology Inc. NOTES:

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9.0 OSCILLATOR CONFIGURATION

The oscillator system for the PIC24FJ128GL306 family devices have the following features:

• An On-Chip PLL Block to Provide a Range of Frequency Options for the System Clock
• Software-Controllable Switching between Various Clock Sources
• Software-Controllable Postscaler for Selective Clocking of CPU for System Power Savings
• A Fail-Safe Clock Monitor (FSCM) that Detects Clock Failure and Permits Safe Application Recovery or Shutdown
• A Separate and Independently Configurable System Clock Output for Synchronizing External Hardware A simplified diagram of the oscillator system is shown in Figure 9-1. FIGURE 9-1: PIC24FJ128GL306 FAMILY CLOCK DIAGRAM Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive reference source. For more information, refer to “Oscillator” (www.microchip.com/ DS39700) in the “dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. PIC24FJ128GL306 Family Secondary Oscillator SOSCEN Enable Oscillator SOSCO SOSCI WDT, Other Modules OSCI OSCO Primary Oscillator XT, HS, EC FCY RCDIV[2:0] Timer, CCP , RTCC, CLC, WDT, PWRT OSCFDIV SOSC Clock Control Logic FSCM DOZE[14:12] XTPLL, HSPLL ECPLL,FRCPLLPLL and DIV PLLMODE[3:0] CPDIV[1:0] PLL LPRC FRC DIV[14:0] LPRC Oscillator FRC Divider ÷ n Postscaler WDT, RTCC, CLC FRC Self-Tune Control 32 kHz 8 kHz 31.25 kHz to CPU FOSC to MCCPs FP to Peripherals Peripheral Clock FCY

DS30010198B-page 96  2019-2020 Microchip Technology Inc.

9.1 CPU Clocking Scheme

The system clock source can be provided by one of four sources:

• Primary Oscillator (POSC) on the OSCI and OSCO pins
• Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins
• Fast Internal RC (FRC) Oscillator
• Low-Power Internal RC (LPRC) Oscillator The Primary Oscillator and FRC sources have the option of using the internal PLL block, which can generate a 4x, 6x or 8x PLL clock. If the PLL is used, the PLL clocks can then be postscaled, if necessary, and used as the system clock. Refer to Section 9.7 “Oscillator Modes” for additional information. The internal FRC provides an 8 MHz clock source. Each clock source (XTPLL, ECPLL, FRCPLL, HS, XT, EC, FRC, LPRC and SOSC) can be used as an input to an additional divider, which can then be used to produce a divided clock source for use as a system clock (OSCFDIV). The selected clock source generates the processor and peripheral clock sources. The processor clock source is divided by two to produce the internal instruc- tion cycle clock, F CY. In this document, the instruction cycle clock is also denoted by F OSC/2. The internal instruction cycle clock, FOSC/2, can be provided on the OSCO I/O pin for some operating modes of the Primary Oscillator.

9.2 Initial Configuration on POR

The oscillator source (and operating mode) that is used at a device Power-on Reset event is selected using Configuration bit settings. The Oscillator Configuration bit settings are located in the Configuration registers in the program memory (refer to Section 27.1 “Configu- ration Bits” for further details). The Primary Oscillator Configuration bits, POSCMD[1:0] (FOSC[1:0]), and the Oscillator Select Configuration bits, FNOSC[2:0] (FOSCSEL[2:0]), select the oscillator source that is used at a Power-on Reset. The OSCFDIV clock source is the default (unprogrammed) selection; the default input source to the OSCFDIV divider is the FRC clock source. Other oscillators may be chosen by programming these bit locations. The Configuration bits allow users to choose between the various Clock modes shown in Table 9-1.

9.2.1 CLOCK SWITCHING MODE

The FCKSM[1:0] Configuration bits (FOSC[7:6]) are used to jointly configure device clock switching and the Fail-Safe Clock Monitor (FSCM). Clock switching is enabled only when FCKSM1 is programmed (‘0’). The FSCM is enabled only when FCKSM[1:0] are both programmed (‘00’). TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Oscillator Source POSCMD[1:0] FNOSC[2:0] Notes Oscillator with Frequency Division (OSCFDIV) Internal/External 11 111 1, 2, 3 Low-Power RC Oscillator (LPRC) Internal 11 101 3 Secondary (Timer1) Oscillator (SOSC) Secondary 11 100 3 Primary Oscillator (XT) with PLL Module (XTPLL) Primary 01 011 Primary Oscillator (EC) with PLL Module (ECPLL) Primary 00 011 Primary Oscillator (HS) Primary 10 010 Primary Oscillator (XT) Primary 01 010 Primary Oscillator (EC) Primary 00 010 Fast RC Oscillator with PLL Module (FRCPLL) Internal 11 001 3 Fast RC Oscillator (FRC) Internal 11 000 3 Note 1: The input oscillator to the OSCFDIV Clock mode is determined by the RCDIV[2:0] (CLKDIV[10:8) bits. At POR, the default value selects the FRC module. 2: This is the default Oscillator mode for an unprogrammed (erased) device. 3: OSCO pin function is determined by the OSCIOFNC Configuration bit.

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9.3 Control Registers

The operation of the oscillator is controlled by five Special Function Registers:

• OSCCON
• C L K D I V
• O S C T U N
• OSCDIV
• O S C F D I V The OSCCON register (Register 9-1) is the main control register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. OSCCON is protected by a write lock to prevent inadvertent clock switches. See Section 9.4 “Clock Switching Operation” for more information. The CLKDIV register ( Register 9-2) controls the features associated with Doze mode, as well as the postscalers for the OSCFDIV Clock mode and the PLL module. The OSCTUN register (Register 9-3) allows the user to fine-tune the FRC Oscillator over a range of approximately ±1.5%. The OSCDIV and OSCFDIV registers provide control for the system oscillator frequency divider.

DS30010198B-page 98  2019-2020 Microchip Technology Inc. REGISTER 9-1: OSCCON: OS CILLATOR CONTROL REGISTER(1) U-0 R-x (2) R-x(2) R-x(2) U-0 R/W-x (2) R/W-x(2) R/W-x(2) — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 bit 15 bit 8 R/W-0 R/W-0 R-0 (4) U-0 R/CO-0 R/W-0 R/W-0 R/W-0 CLKLOCK(5) IOLOCK(3) LOCK — CF POSCEN SOSCEN OSWEN bit 7 bit 0 Legend: CO = Clearable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC[2:0]: Current Oscillator Selection bits(2) 111 = Oscillator with Frequency Divider (OSCFDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC[2:0]: New Oscillator Selection bits(2) 111 = Oscillator with Frequency Divider (OSCFDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) bit 7 CLKLOCK: Clock Selection Lock Enable bit(5) If FSCM is Enabled (FCKSM[1:0] = 00): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is Disabled (FCKSM[1:0] = 1x): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit. bit 6 IOLOCK: I/O Lock Enable bit(3) 1 = I/O lock is active 0 = I/O lock is not active Note 1: OSCCON is protected by a write lock to prevent inadvertent clock switches. See Section 9.4 “Clock Switching Operation” for more information. 2: Reset values for these bits are determined by the FNOSCx Configuration bits. 3: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. 4: This bit also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. 5: When CLKLOCK is set, the NOSC[2:0], OSWEN, CPDIV[1:0] and PLLEN bits cannot be modified.

 2019-2020 Microchip Technology Inc. DS30010198B-page 99 PIC24FJ128GL306 FAMILY bit 5 LOCK: PLL Lock Status bit(4) 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected bit 2 POSCEN: Primary Oscillator Sleep Enable bit 1 = Primary Oscillator continues to operate during Sleep mode 0 = Primary Oscillator is disabled during Sleep mode bit 1 SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit 1 = Enables Secondary Oscillator 0 = Disables Secondary Oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Initiates an oscillator switch to a clock source specified by the NOSC[2:0] bits 0 = Oscillator switch is complete REGISTER 9-1: OSCCON: OS CILLATOR CONTROL REGISTER(1) (CONTINUED) Note 1: OSCCON is protected by a write lock to prevent inadvertent clock switches. See Section 9.4 “Clock Switching Operation” for more information. 2: Reset values for these bits are determined by the FNOSCx Configuration bits. 3: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. 4: This bit also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. 5: When CLKLOCK is set, the NOSC[2:0], OSWEN, CPDIV[1:0] and PLLEN bits cannot be modified.

DS30010198B-page 100  2019-2020 Microchip Technology Inc. REGISTER 9-2: CLKDIV: CLOCK DIVIDER REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 ROI DOZE2 DOZE1 DOZE0 DOZEN (1) RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 CPDIV1 CPDIV0 PLLEN — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE[2:0]: CPU Peripheral Clock Ratio Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 (default) 010 = 1:4 001 = 1:2 000 = 1:1 bit 11 DOZEN: Doze Enable bit(1) 1 = DOZE[2:0] bits specify the CPU peripheral clock ratio 0 = CPU peripheral clock ratio is set to 1:1 bit 10-8 RCDIV[2:0]: System Frequency Divider Clock Source Select bits 111 = Reserved; do not use 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator (XT, HS, EC) with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator (FRC) with PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) bit 7-6 CPDIV[1:0]: System Clock Select bits (postscaler select from PLL, 32 MHz clock branch) 11 = 4 MHz (divide-by-8) 10 = 8 MHz (divide-by-4) 01 = 16 MHz (divide-by-2) 00 = 32 MHz (divide-by-1) bit 5 PLLEN: PLL Enable bit 1 = PLL is always active 0 = PLL is only active when a PLL Oscillator mode is selected (OSCCON[14:12] = 011 or 001) bit 4-0 Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.

 2019-2020 Microchip Technology Inc. DS30010198B-page 101 PIC24FJ128GL306 FAMILY REGISTER 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STEN —S T S I D L S T S R C (1) STLOCK STLPOL STOR STORPOL bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN[5:0] (2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 STEN: FRC Self-Tune Enable bit 1 = FRC self-tuning is enabled; TUNx bits are controlled by hardware 0 = FRC self-tuning is disabled; application may optionally control the TUNx bits bit 14 Unimplemented: Read as ‘0’ bit 13 STSIDL: FRC Self-Tune Stop in Idle bit 1 = Self-tuning stops during Idle mode 0 = Self-tuning continues during Idle mode bit 12 STSRC: FRC Self-Tune Reference Clock Source bit(1) 1 = Reserved 0 = FRC is an approximate match to the 32.768 kHz SOSC tolerance bit 11 STLOCK: FRC Self-Tune Lock Status bit 1 = FRC accuracy is currently within ±0.2% of the STSRC reference accuracy 0 = FRC accuracy may not be within ±0.2% of the STSRC reference accuracy bit 10 STLPOL: FRC Self-Tune Lock Interrupt Polarity bit 1 = A self-tune lock interrupt is generated when STLOCK is ‘0’ 0 = A self-tune lock interrupt is generated when STLOCK is ‘1’ bit 9 STOR: FRC Self-Tune Out of Range Status bit 1 = STSRC reference clock error is beyond the range of TUN[5:0]; no tuning is performed 0 = STSRC reference clock is within the tunable range; tuning is performed bit 8 STORPOL: FRC Self-Tune Out of Range Interrupt Polarity bit 1 = A self-tune out of range interrupt is generated when STOR is ‘0’ 0 = A self-tune out of range interrupt is generated when STOR is ‘1’ bit 7-6 Unimplemented: Read as ‘0’ Note 1: Use of either clock tuning reference source has specific application requirements. See Section 9.6 “FRC Active Clock Tuning” for details. 2: These bits are read-only when STEN = 1.

DS30010198B-page 102  2019-2020 Microchip Technology Inc. bit 5-0 TUN[5:0]: FRC Oscillator Tuning bits(2) 011111 = Maximum frequency deviation 011110 = 000001 = 000000 = Center frequency oscillator is running at factory calibrated frequency 111111 = 100001 = 100000 = Minimum frequency deviation REGISTER 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER (CONTINUED) Note 1: Use of either clock tuning reference source has specific application requirements. See Section 9.6 “FRC Active Clock Tuning” for details. 2: These bits are read-only when STEN = 1.

 2019-2020 Microchip Technology Inc. DS30010198B-page 103 PIC24FJ128GL306 FAMILY REGISTER 9-4: OSCDIV: OSCILLATOR DIVISOR REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DIV[14:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 DIV[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-0 DIV[14:0]: Reference Clock Divider bits Specifies the 1/2 period of the reference clock in the source clocks (ex: Period of ref_clk_output = [Reference Source * 2] * DIV[14:0]). 111111111111111 = Oscillator frequency divided by 65,534 (32,767 * 2) 111111111111110 = Oscillator frequency divided by 65,532 (32,766 * 2) 000000000000011 = Oscillator frequency divided by 6 (3 * 2) 000000000000010 = Oscillator frequency divided by 4 (2 * 2) 000000000000001 = Oscillator frequency divided by 2 (1 * 2) (default) 000000000000000 = Oscillator frequency is unchanged (no divider)

DS30010198B-page 104  2019-2020 Microchip Technology Inc. REGISTER 9-5: OSCFDIV: OSCILLATOR FRACTIONAL DIVISOR REGISTER (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRIM[0:7] bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 TRIM[0:8] Trim bits Provides fractional additive to the DIV[14:0] bits value for the 1/2 period of the oscillator clock. 0000_0000_0 = 0/512 (0.0) divisor added to DIVx value 0000_0000_1 = 1/512 (0.001953125) divisor added to DIVx value 0000_0001_0 = 2/512 (0.00390625) divisor added to DIVx value 100000000 = 256/512 (0.5000) divisor added to DIVx value 1111_1111_0 = 510/512 (0.99609375) divisor added to DIVx value 1111_1111_1 = 511/512 (0.998046875) divisor added to DIVx value bit 6-0 Unimplemented: Read as ‘0’ Note 1: TRIMx values greater than zero are ONLY valid when DIVx values are greater than zero.

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9.4 Clock Switching Operation

With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into the switching process.

9.4.1 ENABLING CLOCK SWITCHING

To enable clock switching, the FCKSM1 Configuration bit in FOSC must be programmed to ‘ 0’. (Refer to Section 27.1 “Configuration Bits” for further details.) If the FCKSM1 Configuration bit is unprogrammed (‘1’), the clock switching function and Fail-Safe Clock Monitor function are disabled; this is the default setting. The NOSCx control bits (OSCCON[10:8]) do not control the clock selection when clock switching is disabled. However, the COSC[2:0] bits (OSCCON[14:12]) will reflect the clock source selected by the FNOSCx Configuration bits. The OSWEN control bit (OSCCON[0]) has no effect when clock switching is disabled; it is held at ‘ 0’ at all times.

9.4.2 OSCILLATOR SWITCHING

At a minimum, performing a clock switch requires this basic sequence: 1. If desired, read the COSCx bits (OSCCON[14:12]) to determine the current oscillator source. 2. Perform the unlock sequence to allow a write to the OSCCON register high byte. 3. Write the appropriate value to the NOSCx bits (OSCCON[10:8]) for the new oscillator source. 4. Perform the unlock sequence to allow a write to the OSCCON register low byte. 5. Set the OSWEN bit to initiate the oscillator switch. Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSCx bits with the new value of the NOSCx bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. 2. If a valid clock switch has been initiated, the LOCK (OSCCON[5]) and CF (OSCCON[3]) bits are cleared. 3. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware will wait until the OST expires. If the new source is using the PLL, then the hardware waits until a PLL lock is detected (LOCK = 1). 4. The hardware waits for ten clock cycles from the new clock source and then performs the clock switch. 5. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSCx bits value is transferred to the COSCx bits. 6. The old clock source is turned off at this time, with the exception of LPRC (if WDT or FSCM is enabled) or SOSC (if SOSCEN remains set). Note: The Primary Oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMDx Configuration bits. While an application can switch to and from Primary Oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device. Note 1: The processor will continue to execute code throughout the clock switching sequence. Timing-sensitive code should not be executed during this time. 2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direc- tion. In these instances, the application must switch to FRC mode as a transitional clock source between the two PLL modes.

DS30010198B-page 106  2019-2020 Microchip Technology Inc. A recommended code sequence for a clock switch includes the following: 1. Disable interrupts during the OSCCON register unlock and write sequence. 2. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to OSCCON[15:8] in two back-to-back instructions. 3. Write the new oscillator source to the NOSCx bits in the instruction immediately following the unlock sequence. 4. Execute the unlock sequence for the OSCCON low byte by writing 46h and 57h to OSCCON[7:0] in two back-to-back instructions. 5. Set the OSWEN bit in the instruction immediately following the unlock sequence. 6. Continue to execute code that is not clock-sensitive (optional). 7. Invoke an appropriate amount of software delay (cycle counting) to allow the selected oscillator and/or PLL to start and stabilize. 8. Check to see if OSWEN is ‘ 0’. If it is, the switch was successful. If OSWEN is still set, then check the LOCK bit to determine the cause of the failure. The core sequence for unlocking the OSCCON register and initiating a clock switch is shown in Example 9-1. EXAMPLE 9-1: BASIC CODE SEQUENCE FOR CLOCK SWITCHING

9.5 Fail-Safe Clock Monitoring

The Fail-Safe Clock Monitor (FSCM) detects clock failures. In case of a clock problem, the Fail-Safe Clock Monitor switches the clock to the on-chip Low-Power RC (LPRC) Oscillator and generates the oscillator trap. To enable clock switching, the FCKSM[1:0] Configuration bits in the FOSC register must be programmed to ‘00’.

9.6 FRC Active Clock Tuning

PIC24FJ128GL306 family devices include an auto- matic mechanism to calibrate the FRC during run time. This system uses active clock tuning from a source of known accuracy to maintain the FRC within a very narrow margin of its nominal 8 MHz frequency. The self-tune system is controlled by the bits in the upper half of the OSCTUN register. Setting the STEN bit (OSCTUN[15]) enables the self-tuning feature, allowing the hardware to calibrate to a source selected by the STSRC bit (OSCTUN[12]). When STSRC = 0, the system uses the crystal- controlled SOSC for its calibration source. Regardless of the source, the system uses the TUN[5:0] bits (OSCTUN[5:0]) to change the FRC Oscillator’s frequency. Frequency monitoring and adjustment are dynamic, occurring continuously during run time. While the system is active, the TUNx bits cannot be written to by software. The self-tune system can generate a hardware inter- rupt, FSTIF. The interrupt can result from a drift of the FRC, from the reference, by greater than 0.2% in either direction, or whenever the frequency deviation is beyond the ability of the TUN[5:0] bits to correct (i.e., greater than 1.5%). The STLOCK and STOR status bits (OSCTUN[11,9]) are used to indicate these conditions. The STLPOL and STORPOL bits (OSCTUN[10,8]) configure the FSTIF interrupt to occur in the presence or the absence of the conditions. It is the user’s respon- sibility to monitor both the STLOCK and STOR bits to determine the exact cause of the interrupt. ;Place the new oscillator selection in W0 ;OSCCONH (high byte) Unlock Sequence MOV #OSCCONH, w1 MOV #0x78, w2 MOV #0x9A, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Set new oscillator selection MOV.b WREG, OSCCONH ;OSCCONL (low byte) unlock sequence MOV #OSCCONL, w1 MOV #0x46, w2 MOV #0x57, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Start oscillator switch operation BSET OSCCON, #0 // or use XC16 built-in macro: // Initiate Clock Switch to Primary //Oscillator with PLL (NOSC=0b011) __builtin_write_OSCCONH(0x03); __builtin_write_OSCCONL(OSCCON | 0x01); Note: The STLPOL and STORPOL bits should be ignored when the self-tune system is disabled (STEN = 0).

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9.7 Oscillator Modes

The PLL block is shown in Figure 9-2. In this system, the input from the Primary Oscillator is divided down by a PLL prescaler to generate a 4 MHz output. This is used to drive an on-chip, 96 MHz PLL frequency multi- plier to drive the fixed, divide-by-3 frequency divider and configurable PLL prescaler/divider to generate a range of system clock frequencies. The CPDIV[1:0] bits select the system clock speed. Available clock options are listed in Table 9-2. The user must manually configure the PLL divider to generate the required 4 MHz output using the PLLMODE[3:0] Configuration bits. This limits the choices for Primary Oscillator frequency to a total of eight possibilities, as shown in Table 9-3. TABLE 9-2: SYSTEM CLOCK OPTIONS TABLE 9-3: VALID PRIMARY OSCILLATOR CONFIGURATIONS FIGURE 9-2: PLL BLOCK MCU Clock Division (CPDIV[1:0]) Microcontroller Clock Frequency None (00)3 2 M H z 2 (01)1 6 M H z 4 (10) 8M H z 8 (11) 4M H z Input Oscillator Frequency Clock Mode PLL Mode (PLLMODE[3:0])

48 MHz ECPLL 12 (0111)

32 MHz HSPLL, ECPLL 8 (0110)

24 MHz HSPLL, ECPLL 6 (0101)

20 MHz HSPLL, ECPLL 5 (0100)

16 MHz HSPLL, ECPLL 4 (0011)

12 MHz HSPLL, ECPLL 3 (0010)

8 MHz ECPLL, XTPLL,

2 (0001)

4 MHz ECPLL, XTPLL,

1 (0000) PLL

96 MHz

4 MHz

CPDIV[1:0] PLLMODE[3:0] Input from POSC Input from FRC

32 MHz

 12  8  8  6  5  4  3  2  1  4  2  1 00 Note 1: This MUX is controlled by the COSC[2:0] bits wh en running from the PLL or the NOSC[2:0] bits when preparing to switch to the PLL. 1100 1101 1110  3 (Note 1)

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9.8 Primary Oscillator (PRI or POSC)

The PIC24FJ128GL306 family devices feature a Primary Oscillator (POSC), which is available on the OSCI and OSCO pins. This connection enables an external crystal (or ceramic resonator) to provide the clock to the device. The Primary Oscillator provides three modes of operation:

• Medium Speed Oscillator (XT Mode): The XT mode is a Medium Gain, Medium Frequency mode used to work with crystal frequencies of 3.5 MHz to 10 MHz.
• High-Speed Oscillator (HS Mode): The HS mode is a High-Gain, High-Frequency mode used to work with crystal frequencies of 10 MHz to 32 MHz.
• External Clock Source Operation (EC Mode): If the crystal driver is disabled, the EC mode allows the internal oscillator to be bypassed. The device clocks are generated from an external source (0 MHz to up to 64 MHz) and input on the CLKI pin.

9.9 Low-Power RC (LPRC) Oscillator

The PIC24FJ128GL306 family devices contain one instance of the Low-Power RC (LPRC) Oscillator, which provides a nominal clock frequency of 32 kHz. The LPRC Oscillator is the clock source for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM) circuits in the clock subsystem. The LPRC Oscillator is enabled at power-on. The LPRC Oscillator remains enabled under these conditions:

• The FSCM is enabled
• The WDT is enabled
• The LPRC Oscillator is selected as the system clock If none of these conditions is true, the LPRC Oscillator shuts off after the PWRT expires.

9.10 Secondary Oscillator (SOSC)

9.10.1 BASIC SOSC OPERATION

PIC24FJ128GL306 family devices do not have to set the SOSCEN bit to use the Secondary Oscillator. Any module requiring the SOSC (such as the RTCC or Timer1) will automatically turn on the SOSC when the clock signal is needed. The SOSC, however, has a long start-up time (as long as one second). To avoid delays for peripheral start-up, the SOSC can be manually started using the SOSCEN bit. To use the Secondary Oscillator, the SOSCSEL bit (FOSC[3]) must be set to ‘ 1’. Programming the SOSCSEL bit to ‘0’ configures the SOSC pins for Digital mode, enabling digital I/O functionality on the pins.

9.10.2 CRYSTAL SELECTION

The 32.768 kHz crystal used for the SOSC must have the following specifications in order to properly start up and run at the correct frequency when the SOSC is in High-Power mode (default):

• 12.5 pF loading capacitance
• 1.0 pF shunt capacitance
• A typical ESR of 35k-50k; 70k maximum In addition, the two external crystal loading capacitors should be in the range of 18 pF-22 pF, which will be based on the PC board layout. The capacitors should be C0G, 5% tolerance and rated 25V or greater. The accuracy and duty cycle of the SOSC can be measured on the REFO pin, and is recommended to be in the range of 40-60% and accurate to ±0.65 Hz.

9.10.3 LOW-POWER SOSC OPERATION

The Secondary Oscillator can operate in two distinct lev- els of power consumption based on device configuration. In Low-Power mode, the oscillator operates in a low drive strength, low-power state. By default, the oscillator uses a higher drive strength, and therefore, requires more power. Low-Power mode is selected by Configuration bit, SOSCHP (FDEVOPT1[3]). The lower drive strength of this mode makes the SOSC more sensitive to noise and requires a longer start-up time. This mode can be used with lower load capacitance crystals (6-9 pF) to reduce Sleep current in the RTCC. When Low-Power mode is used, care must be taken in the design and layout of the SOSC circuit to ensure that the oscillator starts up and oscillates properly. PC board layout issues, stray capaci- tance and other factors will need to be carefully controlled in order for the crystal to operate. FIGURE 9-3: REFERENCE CLOCK GENERATOR ROSEL[3:0] 1000 0110 0101 0100 0011 0010 0001 0000 REFI Pin PLL (4/6/8x or 96 MHz) SOSC LPRC FRC POSC Peripheral Clock Oscillator Clock RODIV[14:0] REFO ROOUT To SPI, CCP, CLC Note 1: In Retention mode, the maximum peripheral output frequency to an I/O pin must be limited to 33 kHz or less. Divider

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9.11 Reference Clock Output

In addition to the CLKO output (F OSC/2) available in certain Oscillator modes, the device clock in the PIC24FJ128GL306 family devices can also be config- ured to provide a reference clock output signal to a port pin. This feature is available in all oscillator configura- tions and allows the user to select a greater range of clock submultiples to drive external devices in the application. CLKO is enabled by Configuration bit, OSCIOFNC, and is independent of the REFO refer- ence clock. REFO is mappable to any I/O pin that has mapped output capability. Refer to Table 11-10 for more information. This reference clock output is controlled by the REFOCONL and REFOCONH registers. Setting the ROEN bit (REFOCONL[15]) makes the clock signal available on the REFO pin. The RODIV[14:0] bits (REFOCONH[14:0]) enable the selection of different clock divide options. The ROSWEN bit (REFOCONL[9]) indicates that the clock divider has successfully switched. In order to change the divider, the user should wait until this bit has been cleared. Write the updated values to RODIVx, set the ROSWEN bit and then wait until it is cleared before assuming that the REFO clock is valid. The ROSEL[3:0] bits (REFOCONL[3:0]) determine which clock source is used for the reference clock out- put. The ROSLP bit (REFOCONL[11]) determines if the reference source is available on REFO when the device is in Sleep mode. To use the reference clock output in Sleep mode, both the ROSLP bit must be set and the clock selected by the ROSELx bits must be enabled for operation, during Sleep mode, if possible. Clearing the ROSELx bits allows the reference output frequency to change as the system clock changes during any clock switches. The ROOUT bit enables/disables the reference clock output on the REFO pin. The ROACTIVE bit (REFOCONL[8]) indicates that the module is active; it can be cleared by disabling the module (setting ROEN to ‘ 0’). The user must not change the reference clock source or adjust the divider when the ROACTIVE bit indicates that the module is active. To avoid glitches, the user should not disable the module until the ROACTIVE bit is ‘1’. The PLLSS Configuration bit (FOSC[4]), when cleared, can be used to generate a REFO clock with the PLL that is independent of the system clock. The PLL can- not be used in the primary clock chain. For example, if the system clock is using FRC at 8 MHz, the PLL can use the FRC as the input and generate 32 MHz (PLL4x mode) out of REFO.

DS30010198B-page 110  2019-2020 Microchip Technology Inc. REGISTER 9-6: REFOCONL: REFERENCE OSCILLATOR CONTROL REGISTER LOW R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-0 ROEN — ROSIDL ROOUT ROSLP — ROSWEN ROACTIVE bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — ROSEL[3:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Reference Oscillator module is enabled 0 = Reference Oscillator is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 ROSIDL: REFO Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 ROOUT: Reference Clock Output Enable bit 1 = Reference clock is driven out on the REFO pin 0 = Reference clock is not driven out on the REFO pin bit 11 ROSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference Oscillator continues to run in Sleep 0 = Reference Oscillator is disabled in Sleep bit 10 Unimplemented: Read as ‘0’ bit 9 ROSWEN: Reference Clock RODIVx Switch Enable bit 1 = Switch clock divider; clock divider switching is currently in progress 0 = Clock divider switch has been completed bit 8 ROACTIVE: Reference Clock Request Status bit 1 = Reference clock is active (user should not change the REFO settings) 0 = Reference clock is inactive (user can update the REFO settings) bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 ROSEL[3:0]: Reference Clock Source Select bits 1111-1001 = Reserved 1000 = REFI pin 0111 = Reserved 0110 = PLL 0101 = SOSC 0100 = LPRC 0011 = FRC 0010 = POSC 0001 = System clock (FOSC/2) 0000 = FOSC

 2019-2020 Microchip Technology Inc. DS30010198B-page 111 PIC24FJ128GL306 FAMILY REGISTER 9-7: REFOCONH: REFERENCE OSCILLATOR CONTROL REGISTER HIGH U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — RODIV[14:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RODIV[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-0 RODIV[14:0]: Reference Clock Divider bits Specifies 1/2 period of the reference clock in the source clocks (ex: Period of Output = [Reference Source * 2] * RODIV[14:0]; this equation does not apply to RODIV[14:0] = 0). 111111111111111 = REFO clock is the base clock frequency divided by 65,534 (32,767 * 2) 111111111111110 = REFO clock is the base clock frequency divided by 65,532 (32,766 * 2) 000000000000011 = REFO clock is the base clock frequency divided by 6 (3 * 2) 000000000000010 = REFO clock is the base clock frequency divided by 4 (2 * 2) 000000000000001 = REFO clock is the base clock frequency divided by 2 (1 * 2) 000000000000000 = REFO clock is the same frequency as the base clock (no divider)

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10.0 POWER-SAVING FEATURES

The PIC24FJ128GL306 family of eXtreme low-power devices provides the ability to manage power con- sumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. All PIC24F devices manage power consumption in four different ways:

• Clock Frequency
• Instruction-Based Sleep and Idle modes
• Software Controlled Doze mode
• Selective Peripheral Control in Software Combinations of these methods can be used to selectively tailor an application’s power consumption, while still maintaining critical application features, such as timing-sensitive communications.

10.1 Clock Frequency and Clock

PIC24F devices allow for a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSC[2:0] bits. The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section 9.0 “Oscillator Configuration”.

10.2 Instruction-Based Power-Saving

PIC24F devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution; Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. The assembly syntax of the PWRSAV instruction is shown in Example 10-1. The MPLAB ® XC16 C compiler offers “built-in” functions for the power-saving modes as follows: Idle(); // places part in Idle Sleep(); // places part in Sleep Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to “wake-up”.

10.2.1 SLEEP MODE

Sleep mode has these features:

• The system clock source is shut down. If an on-chip oscillator is used, it is turned off.
• The device current consumption will be reduced to a minimum provided that no I/O pin is sourcing current.
• The Fail-Safe Clock Monitor does not operate during Sleep mode since the system clock source is disabled.
• The LPRC clock will continue to run in Sleep mode if the WDT is enabled.
• The WDT, if enabled, is automatically cleared prior to entering Sleep mode.
• Some device features or peripherals may continue to operate in Sleep mode. Refer to Table 10-2 for peripherals active in Sleep. This includes items, such as the Input Change Notifi- cation (ICN) on the I/O ports or peripherals that use an External Clock input. Any peripheral that requires the system clock source for its operation will be disabled in Sleep mode. The device will wake-up from Sleep mode on any of the these events:
• On any interrupt source that is individually enabled.
• On any form of device Reset.
• On a WDT time-out. On wake-up from Sleep, the processor will restart with the same clock source that was active when Sleep mode was entered. EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive ref- erence source. For more information, refer to “Power-Saving Features with Deep Sleep” (www.microchip.com/DS39727) in the “dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. PWRSAV #0 ; Put the device into SLEEP mode PWRSAV #1 ; Put the device into IDLE mode

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10.2.2 IDLE MODE

Idle mode has these features:

• The CPU will stop executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 10.4 “Selective Peripheral Module Control”).
• If the WDT or FSCM is enabled, the LPRC will also remain active. The device will wake from Idle mode on any of these events:
• Any interrupt that is individually enabled.
• Any device Reset.
• A W D T t i m e - o u t . On wake-up from Idle, the clock is reapplied to the CPU and instruction execution begins immediately, starting with the instruction following the PWRSAV instruction or the first instruction in the ISR.

10.2.3 INTERRUPTS COINCIDENT WITH

Any interrupt that coincides with the execution of a PWRSAV instruction will be held off until entry into Sleep or Idle mode has completed. The device will then wake-up from Sleep or Idle mode.

10.2.4 LOW-VOLTAGE RETENTION

PIC24FJ128GL306 family devices incorporate a second on-chip voltage regulator, designed to provide power to select microcontroller features at 1.2V nominal. This regulator allows features, such as data RAM and the WDT, to be maintained in power-saving modes where they would otherwise be inactive, or maintain them at a lower power than would otherwise be the case. Retention Sleep uses less power than standard Sleep mode, but takes more time to recover and begin execu- tion. An additional 10-15 µs (typical) is required to charge V CAP from 1.2V to 1.8V and start to execute instructions when exiting Retention Sleep. The VREGS bit allows control of speed to exit from the Sleep modes (regular and Retention) at the cost of more power. The regulator band gaps are enabled, which increases the current but reduces time to recover from Sleep by ~10 µs. The low-voltage retention regulator is only available when Sleep mode is invoked. It is controlled by the LPCFG Configuration bit (FPOR[2]) and in firmware by the RETEN bit (RCON[12]). LPCFG must be programmed (= 0) and the RETEN bit must be set (= 1) for the regulator to be enabled.

10.2.5 EXITING FROM LOW-VOLTAGE

All of the methods for exiting from standard Sleep also apply to Retention Sleep (MCLR, INT0, etc.). However, in order to allow the regulator to switch from 1.8V (oper- ating) to Retention mode (1.2V), there is a hardware ‘lockout timer’ from the execution of Retention Sleep until Retention Sleep can be exited. During the ‘lockout time’, the only method to exit Reten- tion Sleep is a POR or MCLR . Interrupts that are asserted (such as INT0) during the ‘lockout time’ are masked. The lockout timer then sets a minimum interval from when the part enters Retention Sleep until it can exit from Retention Sleep. Interrupts are not ‘held pending’ during lockout; they are masked, and in order to exit after the lockout expires, the exiting source must assert after the lockout time. The lockout timer is derived from the LPRC clock, which has a wide (untrimmed) frequency tolerance. The lockout time will be one of the following two cases:

• If the LPRC was not running at the time of Retention Sleep, the lockout time is two LPRC periods + LPRC wake-up time
• If the LPRC was running at the time of Retention Sleep, the lockout time is one LPRC period Refer to Table 30-20 and Table 30-21 in the AC Electrical Specifications for the LPRC timing.

10.2.6 SUMMARY OF LOW-POWER SLEEP

The RETEN bit and the VREGS bit (RCON[12,8]) allow for four different Sleep modes, which will vary by wake- up time and power consumption. Refer to Table 10-1 for a summary of these modes. Specific information about the current consumption and wake times can be found in Section 30.0 “Electrical Characteristics” . Note 1: In Retention mode, the maximum periph- eral output frequency to an I/O pin must be limited to 33 kHz or less. TABLE 10-1: LOW-POWER SLEEP MODES RETEN VREGS MODE Relative Power 0 0 Standby Sleep A Few μA Range 0 1 Sleep 100 μA Range 1 0 Low-Voltage Standby Sleep Less than 1 μA 1 1 Low-Voltage Sleep A Few μA Range

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10.3 Doze Mode

Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. There may be circumstances, however, where this is not practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. Reducing system clock speed may introduce communication errors, while using a power-saving mode may stop communications completely. Doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. In this mode, the system clock contin- ues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. Doze mode is enabled by setting the DOZEN bit (CLKDIV[11]). The ratio between peripheral and core clock speed is determined by the DOZE[2:0] bits (CLKDIV[14:12]). There are eight possible configurations, from 1:1 to 1:256, with 1:1 being the default. It is also possible to use Doze mode to selectively reduce power consumption in event-driven applica- tions. This allows clock-sensitive functions, such as synchronous communications, to continue without interruption while the CPU Idles, waiting for something to invoke an interrupt routine. Enabling the automatic return to full-speed CPU operation on interrupts is enabled by setting the ROI bit (CLKDIV[15]). By default, interrupt events have no effect on Doze mode operation. TABLE 10-2: POWER-SAVING OPERATING MODES Operating Mode Active Clocks Active Peripherals Wake-up Sources Low-Voltage/ Retention Sleep Refer to the respective Peripheral for active clock source Timer, REFO, MCCP, LCD, BOR, WDT, HLVD, RTCC, CMP , CVREF, CLC, UART, SPI, I2C

• Interrupt source that is individually enabled
• Any form of device Reset
• WDT time-out Sleep Refer to the respective Peripheral for active clock source Timer, REFO, MCCP, LCD, BOR, WDT, HLVD, ADC, RTCC, CMP, CV REF, CLC, UART, SPI, I2C
• Interrupt source that is individually enabled
• Any form of device Reset
• WDT time-out Idle All clocks All peripherals • Interrupt source that is individually enabled
• Any form of device Reset
• WDT time-out Doze All clocks All peripherals • Interrupt source that is individually enabled (ROI bit (CLKDIV[15]) should be enabled)
• Any form of device Reset

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10.4 Selective Peripheral Module Control

Idle and Doze modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock. Even so, peripheral modules still remain clocked, and thus, consume power. There may be cases where the application needs what these modes do not provide: the allocation of power resources to CPU processing with minimal power consumption from the peripherals. PIC24F devices address this requirement by allowing peripheral modules to be selectively disabled, reducing or eliminating their power consumption. This can be done with two control bits:

• The Peripheral Enable bit, generically named, “XXXEN”, located in the module’s main control SFR.
• The Peripheral Module Disable (PMD) bit, generically named, “XXXMD”, located in one of the PMD Control registers. Both bits have similar functions in enabling or disabling their associated module. Setting the PMD bit for a module disables all clock sources to that module, reducing its power consumption to an absolute mini- mum. In this state, the control and status registers associated with the peripheral will also be disabled, so writes to those registers will have no effect and read values will be invalid. Many peripheral modules have a corresponding PMD bit. In contrast, disabling a module by clearing its XXXEN bit disables its functionality, but leaves its registers available to be read and written to. This reduces power consumption, but not by as much as setting the PMD bit does. Most peripheral modules have an enable bit; exceptions include input capture, output compare and RTCC. To achieve more selective power savings, peripheral modules can also be selectively disabled when the device enters Idle mode. This is done through the control bit of the generic name format, “XXXIDL”. By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature allows further reduction of power consumption during Idle mode, enhancing power savings for extremely critical power applications.

 2019-2020 Microchip Technology Inc. DS30010198B-page 117 PIC24FJ128GL306 FAMILY TABLE 10-3: PERIPHERAL MODULE DISABLE REGISTER SUMMARY Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets PMD1 T5MD T4MD T3MD T2MD T1MD — — — I2C1MD U2MD U1MD SPI2MD SPI1MD — — ADCMD 0000 PMD3 — — — — — CMPMD RTCCMD — CRCMD — — —U 3 M D —I 2 C 2 M D — 0000 PMD5 — — — — — — — — — — — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 0000 PMD8 — — — — — — —D M T M D — — CLC4MD CLC3MD CLC2MD CLC1MD — — 0000 Legend: — = unimplemented, read as ‘ 0’. Reset values are shown in hexadecimal.

DS30010198B-page 118  2019-2020 Microchip Technology Inc. REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 T5MD T4MD T3MD T2MD T1MD — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 I2C1MD U2MD U1MD SPI2MD SPI1MD — — ADC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 T5MD: Timer5 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 14 T4MD: Timer4 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 13 T3MD: Timer3 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 12 T2MD: Timer2 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 11 T1MD: Timer1 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 10-8 Unimplemented: Read as ‘0’ bit 7 I2C1MD: I2C1 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 6 U2MD: UART2 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 5 U1MD: UART1 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 4 SPI2MD: SPI2 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 3 SPI1MD: SPI1 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 2-1 Unimplemented: Read as ‘0’ bit 0 ADC1MD: A/D Converter Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled

 2019-2020 Microchip Technology Inc. DS30010198B-page 119 PIC24FJ128GL306 FAMILY REGISTER 10-2: PMD3: PERIPHERAL MODULE DISABLE REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 bit 15 bit 8 R/W-0 U-0 U-0 U-0 R/W-0 U-0 R/W-0 U-0 CRCMD — — —U 3 M D — I2C2MD — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 CMPMD: Triple Comparator Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 9 RTCCMD: RTCC Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 8 Unimplemented: Read as ‘0’ bit 7 CRCMD: CRC Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 6-4 Unimplemented: Read as ‘0’ bit 3 U3MD: UART3 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 2 Unimplemented: Read as ‘0’ bit 1 I2C2MD: I2C2 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 0 Unimplemented: Read as ‘0’

DS30010198B-page 120  2019-2020 Microchip Technology Inc. REGISTER 10-3: PMD4: PERIPHERAL MODULE DISABLE REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 — —U 4 M D —R E F O M D —H L V D M D — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 U4MD: UART4 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 4 Unimplemented: Read as ‘0’ bit 3 REFOMD: Reference Clock Output Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 2 Unimplemented: Read as ‘0’ bit 1 HLVDMD: High/Low-Voltage Detect Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 0 Unimplemented: Read as ‘0’

 2019-2020 Microchip Technology Inc. DS30010198B-page 121 PIC24FJ128GL306 FAMILY REGISTER 10-4: PMD5: PERIPHERAL MODULE DISABLE REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 CCP5MD: MCCP5 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 3 CCP4MD: MCCP4 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 2 CCP3MD: MCCP3 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 1 CCP2MD: MCCP2 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 0 CCP1MD: MCCP1 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled

DS30010198B-page 122  2019-2020 Microchip Technology Inc. REGISTER 10-5: PMD6: PERIPHERAL MODULE DISABLE REGISTER 6 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6 LCDMD: LCD Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 5-0 Unimplemented: Read as ‘0’ REGISTER 10-6: PMD7: PERIPHERAL MODULE DISABLE REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — —D M A 1 M D D M A 0 M D — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 DMA1MD: DMA1 Controller (Channels 4 through 7) Disable bit 1 = Controller is disabled 0 = Controller power and clock sources are enabled bit 4 DMA0MD: DMA0 Controller (Channels 0 through 3) Disable bit 1 = Controller is disabled 0 = Controller power and clock sources are enabled bit 3-0 Unimplemented: Read as ‘0’

 2019-2020 Microchip Technology Inc. DS30010198B-page 123 PIC24FJ128GL306 FAMILY REGISTER 10-7: PMD8: PERIPHERAL MODULE DISABLE REGISTER 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — CLC4MD CLC3MD CLC2MD CLC1MD — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 DMTMD: DMT Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 7-6 Unimplemented: Read as ‘0’ bit 5 CLC4MD: CLC4 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 4 CLC3MD: CLC3 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 3 CLC2MD: CLC2 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 2 CLC1MD: CLC1 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 1-0 Unimplemented: Read as ‘0’

DS30010198B-page 124  2019-2020 Microchip Technology Inc. NOTES:

 2019-2020 Microchip Technology Inc. DS30010198B-page 125 PIC24FJ128GL306 FAMILY

11.0 I/O PORTS

All of the device pins (except V DD, V SS, MCLR and OSCI/CLKI) are shared between the peripherals and the Parallel I/O (PIO) ports. All I/O input ports feature Schmitt Trigger (ST) inputs for improved noise immunity.

11.1 Parallel I/O (PIO) Ports

A Parallel I/O port that shares a pin with a peripheral is, in general, subservient to the peripheral. The periph- eral’s output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through”, in which a port’s digital output can drive the input of a peripheral that shares the same pin. Figure 11-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port. All port pins have three registers directly associated with their operation as digital I/Os and one register associated with their operation as analog inputs. The Data Direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a ‘1’, then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the Output Latch register (LATx), read the latch; writes to the latch, write the latch. Reads from the PORTx register, read the port pins; writes to the port pins, write the latch. Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers, and the port pin, will read as zeros. Table 11-3 through Table 11-9 show ANSELx bits and port availability for device variants. When a pin is shared with another peripheral or function that is defined as an input only, it is regarded as a dedicated port because there is no other competing source of inputs. FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive refer- ence source. For more information, refer to “I/O Ports with Peripheral Pin Select (PPS)” (www.microchip.com/DS30009711) in the “dsPIC33/PIC24 Family Refer- ence Manual”. The information in this data sheet supersedes the information in the FRM. QD CK WR LATx + TRIS Latch I/O Pin WR PORTx Data Bus QD CK Data Latch Read PORTx Read TRISx WR TRISx Peripheral Output Data Output Enable Peripheral Input Data I/O Peripheral Module Peripheral Output Enable PIO Module Output Multiplexers Output Data Input Data Peripheral Module Enable Read LATx

DS30010198B-page 126  2019-2020 Microchip Technology Inc.

11.1.1 I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP.

11.1.2 OPEN-DRAIN CONFIGURATION

In addition to the PORTx, LATx and TRISx registers for data control, each port pin can also be individually configured for either a digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits con- figures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than V DD (e.g., 5V) on any desired digital only pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification.

11.2 Configuring Analog Port Pins

(ANSELx) The ANSELx and TRISx registers control the operation of the pins with analog function. Each port pin with analog function is associated with one of the ANSELx bits, which decide if the pin function should be analog or digital. Refer to Table 11-1 for detailed behavior of the pin for different ANSELx and TRISx bit settings. When reading the PORTx register, all pins configured as analog input channels will read as cleared (a low level).

11.2.1 ANALOG INPUT PINS AND

The voltage tolerance of pins used as device inputs is dependent on the pin’s input function. Most input pins are able to handle DC voltages of up to 5.5V, a level typical for digital logic circuits. However, several pins can only tolerate voltages up to V DD. Voltage excursions beyond VDD on these pins should always be avoided. Table 11-2 summarizes the different voltage toler- ances. For more information, refer to Section 30.0 “Electrical Characteristics” for more details. TABLE 11-1: CONFIGURING ANALOG/DIGITAL FUNCTION OF AN I/O PIN Pin Function ANSELx Setting TRISx Setting Comments Analog Input 11 It is recommended to keep ANSELx = 1. Analog Output 11 It is recommended to keep ANSELx = 1. Digital Input 01 Firmware must wait at least one instruction cycle after configuring a pin as a digital input before a valid input value can be read. Digital Output 00 Make sure to disable the analog output function on the pin if any is present. TABLE 11-2: INPUT VOLTAGE LEVELS FOR PO RT OR PIN TOLERATED DESCRIPTION INPUT Port or Pin Tolerated Input Description PORTB[15:7,5:2] 5.5V Tolerates input levels above VDD; useful for most standard logic. PORTD[11:0] PORTE[4:0] PORTF[6:0] PORTG[9,6,3:2] PORTA[0] V DD Only VDD input levels are tolerated. PORTB[6,1:0] PORTC[15:12] PORTE[7:5] PORTG[8:7]

 2019-2020 Microchip Technology Inc. DS30010198B-page 127 PIC24FJ128GL306 FAMILY TABLE 11-3: PORTA PIN AND ANSELA AVAILABILITY Device PORTA I/O Pins RA15 RA14 RA13 RA12 RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 TABLE 11-4: PORTB PIN AND ANSELB AVAILABILITY Device PORTB I/O Pins RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 PIC24FJXXXGL306 x x x x x x x x x x x x x x x x PIC24FJXXXGL305 x x — — x x xxxxxx — —x x PIC24FJXXXGL303 x x — — — x xxxxxx — —x x PIC24FJXXXGL302 x x — — —x — —x x x x — —x x A N S E L B B i t P r e s e n t x x x x x x xxxxxxxxxx TABLE 11-5: PORTC PIN AND ANSELC AVAILABILITY Device PORTC I/O Pins RC15 RC14 RC13 RC12 RC11 RC10 RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 TABLE 11-6: PORTD PIN AND ANSELD AVAILABILITY Device PORTD I/O Pins RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 PIC24FJXXXGL306 — — — — x x xxxxxxxxxx PIC24FJXXXGL305 — — — —x x — — xxxxx — —x

DS30010198B-page 128  2019-2020 Microchip Technology Inc. TABLE 11-7: PORTE PIN AND ANSELE AVAILABILITY Device PORTE I/O Pins RE15 RE14 RE13 RE12 RE11 RE10 RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 PIC24FJXXXGL306 — — — — — — — — xxxxxxxx TABLE 11-8: PORTF PIN AND ANSELF AVAILABILITY Device PORTF I/O Pins RF15 RF14 RF13 RF12 RF11 RF10 RF9 RF8 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 TABLE 11-9: PORTG PIN AND ANSELG AVAILABILITY Device PORTG I/O Pins RG15 RG14 RG13 RG12 RG11 RG10 RG9 RG8 RG7 RG6 RG5 RG4 RG3 RG2 RG1 RG0

 2019-2020 Microchip Technology Inc. DS30010198B-page 129 PIC24FJ128GL306 FAMILY

11.3 Interrupt-on-Change (IOC)

The interrupt-on-change function of the I/O ports allows the PIC24FJ128GL306 family of devices to generate interrupt requests to the processor in response to a Change-of-State (COS) on selected input pins. This feature is capable of detecting input Change-of-States, even in Sleep mode, when the clocks are disabled. Interrupt-on-change functionality is enabled on a pin by setting the IOCPx and/or IOCNx register bit for that pin. For example, PORTC has register names, IOCPC and IOCNC, for these functions. Setting a value of ‘1’ in the IOCPx register enables interrupts for low-to-high tran- sitions, while setting a value of ‘1’ in the IOCNx register enables interrupts for high-to-low transitions. Setting a value of ‘1’ in both register bits will enable interrupts for either case (e.g., a pulse on the pin will generate two interrupts). In order for any IOC to be detected, the global IOC Interrupt Enable bit (IEC1[3]) must be set, the IOCON (PADCON[15]) bit set and the associated ISFx flag cleared. When an interrupt request is generated for a pin, the corresponding status flag (IOCFx register bit) will be set, indicating that a Change-of-State occurred on that pin. The IOCFx register bit will remain set until cleared by writing a zero to it. When any IOCFx flag bit in a given port is set, the corresponding IOCPxF bit in the IOCSTAT register will be set. This flag indicates that a change was detected on one of the bits on the given port. The IOCPxF flag will be cleared when all IOCFx[15:0] bits are cleared. Multiple individual status flags can be cleared by writing a zero to one or more bits using a Read-Modify-Write (RMW) operation. If another edge is detected on a pin whose status bit is being cleared during the Read- Modify-Write sequence, the associated change flag will still be set at the end of the Read-Modify-Write sequence. The user should use the instruction sequence (or equivalent) shown in Example 11-1 to clear the Interrupt-on-Change Status registers. At the end of this sequence, the W0 register will contain a zero for each bit for which the port pin had a change detected. In this way, any indication of a pin changing will not be lost. Due to the asynchronous and real-time nature of the interrupt-on-change, the value read on the port pins may not indicate the state of the port when the change was detected, as a second change can occur during the interval between clearing the flag and reading the port. It is up to the user code to handle this case if it is a possibility in their application. To keep this interval to a minimum, it is recommended that any code modifying the IOCFx registers be run either in the interrupt handler or with interrupts disabled. Each Interrupt-on-Change (IOC) pin has both a weak pull-up and a weak pull-down connected to it. The pull- ups act as a current source connected to the pin, while the pull-downs act as a current sink connected to the pin. These eliminate the need for external resistors when push button or keypad devices are connected. The pull-ups and pull-downs are separately enabled using the IOCPUx registers (for pull-ups) and the IOCPDx registers (for pull-downs). Each IOC pin has individual control bits for its pull-up and pull-down. Set- ting a control bit enables the weak pull-up or pull-down for the corresponding pin. EXAMPLE 11-1: IOC STATUS READ/CLEAR IN ASSEMBLY EXAMPLE 11-2: PORT READ/WRITE IN ASSEMBLY EXAMPLE 11-3: PORT READ/WRITE IN ‘C’ Note: Pull-ups and pull-downs on pins should always be disabled whenever the pin is configured as a digital output. MOV 0xFFFF, W0 ; Initial mask value 0xFFFF -> W0 XOR IOCFx, W0 ; W0 has '1' for each bit set in IOCFx AND IOCFx ; IOCFx & W0 ->IOCFx MOV 0xFF00, W0 ; Configure PORTB[15:8] as inputs MOV W0, TRISB ; and PORTB[7:0] as outputs NOP ; Delay 1 cycle BTSS PORTB, #13 ; Next Instruction TRISB = 0xFF00; // Configure PORTB[15:8] as inputs and PORTB[7:0] as outputs Nop(); // Delay 1 cycle If (PORTBbits.RB13){ }; // Next Instruction

DS30010198B-page 130  2019-2020 Microchip Technology Inc.

11.4 I/O Port Control Registers

REGISTER 11-1: PADCON: PORT CONFIGURATION REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IOCON: Interrupt-on-Change Enable bit 1 = Interrupt-on-change functionality is enabled 0 = Interrupt-on-change functionality is disabled bit 14-0 Unimplemented: Read as ‘0’

 2019-2020 Microchip Technology Inc. DS30010198B-page 131 PIC24FJ128GL306 FAMILY REGISTER 11-2: IOCSTAT: INTERRUPT-ON-CHANGE STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 R/HS/HC-0 R/HS/HC-0 R/HS/HC-0 R/H S/HC-0 R/HS/HC-0 R/HS/HC-0 R/HS/HC-0 — IOCPGF IOCPFF IOCPEF IOCPDF IOCPCF IOCPBF IOCPAF bit 7 bit 0 Legend: HS = Hardware Settable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6 IOCPGF: Interrupt-on-Change PORTG Flag bit 1 = A change was detected on an IOC-enabled pin on PORTG 0 = No change was detected or the user has cleared all detected changes bit 5 IOCPFF: Interrupt-on-Change PORTF Flag bit 1 = A change was detected on an IOC-enabled pin on PORTF 0 = No change was detected or the user has cleared all detected changes bit 4 IOCPEF: Interrupt-on-Change PORTE Flag bit 1 = A change was detected on an IOC-enabled pin on PORTE 0 = No change was detected or the user has cleared all detected changes bit 3 IOCPDF: Interrupt-on-Change PORTD Flag bit 1 = A change was detected on an IOC-enabled pin on PORTD 0 = No change was detected or the user has cleared all detected changes bit 2 IOCPCF: Interrupt-on-Change PORTC Flag bit 1 = A change was detected on an IOC-enabled pin on PORTC 0 = No change was detected or the user has cleared all detected changes bit 1 IOCPBF: Interrupt-on-Change PORTB Flag bit 1 = A change was detected on an IOC-enabled pin on PORTB 0 = No change was detected or the user has cleared all detected changes bit 0 IOCPAF: Interrupt-on-Change PORTA Flag bit 1 = A change was detected on an IOC-enabled pin on PORTA 0 = No change was detected, or the user has cleared all detected change

DS30010198B-page 132  2019-2020 Microchip Technology Inc. REGISTER 11-3: TRISx: OUTPUT ENABLE FOR PORTx REGISTER (1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISx[15:8] bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISx[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 TRISx[15:0]: Output Enable for PORTx bits 1 = LATx[n] is not driven on the PORTx[n] pin 0 = LATx[n] is driven on the PORTx[n] pin Note 1: See Table 11-3 through Table 11-9 for individual bit availability in this register. REGISTER 11-4: PORTx: INPUT DATA FOR PORTx REGISTER (1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PORTx[15:8] bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PORTx[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PORTx[15:0]: PORTx Data Input Value bits Note 1: See Table 11-3 through Table 11-9 for individual bit availability in this register.

 2019-2020 Microchip Technology Inc. DS30010198B-page 133 PIC24FJ128GL306 FAMILY REGISTER 11-5: LATx: OUTPUT DATA FOR PORTx REGISTER (1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x LATx[15:8] bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x LATx[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 LATx[15:0]: PORTx Data Output Value bits Note 1: See Table 11-3 through Table 11-9 for individual bit availability in this register. REGISTER 11-6: ODCx: OPEN-DRAI N ENABLE FOR PORTx REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ODCx[15:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ODCx[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 ODCx[15:0]: PORTx Open-Drain Enable bits 1 = Open-drain is enabled on the PORTx pin 0 = Open-drain is disabled on the PORTx pin Note 1: See Table 11-3 through Table 11-9 for individual bit availability in this register.

DS30010198B-page 134  2019-2020 Microchip Technology Inc. REGISTER 11-7: ANSELx: ANALOG SELECT FOR PORTx REGISTER (1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSELx[15:8] bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSELx[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 ANSELx[15:0]: Analog Select for PORTx bits 1 = Analog input is enabled and digital input is disabled on the PORTx[n] pin 0 = Analog input is disabled and digital input is enabled on the PORTx[n] pin Note 1: See Table 11-3 through Table 11-9 for individual bit availability in this register. REGISTER 11-8: IOCPx: INTERRUPT-ON-CHANGE POSITIVE EDGE x REGISTER (1,2,3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 IOCPx[15:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IOCPx[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 IOCPx[15:0]: Interrupt-on-Change Positive Edge x Enable bits 1 = Interrupt-on-change is enabled on the IOCx pin for a positive going edge; the associated status bit and interrupt flag will be set upon detecting an edge 0 = Interrupt-on-change is disabled on the IOCx pin for a positive going edge Note 1: Setting both IOCPx and IOCNx will enable the IOCx pin for both edges, while clearing both registers will disable the functionality. 2: Changing the value of this register while the module is enabled (IOCON = 1) may cause a spurious IOC event. The corresponding interrupt must be ignored, cleared (using IOCFx) or masked (within the interrupt controller), or this module must be enabled (IOCON = 0) when changing this register. 3: See Table 11-3 through Table 11-9 for individual bit availability in this register.

 2019-2020 Microchip Technology Inc. DS30010198B-page 135 PIC24FJ128GL306 FAMILY REGISTER 11-9: IOCNx: INTERRUPT-ON-CHANGE NEGATIVE EDGE x REGISTER (1,2,3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 IOCNx[15:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IOCNx[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 IOCNx[15:0]: Interrupt-on-Change Negative Edge x Enable bits 1 = Interrupt-on-change is enabled on the IOCx pin for a negative going edge; the associated status bit and interrupt flag will be set upon detecting an edge 0 = Interrupt-on-change is disabled on the IOCx pin for a negative going edge Note 1: Setting both IOCPx and IOCNx will enable the IOCx pin for both edges, while clearing both registers will disable the functionality. 2: Changing the value of this register while the module is enabled (IOCON = 1) may cause a spurious IOC event. The corresponding interrupt must be ignored, cleared (using IOCFx) or masked (within the interrupt controller), or this module must be enabled (IOCON = 0) when changing this register. 3: See Table 11-3 through Table 11-9 for individual bit availability in this register.

DS30010198B-page 136  2019-2020 Microchip Technology Inc. REGISTER 11-10: IOCFx: INTERRUPT-ON-CHANGE FLAG x REGISTER (1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 IOCFx[15:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IOCFx[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 IOCFx[15:0]: Interrupt-on-Change Flag x bits 1 = An enabled change was detected on the associated pin; set when IOCPx = 1 and a positive edge was detected on the IOCx pin, or when IOCNx = 1 and a negative edge was detected on the IOCx pin 0 = No change was detected or the user cleared the detected change Note 1: It is not possible to set the IOCFx register bits with software writes (as this would require the addition of significant logic). To test IOC interrupts, it is recommended to enable the IOC functionality on one or more GPIO pins and then use the corresponding LATx register bit(s) to trigger an IOC interrupt. 2: See Table 11-3 through Table 11-9 for individual bit availability in this register. REGISTER 11-11: IOCPUx: INTERRUPT-ON-CHANGE PULL-UP ENABLE x REGISTER (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 IOCPUx[15:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IOCPUx[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 IOCPUx[15:0]: Interrupt-on-Change Pull-up Enable x bits 1 = Pull-up is enabled 0 = Pull-up is disabled Note 1: See Table 11-3 through Table 11-9 for individual bit availability in this register.

 2019-2020 Microchip Technology Inc. DS30010198B-page 137 PIC24FJ128GL306 FAMILY REGISTER 11-12: IOCPDx: INTERRUPT-ON-CHANGE PULL-DOWN ENABLE x REGISTER (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 IOCPDx[15:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IOCPDx[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 IOCPDx[15:0]: Interrupt-on-Change Pull-Down Enable x bits 1 = Pull-down is enabled 0 = Pull-down is disabled Note 1: See Table 11-3 through Table 11-9 for individual bit availability in this register.

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11.5 Peripheral Pin Select (PPS)

A major challenge in general purpose devices is provid- ing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. In an application that needs to use more than one peripheral multiplexed on a single pin, inconvenient work arounds in application code, or a complete redesign, may be the only option. The Peripheral Pin Select (PPS) feature provides an alternative to these choices by enabling the user’s peripheral set selection and its placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, users can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. The Peripheral Pin Select feature operates over a fixed subset of digital I/O pins. Users may independently map the input and/or output of any one of many digital peripherals to any one of these I/O pins. PPS is per- formed in software and generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established.

11.5.1 AVAILABLE PINS

The number of available pins is dependent on the par- ticular device and its pin count. Pins that support the Peripheral Pin Select feature include the designation, “RPn” or “RPIn”, in their full pin designation, where “n” is the remappable pin number. “RP” is used to desig- nate pins that support both remappable input and output functions, while “RPI” indicates pins that support remappable input functions only. PIC24FJ128GL306 family devices support a larger number of remappable input/output pins than remap- pable input only pins. In this device family, there are up to 33 remappable input/output pins, depending on the pin count of the particular device selected. These pins are numbered, RP0 through RP31 and RPI37. See Table 1-1 for a summary of pinout options in each package offering.

11.5.2 AVAILABLE PERIPHERALS

The peripherals managed by the PPS are all digital only peripherals. These include general serial commu- nications (UART and SPI), general purpose timer clock inputs, timer related peripherals (input capture and output compare) and external interrupt inputs. Also included are the outputs of the comparator module, since these are discrete digital signals. PPS is not available for these peripherals: 2C (input and output)

• Input Change Notifications
• Analog (inputs and outputs)
• I N T 0 A key difference between pin select and non-pin select peripherals is that pin select peripherals are not asso- ciated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In contrast, non-pin select peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral.

11.5.2.1 Peripheral Pin Select Function

Pin-selectable peripheral outputs (e.g., output com- pare, UART transmit) will take priority over general purpose digital functions on a pin, such as port I/O. Specialized digital outputs will take priority over PPS outputs on the same pin. The pin diagrams list peripheral outputs in the order of priority. Refer to them for priority concerns on a particular pin. Unlike PIC24F devices with fixed peripherals, pin- selectable peripheral inputs will never take ownership of a pin. The pin’s output buffer will be controlled by the TRISx setting or by a fixed peripheral on the pin. If the pin is configured in Digital mode, then the PPS input will operate correctly. If an analog function is enabled on the pin, the PPS input will be disabled.

11.5.3 CONTROLLING PERIPHERAL PIN

PPS features are controlled through two sets of Special Function Registers (SFRs): one to map peripheral inputs and one to map outputs. Because they are separately controlled, a particular peripheral’s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. The association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on if an input or an output is being mapped.

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11.5.3.1 Input Mapping

The inputs of the Peripheral Pin Select options are mapped on the basis of the peripheral; that is, a control register associated with a peripheral dictates the pin it will be mapped to. The RPINRx registers are used to configure peripheral input mapping (see Register 11-13 through Register 11-33). Each register contains one or two sets of 6-bit fields, with each set associated with one of the pin-selectable peripherals. Programming a given peripheral’s bit field with an appropriate 6-bit value maps the RPn/RPIn pin with that value to that peripheral. For any given device, the valid range of values for any of the bit fields corre- sponds to the maximum number of Peripheral Pin Selections supported by the device. TABLE 11-10: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) (1) Input Name Function Name Register Function Mapping Bits External Interrupt 1 INT1 RPINR0[13:8] INT1R[5:0] External Interrupt 2 INT2 RPINR1[5:0] INT2R[5:0] External Interrupt 3 INT3 RPINR1[13:8] INT3R[5:0] External Interrupt 4 INT4 RPINR2[5:0] INT4R[5:0] Timer2 External Clock T2CK RPINR3[5:0] T2CKR[5:0] Timer3 External Clock T3CK RPINR3[13:8] T3CKR[5:0] Timer4 External Clock T4CK RPINR4[5:0] T4CKR[5:0] Timer5 External Clock T5CK RPINR4[13:8] T5CKR[5:0] CCP Capture 1 ICM1 RPINR5[5:0] ICM1R[5:0] CCP Capture 2 ICM2 RPINR5[13:8] ICM2R[5:0] CCP Capture 3 ICM3 RPINR6[5:0] ICM3R[5:0] CCP Capture 4 ICM4 RPINR6[13:8] ICM4R[5:0] Output Compare Fault A OCFA RPINR11[5:0] OCFAR[5:0] Output Compare Fault B OCFB RPINR11[13:8] OCFBR[5:0] CCP Clock Input A TCKIA RPINR12[5:0] TCKIAR[5:0] CCP Clock Input B TCKIB RPINR12[13:8] TCKIBR[5:0] Reference Clock Input REFI RPINR13[5:0] REFIR[5:0] Tamper Detect TMPRN RPINR13[13:8] TMPRNR[5:0] CCP Capture 5 ICM5 RPINR14[5:0] ICM5R[5:0] UART3 Receive U3RX RPINR17[13:8] U3RXR[5:0] UART1 Receive U1RX RPINR18[5:0] U1RXR[5:0] UART1 Clear-to-Send U1CTS RPINR18[13:8] U1CTSR[5:0] UART2 Receive U2RX RPINR19[5:0] U2RXR[5:0] UART2 Clear-to-Send U2CTS RPINR19[13:8] U2CTSR[5:0] SPI1 Data Input SDI1 RPINR20[5:0] SDI1R[5:0] SPI1 Clock Input SCK1IN RPINR20[13:8] SCK1R[5:0] SPI1 Slave Select Input SS1IN RPINR21[5:0] SS1R[5:0] UART3 Clear-to-Send U3CTS RPINR21[13:8] U3CTSR[5:0] SPI2 Data Input SDI2 RPINR22[5:0] SDI2R[5:0] SPI2 Clock Input SCK2IN RPINR22[13:8] SCK2R[5:0] SPI2 Slave Select Input SS2IN RPINR23[5:0] SS2R[5:0] Generic Timer External Clock TxCK RPINR23[13:8] TXCKR[5:0] CLC Input A CLCINA RPINR25[5:0] CLCINAR[5:0] CLC Input B CLCINB RPINR25[13:8] CLCINBR[5:0] CLC Input C CLCINC RPINR26[5:0] CLCINCR[5:0] CLC Input D CLCIND RPINR26[13:8] CLCINDR[5:0] UART4 Receive U4RX RPINR27[5:0] U4RXR[5:0] UART4 Clear-to-Send U4CTS RPINR27[13:8] U4CTSR[5:0] Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger (ST) input buffers.

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11.5.3.2 Output Mapping

In contrast to inputs, the outputs of the Peripheral Pin Select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. Each register contains two 6-bit fields, with each field being associated with either one RPa pin or one RPb pin (see Register 11-34, Table 11-13 and Table 11-14). The value of the bit field corresponds to one of the peripher- als and that peripheral’s output is mapped to the pin (see Table 11-11). Because of the mapping technique, the list of peripherals for output mapping also includes a null value of ‘000000’. This permits any given pin to remain disconnected from the output of any of the pin-selectable peripherals. TABLE 11-11: SELECTABLE OUTPUT SO URCES (MAPS FUNCTION TO OUTPUT) Output Function Number Function Output Name

0 None (Pin Disabled) —

1 C1OUT Comparator 1 Output

2 C2OUT Comparator 2 Output

3 U1TX UART1 Transmit

5 U2TX UART2 Transmit

6U 2 R T S UART2 Request-to-Send

7 SDO1 SPI1 Data Output

8 SCK1OUT SPI1 Clock Output

9 SS1OUT SPI1 Slave Select Output

10 SDO2 SPI2 Data Output

11 SCK2OUT SPI2 Clock Output

12 SS2OUT SPI2 Slave Select Output

16 OCM2A CCP2A Output Compare

17 OCM2B CCP2B Output Compare

18 OCM3A CCP3A Output Compare

19 OCM3B CCP3B Output Compare

20 OCM4A CCP4A Output Compare

21 OCM4B CCP4B Output Compare

22 U3TX UART3 Transmit

23 U3RTS

24 U4TX UART4 Transmit

25 U4RTS UART4 Request-to-Send

26 C3OUT Comparator 3 Output

27 PWRGT RTCC Power Control

28 REFO Reference Clock Output

29 CLC1OUT CLC1 Output

30 CLC2OUT CLC2 Output

31 CLC3OUT CLC3 Output

32 CLC4OUT CLC4 Output

33 RTCC RTCC Clock Output

34 OCM5B CCP5B Output Compare

35 OCM5A CCP5A Output Compare

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11.5.3.3 Mapping Limitations

The control schema of the Peripheral Pin Select is extremely flexible. Other than systematic blocks that prevent signal contention, caused by two physical pins being configured as the same functional input or two functional outputs configured as the same pin, there are no hardware enforced lockouts. The flexibility extends to the point of allowing a single input to drive multiple peripherals or a single functional output to drive multiple output pins.

11.5.3.4 Mapping Exceptions for Family

The differences in available remappable pins are summarized in Table 11-12. When developing applications that use remappable pins, users should also keep these things in mind:

• For the RPINRx registers, bit combinations corre- sponding to an unimplemented pin for a particular device are treated as invalid; the corresponding module will not have an input mapped to it.
• For RPORx registers, the bit fields corresponding to an unimplemented pin will also be unimplemented; writing to these fields will have no effect.

11.5.4 CONTROLLING CONFIGURATION

Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. PIC24F devices include three features to prevent alterations to the peripheral map:

• Control register lock sequence
• Continuous state monitoring
• Configuration bit remapping lock

11.5.4.1 Control Register Lock

Under normal operation, writes to the RPINRx and RPORx registers are not allowed. Attempted writes will appear to execute normally, but the contents of the registers will remain unchanged. To change these reg- isters, they must be unlocked in hardware. The register lock is controlled by the IOLOCK bit (OSCCON[6]). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes. To set or clear IOLOCK, a specific command sequence must be executed: 1. Write 46h to OSCCON[7:0]. 2. Write 57h to OSCCON[7:0]. 3. Clear (or set) IOLOCK as a single operation. Unlike the similar sequence with the oscillator’s LOCK bit, IOLOCK remains in one state until changed. This allows all of the Peripheral Pin Selects to be configured with a single unlock sequence, followed by an update to all control registers, then locked with a second lock sequence.

11.5.4.2 Continuous State Monitoring

In addition to being protected from direct writes, the con- tents of the RPINRx and RPORx registers are constantly monitored in hardware by shadow registers. If an unex- pected change in any of the registers occurs (such as cell disturbances caused by ESD or other external events), a Configuration Mismatch Reset will be triggered.

11.5.4.3 Configuration Bit Pin Select Lock

As an additional level of safety, the device can be configured to prevent more than one write session to the RPINRx and RPORx registers. The IOL1WAY (FOSC[5]) Configuration bit blocks the IOLOCK bit from being cleared after it has been set once. If IOLOCK remains set, the register unlock procedure will not execute and the Peripheral Pin Select Control registers cannot be written to. The only way to clear the bit and re-enable peripheral remapping is to perform a device Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows users unlimited access (with the proper use of the unlock sequence) to the Peripheral Pin Select registers. TABLE 11-12: REMAPPABLE PIN EXCEPTIONS FOR PIC24FJ128GL306 FAMILY DEVICES Device RPn Pins (I/O) RPIn Pins Total Unimplemented Total Unimplemented PIC24FJXXXGL306 32 — 1 — PIC24FJXXXGL305 24 — 1 — PIC24FJXXXGL303 15 — 1 — PIC24FJXXXGL302 13 — 1 —

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11.5.5 CONSIDERATIONS FOR

The ability to control Peripheral Pin Selection intro- duces several considerations into application design that could be overlooked. This is particularly true for several common peripherals that are available only as remappable peripherals. The main consideration is that the Peripheral Pin Selects are not available on default pins in the device’s default (Reset) state. Since all RPINRx registers reset to ‘111111’ and all RPORx registers reset to ‘000000’, all Peripheral Pin Select inputs are tied to V SS, and all Peripheral Pin Select outputs are disconnected. This situation requires the user to initialize the device with the proper peripheral configuration before any other application code is executed. Since the IOLOCK bit resets in the unlocked state, it is not necessary to execute the unlock sequence after the device has come out of Reset. For application safety, however, it is best to set IOLOCK and lock the configuration after writing to the control registers. Because the unlock sequence is timing-critical, it must be executed as an assembly language routine in the same manner as changes to the oscillator configura- tion. If the bulk of the application is written in ‘C’, or another high-level language, the unlock sequence should be performed by writing in-line assembly. Choosing the configuration requires the review of all Peripheral Pin Selects and their pin assignments, especially those that will not be used in the application. In all cases, unused pin-selectable peripherals should be disabled completely. Unused peripherals should have their inputs assigned to an unused RPn/RPIn pin function. I/O pins with unused RPn functions should be configured with the null peripheral output. The assignment of a peripheral to a particular pin does not automatically perform any other configuration of the pin’s I/O circuitry. In theory, this means adding a pin- selectable output to a pin may mean inadvertently driving an existing peripheral input when the output is driven. Users must be familiar with the behavior of other fixed peripherals that share a remappable pin and know when to enable or disable them. To be safe, fixed digital peripherals that share the same pin should be disabled when not in use. Along these lines, configuring a remappable pin for a specific peripheral does not automatically turn that feature on. The peripheral must be specifically config- ured for operation and enabled as if it were tied to a fixed pin. Where this happens in the application code (immediately following a device Reset and peripheral configuration or inside the main application routine) depends on the peripheral and its use in the application. A final consideration is that Peripheral Pin Select func- tions neither override analog inputs nor reconfigure pins with analog functions for digital I/Os. If a pin is configured as an analog input on a device Reset, it must be explicitly reconfigured as a digital I/O when used with a Peripheral Pin Select. Example 11-4 shows a configuration for bidirectional communication with flow control using UART1. The following input and output functions are used:

• Input Functions: U1RX, U1CTS
• Output Functions: U1TX, U1RTS EXAMPLE 11-4: CONFIGURING UART1 INPUT AND OUTPUT FUNCTIONS // Unlock Registers asm volatile ("MOV #OSCCON, w1 \\n" "MOV #0x46, w2 \\n" "MOV #0x57, w3 \\n" "MOV.b w2, [w1] \\n" "MOV.b w3, [w1] \\n" "BCLR OSCCON, #6") ; // or use XC16 built-in macro: // __builtin_write_OSCCONL(OSCCON & 0xbf); // Configure Input Functions ( Table 11-10) // Assign U1RX To Pin RP0 RPINR18bits.U1RXR = 0; // Assign U1CTS To Pin RP1 RPINR18bits.U1CTSR = 1; // Configure Output Functions ( Table 11-11) // Assign U1TX To Pin RP2 RPOR1bits.RP2R = 3; // Assign U1RTS To Pin RP3 RPOR1bits.RP3R = 4; // Lock Registers asm volatile ("MOV #OSCCON, w1 \\n" "MOV #0x46, w2 \\n" "MOV #0x57, w3 \\n" "MOV.b w2, [w1] \\n" "MOV.b w3, [w1] \\n" "BSET OSCCON, #6") ; // or use XC16 built-in macro: // __builtin_write_OSCCONL(OSCCON | 0x40);

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11.5.6 PERIPHERAL PIN SELECT

The PIC24FJ128GL306 family of devices implements a total of 36 registers for remappable peripheral configuration:

• Input Remappable Peripheral Registers (21)
• Output Remappable Peripheral Registers (15) Note: Input and Output register values can only be changed if IOLOCK (OSCCON[6]) = 0. See Section 11.5.4.1 “Control Register Lock” for a specific command sequence. REGISTER 11-13: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — I N T 1 R 5I N T 1 R 4I N T 1 R 3I N T 1 R 2I N T 1 R 1I N T 1 R 0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 INT1R[5:0]: Assign External Interrupt 1 (INT1) to the Corresponding RPn or RPIn Pin bits bit 7-0 Unimplemented: Read as ‘0’ REGISTER 11-14: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — I N T 3 R 5I N T 3 R 4I N T 3 R 3I N T 3 R 2I N T 3 R 1I N T 3 R 0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — I N T 2 R 5I N T 2 R 4I N T 2 R 3I N T 2 R 2I N T 2 R 1I N T 2 R 0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 INT3R[5:0]: Assign External Interrupt 3 (INT3) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 INT2R[5:0]: Assign External Interrupt 2 (INT2) to the Corresponding RPn or RPIn Pin bits

DS30010198B-page 144  2019-2020 Microchip Technology Inc. REGISTER 11-15: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — I N T 4 R 5I N T 4 R 4I N T 4 R 3I N T 4 R 2I N T 4 R 1I N T 4 R 0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 INT4R[5:0]: Assign External Interrupt 4 (INT4) to the Corresponding RPn or RPIn Pin bits REGISTER 11-16: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T 3 C K R 5T 3 C K R 4T 3 C K R 3T 3 C K R 2T 3 C K R 1T 3 C K R 0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T 2 C K R 5T 2 C K R 4T 2 C K R 3T 2 C K R 2T 2 C K R 1T 2 C K R 0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 T3CKR[5:0]: Assign Timer3 Clock (T3CK) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 T2CKR[5:0]: Assign Timer2 Clock to (T2CK) the Corresponding RPn or RPIn Pin bits

 2019-2020 Microchip Technology Inc. DS30010198B-page 145 PIC24FJ128GL306 FAMILY REGISTER 11-17: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T5CKR5 T5CKR4 T5CKR3 T5CKR2 T5CKR1 T5CKR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T4CKR5 T4CKR4 T4CKR3 T4CKR2 T4CKR1 T4CKR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 T5CKR[5:0]: Assign Timer5 Clock (T5CK) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 T4CKR[5:0]: Assign Timer4 Clock (T4CK) to the Corresponding RPn or RPIn Pin bits REGISTER 11-18: RPINR5: PERIPHERAL PIN SELECT INPUT REGISTER 5 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — ICM2R5 ICM2R4 ICM2R3 ICM2R2 ICM2R1 ICM2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — ICM1R5 ICM1R4 ICM1R3 ICM1R2 ICM1R1 ICM1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 ICM2R[5:0]: Assign CCP2 Capture Mode (ICM2) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ICM1R[5:0]: Assign CCP1 Capture Mode (ICM1) to the Corresponding RPn or RPIn Pin bits

DS30010198B-page 146  2019-2020 Microchip Technology Inc. REGISTER 11-19: RPINR6: PERIPHERAL PIN SELECT INPUT REGISTER 6 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — ICM4R5 ICM4R4 ICM4R3 ICM4R2 ICM4R1 ICM4R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — ICM3R5 ICM3R4 ICM3R3 ICM3R2 ICM3R1 ICM3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 ICM4R[5:0]: Assign CCP4 Capture Mode (ICM4) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ICM3R[5:0]: Assign CCP3 Capture Mode (ICM3) to the Corresponding RPn or RPIn Pin bits REGISTER 11-20: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — OCFBR5 OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — OCFAR5 OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 OCFBR[5:0]: Assign Output Compare Fault B (OCFB) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 OCFAR[5:0]: Assign Output Compare Fault A (OCFA) to the Corresponding RPn or RPIn Pin bits

 2019-2020 Microchip Technology Inc. DS30010198B-page 147 PIC24FJ128GL306 FAMILY REGISTER 11-21: RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — TCKIBR5 TCKIBR4 TCKIBR3 TCKIBR2 TCKIBR1 TCKIBR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — TCKIAR5 TCKIAR4 TCKIAR3 TCKIAR2 TCKIAR1 TCKIAR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 TCKIBR[5:0]: Assign MCCP Clock Input B (TCKIB) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TCKIAR[5:0]: Assign MCCP Clock Input A (TCKIA) to the Corresponding RPn or RPIn Pin bits REGISTER 11-22: RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — TMPRNR5 TMPRNR4 TMPRNR3 TMPRNR2 TMPRNR1 TMPRNR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — REFIR5 REFIR4 REFIR3 REFIR2 REFIR1 REFIR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 TMPRNR[5:0]: Assign Tamper Detect (TMPRN) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 REFIR[5:0]: Assign Reference Clock Input (REFI) to the Corresponding RPn or RPIn Pin bits

DS30010198B-page 148  2019-2020 Microchip Technology Inc. REGISTER 11-23: RPINR14: PERIPHERAL PIN SELECT INPUT REGISTER 14 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — ICM5R5 ICM5R4 ICM5R3 ICM5R2 ICM5R1 ICM5R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 ICM5R[5:0]: Assign CCP5 Capture Mode (ICM5) to the Corresponding RPn or RPIn Pin bits REGISTER 11-24: RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U3RXR5 U3RXR4 U3RXR3 U3RXR2 U3RXR1 U3RXR0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U3RXR[5:0]: Assign UART3 Receive (U3RX) to the Corresponding RPn or RPIn Pin bits bit 7-0 Unimplemented: Read as ‘0’

 2019-2020 Microchip Technology Inc. DS30010198B-page 149 PIC24FJ128GL306 FAMILY REGISTER 11-25: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U1CTSR[5:0]: Assign UART1 Clear-to-Send (U1CTS) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U1RXR[5:0]: Assign UART1 Receive (U1RX) to the Corresponding RPn or RPIn Pin bits REGISTER 11-26: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U2RXR5 U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U2CTSR[5:0]: Assign UART2 Clear-to-Send (U2CTS) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U2RXR[5:0]: Assign UART2 Receive (U2RX) to the Corresponding RPn or RPIn Pin bits

DS30010198B-page 150  2019-2020 Microchip Technology Inc. REGISTER 11-27: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — S D I 1 R 5S D I 1 R 4S D I 1 R 3S D I 1 R 2S D I 1 R 1S D I 1 R 0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SCK1R[5:0]: Assign SPI1 Clock Input (SCK1IN) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SDI1R[5:0]: Assign SPI1 Data Input (SDI1) to the Corresponding RPn or RPIn Pin bits REGISTER 11-28: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U3CTSR5 U3CTSR4 U3CTSR3 U3CTSR2 U3CTSR1 U3CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SS1R5 SS1R4 SS1R3 SS1R2 SS1R1 SS1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit U3CTSR[5:0]: Assign UART3 Receive (U3CTS) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SS1R[5:0]: Assign SPI1 Slave Select Input (SS1IN) to the Corresponding RPn or RPIn Pin bits

 2019-2020 Microchip Technology Inc. DS30010198B-page 151 PIC24FJ128GL306 FAMILY REGISTER 11-29: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK2R5 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — S D I 2 R 5S D I 2 R 4S D I 2 R 3S D I 2 R 2S D I 2 R 1S D I 2 R 0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SCK2R[5:0]: Assign SPI2 Clock Input (SCK2IN) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SDI2R[5:0]: Assign SPI2 Data Input (SDI2) to the Corresponding RPn or RPIn Pin bits REGISTER 11-30: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — TXCKR5 TXCKR4 TXCKR3 TXCKR2 TXCKR1 TXCKR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SS2R5 SS2R4 SS2R3 SS2R2 SS2R1 SS2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 TXCKR[5:0]: Assign Generic Timer External Clock (TxCK) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SS2R[5:0]: Assign SPI2 Slave Select Input (SS2IN) to the Corresponding RPn or RPIn Pin bits

DS30010198B-page 152  2019-2020 Microchip Technology Inc. REGISTER 11-31: RPINR25: PERIPHERAL PIN SELECT INPUT REGISTER 25 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — CLCINBR5 CLCINBR4 CLCINBR3 C LCINBR2 CLCINBR1 CLCINBR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — CLCINAR5 CLCINAR4 CLCINAR3 C LCINAR2 CLCINAR1 CLCINAR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 CLCINBR[5:0]: Assign CLC Input B (CLCINB) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 CLCINAR[5:0]: Assign CLC Input A (CLCINA) to the Corresponding RPn or RPIn Pin bits REGISTER 11-32: RPINR26: PERIPHERAL PIN SELECT INPUT REGISTER 26 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — CLCINDR5 CLCINDR4 CLCINDR3 CLCINDR2 CLCINDR1 CLCINDR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — CLCINCR5 CLCINCR4 CLCINCR3 CLCINCR2 CLCINCR1 CLCINCR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 CLCINDR[5:0]: Assign CLC Input D (CLCIND) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 CLCINCR[5:0]: Assign CLC Input C (CLCINC) to the Corresponding RPn or RPIn Pin bits

 2019-2020 Microchip Technology Inc. DS30010198B-page 153 PIC24FJ128GL306 FAMILY REGISTER 11-33: RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U4CTSR5 U4CTSR4 U4CTSR3 U4CTSR2 U4CTSR1 U4CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U4RXR5 U4RXR4 U4RXR3 U 4RXR2 U4RXR1 U4RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U4CTSR[5:0]: Assign UART4 Clear-to-Send (U 4CTS) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U4RXR[5:0]: Assign UART4 Receive (U4RX) to the Corresponding RPn or RPIn Pin bits REGISTER 11-34: RPORx: PERIPHERAL PIN SELECT OUTPUT REGISTER x U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RPaR5 RPaR4 RPaR3 RPaR2 RPaR1 RPaR0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RPbR5 RPbR4 RPbR3 RPbR2 RPbR1 RPbR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RPaR[5:0]: RPa Output Pin Mapping bits Peripheral Output Number y is assigned to pin, RPa (see Table 11-11 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RPbR[5:0]: RPb Output Pin Mapping bits Peripheral Output Number y is assigned to pin, RPb (see Table 11-11 for peripheral function numbers).

DS30010198B-page 154  2019-2020 Microchip Technology Inc. TABLE 11-13: PPS INPUT CONT ROL FOR RPINR REGISTERS Register Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 B it 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RPINR1 792h — —I N T 3 R [ 5 : 0 ] — — INT2R[5:0] RPINR3 796h — —T 3 C K R [ 5 : 0 ] — — T2CKR[5:0] RPINR4 798h — —T 5 C K R [ 5 : 0 ] — — T4CKR[5:0] RPINR5 79Ah — —I C M 2 R [ 5 : 0 ] — — ICM1R[5:0] RPINR6 79Ch — —I C M 4 R [ 5 : 0 ] — — ICM3R[5:0] RPINR11 7A6h — — OCFBR[5:0] — —O C F A R [ 5 : 0 ] RPINR12 7A8h — — TCKIBR[5:0] — — TCKIAR[5:0] RPINR13 7AAh — — TMPRNR[5:0] — —R E F I 1 R [ 5 : 0 ] RPINR18 7B4h — — U1CTSR[5:0] — —U 1 R X R [ 5 : 0 ] RPINR19 7B6h — — U2CTSR[5:0] — —U 2 R X R [ 5 : 0 ] RPINR20 7B8h — —S C K 1 R [ 5 : 0 ] — —S D I 1 R [ 5 : 0 ] RPINR21 7BAh — — U3CTSR[5:0] — — SS1R[5:0] RPINR22 7BCh — —S C K 2 R [ 5 : 0 ] — —S D I 2 R [ 5 : 0 ] RPINR23 7BEh — — TXCKR[5:0] — — SS2R[5:0] RPINR25 7C2h — — CLCINBR[5:0] — — CLCINAR[5:0] RPINR26 7C4h — — CLCINDR[5:0] — — CLCINCR[5:0] RPINR27 7C6h — — U4CTSR[5:0] — —U 4 R X R [ 5 : 0 ]

 2019-2020 Microchip Technology Inc. DS30010198B-page 155 PIC24FJ128GL306 FAMILY TABLE 11-14: PPS OUTPUT CONTROL FOR RPOR REGISTERS Register Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RPOR0 7D4h — —R P 1 R [ 5 : 0 ] — — RP0R[5:0] RPOR1 7D6h — —R P 3 R [ 5 : 0 ] — — RP2R[5:0] RPOR2 7D8h — —R P 5 R [ 5 : 0 ] — — RP4R[5:0] RPOR3 7DAh — —R P 7 R [ 5 : 0 ] — — RP6R[5:0] RPOR4 7DCh — —R P 9 R [ 5 : 0 ] — — RP8R[5:0] RPOR5 7DEh — — RP11R[5:0] — — RP10R[5:0] RPOR6 7E0h — — RP13R[5:0] — — RP12R[5:0] RPOR7 7E2h — — RP15R[5:0] — — RP14R[5:0] RPOR8 7E4h — — RP17R[5:0] — — RP16R[5:0] RPOR9 7E6h — — RP19R[5:0] — — RP18R[5:0] RPOR10 7E8h — — RP21R[5:0] — — RP20R[5:0] RPOR11 7EAh — — RP23R[5:0] — — RP22R[5:0] RPOR12 7ECh — — RP25R[5:0] — — RP24R[5:0] RPOR13 7EEh — — RP27R[5:0] — — RP26R[5:0] RPOR14 7F0h — — RP29R[5:0] — — RP28R[5:0] RPOR15 7F2h — — RP31R[5:0] — — RP30R[5:0]

DS30010198B-page 156  2019-2020 Microchip Technology Inc. NOTES:

 2019-2020 Microchip Technology Inc. DS30010198B-page 157 PIC24FJ128GL306 FAMILY

12.0 TIMER1

The Timer1 module is a 16-bit timer, which can serve as the time counter for the Real-Time Clock (RTC) or operate as a free-running, interval timer/counter. Timer1 can operate in three modes:

• 1 6 - B i t T i m e r
• 16-Bit Synchronous Counter
• 16-Bit Asynchronous Counter Timer1 also supports these features:
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation during CPU Idle and Sleep modes
• Interrupt on 16-Bit Period Register Match or Falling Edge of External Gate Signal Figure 12-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS[1:0] bits. 3. Set the Clock and Gating modes using the TCS, TECS[1:0] and TGATE bits. 4. Set or clear the TSYNC bit to configure synchronous or asynchronous operation. 5. Load the timer period value into the PR1 register. 6. If interrupts are required, set the interrupt enable bit, T1IE. Use the priority bits, T1IP[2:0], to set the interrupt priority. FIGURE 12-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive ref- erence source. For more information, refer to “Timers” (www.microchip.com/ DS39704) in the “dsPIC33/PIC24 Family Reference Manual ”. The information in this data sheet supersedes the information in the FRM. TON Sync SOSCI SOSCO PR1 Set T1IF Equal Comparator Reset SOSCEN TSYNC Q QD CK TCKPS[1:0] TGATE TCY TCS TGATE SOSC Input Gate Output Clock Input Select Detail LPRC Input TECS[1:0] T1CK Input SOSCSEL LPRC Clock Input Select Prescaler 1, 8, 64, 256TxCK Input TMR1 Gate Sync Clock Output to TMR1

DS30010198B-page 158  2019-2020 Microchip Technology Inc. REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER (1) R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 TON —T S I D L — — —T E C S 1 T E C S 0 bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timer1 Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-10 Unimplemented: Read as ‘0’ bit 9-8 TECS[1:0]: Timer1 Extended Clock Source Select bits (selected when TCS = 1) 11 = Generic timer (TxCK) external input 10 = LPRC Oscillator 01 = T1CK External Clock input 00 = SOSC bit 7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS[1:0]: Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronizes the External Clock input 0 = Does not synchronize the External Clock input When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit 1 = Extended clock is selected by the timer 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: Changing the value of T1CON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended.

 2019-2020 Microchip Technology Inc. DS30010198B-page 159 PIC24FJ128GL306 FAMILY

13.0 TIMER2/3 AND TIMER4/5

The Timer2/3 and Timer4/5 modules are 32-bit timers, which can also be configured as independent, 16-bit timers with selectable operating modes. As a 32-bit timer, Timer2/3 or Timer4/5 can operate in three modes:

• Two Independent 16-Bit Timers with All 16-Bit Operating modes (except Asynchronous Counter mode)
• Single 32-Bit Timer
• Single 32-Bit Synchronous Counter They also support these features:
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation during Idle and Sleep modes
• Interrupt on a 32-Bit Period Register Match
• A/D Event Trigger (on Timer4/5 in 32-bit mode and Timer5 in 16-bit mode) Individually, all of the 16-bit timers can function as synchronous timers or counters. They also offer the features listed above, except for the A/D event trigger. This trigger is implemented only on Timer4/5 in 32-bit mode and Timer5 in 16-bit mode. The operating modes and enabled features are determined by setting the appropriate bit(s) in the T2CON, T3CON, T4CON and T5CON registers. T2CON and T4CON are shown in generic form in Register 13-1; T3CON and T5CON are shown in Register 13-2. For 32-bit timer/counter operation, Timer2 and Timer4 are the least significant word; Timer3 and Timer5 are the most significant word of the 32-bit timer. To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON[3] = 1 or T4CON[3] = 1). 2. Select the prescaler ratio for Timer2 or Timer4 using the TCKPS[1:0] bits. 3. Set the Clock and Gating modes using the TCS and TGATE bits. If TCS is set to an External Clock, RPINRx (TyCK) must be configured to an available RPn/RPIn pin. For more informa- tion, see Section 11.5 “Peripheral Pin Select (PPS)”. 4. Load the timer period value. PR3 or PR5 will contain the most significant word (msw) of the value, while PR2 or PR4 contains the least significant word (lsw). 5. If interrupts are required, set the interrupt enable bit, T3IE or T5IE. Use the priority bits, T3IP[2:0] or T5IP[2:0], to set the interrupt priority. Note that while Timer2 or Timer4 controls the timer, the interrupt appears as a Timer3 or Timer5 interrupt. 6. Set the TON bit (= 1). The timer value, at any point, is stored in the register pair, TMR[3:2] (or TMR[5:4]). TMR3 (or TMR5) always contains the most significant word of the count, while TMR2 (or TMR4) contains the least significant word. To configure any of the timers for individual 16-bit operation: 1. Clear the T32 bit (T2CON[3] for Timer2 and Timer3 or T4CON[3] for Timer4 and Timer5). 2. Select the timer prescaler ratio using the TCKPS[1:0] bits. 3. Set the Clock and Gating modes using the TCS and TGATE bits. See Section 11.5 “Peripheral Pin Select (PPS)” for more information. 4. Load the timer period value into the PRx register. 5. If interrupts are required, set the interrupt enable bit, TxIE. Use the priority bits, TxIP[2:0], to set the interrupt priority. 6. Set the TON bit (TxCON[15] = 1). Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive refer- ence source. For more information, refer to “Timers” (www.microchip.com/DS39704) in the “dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. Note: For 32-bit operation, T3CON and T5CON control bits are ignored. Only T2CON and T4CON control bits are used for setup and control. Timer2 and Timer4 clocks, and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 and Timer5 interrupt flags.

DS30010198B-page 160  2019-2020 Microchip Technology Inc. FIGURE 13-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM TMR3 TMR2 Set T3IF (T5IF) Equal Comparator PR3 PR2 Reset LSBMSB Note 1: The 32-Bit Timer Configuration bit, T32, must be set fo r 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers. 2: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.5 “Peripheral Pin Select (PPS)” for more information. 3: The A/D event trigger is available only on Timer4/5 in 32-bit mode and Timer4 in 16-bit mode. Data Bus[15:0] Read TMR2 (TMR4)(1) Write TMR2 (TMR4)(1) Q QD CK TGATE TCKPS[1:0] A/D Event Trigger(3) T2CK (T4CLK) TCY TCS(2) TGATE(2) SOSC Input LPRC Input TECS[1:0] TxCK Gate Sync Prescaler 1, 8, 64, 256 Sync TMR3HLD (PR5) (PR4) (TMR4)(TMR5) (TMR5HLD)

DS30010198B-page 162  2019-2020 Microchip Technology Inc. REGISTER 13-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(1) R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 TON —T S I D L — — — TECS1 (2) TECS0(2) bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 T32 (3) —T C S (2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timerx On bit When TxCON[3] = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-bit Timerx/y When TxCON[3] = 0: 1 = Starts 16-bit Timerx 0 = Stops 16-bit Timerx bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timerx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-10 Unimplemented: Read as ‘0’ bit 9-8 TECS[1:0]: Timerx Extended Clock Source Select bits (selected when TCS = 1)(2) When TCS = 1: 11 = Generic timer (TxCK) external input 10 = LPRC Oscillator 01 = TyCK External Clock input 00 = SOSC When TCS = 0: These bits are ignored; the timer is clocked from the internal system clock (FOSC/2). bit 7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS[1:0]: Timerx Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 Note 1: Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. 2: If TCS = 1 and TECS[1:0] = x1, the selected external timer input (TxCK or TyCK) must be configured to an available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”. 3: In 32-bit mode, the T3CON and T5CON control bits do not affect 32-bit timer operation.

 2019-2020 Microchip Technology Inc. DS30010198B-page 163 PIC24FJ128GL306 FAMILY bit 3 T32: 32-Bit Timer Mode Select bit(3) 1 = Timerx and Timery form a single 32-bit timer 0 = Timerx and Timery act as two 16-bit timers bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timerx Clock Source Select bit(2) 1 = Timer source is selected by TECS[1:0] 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ REGISTER 13-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(1) (CONTINUED) Note 1: Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. 2: If TCS = 1 and TECS[1:0] = x1, the selected external timer input (TxCK or TyCK) must be configured to an available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”. 3: In 32-bit mode, the T3CON and T5CON control bits do not affect 32-bit timer operation.

DS30010198B-page 164  2019-2020 Microchip Technology Inc. REGISTER 13-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER(1) R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 TON(2) —T S I D L (2) — — — TECS1 (2,3) TECS0(2,3) bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 —T G A T E (2) TCKPS1(2) TCKPS0(2) — —T C S (2,3) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timery On bit(2) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timery Stop in Idle Mode bit(2) 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-10 Unimplemented: Read as ‘0’ bit 9-8 TECS[1:0]: Timery Extended Clock Source Select bits (selected when TCS = 1)(2,3) 11 = Generic timer (TxCK) external input 10 = LPRC Oscillator 01 = TyCK External Clock input 00 = SOSC bit 7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timery Gated Time Accumulation Enable bit(2) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS[1:0]: Timery Input Clock Prescale Select bits(2) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3-2 Unimplemented: Read as ‘0’ bit 1 TCS: Timery Clock Source Select bit(2,3) 1 = External clock from pin, TyCK (on the rising edge) 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. 2: When 32-bit operation is enabled (T2CON[3] = 1 or T4CON[3] = 1), this bit has no effect on Timery operation; all timer functions are set through T2CON and T4CON. 3: If TCS = 1 and TECS[1:0] = x1, the selected external timer input (TyCK) must be configured to an available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”.

 2019-2020 Microchip Technology Inc. DS30010198B-page 165 PIC24FJ128GL306 FAMILY

14.0 CAPTURE/COMPARE/PWM/

TIMER MODULES (MCCP) PIC24FJ128GL306 family devices include several Capture/Compare/PWM/Timer base modules, which provide the functionality of three different peripherals of earlier PIC24F devices. The module can operate in one of three major modes:

• General Purpose Timer
• Input Capture
• Output Compare/PWM This family of devices features five instances of the MCCP module. MCCP1 provides up to six outputs and an extended range of power control features, whereas MCCP2-MCCP5 support two outputs. The MCCPx modules can be operated only in one of the three major modes at any time. The other modes are not available unless the module is reconfigured for the new mode. A conceptual block diagram for the module is shown in Figure 14-1. All three modules share a time base gener- ator and a common Timer register pair (CCPxTMRH/L); other shared hardware components are added as a particular mode requires. Each module has a total of eight control and status registers:
• CCPxCON1L (Register 14-1)
• CCPxCON1H ( Register 14-2)
• CCPxCON2L (Register 14-3)
• CCPxCON2H ( Register 14-4)
• CCPxCON3L (Register 14-5)
• CCPxCON3H ( Register 14-6)
• CCPxSTATL (Register 14-7) Each module also includes eight buffer/counter registers that serve as Timer Value registers or data holding buffers:
• CCPxTMRH/CCPxTMRL (CCPx Timer High/Low Counters)
• CCPxPRH/CCPxPRL (CCPx Timer Period High/ Low)
• CCPxRAH/CCPxRAL (CCPx Primary Output Compare Data High/Low Buffers)
• CCPxRBH/CCPxRBL (CCPx Secondary Output Compare Data High/Low Buffers)
• CCPxBUFH/CCPxBUFL (CCPx Input Capture High/Low Buffers) FIGURE 14-1: MCCPx CONC EPTUAL BLOCK DIAGRAM Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive reference source. For more information, refer to “Capture/Compare/PWM/Timer (MCCP and SCCP)” (www.microchip.com/ DS30003035) in the “dsPIC33/PIC24 Fam- ily Reference Manual”. The information in this data sheet supersedes the information in the FRM. Clock Sources Input Capture Output Compare/PWM T32 CCSEL MOD[3:0] Sync and Gating Sources 16/32-Bit CCPxIF CCTxIF External Compare/PWM Output(s) OCFA/OCFBTimer Sync/Trigger Out Special Trigger (to A/D) Capture Input Time Base Generator CCPxTMRH/L

DS30010198B-page 166  2019-2020 Microchip Technology Inc.

14.1 Time Base Generator

The Timer Clock Generator (TCG) generates a clock for the module’s internal time base using one of the clock signals already available on the microcontroller. This is used as the time reference for the module in its three major modes. The internal time base is shown in Figure 14-2. There are eight inputs available to the clock generator, which are selected using the CLKSEL[2:0] bits (CCPxCON1L[10:8]). Available sources include the FRC and LPRC, the Secondary Oscillator and the TCLKI External Clock inputs. The system clock is the default source (CLKSEL[2:0] = 000). On PIC24FJ128GL306 family devices, clock sources to the MCCPx modules must be synchronized with the system clock. As a result, when clock sources are selected, clock input timing restrictions or module operating restrictions may exist. FIGURE 14-2: TIMER CLOCK GENERATOR CLKSEL[2:0] TMRPS[1:0] Prescaler Clock Synchronizer TMRSYNC Gate(1) SSDG Clock Sources To Rest of Module Note 1: Gating is available in Timer modes only.

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14.2 General Purpose Timer

Timer mode is selected when CCSEL = 0 and MOD[3:0] = 0000. The timer can function as a 32-bit timer or a dual 16-bit timer, depending on the setting of the T32 bit (Table 14-1). TABLE 14-1: TIMER OPERATION MODE Dual 16-Bit Timer mode provides a simple timer function with two independent 16-bit timer/counters. The primary timer uses the CCPxTMRL and CCPxPRL registers. Only the primary timer can interact with other modules on the device. It generates the MCCPx Sync out signals for use by other MCCPx modules. It can also use the SYNC[4:0] bits’ signal generated by other modules. The secondary timer uses the CCPxTMRH and CCPxPRH registers. It is intended to be used only as a periodic interrupt source for scheduling CPU events. It does not generate an output Sync/trigger signal like the primary time base. In Dual Timer mode, the CCPx Timer Period High register, CCPxPRH, generates the MCCPx compare event (CCPxIF) used by many other modules on the device. The 32-Bit Timer mode uses the CCPxTMRL and CCPxTMRH registers, together, as a single 32-bit timer. When CCPxTMRL overflows, CCPxTMRH increments by one. This mode provides a simple timer function when it is important to track long time periods. Note that the T32 bit (CCPxCON1L[5]) should be set before the CCPxTMRL or CCPxPRH registers are written to initialize the 32-bit timer.

14.2.1 SYNC AND TRIGGER OPERATION

In both 16-bit and 32-bit modes, the timer can also function in either Synchronization (“Sync”) or Trigger mode operation. Both use the SYNC[4:0] bits (CCPxCON1H[4:0]) to determine the input signal source. The difference is how that signal affects the timer. In Sync operation, the Timer Reset or clear occurs when the input selected by SYNC[4:0] is asserted. The timer immediately begins to count again from zero unless it is held for some other reason. Sync operation is used when- ever the TRIGEN bit (CCPxCON1H[7]) is cleared. The SYNC[4:0] bits can have any value except ‘11111’. In Trigger mode operation, the timer is held in Reset until the input selected by SYNC[4:0] is asserted; when it occurs, the timer starts counting. Trigger operation is used whenever the TRIGEN bit is set. In Trigger mode, the timer will continue running after a trigger event as long as the CCPTRIG bit (CCPxSTATL[7]) is set. To clear CCPTRIG, the TRCLR bit (CCPxSTATL[5]) must be set to clear the trigger event, reset the timer and hold it at zero until another trigger event occurs. On PIC24FJ128GL306 family devices, Trigger mode operation can only be used when the system clock is the time base source (CLKSEL[2:0] = 000). FIGURE 14-3: DUAL 16-BIT TIMER MODE T32 (CCPxCON1L[5]) Operating Mode

0 Dual Timer Mode (16-bit)

1 Timer Mode (32-bit)

SYNC[4:0] Time Base Generator Sync/ Trigger Control Comparator

DS30010198B-page 168  2019-2020 Microchip Technology Inc. FIGURE 14-4: 32-BIT TIMER MODE

14.3 Output Compare Mode

Output Compare mode compares the Timer register value with the value of one or two Compare registers, depending on its mode of operation. The Output Compare x module, on compare match events, has the ability to generate a single output transition or a train of output pulses. Like most PIC ® MCU peripherals, the Output Compare x module can also generate interrupts on a compare match event. Table 14-2 shows the various modes available in Output Compare modes. TABLE 14-2: OUTPUT COMPARE/PWM MODES CCPxTMRL CCPxPRL Comparator Set CCTxIF CCPxTMRH CCPxPRH Clock Sources Sync/ Trigger Control SYNC[4:0] Time Base Generator MOD[3:0] (CCPxCON1L[3:0]) T32 (CCPxCON1L[5]) Operating Mode 0001 0 Output High on Compare (16-bit) Single Edge Mode 0001 1 Output High on Compare (32-bit) 0010 0 Output Low on Compare (16-bit) 0010 1 Output Low on Compare (32-bit) 0011 0 Output Toggle on Compare (16-bit) 0011 1 Output Toggle on Compare (32-bit) 0100 0 Dual Edge Compare (16-bit) Dual Edge Mode 0101 0 Dual Edge Compare (16-bit buffered) PWM Mode 0110 0 Center-Aligned Pulse (16-bit buffered)(1) Center PWM Mode 0111 0 Variable Frequency Pulse (16-bit)(1) 1111 0 External Input Source Mode (16-bit) Note 1: Available only on the MCCP1 module.

 2019-2020 Microchip Technology Inc. DS30010198B-page 169 PIC24FJ128GL306 FAMILY FIGURE 14-5: OUTPUT COMPARE x BLOCK DIAGRAM CCPxRA Buffer Comparator CCPxCON1H/L CCPxCON2H/L OCx Output, Output Compare CCPx Pin(s) CCPxRB Buffer Comparator Fault Logic Match Match Time Base Generator Increment Reset OCx Clock Sources Trigger and Sync Sources Reset Match Event OCFA/OCFB CCPxRAH/L Event Event Rollover Rollover/Reset Rollover/Reset CCPxCON3H/L Auto-Shutdown and Polarity ControlEdge Detect Interrupt Comparator Trigger and Sync Logic CCPxPRL CCPxRBH/L CCPxTMRH/L

DS30010198B-page 170  2019-2020 Microchip Technology Inc.

14.4 Input Capture Mode

Input Capture mode is used to capture a timer value from an independent timer base upon an event on an input pin or other internal Trigger source. The input capture features are useful in applications requiring frequency (time period) and pulse measurement. Figure 14-6 depicts a simplified block diagram of the Input Capture mode. Input Capture mode uses a dedicated 16/32-bit, synchro- nous, up counting timer for the capture function. The timer value is written to the FIFO when a capture event occurs. The internal value may be read (with a synchronization delay) using the CCPxTMRH/L registers. To use Input Capture mode, the CCSEL bit (CCPxCON1L[4]) must be set. The T32 and MOD[3:0] bits are used to select the proper Capture mode, as shown in Table 14-3. FIGURE 14-6: INPUT CAPTURE x BLOCK DIAGRAM TABLE 14-3: INPUT CAPTURE MODES MOD[3:0] (CCPxCON1L[3:0]) T32 (CCPxCON1L[5]) Operating Mode 0000 0 Edge Detect (16-bit capture) 0000 1 Edge Detect (32-bit capture) 0001 0 Every Rising (16-bit capture) 0001 1 Every Rising (32-bit capture) 0010 0 Every Falling (16-bit capture) 0010 1 Every Falling (32-bit capture) 0011 0 Every Rise/Fall (16-bit capture) 0011 1 Every Rise/Fall (32-bit capture) 0100 0 Every 4th Rising (16-bit capture) 0100 1 Every 4th Rising (32-bit capture) 0101 0 Every 16th Rising (16-bit capture) 0101 1 Every 16th Rising (32-bit capture) CCPxBUFx 4-Level FIFO Buffer MOD[3:0] Set CCPxIF OPS[3:0] Interrupt Logic System Bus Event and Trigger and Sync Logic Clock Select ICx Clock Sources Trigger and Sync Sources ICS[2:0] 16CCPxTMRH/L Increment Reset T32 Edge Detect Logic and Clock Synchronizer

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14.5 Auxiliary Output

The MCCPx modules have an auxiliary (secondary) output that provides other peripherals access to inter- nal module signals. The auxiliary output is intended to connect to other MCCPx modules, or other digital peripherals, to provide these types of functions:

• Time Base Synchronization
• Peripheral Trigger and Clock Inputs
• Signal Gating The type of output signal is selected using the AUXOUT[1:0] control bits (CCPxCON2H[4:3]). The type of output signal is also dependent on the module operating mode. TABLE 14-4: AUXILIARY OUTPUT AUXOUT[1:0] CCSEL MOD[3:0] Comments Signal Description 00 x xxxx Auxiliary Output Disabled No Output 01 0 0000 Time Base Modes Time Base Period Reset or Rollover

10 Special Event Trigger Output

11 No Output

Output Compare Modes Time Base Period Reset or Rollover

10 Output Compare Event Signal

11 Output Compare Signal

01 1 xxxx Input Capture Modes Time Base Period Reset or Rollover

10 Reflects the Value of the ICDIS bit

11 Input Capture Event Signal

DS30010198B-page 172  2019-2020 Microchip Technology Inc. REGISTER 14-1: CCPxCON1L: CCP x CONTROL 1 LOW REGISTERS R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCPON — CCPSIDL CCPSLP TMRSYNC CLKSEL2 CLKSEL1 CLKSEL0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMRPS1 TMRPS0 T32 CCSEL MOD3 MOD2 MOD1 MOD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CCPON: CCPx Module Enable bit 1 = Module is enabled with an operating mode specified by the MOD[3:0] control bits 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 CCPSIDL: CCPx Stop in Idle Mode Bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 CCPSLP: CCPx Sleep Mode Enable bit 1 = Module continues to operate in Sleep modes 0 = Module does not operate in Sleep modes bit 11 TMRSYNC: Time Base Clock Synchronization bit 1 = Module time base clock is synchronized to the internal system clocks; timing restrictions apply 0 = Module time base clock is not synchronized to the internal system clocks bit 10-8 CLKSEL[2:0]: CCPx Time Base Clock Select bits 111 = TCKIA pin 110 = TCKIB pin 101 = PLL clock 100 = 2x system clock 010 = SOSC clock 001 = Reference clock output 000 = System clock For MCCP1 and MCCP5: 011 = CLC1 output For MCCP2: 011 = CLC2 output For MCCP3: 011 = CLC3 output For MCCP4: 011 = CLC4 output bit 7-6 TMRPS[1:0]: Time Base Prescale Select bits 11 = 1:64 Prescaler 10 = 1:16 Prescaler 01 = 1:4 Prescaler 00 = 1:1 Prescaler Note 1: Available only on the MCCP1 module.

 2019-2020 Microchip Technology Inc. DS30010198B-page 173 PIC24FJ128GL306 FAMILY bit 5 T32: 32-Bit Time Base Select bit 1 = Uses 32-bit time base for timer, single edge output compare or input capture function 0 = Uses 16-bit time base for timer, single edge output compare or input capture function bit 4 CCSEL: Capture/Compare Mode Select bit 1 = Input capture peripheral 0 = Output compare/PWM/timer peripheral (exact function is selected by the MOD[3:0] bits) bit 3-0 MOD[3:0]: CCPx Mode Select bits For CCSEL = 1 (Input Capture modes): 1xxx = Reserved 011x = Reserved 0101 = Capture every 16th rising edge 0100 = Capture every 4th rising edge 0011 = Capture every rising and falling edge 0010 = Capture every falling edge 0001 = Capture every rising edge 0000 = Capture every rising and falling edge (Edge Detect mode) For CCSEL = 0 (Output Compare/Timer modes): 1111 = External Input mode: Pulse generator is disabled, source is selected by ICS[2:0] 1110 = Reserved 110x = Reserved 10xx = Reserved 0111 = Variable Frequency Pulse mode(1) 0110 = Center-Aligned Pulse Compare mode, buffered(1) 0101 = Dual Edge Compare mode, buffered 0100 = Dual Edge Compare mode 0011 = 16-Bit/32-Bit Single Edge mode, toggles output on compare match 0010 = 16-Bit/32-Bit Single Edge mode, drives output low on compare match 0001 = 16-Bit/32-Bit Single Edge mode, drives output high on compare match 0000 = 16-Bit/32-Bit Timer mode, output functions are disabled REGISTER 14-1: CCPxCON1L: CCPx CONT ROL 1 LOW REGISTERS (CONTINUED) Note 1: Available only on the MCCP1 module.

DS30010198B-page 174  2019-2020 Microchip Technology Inc. REGISTER 14-2: CCPxCON1H: CCPx CONTROL 1 HIGH REGISTERS R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 OPSSRC(1) RTRGEN(2) — — OPS3 (3) OPS2(3) OPS1(3) OPS0(3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRIGEN ONESHOT ALTSYNC SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 OPSSRC: Output Postscaler Source Select bit(1) 1 = Output postscaler scales module trigger output events 0 = Output postscaler scales time base interrupt events bit 14 RTRGEN: Retrigger Enable bit(2) 1 = Time base can be retriggered when the TRIGEN bit = 1 0 = Time base may not be retriggered when the TRIGEN bit = 1 bit 13-12 Unimplemented: Read as ‘0’ bit 11-8 OPS3[3:0]: CCPx Interrupt Output Postscale Select bits(3) 1111 = Interrupt every 16th time base period match 1110 = Interrupt every 15th time base period match ... 0100 = Interrupt every 5th time base period match 0011 = Interrupt every 4th time base period match or 4th input capture event 0010 = Interrupt every 3rd time base period match or 3rd input capture event 0001 = Interrupt every 2nd time base period match or 2nd input capture event 0000 = Interrupt after each time base period match or input capture event bit 7 TRIGEN: CCPx Trigger Enable bit 1 = Trigger operation of time base is enabled 0 = Trigger operation of time base is disabled bit 6 ONESHOT: One-Shot Mode Enable bit 1 = One-Shot Trigger mode is enabled; Trigger mode duration is set by the OSCNT[2:0] bits 0 = One-Shot Trigger mode is disabled bit 5 ALTSYNC: CCPx Clock Select bit 1 = An alternate signal is used as the module synchronization output signal 0 = The module synchronization output signal is the Time Base Reset/rollover event bit 4-0 SYNC[4:0]: CCPx Synchronization Source Select bits See Table 14-5 for the definition of inputs. Note 1: This control bit has no function in Input Capture modes. 2: This control bit has no function when TRIGEN = 0. 3: Output postscale settings, from 1:5 to 1:16 (0100-1111), will result in a FIFO buffer overflow for Input Capture modes.

 2019-2020 Microchip Technology Inc. DS30010198B-page 175 PIC24FJ128GL306 FAMILY TABLE 14-5: SYNCHRONIZATION SOURCES SYNC[4:0] Synchronization Source

11111 None; Timer with Rollover on CCPxPR Match or FFFFh

11110 Reserved

11101 Reserved

11100 Reserved

11011 A/D Start Conversion

11010 CMP3 Trigger

11001 CMP2 Trigger

11000 CMP1 Trigger

10111 Reserved

10110 Reserved

10101 Reserved

10100 Reserved

10011 CLC4 Out

10010 CLC3 Out

10001 CLC2 Out

10000 CLC1 Out

01111 Reserved

01110 Reserved

01101 Reserved

01100 Reserved

01011 INT2 Pad

01010 INT1 Pad

01001 INT0 Pad

01000 Reserved

00111 Reserved

00110 MCCP5 Sync Out

00101 MCCP4 Sync Out

00100 MCCP3 Sync Out

00011 MCCP2 Sync Out

00010 MCCP1 Sync Out

00001 MCCPx Sync Out(1)

00000 MCCPx Timer Sync Out(1)

Note 1: CCP1 when connected to CCP1, CCP2 when connected to CCP2, etc.

DS30010198B-page 176  2019-2020 Microchip Technology Inc. REGISTER 14-3: CCPxCON2L: CCP x CONTROL 2 LOW REGISTERS R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 PWMRSEN ASDGM — SSDG — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ASDG7 ASDG6 ASDG5 ASDG4 ASDG3 ASDG2 ASDG1 ASDG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWMRSEN: CCPx PWM Restart Enable bit 1 = ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input has ended 0 = ASEVT bit must be cleared in software to resume PWM activity on output pins bit 14 ASDGM: CCPx Auto-Shutdown Gate Mode Enable bit 1 = Waits until the next Time Base Reset or rollover for shutdown to occur 0 = Shutdown event occurs immediately bit 13 Unimplemented: Read as ‘0’ bit 12 SSDG: CCPx Software Shutdown/Gate Control bit 1 = Manually forces auto-shutdown, timer clock gate or input capture signal gate event (setting of ASDGM bit still applies) 0 = Normal module operation bit 11-8 Unimplemented: Read as ‘0’ bit 7-0 ASDG[7:0]: CCPx Auto-Shutdown/Gating Source Enable bits 1 = ASDGx Source n is enabled (see Table 14-6 for auto-shutdown/gating sources) 0 = ASDGx Source n is disabled TABLE 14-6: AUTO-SHUTDOWN SOURCES ASDG[7:0] Auto-Shutdown Source MCCP1 MCCP2 MCCP3 MCCP4 MCCP5 1xxx xxxx OCFB x1xx xxxx OCFA xx1x xxxx CLC1 CLC2 CLC3 CLC4 CLC1 xxx1 xxxx MCCP2 OCM Out MCCP1 OCM Out MCCP1 OCM Out MCCP1 OCM Out MCCP1 OCM Out xxxx 1xxx MCCP3 OCM Out MCCP3 OCM Out MCCP4 OCM Out MCCP5 OCM Out MCCP2 OCM Out xxxx x1xx CMP3 Out xxxx xx1x CMP2 Out xxxx xxx1 CMP1 Out

 2019-2020 Microchip Technology Inc. DS30010198B-page 177 PIC24FJ128GL306 FAMILY REGISTER 14-4: CCPxCON2H: CCPx CONTROL 2 HIGH REGISTERS R/W-0 U-0 R/W-0 (1) R/W-0(1) R/W-0(1) R/W-0(1) R/W-0 R/W-1 OENSYNC — OCFEN OCEEN OCDEN OCCEN OCBEN OCAEN bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ICGSM1 ICGSM0 — AUXOUT1 AUXOUT0 ICS2 ICS1 ICS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 OENSYNC: Output Enable Synchronization bit 1 = Update by output enable bits occurs on the next Time Base Reset or rollover 0 = Update by output enable bits occurs immediately bit 14 Unimplemented: Read as ‘0’ bit 13-8 OC[F:A]EN: Output Enable/Steering Control bits(1) 1 = OCMnx pin is controlled by the CCPx module and produces an output compare or PWM signal 0 = OCMnx pin is not controlled by the CCPx module; the pin is available to the port logic or another peripheral multiplexed on the pin bit 7-6 ICGSM[1:0]: Input Capture Gating Source Mode Control bits 11 = Reserved 10 = One-Shot mode: Falling edge from gating source disables future capture events (ICDIS = 1) 01 = One-Shot mode: Rising edge from gating source enables future capture events (ICDIS = 0) 00 = Level-Sensitive mode: A high level from gating source will enable future capture events; a low level will disable future capture events bit 5 Unimplemented: Read as ‘0’ bit 4-3 AUXOUT[1:0]: Auxiliary Output Signal on Event Selection bits 11 = Input capture or output compare event; no signal in Timer mode 10 = Signal output is defined by module operating mode (see Table 14-4) 01 = Time base rollover event (all modes) 00 =D i s a b l e d bit 2-0 ICS[2:0]: Input Capture Source Select bits 111 = CLC4 output 110 = CLC3 output 101 = CLC2 output 100 = CLC1 output 011 = Comparator 3 output 010 = Comparator 2 output 001 = Comparator 1 output 000 = Input Capture x (ICMx) I/O pin Note 1: The OC[F:C]EN bits are available only on the MCCP1 module.

DS30010198B-page 178  2019-2020 Microchip Technology Inc. REGISTER 14-5: CCPxCON3L: CCP x CONTROL 3 LOW REGISTERS U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — —D T [ 5 : 0 ] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 DT[5:0]: CCPx Dead-Time Select bits 111111 = Inserts 63 dead-time delay periods between complementary output signals 111110 = Inserts 62 dead-time delay periods between complementary output signals ... 000010 = Inserts 2 dead-time delay periods between complementary output signals 000001 = Inserts 1 dead-time delay period between complementary output signals 000000 = Dead-time logic is disabled

 2019-2020 Microchip Technology Inc. DS30010198B-page 179 PIC24FJ128GL306 FAMILY REGISTER 14-6: CCPxCON3H: CCPx CONTROL 3 HIGH REGISTERS R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 OETRIG OSCNT2 OSCNT1 OSCNT0 —O U T M 2 O U T M 1 O U T M 0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — POLACE POLBDF PSSACE1 PSSACE0 PSSBDF1 PSSBDF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 OETRIG: CCPx Dead-Time Select bit 1 = For Triggered mode (TRIGEN = 1): Module does not drive enabled output pins until triggered 0 = Normal output pin operation bit 14-12 OSCNT[2:0]: One-Shot Event Count bits 111 = Extends one-shot event by 7 time base periods (8 time base periods total) 110 = Extends one-shot event by 6 time base periods (7 time base periods total) 101 = Extends one-shot event by 5 time base periods (6 time base periods total) 100 = Extends one-shot event by 4 time base periods (5 time base periods total) 011 = Extends one-shot event by 3 time base periods (4 time base periods total) 010 = Extends one-shot event by 2 time base periods (3 time base periods total) 001 = Extends one-shot event by 1 time base period (2 time base periods total) 000 = Does not extend one-shot trigger event bit 11 Unimplemented: Read as ‘0’ bit 10-8 OUTM[2:0]: PWMx Output Mode Control bits 111 = Reserved 110 = Output Scan mode 101 = Brush DC Output mode, forward 100 = Brush DC Output mode, reverse 011 = Reserved 010 = Half-Bridge Output mode 001 = Push-Pull Output mode 000 = Steerable Single Output mode bit 7-6 Unimplemented: Read as ‘0’ bit 5 POLACE: CCPx Output Pins, OCMxA, OCMxC and OCMxE, Polarity Control bit 1 = Output pin polarity is active-low 0 = Output pin polarity is active-high bit 4 POLBDF: CCPx Output Pins, OCMxB, OCMxD and OCMxF, Polarity Control bit 1 = Output pin polarity is active-low 0 = Output pin polarity is active-high bit 3-2 PSSACE[1:0]: PWMx Output Pins, OCMxA, OCMxC and OCMxE, Shutdown State Control bits 11 = Pins are driven active when a shutdown event occurs 10 = Pins are driven inactive when a shutdown event occurs 0x = Pins are tri-stated when a shutdown event occurs bit 1-0 PSSBDF[1:0]: PWMx Output Pins, OCMxB, OCMxD, and OCMxF, Shutdown State Control bits 11 = Pins are driven active when a shutdown event occurs 10 = Pins are driven inactive when a shutdown event occurs 0x = Pins are in a high-impedance state when a shutdown event occurs

DS30010198B-page 180  2019-2020 Microchip Technology Inc. REGISTER 14-7: CCPxSTATL: CCPx STATUS REGISTER LOW U-0 U-0 U-0 U-0 U-0 W-0 U-0 U-0 bit 15 bit 8 R-0 W1-0 W1-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 CCPTRIG TRSET TRCLR ASEVT SCEVT ICDIS ICOV ICBNE bit 7 bit 0 Legend: C = Clearable bit W = Writable bit R = Readable bit W1 = Write ‘1’ Only bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 ICGARM: Input Capture Gate Arm bit A write of ‘1’ to this location will arm the Input Capture x module for a one-shot gating event when ICGSM[1:0] = 01 or 10; read as ‘0’. bit 9-8 Unimplemented: Read as ‘0’ bit 7 CCPTRIG: CCPx Trigger Status bit 1 = Timer has been triggered and is running 0 = Timer has not been triggered and is held in Reset bit 6 TRSET: CCPx Trigger Set Request bit Writes ‘1’ to this location to trigger the timer when TRIGEN = 1 (location always reads as ‘0’). bit 5 TRCLR: CCPx Trigger Clear Request bit Writes ‘1’ to this location to cancel the timer trigger when TRIGEN = 1 (location always reads as ‘0’). bit 4 ASEVT: CCPx Auto-Shutdown Event Status/Control bit 1 = A shutdown event is in progress; CCPx outputs are in the Shutdown state 0 = CCPx outputs operate normally bit 3 SCEVT: Single Edge Compare Event Status bit 1 = A single edge compare event has occurred 0 = A single edge compare event has not occurred bit 2 ICDIS: Input Capture x Disable bit 1 = Event on Input Capture x pin (ICMx) does not generate a capture event 0 = Event on Input Capture x pin will generate a capture event bit 1 ICOV: Input Capture x Buffer Overflow Status bit 1 = The Input Capture x FIFO buffer has overflowed 0 = The Input Capture x FIFO buffer has not overflowed bit 0 ICBNE: Input Capture x Buffer Status bit 1 = Input Capture x buffer has data available 0 = Input Capture x buffer is empty

 2019-2020 Microchip Technology Inc. DS30010198B-page 181 PIC24FJ128GL306 FAMILY

15.0 SERIAL PERIPHERAL

INTERFACE (SPI) The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D Converters, etc. The SPI module is compatible with the Motorola ® SPI and SIOP interfaces. All devices in the PIC24FJ128GL306 family include two SPI modules. The module supports operation in two buffer modes. In Standard Buffer mode, datum is shifted through a single serial buffer. In Enhanced Buffer mode, data are shifted through a FIFO buffer. The FIFO level depends on the configured mode. Variable length data can be transmitted and received from 2 to 32 bits. The module also supports a basic framed SPI protocol while operating in either Master or Slave mode. A total of four framed SPI configurations are supported. The module also supports Audio modes. Four different Audio modes are available. 2S mode

• Left Justified mode
• Right Justified mode
• P C M / D S P m o d e In each of these modes, the serial clock is free-running and audio data are always transferred. If an audio protocol data transfer takes place between two devices, then usually one device is the Master and the other is the Slave. However, audio data can be transferred between two Slaves. Because the audio protocols require free-running clocks, the Master can be a third party controller. In either case, the Master generates two free-running clocks: SCKx and LRC (Left, Right Channel Clock/SSx /FSYNC). The SPI serial interface consists of four pins:
• SDIx: Serial Data Input
• SDOx: Serial Data Output
• SCKx: Shift Clock Input or Output
• SSx : Active-Low Slave Select or Frame Synchronization I/O Pulse The SPI module can be configured to operate using two, three or four pins. In the 3-pin mode, SSx is not used. In the 2-pin mode, both SDOx and SSx are not used. The SPI module has the ability to generate three inter- rupts reflecting the events that occur during the data communication. The following types of interrupts can be generated: 1. Receive interrupts are signalled by SPIxRXIF. This event occurs when: - RX watermark interrupt - SPIROV = 1 - SPIRBF = 1 - SPIRBE = 1 provided the respective mask bits are enabled in SPIxIMSKL/H. 2. Transmit interrupts are signalled by SPIxTXIF. This event occurs when: - TX watermark interrupt - SPITUR = 1 - SPITBF = 1 - SPITBE = 1 provided the respective mask bits are enabled in SPIxIMSKL/H. 3. General interrupts are signalled by SPIxIF. This event occurs when - FRMERR = 1 - SPIBUSY = 1 -S R M T = 1 provided the respective mask bits are enabled in SPIxIMSKL/H. A block diagram of the module in Enhanced Buffer mode is shown in Figure 15-1. Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive reference source. To complement the infor- mation in this data sheet, refer to “Serial Peripheral Interface (SPI) with Audio Codec Support” ( www.microchip.com/ DS70005136) in the “dsPIC33/PIC24 Family Reference Manual”. The informa- tion in this data sheet supersedes the information in the FRM. Note: FIFO depth for this device is 32 (in 8-Bit Data mode). Note: Do not perform Read-Modify-Write opera- tions (such as bit-oriented instructions) on the SPIxBUF register in either Standard or Enhanced Buffer mode. Note: In this section, the SPI modules are referred to together as SPIx, or separately as SPI1 or SPI2. Special Function Regis- ters will follow a similar notation. For example, SPIxCON1 and SPIxCON2 refer to the control registers for either of the two SPI modules.

DS30010198B-page 182  2019-2020 Microchip Technology Inc.

15.1 Master Mode Operation

Perform the following steps to set up the SPIx module for Master mode operation: 1. Disable the SPIx interrupts in the respective IECx register. 2. Stop and reset the SPIx module by clearing the SPIEN bit. 3. Clear the receive buffer. 4. Clear the ENHBUF bit (SPIxCON1L[0]) if using Standard Buffer mode or set the bit if using Enhanced Buffer mode. 5. If SPIx interrupts are not going to be used, skip this step. Otherwise, the following additional steps are performed: a) Clear the SPIx interrupt flags/events in the respective IFSx register. b) Write the SPIx interrupt priority and sub-priority bits in the respective IPCx register. c) Set the SPIx interrupt enable bits in the respective IECx register. 6. Write the Baud Rate register, SPIxBRGL. 7. Clear the SPIROV bit (SPIxSTATL[6]). 8. Write the desired settings to the SPIxCON1L register with MSTEN (SPIxCON1L[5]) = 1. 9. Enable SPI operation by setting the SPIEN bit (SPIxCON1L[15]). 10. Write the data to be transmitted to the SPIxBUFL and SPIxBUFH registers. Transmis- sion (and reception) will start as soon as data are written to the SPIxBUFL/H registers.

15.2 Slave Mode Operation

The following steps are used to set up the SPIx module for the Slave mode of operation: 1. If using interrupts, disable the SPIx interrupts in the respective IECx register. 2. Stop and reset the SPIx module by clearing the SPIEN bit. 3. Clear the receive buffer. 4. Clear the ENHBUF bit (SPIxCON1L[0]) if using Standard Buffer mode or set the bit if using Enhanced Buffer mode. 5. If using interrupts, the following additional steps are performed: a) Clear the SPIx interrupt flags/events in the respective IFSx register. b) Write the SPIx interrupt priority and sub-priority bits in the respective IPCx register. c) Set the SPIx interrupt enable bits in the respective IECx register. 6. Clear the SPIROV bit (SPIxSTATL[6]). 7. Write the desired settings to the SPIxCON1L register with MSTEN (SPIxCON1L[5]) = 0. 8. Enable SPI operation by setting the SPIEN bit (SPIxCON1L[15]). 9. Transmission (and reception) will start as soon as the Master provides the serial clock. The following additional features are provided in Slave mode:

• Slave Select Synchronization: The SSx pin allows a Synchronous Slave mode. If the SSEN bit (SPIxCON1L[7]) is set, transmission and reception are enabled in Slave mode only if the SSx pin is driven to a low state. The port out- put or other peripheral outputs must not be driven in order to allow the SSx pin to function as an input. If the SSEN bit is set and the SSx pin is driven high, the SDOx pin is no longer driven and will tri-state, even if the module is in the middle of a transmission. An aborted transmission will be tried again the next time the SSx pin is driven low using the data held in the SPIxTXB register. If the SSEN bit is not set, the SSx pin does not affect the module operation in Slave mode.
• SPITBE Status Flag Operation: The SPITBE bit (SPIxSTATL[3]) has a different function in the Slave mode of operation. The following describes the function of SPITBE for various settings of the Slave mode of operation: - If SSEN (SPIxCON1L[7]) is cleared, the SPITBE bit is cleared when SPIxBUF is loaded by the user code. It is set when the module transfers SPIxTXB to SPIxTXSR. This is similar to the SPITBE bit function in Master mode. - If SSEN is set, SPITBE is cleared when SPIxBUF is loaded by the user code. How- ever, it is set only when the SPIx module completes data transmission. A transmission will be aborted when the SSx pin goes high and may be retried at a later time. So, each data word is held in SPIxTXB until all bits are transmitted to the receiver.

 2019-2020 Microchip Technology Inc. DS30010198B-page 183 PIC24FJ128GL306 FAMILY FIGURE 15-1: SPIx MODULE BL OCK DIAGRAM (ENHANCED MODE)

15.3 Audio Mode Operation

To initialize the SPIx module for Audio mode, follow the steps to initialize it for Master/Slave mode, but also set the AUDEN bit (SPIxCON1H[15]). In Master+Audio mode:

• This mode enables the device to generate SCKx and LRC pulses as long as the SPIEN bit (SPIxCON1L[15]) = 1.
• The SPIx module generates LRC and SCKx continuously, in all cases, regardless of the transmit data while in Master mode.
• The SPIx module drives the leading edge of LRC and SCKx within one SCKx period, and the serial data shift in and out continuously, even when the TX FIFO is empty. In Slave+Audio mode:
• This mode enables the device to receive SCKx and LRC pulses as long as the SPIEN bit (SPIxCON1L[15]) = 1.
• The SPIx module drives zeros out of SDOx, but does not shift data out or in (SDIx) until the module receives the LRC (i.e., the edge that precedes the left channel).
• Once the module receives the leading edge of LRC, it starts receiving data if DISSDI (SPIxCON1L[4]) = 0 and the serial data shift out continuously, even when the TX FIFO is empty. Read Write Internal Data Bus SDIx SDOx SSx/FSYNC SCKx MSB Shift Control Edge Select Enable Master Clock Transmit Peripheral Clock MCLKEN SPIxRXSR URDTEN TXELM[5:0] = 6’b0 MSB Baud Rate Generator SSx and FSYNC Control Clock Control SPIxTXSR Clock Control Receive SPIxURDTSPIxTXB Edge Select SPIxRXB REFO

DS30010198B-page 184  2019-2020 Microchip Technology Inc.

15.4 SPI Control Registers

REGISTER 15-1: SPIxCON1L: SP Ix CONTROL REGISTER 1 LOW R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPIEN — SPISIDL DISSDO MODE32 (1,4) MODE16(1,4) SMP CKE (1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN(2) CKP MSTEN DISSDI DISSCK MCLKEN (3) SPIFE ENHBUF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx On bit 1 = Enables module 0 = Turns off and resets module, disables clocks, disables interrupt event generation, allows SFR modifications bit 14 Unimplemented: Read as ‘0’ bit 13 SPISIDL: SPIx Stop in Idle Mode bit 1 = Halts in CPU Idle mode 0 = Continues to operate in CPU Idle mode bit 12 DISSDO: Disable SDOx Output Port bit 1 = SDOx pin is not used by the module; pin is controlled by the port function 0 = SDOx pin is controlled by the module bit 11-10 MODE[32,16]: Serial Word Length bits(1,4) AUDEN = 0: MODE32 MODE16 COMMUNICATION FIFO DEPTH 1x 32-Bit 8 01 16-Bit 16 00 8-Bit 32 AUDEN = 1: MODE32 MODE16 COMMUNICATION 11 24-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame 10 32-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame 01 16-Bit Data, 16-Bit FIFO, 32-Bit Channel/64-Bit Frame 00 16-Bit Data, 16-Bit FIFO, 16-Bit Channel/32-Bit Frame bit 9 SMP: SPIx Data Input Sample Phase bit Master Mode: 1 = Input datum is sampled at the end of data output time 0 = Input datum is sampled at the middle of data output time Slave Mode: Input datum is always sampled at the middle of data output time, regardless of the SMP setting. Note 1: When AUDEN = 1, this module functions as if CKE = 0, regardless of its actual value. 2: When FRMEN = 1, SSEN is not used. 3: MCLKEN can only be written when the SPIEN bit = 0. 4: This channel is not meaningful for DSP/PCM mode as LRC follows the FRMSYPW bit.

 2019-2020 Microchip Technology Inc. DS30010198B-page 185 PIC24FJ128GL306 FAMILY bit 8 CKE: SPIx Clock Edge Select bit(1) 1 = Transmit happens on transition from active clock state to Idle clock state 0 = Transmit happens on transition from Idle clock state to active clock state bit 7 SSEN: Slave Select Enable bit (Slave mode)(2) 1 = SSx pin is used by the macro in Slave mode; SSx pin is used as the Slave select input 0 = SSx pin is not used by the macro (SSx pin will be controlled by the port I/O) bit 6 CKP: SPIx Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode bit 4 DISSDI: Disable SDIx Input Port bit 1 = SDIx pin is not used by the module; pin is controlled by the port function 0 = SDIx pin is controlled by the module bit 3 DISSCK: Disable SCKx Output Port bit 1 = SCKx pin is not used by the module; pin is controlled by the port function 0 = SCKx pin is controlled by the module bit 2 MCLKEN: Master Clock Enable bit(3) 1 = REFO is used by the BRG 0 = Peripheral clock is used by the BRG bit 1 SPIFE: Frame Sync Pulse Edge Select bit 1 = Frame Sync pulse (Idle-to-active edge) coincides with the first bit clock 0 = Frame Sync pulse (Idle-to-active edge) precedes the first bit clock bit 0 ENHBUF: Enhanced Buffer Mode Enable bit 1 = Enhanced Buffer mode is enabled 0 = Enhanced Buffer mode is disabled REGISTER 15-1: SPIxCON1L: SPIx CO NTROL REGISTER 1 LOW (CONTINUED) Note 1: When AUDEN = 1, this module functions as if CKE = 0, regardless of its actual value. 2: When FRMEN = 1, SSEN is not used. 3: MCLKEN can only be written when the SPIEN bit = 0. 4: This channel is not meaningful for DSP/PCM mode as LRC follows the FRMSYPW bit.

DS30010198B-page 186  2019-2020 Microchip Technology Inc. REGISTER 15-2: SPIxCON1H: SPIx CONTROL REGISTER 1 HIGH R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AUDEN(1) SPISGNEXT IGNROV IGNTUR AUDMONO (2) URDTEN(3) AUDMOD1(4) AUDMOD0(4) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT2 FRMCNT1 FRMCNT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 AUDEN: Audio Codec Support Enable bit(1) 1 = Audio protocol is enabled; MSTEN controls the direction of both the SCKx and frame (a.k.a. LRC), and this module functions as if FRMEN = 1, FRMSYNC = MSTEN, FRMCNT[2:0] = 001 and SMP = 0, regardless of their actual values 0 = Audio protocol is disabled bit 14 SPISGNEXT: SPIx Sign-Extend RX FIFO Read Data Enable bit 1 = Data from RX FIFO are sign-extended 0 = Data from RX FIFO are not sign-extended bit 13 IGNROV: Ignore Receive Overflow bit 1 = A Receive Overflow (ROV) is NOT a critical error; during ROV, data in the FIFO are not overwritten by the receive data 0 = A ROV is a critical error that stops SPI operation bit 12 IGNTUR: Ignore Transmit Underrun bit 1 = A Transmit Underrun (TUR) is NOT a critical error and data indicated by URDTEN are transmitted until the SPIxTXB is not empty 0 = A TUR is a critical error that stops SPI operation bit 11 AUDMONO: Audio Data Format Transmit bit(2) 1 = Audio data are mono (i.e., each data word is transmitted on both left and right channels) 0 = Audio data are stereo bit 10 URDTEN: Transmit Underrun Data Enable bit(3) 1 = Transmits data out of the SPIxURDTL/H registers during Transmit Underrun conditions 0 = Transmits the last received data during Transmit Underrun conditions bit 9-8 AUDMOD[1:0]: Audio Protocol Mode Selection bits(4) 11 = PCM/DSP mode 10 = Right Justified mode: This module functions as if SPIFE = 1, regardless of its actual value 01 = Left Justified mode: This module functions as if SPIFE = 1, regardless of its actual value 00 = I2S mode: This module functions as if SPIFE = 0, regardless of its actual value bit 7 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support is enabled (SSx pin is used as the FSYNC input/output) 0 = Framed SPIx support is disabled Note 1: AUDEN can only be written when the SPIEN bit = 0. 2: AUDMONO can only be written when the SPIEN bit = 0 and is only valid for AUDEN = 1. 3: URDTEN is only valid when IGNTUR = 1. 4: AUDMOD[1:0] bits can only be written when the SPIEN bit =0 and are only valid when AUDEN =1. When NOT in PCM/DSP mode, this module functions as if FRMSYPW = 1, regardless of its actual value.

 2019-2020 Microchip Technology Inc. DS30010198B-page 187 PIC24FJ128GL306 FAMILY bit 6 FRMSYNC: Frame Sync Pulse Direction Control bit 1 = Frame Sync pulse input (Slave) 0 = Frame Sync pulse output (Master) bit 5 FRMPOL: Frame Sync/Slave Select Polarity bit 1 = Frame Sync pulse/Slave select is active-high 0 = Frame Sync pulse/Slave select is active-low bit 4 MSSEN: Master Mode Slave Select Enable bit 1 = SPIx Slave select support is enabled with polarity determined by FRMPOL (SSx pin is automatically driven during transmission in Master mode) 0 = SPIx Slave select support is disabled (SSx pin will be controlled by port I/O) bit 3 FRMSYPW: Frame Sync Pulse-Width bit 1 = Frame Sync pulse is one serial word length wide (as defined by MODE[32,16]/WLENGTH[4:0]) 0 = Frame Sync pulse is one clock (SCKx) wide bit 2-0 FRMCNT[2:0]: Frame Sync Pulse Counter bits Controls the number of serial words transmitted per Sync pulse. 111 = Reserved 110 = Reserved 101 = Generates a Frame Sync pulse on every 32 serial words 100 = Generates a Frame Sync pulse on every 16 serial words 011 = Generates a Frame Sync pulse on every 8 serial words 010 = Generates a Frame Sync pulse on every 4 serial words 001 = Generates a Frame Sync pulse on every 2 serial words (value used by audio protocols) 000 = Generates a Frame Sync pulse on each serial word REGISTER 15-2: SPIxCON1H: SPIx CONTROL REGISTER 1 HIGH (CONTINUED) Note 1: AUDEN can only be written when the SPIEN bit = 0. 2: AUDMONO can only be written when the SPIEN bit = 0 and is only valid for AUDEN = 1. 3: URDTEN is only valid when IGNTUR = 1. 4: AUDMOD[1:0] bits can only be written when the SPIEN bit =0 and are only valid when AUDEN =1. When NOT in PCM/DSP mode, this module functions as if FRMSYPW = 1, regardless of its actual value.

DS30010198B-page 188  2019-2020 Microchip Technology Inc. REGISTER 15-3: SPIxCON2L: SP Ix CONTROL REGISTER 2 LOW U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — WLENGTH[4:0] (1,2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 WLENGTH[4:0]: Variable Word Length bits(1,2) 11111 = 32-bit data 11110 = 31-bit data 11101 = 30-bit data 11100 = 29-bit data 11011 = 28-bit data 11010 = 27-bit data 11001 = 26-bit data 11000 = 25-bit data 10111 = 24-bit data 10110 = 23-bit data 10101 = 22-bit data 10100 = 21-bit data 10011 = 20-bit data 10010 = 19-bit data 10001 = 18-bit data 10000 = 17-bit data 01111 = 16-bit data 01110 = 15-bit data 01101 = 14-bit data 01100 = 13-bit data 01011 = 12-bit data 01010 = 11-bit data 01001 = 10-bit data 01000 = 9-bit data 00111 = 8-bit data 00110 = 7-bit data 00101 = 6-bit data 00100 = 5-bit data 00011 = 4-bit data 00010 = 3-bit data 00001 = 2-bit data 00000 = See MODE[32,16] bits in SPIxCON1L[11:10] Note 1: These bits are effective when AUDEN = 0 only. 2: Varying the length by changing these bits does not affect the depth of the TX/RX FIFO.

 2019-2020 Microchip Technology Inc. DS30010198B-page 189 PIC24FJ128GL306 FAMILY REGISTER 15-4: SPIxSTATL: SPIx STATUS REGISTER LOW U-0 U-0 U-0 HS/R/C-0 HSC/R-0 U-0 U-0 HSC/R-0 — — — FRMERR SPIBUSY — — SPITUR (1) bit 15 bit 8 HSC/R-0 HS/R/C-0 HSC/R-1 U-0 HSC/R-1 U-0 HSC/R-0 HSC/R-0 SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit x = Bit is unknown R = Readable bit W = Writable bit ‘0’ = Bit is cleared HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ bit 15-13 Unimplemented: Read as ‘0’ bit 12 FRMERR: SPIx Frame Error Status bit 1 = Frame error is detected 0 = No frame error is detected bit 11 SPIBUSY: SPIx Activity Status bit 1 = Module is currently busy with some transactions 0 = No ongoing transactions (at time of read) bit 10-9 Unimplemented: Read as ‘0’ bit 8 SPITUR: SPIx Transmit Underrun Status bit(1) 1 = Transmit buffer has encountered a Transmit Underrun (TUR) condition 0 = Transmit buffer does not have a Transmit Underrun condition bit 7 SRMT: Shift Register Empty Status bit 1 = No current or pending transactions (i.e., neither SPIxTXB or SPIxTXSR contains data to transmit) 0 = Current or pending transactions bit 6 SPIROV: SPIx Receive Overflow Status bit 1 = A new byte/half-word/word has been completely received when the SPIxRXB is full 0 = No overflow bit 5 SPIRBE: SPIx RX Buffer Empty Status bit 1 = RX buffer is empty 0 = RX buffer is not empty Standard Buffer Mode: Automatically set in hardware when SPIxBUF is read from, reading SPIxRXB. Automatically cleared in hardware when SPIx transfers data from SPIxRXSR to SPIxRXB. Enhanced Buffer Mode: Indicates RXELM[5:0] = 6’b000000. bit 4 Unimplemented: Read as ‘0’ bit 3 SPITBE: SPIx Transmit Buffer Empty Status bit 1 = SPIxTXB is empty 0 = SPIxTXB is not empty Standard Buffer Mode: Automatically set in hardware when SPIx transfers data from SPIxTXB to SPIxTXSR. Automatically cleared in hardware when SPIxBUF is written, loading SPIxTXB. Enhanced Buffer Mode: Indicates TXELM[5:0] = 6’b000000. Note 1: SPITUR is cleared when SPIEN = 0. When IGNTUR = 1, SPITUR provides dynamic status of the Transmit Underrun condition, but does not stop RX/TX operation and does not need to be cleared by software.

DS30010198B-page 190  2019-2020 Microchip Technology Inc. bit 2 Unimplemented: Read as ‘0’ bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = SPIxTXB is full 0 = SPIxTXB not full Standard Buffer Mode: Automatically set in hardware when SPIxBUF is written, loading SPIxTXB. Automatically cleared in hardware when SPIx transfers data from SPIxTXB to SPIxTXSR. Enhanced Buffer Mode: Indicates TXELM[5:0] = 6’b111111. bit 0 SPIRBF: SPIx Receive Buffer Full Status bit 1 = SPIxRXB is full 0 = SPIxRXB is not full Standard Buffer Mode: Automatically set in hardware when SPIx transfer s data from SPIxRXSR to SPIxRXB. Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB. Enhanced Buffer Mode: Indicates RXELM[5:0] = 6’b111111. REGISTER 15-4: SPIxSTATL: SPIx STATUS REGISTER LOW (CONTINUED) Note 1: SPITUR is cleared when SPIEN = 0. When IGNTUR = 1, SPITUR provides dynamic status of the Transmit Underrun condition, but does not stop RX/TX operation and does not need to be cleared by software.

 2019-2020 Microchip Technology Inc. DS30010198B-page 191 PIC24FJ128GL306 FAMILY REGISTER 15-5: SPIxSTATH: SPIx STATUS REGISTER HIGH (4) U-0 U-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 — —R X E L M 5 (3) RXELM4(2) RXELM3(1) RXELM2 RXELM1 RXELM0 bit 15 bit 8 U-0 U-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 — — TXELM5 (3) TXELM4(2) TXELM3(1) TXELM2 TXELM1 TXELM0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RXELM[5:0]: Receive Buffer Element Count bits (valid in Enhanced Buffer mode)(1,2,3) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TXELM[5:0]: Transmit Buffer Element Count bits (valid in Enhanced Buffer mode)(1,2,3) Note 1: RXELM3 and TXELM3 bits are only present when FIFODEPTH = 8 or higher. 2: RXELM4 and TXELM4 bits are only present when FIFODEPTH = 16 or higher. 3: RXELM5 and TXELM5 bits are only present when FIFODEPTH = 32. 4: See the MODE32/16 bits in the SPIxCON1L register.

DS30010198B-page 192  2019-2020 Microchip Technology Inc. REGISTER 15-6: SPIxBUFL: SPIx BUFFER REGISTER LOW R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATA[15:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATA[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 DATA[15:0]: SPIx FIFO Data bits When the MODE[32,16] or WLENGTH[4:0] bits select 16 to 9-bit data, the SPIx only uses DATA[15:0]. When the MODE[32,16] or WLENGTH[4:0] bits select 8 to 2-bit data, the SPIx only uses DATA[7:0]. REGISTER 15-7: SPIxBUFH: SPIx BUFFER REGISTER HIGH R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATA[31:24] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATA[23:16] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 DATA[31:16]: SPIx FIFO Data bits When the MODE[32,16] or WLENGTH[4:0] bits select 32 to 25-bit data, the SPIx uses DATA[31:16]. When the MODE[32,16] or WLENGTH[4:0] bits select 24 to 17-bit data, the SPIx only uses DATA[23:16].

 2019-2020 Microchip Technology Inc. DS30010198B-page 193 PIC24FJ128GL306 FAMILY REGISTER 15-8: SPIxBRGL: SPIx BAUD RATE GENERATOR REGISTER LOW U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BRG7:0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-0 BRG[12:0]: SPIx Baud Rate Generator Divisor bits(1) Note 1: Changing the BRG value when SPIEN = 1 causes undefined behavior.

DS30010198B-page 194  2019-2020 Microchip Technology Inc. REGISTER 15-9: SPIxIMSKL: SPIx INTERRUPT MASK REGISTER LOW U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 — — — FRMERREN BUSYEN — — SPITUREN bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 SRMTEN SPIROVEN SPIRBEN — SPITBEN — SPITBFEN SPIRBFEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 FRMERREN: Enable Interrupt Events via FRMERR bit 1 = Frame error generates an interrupt event 0 = Frame error does not generate an interrupt event bit 11 BUSYEN: Enable Interrupt Events via SPIBUSY bit 1 = SPIBUSY generates an interrupt event 0 = SPIBUSY does not generate an interrupt event bit 10-9 Unimplemented: Read as ‘0’ bit 8 SPITUREN: Enable Interrupt Events via SPITUR bit 1 = Transmit Underrun (TUR) generates an interrupt event 0 = Transmit Underrun does not generate an interrupt event bit 7 SRMTEN: Enable Interrupt Events via SRMT bit 1 = Shift Register Empty (SRMT) generates interrupt events 0 = Shift Register Empty does not generate interrupt events bit 6 SPIROVEN: Enable Interrupt Events via SPIROV bit 1 = SPIx Receive Overflow (ROV) generates an interrupt event 0 = SPIx Receive Overflow does not generate an interrupt event bit 5 SPIRBEN: Enable Interrupt Events via SPIRBE bit 1 = SPIx receive buffer empty generates an interrupt event 0 = SPIx receive buffer empty does not generate an interrupt event bit 4 Unimplemented: Read as ‘0’ bit 3 SPITBEN: Enable Interrupt Events via SPITBE bit 1 = SPIx transmit buffer empty generates an interrupt event 0 = SPIx transmit buffer empty does not generate an interrupt event bit 2 Unimplemented: Read as ‘0’ bit 1 SPITBFEN: Enable Interrupt Events via SPITBF bit 1 = SPIx transmit buffer full generates an interrupt event 0 = SPIx transmit buffer full does not generate an interrupt event bit 0 SPIRBFEN: Enable Interrupt Events via SPIRBF bit 1 = SPIx receive buffer full generates an interrupt event 0 = SPIx receive buffer full does not generate an interrupt event

 2019-2020 Microchip Technology Inc. DS30010198B-page 195 PIC24FJ128GL306 FAMILY REGISTER 15-10: SPIxIMSKH: SPIx INTERRUPT MASK REGISTER HIGH R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXWIEN — RXMSK5 (1) RXMSK4(1,4) RXMSK3(1,3) RXMSK2(1,2) RXMSK1(1) RXMSK0(1) bit 15 bit 8 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXWIEN —T X M S K 5 (1) TXMSK4(1,4) TXMSK3(1,3) TXMSK2(1,2) TXMSK1(1) TXMSK0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 RXWIEN: Receive Watermark Interrupt Enable bit 1 = Triggers receive buffer element watermark interrupt when RXMSK[5:0]  RXELM[5:0] 0 = Disables receive buffer element watermark interrupt bit 14 Unimplemented: Read as ‘0’ bit 13-8 RXMSK[5:0]: RX Buffer Mask bits(1,2,3,4) RX mask bits; used in conjunction with the RXWIEN bit. bit 7 TXWIEN: Transmit Watermark Interrupt Enable bit 1 = Triggers transmit buffer element watermark interrupt when TXMSK[5:0] = TXELM[5:0] 0 = Disables transmit buffer element watermark interrupt bit 6 Unimplemented: Read as ‘0’ bit 5-0 TXMSK[5:0]: TX Buffer Mask bits(1,2,3,4) TX mask bits; used in conjunction with the TXWIEN bit. Note 1: Mask values higher than FIFODEPTH are not valid. The module will not trigger a match for any value in this case. 2: RXMSK2 and TXMSK2 bits are only present when FIFODEPTH = 8 or higher. 3: RXMSK3 and TXMSK3 bits are only present when FIFODEPTH = 16 or higher. 4: RXMSK4 and TXMSK4 bits are only present when FIFODEPTH = 32.

DS30010198B-page 196  2019-2020 Microchip Technology Inc. REGISTER 15-11: SPIxURDTL: SPIx UNDERRUN DATA REGISTER LOW R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 URDATA[15:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 URDATA[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 URDATA[15:0]: SPIx Underrun Data bits These bits are only used when URDTEN = 1. This register holds the data to transmit when a Transmit Underrun condition occurs. When the MODE[32,16] or WLENGTH[4:0] bits select 16 to 9-bit data, the SPIx only uses URDATA[15:0]. When the MODE[32,16] or WLENGTH[4:0] bits select 8 to 2-bit data, the SPIx only uses URDATA[7:0]. REGISTER 15-12: SPIxURDTH: SPIx UNDERRUN DATA REGISTER HIGH R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 URDATA[31:24] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 URDATA[23:16] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 URDATA[31:16]: SPIx Underrun Data bits These bits are only used when URDTEN = 1. This register holds the data to transmit when a Transmit Underrun condition occurs. When the MODE[32,16] or WLENGTH[4:0] bits select 32 to 25-bit data, the SPIx only uses URDATA[31:16]. When the MODE[32,16] or WLENGTH[4:0] bits select 24 to 17-bit data, the SPIx only uses URDATA[23:16].

 2019-2020 Microchip Technology Inc. DS30010198B-page 197 PIC24FJ128GL306 FAMILY FIGURE 15-2: SPIx MASTER/SLA VE CONNECTION (STANDARD MODE) Serial Transmit Buffer (SPIxTXB)(2) Shift Register (SPIxTXSR) LSbMSb SDIx SDOx Processor 2 (SPIx Slave) SCKx SSx(1) Serial Receive Buffer (SPIxRXB)(2) Serial Receive Buffer (SPIxRXB)(2) Shift Register (SPIxRXSR) MSb LSb SDOx SDIx Processor 1 (SPIx Master) Serial Clock MSSEN (SPIxCON1H[4]) = 1 and MSTEN (SPIxCON1L[5]) = 0 Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory-mapped to SPIxBUF. SCKxSerial Transmit Buffer (SPIxTXB)(2) MSTEN (SPIxCON1L[5]) = 1 SPIx Buffer (SPIxBUF) SPIx Buffer (SPIxBUF) Shift Register (SPIxTXSR) Shift Register (SPIxRXSR) MSb LSb LSbMSb SDOx SDIx

DS30010198B-page 198  2019-2020 Microchip Technology Inc. FIGURE 15-3: SPIx MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES) Serial Transmit FIFO (SPIxTXB)(2) Shift Register (SPIxTXSR) LSbMSb SDIx SDOx Processor 2 (SPIx Slave) SCKx SSx(1) Serial Receive FIFO (SPIxRXB)(2) Serial Receive FIFO (SPIxRXB)(2) Shift Register (SPIxRXSR) MSb LSb SDOx SDIx Processor 1 (SPIx Master) Serial Clock MSSEN (SPIxCON1H[4]) = 1 and MSTEN (SPIxCON1L[5]) = 0 SCKxSerial Transmit FIFO (SPIxTXB)(2) MSTEN (SPIxCON1L[5]) = 1 SPIx Buffer (SPIxBUF) SPIx Buffer (SPIxBUF) Shift Register (SPIxTXSR) Shift Register (SPIxRXSR) MSb LSb LSbMSb SDOx SDIx Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User must write transmit data to read the received dat a from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory-mapped to SPIxBUF.

 2019-2020 Microchip Technology Inc. DS30010198B-page 199 PIC24FJ128GL306 FAMILY FIGURE 15-4: SPIx MASTER, FR AME MASTER CONNECTION DIAGRAM PIC24FJ128GL306 Serial Clock SCKx Frame Sync Pulse(1,2) SDIx SDOx Processor 2 SSx SCKx (SPIx Master, Frame Master) Serial Receive Buffer (SPIxRXB)(3) Shift Register (SPIxRXSR) Shift Register (SPIxTXSR) Serial Transmit Buffer (SPIxTXB)(3) (SPIxBUF) SPI Buffer Serial Receive Buffer (SPIxTXB)(3) Shift Register (SPIxRXSR) Shift Register (SPIxTXSR) Serial Transmit Buffer (SPIxTXB)(3) (SPIxBUF) SPI Buffer (SPIx Slave, Frame Slave) SSx(1) SDOx SDIx MSb LSb Note 1: In Framed SPI modes, the SSx pin is used to transmit/receive the Frame Synchronization pulse. 2: Framed SPI modes require the use of all four pins (i.e., using the SSx pin is not optional). 3: The SPIxTXB and SPIxRXB registers are memory-mapped to the SPIxBUF register. MSb LSb MSb LSb MSb LSb

 2019-2020 Microchip Technology Inc. DS30010198B-page 201 PIC24FJ128GL306 FAMILY

16.0 INTER-INTEGRATED CIRCUIT

(I2C) The Inter-Integrated Circuit (I 2C) module is a serial interface useful for communicating with other periph- eral or microcontroller devices. These peripheral devices may be serial EEPROMs, display drivers, A/D Converters, etc. The I 2C module supports these features:

• Independent Master and Slave Logic
• 7-Bit and 10-Bit Device Addresses
• General Call Address as Defined in the I2C Protocol
• Clock Stretching to Provide Delays for the Processor to Respond to a Slave Data Request
• Both 100 kHz, 400 kHz and 1 MHz Bus Specifications
• Configurable Address Masking
• Multi-Master modes to Prevent Loss of Messages in Arbitration
• Bus Repeater mode, Allowing the Acceptance of All Messages as a Slave, regardless of the Address
• Automatic SCL
• PMBus™ Support A block diagram of the module is shown in Figure 16-1.

16.1 Communicating as a Master in a

The details of sending a message in Master mode depends on the communications protocol for the device being communicated with. Typically, the sequence of events is as follows: 1. Assert a Start condition on SDAx and SCLx. 2. Send the I 2C device address byte to the Slave with a write indication. 3. Wait for and verify an Acknowledge from the Slave. 4. Send the first data byte (sometimes known as the command) to the Slave. 5. Wait for and verify an Acknowledge from the Slave. 6. Send the serial memory address low byte to the Slave. 7. Repeat Steps 4 and 5 until all data bytes are sent. 8. Assert a Repeated Start condition on SDAx and SCLx. 9. Send the device address byte to the Slave with a read indication. 10. Wait for and verify an Acknowledge from the Slave. 11. Enable Master reception to receive serial memory data. 12. Generate an ACK or NACK condition at the end of a received byte of data. 13. Generate a Stop condition on SDAx and SCLx. Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive ref- erence source. For more information, refer to “Inter-Integrated Circuit (I 2C)” (www.microchip.com/DS70000195) in the “dsPIC33/PIC24 Family Reference Man- ual”. The information in this data sheet supersedes the information in the FRM.

DS30010198B-page 202  2019-2020 Microchip Technology Inc. FIGURE 16-1: I2Cx BLOCK DIAGRAM I2CxRCV Internal Data Bus SCLx SDAx Shift Match Detect Start and Stop Bit Detect Clock Address Match Clock Stretching I2CxTRN LSb Shift Clock BRG Down Counter Reload Control TCY/2 Start and Stop Bit Generation Acknowledge Generation Collision Detect I2CxCON I2CxSTAT Control Logic Read LSb Write Read I2CxBRG I2CxRSR Write Read Write Read Write Read Write Read Write Read I2CxMSK I2CxADD

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16.2 Setting Baud Rate When Operating

To compute the Baud Rate Generator reload value, use Equation 16-1. EQUATION 16-1: COMPUTING BAUD RATE RELOAD VALUE(1,2,3)

16.3 Slave Address Masking

The I2CxMSK register ( Register 16-4) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2CxMSK register causes the Slave module to respond, whether the corresponding address bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK is set to ‘0010000000’, the Slave module will detect both addresses, ‘0000000000’ and ‘0010000000’. To enable address masking, the Intelligent Peripheral Management Interface (IPMI) must be disabled by clearing the STRICT bit (I2CxCONL[11]). TABLE 16-2: I2Cx RESERVED ADDRESSES (1) Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. 2: These clock rate values are for guidance only. The actual clock rate can be affected by various system-level para- meters. The actual clock rate should be measured in its intended application. 3: I2CxBRG values of 0 to 3 are forbidden. FSCL = FCY (I2CxBRG + 2) * 2 [ FCY (FSCL * 2) – 2 or: ]I2CxBRG = Note: As a result of changes in the I2C protocol, the addresses in Table 16-2 are reserved and will not be Acknowledged in Slave mode. This includes any address mask settings that include any of these addresses. TABLE 16-1: I2Cx CLOCK RATES (1,2) Required System FSCL FCY I2CxBRG Value Actual FSCL (Decimal) (Hexadecimal) 100 kHz 16 MHz 78 4E 100 kHz 100 kHz 8 MHz 38 26 100 kHz 100 kHz 4 MHz 18 12 100 kHz 400 kHz 16 MHz 18 12 400 kHz 400 kHz 8 MHz 8 8 400 kHz 400 kHz 4 MHz 3 3 400 kHz 1M H z 1 6M H z 6 6 1M H z Note 1: Based on F CY = FOSC/2; Doze mode and PLL are disabled. 2: These clock rate values are for guidance only. The actual clock rate can be affected by various system-level parameters. The actual clock rate should be measured in its intended application. Slave Address R/W Bit Description 0000 000 0 General Call Address(2) 0000 000 1 Start Byte 0000 001 x C-Bus Address 0000 01x x Reserved 0000 1xx x HS Mode Master Code 1111 0xx x 10-Bit Slave Upper Byte(3) 1111 1xx x Reserved Note 1: The address bits listed here will never cause an address match independent of address mask settings. 2: This address will be Acknowledged only if GCEN = 1. 3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.

DS30010198B-page 204  2019-2020 Microchip Technology Inc. REGISTER 16-1: I2CxCONL: I2 Cx CONTROL REGISTER LOW R/W-0 U-0 HC/R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL (1) STRICT A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 HC/R/W-0 HC/R/ W-0 HC/R/W-0 HC/R/W-0 HC/R/W-0 GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 I2CEN: I2Cx Enable bit (writable from software only) 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module; all I2C pins are controlled by port functions bit 14 Unimplemented: Read as ‘0’ bit 13 I2CSIDL: I2Cx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 SCLREL: SCLx Release Control bit (I2C Slave mode only)(1) Module resets and (I2CEN = 0) sets SCLREL = 1. If STREN = 0:(2) 1 = Releases clock 0 = Forces clock low (clock stretch) If STREN = 1: 1 = Releases clock 0 = Holds clock low (clock stretch); user may program this bit to ‘0’, clock stretch at next SCLx low bit 11 STRICT: I2Cx Strict Reserved Address Rule Enable bit 1 = Strict reserved addressing is enforced (for reserved addresses, refer to Table 16-2) In Slave Mode: The device does not respond to reserved address space and addresses falling in that category are NACKed. In Master Mode: The device is allowed to generate addresses with reserved address space. 0 = Reserved addressing would be Acknowledged In Slave Mode: The device will respond to an address falling in the reserved address space. When there is a match with any of the reserved addresses, the device will generate an ACK. In Master Mode: Reserved. bit 10 A10M: 10-Bit Slave Address Flag bit 1 = I2CxADD is a 10-bit Slave address 0 = I2CxADD is a 7-bit Slave address bit 9 DISSLW: Slew Rate Control Disable bit 1 = Slew rate control is disabled for Standard Speed mode (100 kHz, also disabled for 1 MHz mode) 0 = Slew rate control is enabled for High-Speed mode (400 kHz) Note 1: Automatically cleared to ‘0’ at the beginning of Slave transmission; automatically cleared to ‘0’ at the end of Slave reception. The user software must provide a delay between writing to the transmit buffer and set- ting the SCLREL bit. This delay must be greater than the minimum setup time for Slave transmissions, as specified in Section 30.0 “Electrical Characteristics”. 2: Automatically cleared to ‘0’ at the beginning of Slave transmission. 3: SMBus 3.0 specification input level can be selected by the SMB3EN Configuration bit (FDEVOPT1[10]).

 2019-2020 Microchip Technology Inc. DS30010198B-page 205 PIC24FJ128GL306 FAMILY bit 8 SMEN: SMBus Input Levels Enable bit(3) 1 = Enables input logic so thresholds are compliant with the SMBus specification 0 = Disables SMBus-specific inputs bit 7 GCEN: General Call Enable bit (I2C Slave mode only) 1 = Enables interrupt when a general call address is received in I2CxRSR; module is enabled for reception 0 = General call address is disabled bit 6 STREN: SCLx Clock Stretch Enable bit In I2C Slave mode only; used in conjunction with the SCLREL bit. 1 = Enables clock stretching 0 = Disables clock stretching bit 5 ACKDT: Acknowledge Data bit In I2C Master mode during Master Receive mode. The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. In I2C Slave mode when AHEN = 1 or DHEN = 1. The value that the Slave will transmit when it initiates an Acknowledge sequence at the end of an address or data reception. 1 = NACK is sent 0 = ACK is sent bit 4 ACKEN: Acknowledge Sequence Enable bit In I2C Master mode only; applicable during Master Receive mode. 1 = Initiates Acknowledge sequence on SDAx and SCLx pins, and transmits the ACKDT data bit 0 = Acknowledge sequence is Idle bit 3 RCEN: Receive Enable bit (I2C Master mode only) 1 = Enables Receive mode for I 2C; automatically cleared by hardware at the end of the 8-bit receive data byte 0 = Receive sequence is not in progress bit 2 PEN: Stop Condition Enable bit (I2C Master mode only) 1 = Initiates Stop condition on the SDAx and SCLx pins 0 = Stop condition is Idle bit 1 RSEN: Restart Condition Enable bit (I2C Master mode only) 1 = Initiates Restart condition on the SDAx and SCLx pins 0 = Restart condition is Idle bit 0 SEN: Start Condition Enable bit (I2C Master mode only) 1 = Initiates Start condition on the SDAx and SCLx pins 0 = Start condition is Idle REGISTER 16-1: I2CxCONL: I2Cx CO NTROL REGISTER LOW (CONTINUED) Note 1: Automatically cleared to ‘0’ at the beginning of Slave transmission; automatically cleared to ‘0’ at the end of Slave reception. The user software must provide a delay between writing to the transmit buffer and set- ting the SCLREL bit. This delay must be greater than the minimum setup time for Slave transmissions, as specified in Section 30.0 “Electrical Characteristics”. 2: Automatically cleared to ‘0’ at the beginning of Slave transmission. 3: SMBus 3.0 specification input level can be selected by the SMB3EN Configuration bit (FDEVOPT1[10]).

DS30010198B-page 206  2019-2020 Microchip Technology Inc. REGISTER 16-2: I2CxCONH: I2 Cx CONTROL REGISTER HIGH U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — PCIE SCIE BOEN SDAHT (1) SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6 PCIE: Stop Condition Interrupt Enable bit (I 2C Slave mode only) 1 = Enables interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled bit 5 SCIE: Start Condition Interrupt Enable bit (I2C Slave mode only) 1 = Enables interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled bit 4 BOEN: Buffer Overwrite Enable bit (I2C Slave mode only) 1 = I2CxRCV is updated and an ACK is generated for a received address/data byte, ignoring the state of the I2COV bit only if the RBF bit = 0 0 = I2CxRCV is only updated when I2COV is clear bit 3 SDAHT: SDAx Hold Time Selection bit(1) 1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx 0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If, on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the BCL bit is set and the bus goes Idle. This Detection mode is only valid during data and ACK transmit sequences. 1 = Enables Slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I 2C Slave mode only) 1 = Following the 8th falling edge of SCLx for a matching received address byte; the SCLREL bit (I2CxCONL[12]) will be cleared and SCLx will be held low 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCLx for a received data byte; Slave hardware clears the SCLREL bit (I2CxCONL[12]) and SCLx is held low 0 = Data holding is disabled Note 1: This bit must be set to ‘0’ for 1 MHz operation.

 2019-2020 Microchip Technology Inc. DS30010198B-page 207 PIC24FJ128GL306 FAMILY REGISTER 16-3: I2CxSTAT: I2Cx STATUS REGISTER HSC/R-0 HSC/R-0 HSC/R-0 U-0 U-0 HSC/R/C-0 HSC/R-0 HSC/R-0 ACKSTAT TRSTAT ACKTIM — — BCL GCSTAT ADD10 bit 15 bit 8 HS/R/C-0 HS/R/C-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 IWCOL I2COV D/A PS R / W RBF TBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit ‘0’ = Bit is cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set HSC = Hardware Settable/Clearable bit bit 15 ACKSTAT: Acknowledge Status bit (updated in all Master and Slave modes) 1 = Acknowledge was not received from Slave 0 = Acknowledge was received from Slave bit 14 TRSTAT: Transmit Status bit (when operating as I 2C Master; applicable to Master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress bit 13 ACKTIM: Acknowledge Time Status bit (valid in I2C Slave mode only) 1 = Indicates I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCLx clock 0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCLx clock bit 12-11 Unimplemented: Read as ‘0’ bit 10 BCL: Bus Collision Detect bit (Master/Slave mode; cleared when I2C module is disabled, I2CEN = 0) 1 = A bus collision has been detected during a Master or Slave transmit operation 0 = No bus collision has been detected bit 9 GCSTAT: General Call Status bit (cleared after Stop detection) 1 = General call address was received 0 = General call address was not received bit 8 ADD10: 10-Bit Address Status bit (cleared after Stop detection) 1 = 10-bit address was matched 0 = 10-bit address was not matched bit 7 IWCOL: I2Cx Write Collision Detect bit 1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy; must be cleared in software 0 = No collision bit 6 I2COV: I2Cx Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte; I2COV is a “don’t care” in Transmit mode, must be cleared in software 0 = No overflow bit 5 D/A: Data/Address bit (when operating as I2C Slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received or transmitted was an address bit 4 P: I2Cx Stop bit Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0. 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last

DS30010198B-page 208  2019-2020 Microchip Technology Inc. bit 3 S: I2Cx Start bit Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0. 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start (or Repeated Start) bit was not detected last bit 2 R/W: Read/Write Information bit (when operating as I2C Slave) 1 = Read: Indicates the data transfer is output from the Slave 0 = Write: Indicates the data transfer is input to the Slave bit 1 RBF: Receive Buffer Full Status bit 1 = Receive is complete, I2CxRCV is full 0 = Receive is not complete, I2CxRCV is empty bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit is in progress, I2CxTRN is full (8 bits of data) 0 = Transmit is complete, I2CxTRN is empty REGISTER 16-3: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) REGISTER 16-4: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSK[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 MSK[9:0]: I2Cx Mask for Address Bit x Select bits 1 = Enables masking for bit x of the incoming message address; bit match is not required in this position 0 = Disables masking for bit x; bit match is required in this position

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17.0 UNIVERSAL ASYNCHRONOUS

(UART) The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the PIC24F device family. The UART is a full-duplex, asynchronous system that can communicate with peripheral devices, such as personal computers, LIN/J2602, RS-232 and RS-485 interfaces. The module also supports a hardware flow control option with the UxCTS and UxRTS pins. The UART module includes an IrDA® encoder/decoder unit. The PIC24FJ128GL306 family devices are equipped with four UART modules, referred to as UART1, UART2, UART3 and UART4. The primary features of the UARTx modules are:

• Full-Duplex, 8 or 9-Bit Data Transmission through the UxTX and UxRX Pins
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Hardware Flow Control Option with the UxCTS and UxRTS Pins
• Fully Integrated Baud Rate Generator with 16-Bit Prescaler
• Baud Rates Range from Up to 1 Mbps and Down to

15 Hz at 16 MIPS in 16x mode

• Baud Rates Range from Up to 4 Mbps and Down to

61 Hz at 16 MIPS in 4x mode

• 4-Deep, First-In-First-Out (FIFO) Transmit Data Buffer
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
• Support for 9-Bit mode with Address Detect (9th bit = 1)
• Separate Transmit and Receive Interrupts
• Loopback mode for Diagnostic Support
• Polarity Control for Transmit and Receive Lines
• Support for Sync and Break Characters
• Supports Automatic Baud Rate Detection
• I r D A ® Encoder and Decoder Logic
• Includes DMA Support
• 16x Baud Clock Output for IrDA Support A simplified block diagram of the UARTx module is shown in Figure 17-1. The UARTx module consists of these key important hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive reference source. For more information, refer to “Universal Asynchronous Receiver Transmitter (UART)” (www.microchip.com/DS70000582) in the “dsPIC33/PIC24 Family Reference Man- ual”. The information in this data sheet supersedes the information in the FRM. Note: Throughout this section, references to register and bit names that may be asso- ciated with a specific UART module are referred to generically by the use of ‘x’ in place of the specific module number. Thus, “UxSTA” might refer to the Status register for either UART1, UART2, UART3 or UART4.

DS30010198B-page 210  2019-2020 Microchip Technology Inc. FIGURE 17-1: UARTx SIMP LIFIED BLOCK DIAGRAM IrDA® UARTx Receiver UxTX(1) UxCTS(1) UxRTS/BCLKx(1) Note 1: The UART1, UART2, UART3 and UART4 inputs and outputs must all be assigned to available RPn/RPIn pins before use. See Section 11.5 “Peripheral Pin Select (PPS)” for more information. Baud Rate Generator UARTx Transmitter UxRX(1) Hardware Flow Control

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17.1 UARTx Baud Rate Generator (BRG)

The UARTx module includes a dedicated, 16-bit Baud Rate Generator. The UxBRG register controls the period of a free-running, 16-bit timer. Equation 17-1 shows the formula for computation of the baud rate when BRGH = 0. EQUATION 17-1: UARTx BAUD RATE WITH BRGH = 0(1,2) Example 17-1 shows the calculation of the baud rate error for the following conditions:

• F CY = 4 MHz
• Desired Baud Rate = 9600 The maximum baud rate (BRGH = 0) possible is FCY/16 (for UxBRG = 0) and the minimum baud rate possible is FCY/(16 * 65536). Equation 17-2 shows the formula for computation of the baud rate when BRGH = 1. EQUATION 17-2: UARTx BAUD RATE WITH BRGH = 1(1,2) The maximum baud rate (BRGH = 1) possible is FCY/4 (for UxBRG = 0) and the minimum baud rate possible is FCY/(4 * 65536). Writing a new value to the UxBRG register causes the BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate. EXAMPLE 17-1: BAUD RATE ERROR CALCULATION (BRGH = 0)(1) Note 1: FCY denotes the instruction cycle clock frequency (FOSC/2). 2: Based on FCY = FOSC/2; Doze mode and PLL are disabled. Baud Rate = FCY 16 • (UxBRG + 1) UxBRG = FCY 16 • Baud Rate – 1 Note 1: FCY denotes the instruction cycle clock frequency. 2: Based on FCY = FOSC/2; Doze mode and PLL are disabled. Baud Rate = FCY 4 • (UxBRG + 1) UxBRG = FCY 4 • Baud Rate – 1 Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. Desired Baud Rate = F CY/(16 (UxBRG + 1)) Solving for UxBRG Value: UxBRG = ((F CY/Desired Baud Rate)/16) – 1 UxBRG = 25 Calculated Baud Rate = 4000000/(16 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desi red Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16%

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17.2 Transmitting in 8-Bit Data Mode

1. Set up the UARTx: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the UxBRG register. c) Set up transmit and receive interrupt enable and priority bits. 2. Enable the UARTx. 3. Set the UTXEN bit (causes a transmit interrupt, two cycles after being set). 4. Write a data byte to the lower byte of the UxTXREG word. The value will be immediately transferred to the Transmit Shift Register (TSR) and the serial bit stream will start shifting out with the next rising edge of the baud clock. 5. Alternatively, the data byte may be transferred while UTXEN = 0 and then the user may set UTXEN. This will cause the serial bit stream to begin immediately because the baud clock will start from a cleared state. 6. A transmit interrupt will be generated as per interrupt control bits, UTXISEL[1:0].

17.3 Transmitting in 9-Bit Data Mode

1. Set up the UARTx (as described in Section 17.2 “Transmitting in 8-Bit Data Mode”). 2. Enable the UARTx. 3. Set the UTXEN bit (causes a transmit interrupt). 4. Write UxTXREG as a 16-bit value only. 5. A word write to UxTXREG triggers the transfer of the 9-bit data to the TSR. The serial bit stream will start shifting out with the first rising edge of the baud clock. 6. A transmit interrupt will be generated as per the setting of control bits, UTXISELx.

17.4 Break and Sync Transmit

The following sequence will send a message frame header, made up of a Break, followed by an auto-baud Sync byte. 1. Configure the UARTx for the desired mode. 2. Set UTXEN and UTXBRK to set up the Break character. 3. Load the UxTXREG with a dummy character to initiate transmission (value is ignored). 4. Write ‘55h’ to UxTXREG; this loads the Sync character into the transmit FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits.

17.5 Receiving in 8-Bit or 9-Bit Data

1. Set up the UARTx (as described in Section 17.2 “Transmitting in 8-Bit Data Mode”). 2. Enable the UARTx by setting the URXEN bit (UxSTA[12]). 3. A receive interrupt will be generated when one or more data characters have been received as per interrupt control bits, URXISEL[1:0]. 4. Read the OERR bit to determine if an overrun error has occurred. The OERR bit must be reset in software. 5. Read UxRXREG. The act of reading the UxRXREG character will move the next character to the top of the receive FIFO, including a new set of PERR and FERR values.

17.6 Operation of UxCTS and UxRTS

UARTx Clear-to-Send (UxCTS ) and Request-to-Send (UxRTS) are the two hardware controlled pins that are associated with the UARTx modules. These two pins allow the UARTx to operate in Simplex and Flow Control mode. They are implemented to control the transmission and reception between the Data Terminal Equipment (DTE). The UEN[1:0] bits in the UxMODE register configure these pins.

17.7 Infrared Support

The UARTx module provides two types of infrared UART support: one is the IrDA clock output to support an external IrDA encoder and decoder device (legacy module support), and the other is the full implementa- tion of the IrDA encoder and decoder. Note that because the IrDA modes require a 16x baud clock, they will only work when the BRGH bit (UxMODE[3]) is ‘0’.

17.7.1 IrDA CLOCK OUTPUT FOR

To support external IrDA encoder and decoder devices, the BCLKx pin (same as the UxRTS pin) can be configured to generate the 16x baud clock. When UEN[1:0] = 11, the BCLKx pin will output the 16x baud clock if the UARTx module is enabled; it can be used to support the IrDA codec chip.

17.7.2 BUILT-IN IrDA ENCODER AND

The UARTx has full implementation of the IrDA encoder and decoder as part of the UARTx module. The built-in IrDA encoder and decoder functionality is enabled using the IREN bit (UxMODE[12]). When enabled (IREN = 1), the receive pin (UxRX) acts as the input from the infrared receiver. The transmit pin (UxTX) acts as the output to the infrared transmitter.

 2019-2020 Microchip Technology Inc. DS30010198B-page 213 PIC24FJ128GL306 FAMILY REGISTER 17-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UARTEN(1) — USIDL IREN (2) RTSMD — UEN1 UEN0 bit 15 bit 8 HC/R/W-0 R/W-0 HC/R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UARTEN: UARTx Enable bit(1) 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN[1:0] 0 = UARTx is disabled; all UARTx pins are controlled by port latches, UARTx power consumption is minimal bit 14 Unimplemented: Read as ‘0’ bit 13 USIDL: UARTx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2) 1 = IrDA encoder and decoder are enabled 0 = IrDA encoder and decoder are disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN[1:0]: UARTx Enable bits 11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by port latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS /BCLKx pins are controlled by port latches bit 7 WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit 1 = UARTx continues to sample the UxRX pin; interrupt is generated on the falling edge, bit is cleared in hardware on the following rising edge 0 = No wake-up is enabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Enables Loopback mode 0 = Loopback mode is disabled bit 5 ABAUD: Auto-Baud Enable bit 1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement is disabled or completed bit 4 URXINV: UARTx Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”. 2: This feature is only available for the 16x BRG mode (BRGH = 0).

DS30010198B-page 214  2019-2020 Microchip Technology Inc. bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode (4 BRG clock cycles per bit) 0 = Standard Speed mode (16 BRG clock cycles per bit) bit 2-1 PDSEL[1:0]: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit REGISTER 17-1: UxMODE: UARTx MODE REGISTER (CONTINUED) Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”. 2: This feature is only available for the 16x BRG mode (BRGH = 0).

 2019-2020 Microchip Technology Inc. DS30010198B-page 215 PIC24FJ128GL306 FAMILY REGISTER 17-2: UxSTA: UARTx ST ATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 HC/R/W-0 R/W-0 HSC/R-0 HSC/R-1 UTXISEL1 UTXINV (1) UTXISEL0 — UTXBRK UTXEN (2) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 HSC/R-1 HSC/R-0 HSC/R-0 HS/R/C-0 HSC/R-0 URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HS = Hardware Settable bit HC = Hardware Clearable bit bit 15,13 UTXISEL[1:0]: UARTx Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) bit 14 UTXINV: UARTx IrDA® Encoder Transmit Polarity Inversion bit(1) IREN = 0: 1 = UxTX Idle state is ‘0’ 0 = UxTX Idle state is ‘1’ IREN = 1: 1 = UxTX Idle state is ‘1’ 0 = UxTX Idle state is ‘0’ bit 12 Unimplemented: Read as ‘0’ bit 11 UTXBRK: UARTx Transmit Break bit 1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission is disabled or completed bit 10 UTXEN: UARTx Transmit Enable bit(2) 1 = Transmit is enabled, UxTX pin is controlled by UARTx 0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is controlled by the port bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written bit 8 TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued Note 1: The value of this bit only affects the transmit properties of the module when the IrDA® encoder is enabled (IREN = 1). 2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”.

DS30010198B-page 216  2019-2020 Microchip Technology Inc. bit 7-6 URXISEL[1:0]: UARTx Receive Interrupt Mode Selection bits 11 = Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has four data characters) 10 = Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e., has three data characters) 0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer; receive buffer has one or more characters bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode is enabled (if 9-bit mode is not selected, this does not take effect) 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (the character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (the character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed (clearing a previously set OERR bit (‘1’ to ‘0’ transition) will reset the receive buffer and the RSR to the empty state) bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) Note 1: The value of this bit only affects the transmit properties of the module when the IrDA® encoder is enabled (IREN = 1). 2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”.

 2019-2020 Microchip Technology Inc. DS30010198B-page 217 PIC24FJ128GL306 FAMILY REGISTER 17-3: UxRXREG: UARTx RECEIVE REGISTER (NORMALLY READ-ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0 bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 UxRXREG[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 UxRXREG[8:0]: Data of the Received Character bits REGISTER 17-4: UxTXREG: UARTx TRANSMIT REGISTER (NORMALLY WRITE-ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 W-x bit 15 bit 8 W-x W-x W-x W-x W-x W-x W-x W-x UxTXREG[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 UxTXREG[8:0]: Data of the Transmitted Character bits

DS30010198B-page 218  2019-2020 Microchip Technology Inc. REGISTER 17-5: UxBRG: UARTx BAUD RATE GENERATOR REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BRG[15:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BRG[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 BRG[15:0]: Baud Rate Divisor bits REGISTER 17-6: UxADMD: UARTx ADDRESS DETECT AND MATCH REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADMMASK7 ADMMASK6 ADMMASK5 ADMMASK4 ADMMASK3 ADMMASK2 ADMMASK1 ADMMASK0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADMADDR7 ADMADDR6 ADMADDR5 ADMADDR4 ADMADDR3 ADMADDR2 ADMADDR1 ADMADDR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 ADMMASK[7:0]: ADMADDR[7:0] (UxADMD[7:0]) Masking bits For ADM MASKx: 1 = ADMADDRx is used to detect the address match 0 = ADMADDRx is not used to detect the address match bit 7-0 ADMADDR[7:0]: Address Detect Task Off-Load bits Used with the ADMMASK[7:0] bits (UxADMD[15:8]) to offload the task of detecting the address character from the processor during Address Detect mode.

 2019-2020 Microchip Technology Inc. DS30010198B-page 219 PIC24FJ128GL306 FAMILY

18.0 LIQUID CRYSTAL DISPLAY

(LCD) CONTROLLER The Liquid Crystal Display (LCD) controller generates the data and timing control required to directly drive a static or multiplexed LCD panel. The module can drive up to eight commons signals on all devices, and from 9 to 36 segments, depending on the specific device. The LCD controller includes these features:

• Direct Driving of LCD Panel
• Three LCD Clock Sources with Selectable Prescaler
• Up to Eight Commons: - Static (one common) - 1/2 multiplex (two commons) - 1/3 multiplex (three commons) - 1/4 multiplex (four commons) - 1/5 multiplex (five commons) - 1/6 multiplex (six commons) - 1/7 multiplex (seven commons) - 1/8 multiplex (eight commons)
• Ability to Drive Up to 9 (in 28-pin devices) or Up to 36 (in 64-pin devices) Segments, Depending on the Multiplexing Mode Selected; Table 18-1 shows the segment availability
• Static, 1/2 or 1/3 LCD Bias
• On-Chip Bias Generator with Dedicated Charge Pump to Support a Range of Fixed and Bias Options
• Internal Resistors for Bias Voltage Generation
• Software Contrast Control for LCD Using Internal Biasing
• Core-Independent Automatic Display Features: - Dual display memory used to display two different content displays - Blink mode of individual pixels or the complete pixels - Blanking of individual pixels or the complete pixels - Timing schedule can be changed without core intervention based on user configurations A simplified block diagram of the module is shown in Figure 18-1. Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a compre- hensive reference source. To complement the information in this data sheet, refer to “Liquid Crystal Display (LCD) ” (www.microchip.com/DS30009740 ) in the “dsPIC33/PIC24 Family Reference Manual”. Note: To be driven by the LCD controller, pins must be set as analog inputs. For the port corre- sponding to the desired common or segment pin, set TRISx = 1 and ANSELx =1. TABLE 18-1: LCD SEGMENT AVAILABILITY Device Segments SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG PIC24FJXXXGL306 x x x x x x x x x x x x x x x x x x PIC24FJXXXGL305 x x x — — xxxxxxx — —x x — — Device Segments SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG PIC24FJXXXGL306 x x x x x x x x x x x x x x x x x x PIC24FJXXXGL305 —x x —x x x x — xxxxx — — — —

DS30010198B-page 220  2019-2020 Microchip Technology Inc. FIGURE 18-1: LCD CONTRO LLER MODULE BLOCK DIAGRAM FRC Oscillator ... LCDDATA31 LCDDATA30 LCDDATA1 LCDDATA0 LCD DATA 32 x 18 (= 8 x 64) 512 LCDCON LCDPS LCDSEx Timing Control LCDREG LCDREF Resistor Ladder LCD LCD BIAS Generation Charge PumpLPRC Oscillator SOSC (Secondary Oscillator) LCD Clock Source Select COMx[7:0] SEG[62:0] Data Bus Bias Voltage To I/O Pins to MUX

 2019-2020 Microchip Technology Inc. DS30010198B-page 221 PIC24FJ128GL306 FAMILY

18.1 LCD Control Registers

REGISTER 18-1: LCDCON: LCD CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SLPEN WERR CS1 CS0 LMUX2 LMUX1 LMUX0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 LCDEN: LCD Driver Enable bit 1 = LCD driver module is enabled 0 = LCD driver module is not enabled bit 14 Unimplemented: Read as ‘0’ bit 13 LCDSIDL: Stop LCD Drive in CPU Idle Mode Control bit 1 = LCD driver halts in CPU Idle mode 0 = LCD driver continues to operate in CPU Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 SLPEN: LCD Driver Enable in Sleep Mode bit 1 = LCD driver module is disabled in Sleep mode 0 = LCD driver module is enabled in Sleep mode bit 5 WERR: LCD Write Failed Error bit 1 = LCDDATAx register is written while WA (LCDPS[4]) = 0 (must be cleared in software) 0 = No LCD write error bit 4-3 CS[1:0]: Clock Source Select bits 1x = SOSC 01 = LPRC 00 = FRC bit 2-0 LMUX[2:0]: LCD Commons Select bits LMUX[2:0] Multiplex Bias 010 1/3 MUX (COM[2:0]) 1/2 or 1/3 001 1/2 MUX (COM[1:0]) 1/2 or 1/3

000 Static (COM0) Static

DS30010198B-page 222  2019-2020 Microchip Technology Inc. REGISTER 18-2: LCDREG: LCD CHARGE PUMP CONTROL REGISTER RW-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 RW-0 RW-0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CPEN: 3.6V Charge Pump Enable bit 1 = The regulator generates the highest (3.6V) voltage 0 = Highest voltage in the system is supplied externally (AV DD) bit 14-2 Unimplemented: Read as ‘0’ bit 1-0 CLKSEL[1:0]: Regulator Clock Select Control bits 11 = SOSC 10 = 8 MHz FRC 01 = 32 kHz LPRC 00 = Disables regulator and floats regulator voltage output

 2019-2020 Microchip Technology Inc. DS30010198B-page 223 PIC24FJ128GL306 FAMILY REGISTER 18-3: LCDPS: LCD PHASE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 WFT: Waveform Type Select bit 1 = Type-B waveform (phase changes on each frame boundary) 0 = Type-A waveform (phase changes within each common type) bit 6 BIASMD: Bias Mode Select bit When LMUX[2:0] = 000 or 011 through 111: 0 = Static Bias mode (do not set this bit to ‘1’) When LMUX[2:0] = 001 or 010: 1 = 1/2 Bias mode 0 = 1/3 Bias mode bit 5 LCDA: LCD Active Status bit 1 = LCD driver module is active 0 = LCD driver module is inactive bit 4 WA: LCD Write Allow Status bit 1 = Write into the LCDDATAx registers is allowed 0 = Write into the LCDDATAx registers is not allowed bit 3-0 LP[3:0]: LCD Prescaler Select bits 1111 = 1:16 1110 = 1:15 1101 = 1:14 1100 = 1:13 1011 = 1:12 1010 = 1:11 1001 = 1:10 1000 = 1:9 0111 = 1:8 0110 = 1:7 0101 = 1:6 0100 = 1:5 0011 = 1:4 0010 = 1:3 0001 = 1:2 0000 = 1:1

DS30010198B-page 224  2019-2020 Microchip Technology Inc. REGISTER 18-4: LCDSEx: LCD SEGMENT x ENABLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SE(n+15) SE(n+14) SE(n+13) SE(n+12) SE(n+11) SE(n+10) SE(n+9) SE(n+8) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SE(n+7) SE(n+6) SE(n+5) SE(n+4) SE(n+3) SE(n+2) SE(n+1) SE(n) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 SE(n+15):SE(n): Segment Enable bits For LCDSE0: n = 0 For LCDSE1: n = 16 For LCDSE2: n = 32 For LCDSE3: n = 48 1 = Segment function of the pin is enabled, digital I/O is disabled 0 = Segment function of the pin is disabled, digital I/O is enabled

 2019-2020 Microchip Technology Inc. DS30010198B-page 225 PIC24FJ128GL306 FAMILY REGISTER 18-5: LCDDATAx: LCD DATA x REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 S(n+15)Cy S(n+14)Cy S(n+13)Cy S(n+12)Cy S(n+11)Cy S(n+10)Cy S(n+9)Cy S(n+8)Cy bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 S(n+7)Cy S(n+6)Cy S(n+5)Cy S(n+4)Cy S(n+3)Cy S(n+2)Cy S(n+1)Cy S(n)Cy bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 S(n+15)Cy:S(n)Cy: Pixel On bits For Registers, LCDDATA0 through LCDDATA3: n = (16x), y = 0 For Registers, LCDDATA4 through LCDDATA7: n = (16(x – 4)), y = 1 For Registers, LCDDATA8 through LCDDATA11: n = (16(x – 8)), y = 2 For Registers, LCDDATA12 through LCDDATA15: n = (16(x – 12)), y = 3 For Registers, LCDDATA16 through LCDDATA19: n = (16(x – 16)), y = 4 For Registers, LCDDATA20 through LCDDATA23: n = (16(x – 20)), y = 5 For Registers, LCDDATA24 through LCDDATA27: n = (16(x – 24)), y = 6 For Registers, LCDDATA28 through LCDDATA31: n = (16(x – 28)), y = 7 1 = Pixel is on 0 = Pixel is off Note 1: Table 18-2 shows the correlation of each bit in the LCDDATAx registers to the respective common and segment signals. TABLE 18-2: LCD DATA REGISTERS AND BITS FOR SEGMENT AND COM COMBINATIONS COM Lines Segments 0 to 15 16 to 31 32 to 47 48 to 64

0 LCDDATA0 LCDDATA1 LCDDATA2 LCDDATA3

S00C0:S15C0 S16C0:S31C0 S32C0:S47C0 S48C0:S63C0

1 LCDDATA4 LCDDATA5 LCDDATA6 LCDDATA7

S00C1:S15C1 S16C1:S31C1 S32C1:S47C1 S48C1:S63C1

2 LCDDATA8 LCDDATA9 LCDDATA10 LCDDATA11

S00C2:S15C2 S16C2:S31C2 S32C2:S47C2 S48C2:S63C2

3 LCDDATA12 LCDDATA13 LCDDATA14 LCDDATA15

S00C3:S15C3 S16C3:S31C3 S32C3:S47C3 S48C3:S63C3

4 LCDDATA16 LCDDATA17 LCDDATA18 LCDDATA19

S00C4:S15C4 S16C4:S31C4 S32C4:S47C4 S48C4:S63C4

5 LCDDATA20 LCDDATA21 LCDDATA22 LCDDATA23

S00C5:S15C5 S16C5:S31C5 S32C5:S47C5 S48C5:S63C5

6 LCDDATA24 LCDDATA25 LCDDATA26 LCDDATA27

S00C6:S15C6 S16C6:S31C6 S32C6:S47C6 S48C6:S63C6

7 LCDDATA28 LCDDATA29 LCDDATA30 LCDDATA31

S00C7:S15C7 S16C7:S31C7 S32C7:S47C7 S48C7:S63C7

DS30010198B-page 226  2019-2020 Microchip Technology Inc. REGISTER 18-6: LCDREF: LCD REFE RENCE LADDER CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LCDIRE — LCDCST2 LCDCST1 LCDCST0 VLCD3PE VLCD2PE VLCD1PE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 LRLAP1 LRLAP0 LRLBP1 LRLBP0 — LRLAT2 LRLAT1 LRLAT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 LCDIRE: LCD Internal Reference Enable bit 1 = Internal LCD reference is enabled and connected to the internal contrast control circuit 0 = Internal LCD reference is disabled bit 14 Unimplemented: Read as ‘0’ bit 13-11 LCDCST[2:0]: LCD Contrast Control bits Selects the Resistance of the LCD Contrast Control Resistor Ladder: 111 = Resistor ladder is at maximum resistance (minimum contrast) 110 = Resistor ladder is at 6/7th of maximum resistance 101 = Resistor ladder is at 5/7th of maximum resistance 100 = Resistor ladder is at 4/7th of maximum resistance 011 = Resistor ladder is at 3/7th of maximum resistance 010 = Resistor ladder is at 2/7th of maximum resistance 001 = Resistor ladder is at 1/7th of maximum resistance 000 = Minimum resistance (maximum contrast); resistor ladder is shorted bit 10 VLCD3PE: LCD Bias 3 Pin Enable bit 1 = Bias 3 level is connected to the external pin, LCDBIAS3 0 = Bias 3 level is internal (internal resistor ladder) bit 9 VLCD2PE: LCD Bias 2 Pin Enable bit 1 = Bias 2 level is connected to the external pin, LCDBIAS2 0 = Bias 2 level is internal (internal resistor ladder) bit 8 VLCD1PE: LCD Bias 1 Pin Enable bit 1 = Bias 1 level is connected to the external pin, LCDBIAS1 0 = Bias 1 level is internal (internal resistor ladder) bit 7-6 LRLAP[1:0]: LCD Reference Ladder A Time Power Control bits During Time Interval A: 11 = Internal LCD reference ladder is powered in High-Power mode 10 = Internal LCD reference ladder is powered in Medium Power mode 01 = Internal LCD reference ladder is powered in Low-Power mode 00 = Internal LCD reference ladder is powered down and unconnected bit 5-4 LRLBP[1:0]: LCD Reference Ladder B Time Power Control bits During Time Interval B: 11 = Internal LCD reference ladder is powered in High-Power mode 10 = Internal LCD reference ladder is powered in Medium Power mode 01 = Internal LCD reference ladder is powered in Low-Power mode 00 = Internal LCD reference ladder is powered down and unconnected bit 3 Unimplemented: Read as ‘0’

 2019-2020 Microchip Technology Inc. DS30010198B-page 227 PIC24FJ128GL306 FAMILY bit 2-0 LRLAT[2:0]: LCD Reference Ladder A Time Interval Control bits Sets the number of 32 clock counts when the A Time Interval Power mode is active. For Type-A Waveforms (WFT = 0): 111 = Internal LCD reference ladder is in A Power mode for 7 clocks and B Power mode for 9 clocks 110 = Internal LCD reference ladder is in A Power mode for 6 clocks and B Power mode for 10 clocks 101 = Internal LCD reference ladder is in A Power mode for 5 clocks and B Power mode for 11 clocks 100 = Internal LCD reference ladder is in A Power mode for 4 clocks and B Power mode for 12 clocks 011 = Internal LCD reference ladder is in A Power mode for 3 clocks and B Power mode for 13 clocks 010 = Internal LCD reference ladder is in A Power mode for 2 clocks and B Power mode for 14 clocks 001 = Internal LCD reference ladder is in A Power mode for 1 clock and B Power mode for 15 clocks 000 = Internal LCD reference ladder is always in B Power mode For Type-B Waveforms (WFT = 1): 111 = Internal LCD reference ladder is in A Power mode for 7 clocks and B Power mode for 25 clocks 110 = Internal LCD reference ladder is in A Power mode for 6 clocks and B Power mode for 26 clocks 101 = Internal LCD reference ladder is in A Power mode for 5 clocks and B Power mode for 27 clocks 100 = Internal LCD reference ladder is in A Power mode for 4 clocks and B Power mode for 28 clocks 011 = Internal LCD reference ladder is in A Power mode for 3 clocks and B Power mode for 29 clocks 010 = Internal LCD reference ladder is in A Power mode for 2 clocks and B Power mode for 30 clocks 001 = Internal LCD reference ladder is in A Power mode for 1 clock and B Power mode for 31 clocks 000 = Internal LCD reference ladder is always in B Power mode REGISTER 18-6: LCDREF: LCD REFERENCE LADDER CONTROL REGISTER (CONTINUED)

DS30010198B-page 228  2019-2020 Microchip Technology Inc. REGISTER 18-7: LCDACTRL: LCD AUTOMATIC CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SMFCS[2:0](1,2,3,4,5) BLINKFCS[2:0](4,5,6,7) BLINKMODE[1:0](8,9) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BLANKFCS[2:0](3,5,6,7,10,11) BLANKMODE[1:0] FCCS[1:0] ELCDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 SMFCS[2:0]: Frame Counter Selection for Data Memory Selection bits(1,2,3,4,5) When DMSEL[1:0] = 10 (one-time switchover from current display memory to another memory): 000 = Reserved 001 = Selects Frame Counter 0 (FC0) When DMSEL[1:0] = 11 (continues to switch over from one memory to another memory): 000 = Reserved 001 = Selects Frame Counter 0 (FC0) 010 = Selects Frame Counter 0 (FC0), then continues with Frame Counter 1 (FC1) at the frequency given by the time event 011 = Reserved When DMSEL[1:0] = 11 (continues to switch over from one memory to another with a repeated pattern): 100 = Alternates between FC0 and FC1 at the frequency given by the time event 101 = Reserved 110 = Reserved 111 = Reserved Note 1: Secondary memory is selected for pixel enable to Blink or Blank when BLINKMODE[1:0] = 01 | BLANKMODE[1:0] = 01. 2: Secondary memory is used to store data to display or selects the pixel to Blink or Blank. 3: FC1 is used when Blink mode is not selected (i.e., BLINKMODE[1:0] = 00 | 11). 4: FC2 is used when Blank mode is not selected (i.e., BLANKMODE[1:0] = 00 | 11). 5: Frame counter selection switchover based on time event. 6: Pixel will alternate between ON and OFF state at the frequency given by the selected frame counter. 7: FC0 is used when secondary memory is not selected with switchover function (i.e., DMSEL[1:0] = 00 or 01). 8: Blink mode ON state is effective to the pixel when Blank mode is off. 9: Blink mode OFF state drives ‘0’ to the pixel. 10: One-time Blank continues to Blank until a user changes the Blank mode to enable or disable the enhanced LCD feature (clears ELCDEN) or SBLANK is clear. 11: In One-Time Blank Configuration mode, the pixel continues to Blink (to alternate between on and off) until the timer event happens.

 2019-2020 Microchip Technology Inc. DS30010198B-page 229 PIC24FJ128GL306 FAMILY bit 12-10 BLINKFCS[2:0]: Frame Counter Selection for Blink Selection bits (BLINKMODE = 01 or 10)(4,5,6,7) 000 = Reserved 001 = Selects Frame Counter 1 (FC1) 010 = Selects Frame Counter 0 (FC0), then continues with Frame Counter 1 (FC1) at the frequency given by the time event 011 = Reserved 100 = Alternates between FC0 and FC1 at the frequency given by the time event (repeated pattern) 101 = Reserved 110 = Reserved 111 = Reserved bit 9-8 BLINKMODE[1:0]: Blink Mode bits(8,9) 00 = Blink mode is disabled 01 = Blink mode is enabled with selected pixels (when DMSEL[1:0] = 00) 10 = Blink mode is enabled with all pixels 11 = Reserved bit 7-5 BLANKFCS[2:0]: Blank Operation Selection from Frame Counter Selection bits(3,5,6,7,10,11) (when BLANKMODE[1:0] = 01 or 10) 000 = Reserved 001 = Selects Frame Counter 2 (FC2) 010 = Selects Frame Counter 0 (FC0), then continues with Frame Counter 1 (FC1) at the frequency given by the time event 011 = Reserved 100 = Alternates between FC0 and FC1 at the frequency given by the time event (repeated pattern) 101 = Reserved 110 = One-time Blank selects Frame Counter 2 (FC2) by the time event(10,11) 111 = Reserved bit 4-3 BLANKMODE[1:0]: Blank Mode bits 00 = Blank mode is disabled 01 = Blank mode is enabled with selected pixels (when DMSEL[1:0] = 00) 10 = Blank mode is enabled with all pixels 11 = Reserved bit 2-1 FCCS[1:0]: Clock Source bits 00 = LCD clock 01 = RTCC 10 = CLC1 11 = CLC2 bit 0 ELCDEN: Enhancement LCD Enable bit 1 = Enhancement function is enabled 0 = Enhancement function is disabled REGISTER 18-7: LCDACTRL: LCD AUTOMATIC CONTROL REGISTER (CONTINUED) Note 1: Secondary memory is selected for pixel enable to Blink or Blank when BLINKMODE[1:0] = 01 | BLANKMODE[1:0] = 01. 2: Secondary memory is used to store data to display or selects the pixel to Blink or Blank. 3: FC1 is used when Blink mode is not selected (i.e., BLINKMODE[1:0] = 00 | 11). 4: FC2 is used when Blank mode is not selected (i.e., BLANKMODE[1:0] = 00 | 11). 5: Frame counter selection switchover based on time event. 6: Pixel will alternate between ON and OFF state at the frequency given by the selected frame counter. 7: FC0 is used when secondary memory is not selected with switchover function (i.e., DMSEL[1:0] = 00 or 01). 8: Blink mode ON state is effective to the pixel when Blank mode is off. 9: Blink mode OFF state drives ‘0’ to the pixel. 10: One-time Blank continues to Blank until a user changes the Blank mode to enable or disable the enhanced LCD feature (clears ELCDEN) or SBLANK is clear. 11: In One-Time Blank Configuration mode, the pixel continues to Blink (to alternate between on and off) until the timer event happens.

DS30010198B-page 230  2019-2020 Microchip Technology Inc. REGISTER 18-8: LCDASTAT: LCD AUTOMATIC STATUS REGISTER U-0 R/C-0 R-0 R-0 R/C-0 R/C-0 R/C-0 R/C-0 —S B L A N K (1,2,3,4) SMEMACT PMEMACT TEVENTO FC2O FC1O FC0O bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SMLOCK(7) SMCLEAR PMLOCK (5,6) PMCLEAR SMEMEN PMEMDIS DMSEL1 DMSEL0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 SBLANK: Blank Status bit(1,2,3,4) 1 = Pixels are in continuous Blank 0 = Pixels are not in continuous Blank bit 13 SMEMACT: Secondary Memory Active bit 1 = Data display is from secondary memory 0 = Data display is not from secondary memory bit 12 PMEMACT: Primary Memory Active bit 1 = Data display is from primary memory 0 = Data display is not from primary memory bit 11 TEVENTO: Time Event Overflow bit 1 = This flag is set when the time event overflows 0 = Timer event does not overflow bit 10 FC2O: Frame Counter 2 Overflow bit 1 = This flag is set when Frame Counter 2 overflows 0 = Frame Counter 2 does not overflow bit 9 FC1O: Frame Counter 1 Overflow bit 1 = This flag is set when Frame Counter 1 overflows 0 = Frame Counter 1 does not overflow bit 8 FC0O: Frame Counter 0 Overflow bit 1 = This flag is set when Frame Counter 0 overflows 0 = Frame Counter 0 does not overflow Note 1: Reflects BLANKFCS[2:0] = 110 status. 2: It is the user’s responsibility to clear the bit to make LCD active. 3: This bit is cleared by hardware when the user changes Blank mode = 0 or clears the ELCDEN bit. 4: This flag bit is used to generate an enhanced feature interrupt. 5: This bit is effective when SMEMEN = 1; otherwise, the write follows the Write Allow bit, WA (LCDPS[4]). 6: When the PMLOCK bit is set, it does not allow the user to write to the primary memory. 7: When the SMLOCK bit is set, it does not allow the user to write to the secondary memory.

 2019-2020 Microchip Technology Inc. DS30010198B-page 231 PIC24FJ128GL306 FAMILY bit 7 SMLOCK: Secondary Memory Lock Enable bit(7) 1 = Secondary memory is locked 0 = Secondary memory is unlocked bit 6 SMCLEAR: Secondary Memory Clear Enable bit 1 = Secondary memory is cleared immediately 0 = Secondary memory is not cleared bit 5 PMLOCK: Primary Memory Lock Enable bit(5,6) 1 = Primary memory is locked 0 = Primary memory is unlocked bit 4 PMCLEAR: Primary Memory Clear Enable bit 1 = Primary memory is cleared immediately 0 = Primary memory is not cleared bit 3 SMEMEN: Secondary Memory Enable bit 1 = Secondary memory is enabled 0 = Secondary memory is disabled bit 2 PMEMDIS: Primary Memory Disable bit 1 = Primary memory is disabled 0 = Primary memory is enabled bit 1-0 DMSEL[1:0]: Data Memory Selection bits 11 = Continues alternating selection between primary and secondary memories based on SMFCS[2:0] 10 = Alternates selection between primary and secondary memories on SMFCS[2:0] 01 = Selects secondary memory as display memory 00 = Selects primary memory as display memory REGISTER 18-8: LCDASTAT: LCD AUTOMATIC STATUS REGISTER (CONTINUED) Note 1: Reflects BLANKFCS[2:0] = 110 status. 2: It is the user’s responsibility to clear the bit to make LCD active. 3: This bit is cleared by hardware when the user changes Blank mode = 0 or clears the ELCDEN bit. 4: This flag bit is used to generate an enhanced feature interrupt. 5: This bit is effective when SMEMEN = 1; otherwise, the write follows the Write Allow bit, WA (LCDPS[4]). 6: When the PMLOCK bit is set, it does not allow the user to write to the primary memory. 7: When the SMLOCK bit is set, it does not allow the user to write to the secondary memory.

DS30010198B-page 232  2019-2020 Microchip Technology Inc. REGISTER 18-9: LCDFC0: LCD FRAME COUNTER 0 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FC0[15:8](1,2,3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FC0[7:0](1,2,3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 FC0[15:0]: Time Base Value bits(1,2,3) These bits define the overflow value. Note 1: It is recommended to make the FC0x values to be multiples of the frame frequency. 2: FC0x value must be greater than two. 3: FC0x should not be written when ELCDEN = 1. REGISTER 18-10: LCDFC1: LCD FRAME COUNTER 1 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FC1[15:8](1,2,3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FC1[7:0](1,2,3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 FC1[15:0]: Time Base Value bits(1,2,3) These bits define the overflow value. Note 1: It is recommended to make the FC1x values to be multiples of the frame frequency. 2: FC1x value must be greater than two. 3: FC1x should not be written when ELCDEN = 1.

 2019-2020 Microchip Technology Inc. DS30010198B-page 233 PIC24FJ128GL306 FAMILY REGISTER 18-11: LCDFC2: LCD FRAME COUNTER 2 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FC2[15:8](1,2,3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FC2[7:0](1,2,3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 FC2[15:0]: Time Base Value bits(1,2,3) These bits define the overflow value. Note 1: It is recommended to make the FC2x values to be multiples of the frame frequency. 2: FC2x value must be greater than two. 3: FC2x should not be written when ELCDEN = 1. REGISTER 18-12: LCDEVENT: LCD TI ME EVENT SELECTION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TEVENT[15:8](1,2,3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TEVENT[7:0](1,2,3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15:0 TEVENT[15:0]: Time Base Event Value bits(1,2,3) These bits define the time event value. Note 1: The TEVENTx value should be multiples of the frame frequency. 2: The TEVENTx value should be greater than the FCx value. 3: The overflow is (TEVENTx * 16 ±1); the TEVENTx overflow gets ±1 based on the TEVENTx ratio with the FCx value.

DS30010198B-page 234  2019-2020 Microchip Technology Inc. REGISTER 18-13: LCDSDATAx: LCD SDATA x REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 S(n+15)Cy S(n+14)Cy S(n+13)Cy S(n+12)Cy S(n+11)Cy S(n+10)Cy S(n+9)Cy S(n+8)Cy bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 S(n+7)Cy S(n+6)Cy S(n+5)Cy S(n+4)Cy S(n+3)Cy S(n+2)Cy S(n+1)Cy S(n)Cy bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15:0 S(n+15)Cy:S(n)Cy: Pixel Blink/Blank Enable bits (Segment x and Common y) If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01: 1 = Pixel is selected for Blink or Blank 0 = Pixel is not selected for Blink or Blank Else: SEGxCOMy: Pixel Data bits (Segment x and Common y) 1 = Pixel on (dark) 0 = Pixel off (clear) TABLE 18-3: LCD SDATA REGISTERS AND BITS FOR SEGMENT AND COM COMBINATIONS COM Lines Segments 0 to 15 16 to 31 32 to 47 48 to 64

0 LCDSDATA0 LCDSDATA1 LCDSDATA2 LCDSDATA3

S00C0:S15C0 S16C0:S31C0 S32C0:S47C0 S48C0:S63C0

1 LCDSDATA4 LCDSDATA5 LCDSDATA6 LCDSDATA7

S00C1:S15C1 S16C1:S31C1 S32C1:S47C1 S48C1:S63C1

2 LCDSDATA8 LCDSDATA9 LCDSDATA10 LCDSDATA11

S00C2:S15C2 S16C2:S31C2 S32C2:S47C2 S48C2:S63C2

3 LCDSDATA12 LCDSDATA13 LCDSDATA14 LCDSDATA15

S00C3:S15C3 S16C3:S31C3 S32C3:S47C3 S48C3:S63C3

4 LCDSDATA16 LCDSDATA17 LCDSDATA18 LCDSDATA19

S00C4:S15C4 S16C4:S31C4 S32C4:S47C4 S48C4:S63C4

5 LCDSDATA20 LCDSDATA21 LCDSDATA22 LCDSDATA23

S00C5:S15C5 S16C5:S31C5 S32C5:S47C5 S48C5:S63C5

6 LCDSDATA24 LCDSDATA25 LCDSDATA26 LCDSDATA27

S00C6:S15C6 S16C6:S31C6 S32C6:S47C6 S48C6:S63C6

7 LCDSDATA28 LCDSDATA29 LCDSDATA30 LCDSDATA31

S00C7:S15C7 S16C7:S31C7 S32C7:S47C7 S48C7:S63C7

 2019-2020 Microchip Technology Inc. DS30010198B-page 235 PIC24FJ128GL306 FAMILY

19.0 REAL-TIME CLOCK AND

CALENDAR (RTCC) WITH TIMESTAMP The RTCC provides the user with a Real-Time Clock and Calendar (RTCC) function that can be calibrated. Key features of the RTCC module are:

• Selectable Clock Source
• Provides Hours, Minutes and Seconds Using 24-Hour Format
• Visibility of One Half Second Period
• Provides Calendar – Weekday, Date, Month and Year
• Alarm-Configurable for Half a Second, 1 Second,

10 Seconds, 1 Minute, 10 Minutes, 1 Hour, 1 Day,

1 Week, 1 Month or 1 Year

• Alarm Repeat with Decrementing Counter
• Alarm with Indefinite Repeat Chime
• Year 2000 to 2099 Leap Year Correction
• BCD Format for Smaller Software Overhead
• Optimized for Long-Term Battery Operation
• User Calibration of the 32.768 kHz Clock Crystal/32 kHz INTRC Frequency with Periodic Auto-Adjust
• Fractional Second Synchronization
• Calibration to within ±2.64 Seconds Error per Month
• Calibrates Up to 260 ppm of Crystal Error
• Ability to Periodically Wake-up External Devices without CPU Intervention (external power control)
• Power Control Output for External Circuit Control
• Calibration takes Effect Every 15 Seconds
• Timestamp Capture Register for Time and Date
• Programmable Prescaler and Clock Divider Circuit allows Operation with Any Clock Source Up to 32 MHz, Including 32.768 kHz Crystal, 50/60 Hz Powerline Clock, External Real-Time Clock (RTC) or 32 kHz LPRC Clock

19.1 RTCC Source Clock

The RTCC clock divider block converts the incoming oscillator source into accurate 1/2 and 1 second clocks for the RTCC. The clock divider is optimized to work with three different oscillator sources:

• 32.768 kHz Crystal Oscillator
• 32 kHz Low-Power RC Oscillator (LPRC)
• External 50 Hz or 60 Hz Powerline Frequency An asynchronous prescaler, PS[1:0] (RTCCON2L[5:4]), is provided that allows the RTCC to work with higher speed clock sources, such as the system clock. Divide ratios of 1:16, 1:64 or 1:256 may be selected, allowing sources up to 32 MHz to clock the RTCC.

19.1.1 COARSE FREQUENCY DIVISION

The clock divider block has a 16-bit counter used to divide the input clock frequency. The divide ratio is set by the DIV[15:0] register bits (RTCCON2H[15:0]). The DIV[15:0] bits should be programmed with a value to produce a nominal 1/2 second clock divider count period.

19.1.2 FINE FREQUENCY DIVISION

The fine frequency division is set using the FDIV[4:0] (RTCCON2L[15:11]) bits. Increasing the FDIVx value will lengthen the overall clock divider period. If FDIV[4:0] = 00000, the fine frequency division circuit is effectively disabled. Otherwise, it will optionally remove a clock pulse from the input of the clock divider every 1/2 second. This functionality will allow the user to remove up to 31 pulses over a fixed period of 16 seconds, depending on the value of FDIVx. The value for DIV[15:0] is calculated as shown in Equation 19-1. The fractional remainder of the DIV[15:0] calculation result can be used to calculate the value for FDIV[4:0]. EQUATION 19-1: RTCC CLOCK DIVIDER OUTPUT FREQUENCY Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive reference source. For more information, refer to “RTCC with Timestamp” (www.microchip.com/DS70005193) in the “dsPIC33/PIC24 Family Reference Man- ual”. The information in this data sheet supersedes the information in the FRM. The DIV[15:0] value is the integer part of this calculation: The FDIV[4:0] value is the fractional part of the DIV[15:0] calculation, multiplied by 32. FOUT = FIN 2 • (PS[1:0] Prescaler) • (DIV[15:0] + 1) +FDIV[4:0] DIV[15:0] = FIN 2 • (PS[1:0] Prescaler) – 1

DS30010198B-page 236  2019-2020 Microchip Technology Inc. FIGURE 19-1: RTCC BLOCK DIAGRAM RTCC RTCOE CLKSEL[1:0] Alarm Registers ComparatorsPower Control Repeat Control Time/Date Registers Timestamp Time/ Date Registers PS[1:0] PWCPS[1:0] Second OUTSEL[2:0] Clock Divider PPS Note 1: In Retention mode, the maximum peripheral output frequency to an I/O pin must be limited to 33 kHz or less.

 2019-2020 Microchip Technology Inc. DS30010198B-page 237 PIC24FJ128GL306 FAMILY

19.2 RTCC Module Registers

The RTCC module registers are organized into four categories:

• RTCC Control Registers
• RTCC Value Registers
• Alarm Value Registers
• Timestamp Registers

19.2.1 REGISTER MAPPING

Previous RTCC implementations used a Register Pointer to access the RTCC Time and Date registers, as well as the Alarm Time and Date registers. These registers are now mapped to memory and are individually addressable.

19.2.2 WRITE LOCK

To prevent spurious changes to the Time Control or Time Value registers, the WRLOCK bit (RTCCON1L[11]) must be cleared (‘0’). The POR default state is when the WRLOCK bit is ‘0’ and is cleared on any device Reset (POR, BOR, MCLR ). It is recommended that the WRLOCK bit be set to ‘ 1’ after the Date and Time registers are properly initialized, and after the RTCEN bit (RTCCON1L[15]) has been set. Any attempt to write to the RTCEN bit, the RTCCON2L/H registers, or the Date or Time registers, will be ignored as long as WRLOCK is ‘1’. The Alarm, Power Control and Timestamp registers can be changed when WRLOCK is ‘1’. Clearing the WRLOCK bit requires an unlock sequence after it has been written to a ‘1’, writing two bytes con- secutively to the NVMKEY register. A sample assembly sequence is shown in Example 19-1. If WRLOCK is already cleared, it can be set to ‘ 1’ without using the unlock sequence.

19.2.3 SELECTING RTCC CLOCK SOURCE

The clock source for the RTCC module can be selected using the CLKSEL[1:0] bits in the RTCCON2L register. When the bits are set to ‘00’, the Secondary Oscillator (SOSC) is used as the reference clock and when the bits are ‘01’, LPRC is used as the reference clock. When CLKSEL[1:0] = 10, the external powerline (50 Hz and 60 Hz) is used as the clock source. When CLKSEL[1:0] = 11, the system clock is used as the clock source. EXAMPLE 19-1: SETTING THE WRLOCK BIT Note: To avoid accidental writes to the timer, it is recommended that the WRLOCK bit (RTCCON1L[11]) is kept clear at any other time. For the WRLOCK bit to be set, there is only one instruction cycle time window allowed between the 55h/AA sequence and the setting of WRLOCK; therefore, it is recommended that code follow the procedure in Example 19-1. DISI #6 ;disable interrupts for 6 instructions MOV #NVKEY, W1 MOV #0x55, W2 ; first unlock code MOV W2, [W1] ; write first unlock code MOV #0xAA, W3 ; second unlock sequence MOV W3, [W1] ; write second unlock sequence BCLR RTCCON1L, #WRLOCK ; clear the WRLOCK bit

DS30010198B-page 238  2019-2020 Microchip Technology Inc.

19.3 RTCC Registers

19.3.1 RTCC CONTROL REGISTERS

REGISTER 19-1: RTCCON1L: RTCC CONTROL REGISTER 1 LOW R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 RTCEN — — — WRLOCK PWCEN PWCPOL PWCPOE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 RTCOE OUTSEL2 OUTSEL1 OUTSEL0 — — — TSAEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 RTCEN: RTCC Enable bit 1 = RTCC is enabled and counts from selected clock source 0 = RTCC is not enabled bit 14-12 Unimplemented: Read as ‘0’ bit 11 WRLOCK: RTCC Register Write Lock bit 1 = RTCC registers are locked 0 = RTCC registers may be written to by user bit 10 PWCEN: Power Control Enable bit 1 = Power control is enabled 0 = Power control is disabled bit 9 PWCPOL: Power Control Polarity bit 1 = Power control output is active-high 0 = Power control output is active-low bit 8 PWCPOE: Power Control Output Enable bit 1 = Power control output pin is enabled 0 = Power control output pin is disabled bit 7 RTCOE: RTCC Output Enable bit 1 = RTCC output is enabled 0 = RTCC output is disabled bit 6-4 OUTSEL[2:0]: RTCC Output Signal Selection bits 111 = Unused 110 = Unused 101 = Unused 100 = Timestamp A event 011 = Power control 010 = RTCC input clock 001 = Second clock 000 = Alarm event bit 3-1 Unimplemented: Read as ‘0’ bit 0 TSAEN: Timestamp A Enable bit 1 = Timestamp event will occur when a low pulse is detected on the TMPRN pin 0 = Timestamp is disabled

 2019-2020 Microchip Technology Inc. DS30010198B-page 239 PIC24FJ128GL306 FAMILY REGISTER 19-2: RTCCON1H: RTCC CONTROL REGISTER 1 HIGH R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ALRMEN CHIME — — AMASK3 AMASK2 AMASK1 AMASK0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALMRPT7 ALMRPT6 ALMRPT5 ALMRPT4 ALMRPT3 ALMRPT2 ALMRPT1 ALMRPT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ALMRPT[7:0] = 00h and CHIME = 0) 0 = Alarm is disabled bit 14 CHIME: Chime Enable bit 1 = Chime is enabled; ALMRPT[7:0] bits roll over from 00h to FFh 0 = Chime is disabled; ALMRPT[7:0] bits stop once they reach 00h bit 13-12 Unimplemented: Read as ‘0’ bit 11-8 AMASK[3:0]: Alarm Mask Configuration bits 0000 = Every half second 0001 = Every second 0010 = Every ten seconds 0011 = Every minute 0100 = Every ten minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29th, once every four years) 101x = Reserved – do not use 11xx = Reserved – do not use bit 7-0 ALMRPT[7:0]: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times 00000000 = Alarm will repeat 0 more times The counter decrements on any alarm event. The counter is prevented from rolling over from ‘00’ to ‘FF’ unless CHIME = 1.

DS30010198B-page 240  2019-2020 Microchip Technology Inc. REGISTER 19-3: RTCCON2L: RT CC CONTROL REGISTER 2 LOW R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 PWCPS1 PWCPS0 PS1 PS0 — — CLKSEL1 CLKSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 FDIV[4:0]: Fractional Clock Divide bits 00000 = No fractional clock division 00001 = Increase period by 1 RTCC input clock cycle every 16 seconds 00010 = Increase period by 2 RTCC input clock cycles every 16 seconds 11101 = Increase period by 30 RTCC input clock cycles every 16 seconds 11111 = Increase period by 31 RTCC input clock cycles every 16 seconds bit 10-8 Unimplemented: Read as ‘0’ bit 7-6 PWCPS[1:0]: Power Control Prescale Select bits 00 = 1:1 01 = 1:16 10 = 1:64 11 = 1:256 bit 5-4 PS[1:0]: Prescale Select bits 00 = 1:1 01 = 1:16 10 = 1:64 11 = 1:256 bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CLKSEL[1:0]: Clock Select bits 00 = SOSC 01 = LPRC 10 = PWRLCLK pin 11 = System clock

 2019-2020 Microchip Technology Inc. DS30010198B-page 241 PIC24FJ128GL306 FAMILY

19.3.2 RTCVAL REGISTER MAPPINGS

REGISTER 19-4: RTCCON2H: RTCC CONTROL REGISTER 2 HIGH(1) R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 DIV[15:8] bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 DIV[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 DIV[15:0]: Clock Divide bits Sets the period of the clock divider counter; value should cause a nominal 1/2 second underflow. Note 1: A write to this register is only allowed when WRLOCK = 1.

DS30010198B-page 242  2019-2020 Microchip Technology Inc. REGISTER 19-5: RTCCON3L: RT CC CONTROL REGISTER 3 LOW R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWCSAMP[7:0] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWCSTAB7:0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 PWCSAMP[7:0]: Power Control Sample Window Timer bits 11111111 = Sample window is always enabled, even when PWCEN = 0 11111110 = Sample window is 254 TPWCCLK clock periods 00000001 = Sample window is 1 T PWCCLK clock period 00000000 = No sample window bit 7-0 PWCSTAB[7:0]: Power Control Stability Window Timer bits(1) 11111111 = Stability window is 255 TPWCCLK clock periods 11111110 = Stability window is 254 TPWCCLK clock periods 00000001 = Stability window is 1 T PWCCLK clock period 00000000 = No stability window; sample window starts when the alarm event triggers Note 1: The sample window always starts when the stability window timer expires, except when its initial value is 00h.

 2019-2020 Microchip Technology Inc. DS30010198B-page 243 PIC24FJ128GL306 FAMILY REGISTER 19-6: RTCSTATL: RTCC STATUS REGISTER LOW U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 R/C-0 U-0 R/C-0 R-0 R-0 R-0 — — ALMEVT — TSAEVT (1) SYNC ALMSYNC HALFSEC (2) bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 ALMEVT: Alarm Event bit 1 = An alarm event has occurred 0 = An alarm event has not occurred bit 4 Unimplemented: Read as ‘0’ bit 3 TSAEVT: Timestamp A Event bit (1) 1 = A timestamp event has occurred 0 = A timestamp event has not occurred bit 2 SYNC: Synchronization Status bit 1 = TIMEL/H registers may change during software read 0 = TIMEL/H registers may be read safely bit 1 ALMSYNC: Alarm Synchronization Status bit 1 = Alarm registers (ALMTIMEL/H and ALMDATEL/H) and Alarm Mask Configuration bits (AMASK[3:0]) should not be modified, and Alarm control bits (ALRMEN, ALMRPT[7:0]) may change during software read 0 = Alarm registers and Alarm control bits may be written/modified safely bit 0 HALFSEC: Half Second Status bit(2) 1 = Second half period of a second 0 = First half period of a second Note 1: User software may write a ‘1’ to this location to initiate a Timestamp A event; timestamp capture is not valid until TSAEVT reads as ‘1’. 2: This bit is read-only; it is cleared to ‘0’ on a write to the SECONE[3:0] bits.

DS30010198B-page 244  2019-2020 Microchip Technology Inc.

19.3.3 RTCC VALUE REGISTERS

REGISTER 19-7: TIMEL: RTCC TIME REGISTER LOW U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 SECTEN[2:0]: Binary Coded Decimal Value of Seconds ‘10’ Digit bits Contains a value from 0 to 5. bit 11-8 SECONE[3:0]: Binary Coded Decimal Value of Seconds ‘1’ Digit bits Contains a value from 0 to 9. bit 7-0 Unimplemented: Read as ‘0’ REGISTER 19-8: TIMEH: RTCC TIME REGISTER HIGH U-0 U-0 R/W-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-12 HRTEN[1:0]: Binary Coded Decimal Value of Hours ‘10’ Digit bits Contains a value from 0 to 2. bit 11-8 HRONE[3:0]: Binary Coded Decimal Value of Hours ‘1’ Digit bits Contains a value from 0 to 9. bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINTEN[2:0]: Binary Coded Decimal Value of Minutes ‘10’ Digit bits Contains a value from 0 to 5. bit 3-0 MINONE[3:0]: Binary Coded Decimal Value of Minutes ‘1’ Digit bits Contains a value from 0 to 9.

 2019-2020 Microchip Technology Inc. DS30010198B-page 245 PIC24FJ128GL306 FAMILY REGISTER 19-9: DATEL: RTCC DATE REGISTER LOW U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-12 DAYTEN[1:0]: Binary Coded Decimal Value of Days ‘10’ Digit bits Contains a value from 0 to 3. bit 11-8 DAYONE[3:0]: Binary Coded Decimal Value of Days ‘1’ Digit bits Contains a value from 0 to 9. bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 WDAY[2:0]: Binary Coded Decimal Value of Weekdays ‘1’ Digit bits Contains a value from 0 to 6. REGISTER 19-10: DATEH: RTCC DATE REGISTER HIGH R/W-0 R/W-0 R/W-0 R/W-0 R/W-x R/W-x R/W-x R/W-x YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 bit 15 bit 8 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 YRTEN[3:0]: Binary Coded Decimal Value of Years ‘10’ Digit bits bit 11-8 YRONE[3:0]: Binary Coded Decimal Value of Years ‘1’ Digit bits bit 7-5 Unimplemented: Read as ‘0’ bit 4 MTHTEN: Binary Coded Decimal Value of Months ‘10’ Digit bit Contains a value either 0 or 1. bit 3-0 MTHONE[3:0]: Binary Coded Decimal Value of Months ‘1’ Digit bits Contains a value from 0 to 9.

DS30010198B-page 246  2019-2020 Microchip Technology Inc.

19.3.4 ALARM VALUE REGISTERS

REGISTER 19-11: ALMTIMEL: RTCC ALARM TIME REGISTER LOW U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 SECTEN[2:0]: Binary Coded Decimal Value of Seconds ‘10’ Digit bits Contains a value from 0 to 5. bit 11-8 SECONE[3:0]: Binary Coded Decimal Value of Seconds ‘1’ Digit bits Contains a value from 0 to 9. bit 7-0 Unimplemented: Read as ‘0’ REGISTER 19-12: ALMTIMEH: RTCC ALARM TIME REGISTER HIGH U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-12 HRTEN[1:0]: Binary Coded Decimal Value of Hours ‘10’ Digit bits Contains a value from 0 to 2. bit 11-8 HRONE[3:0]: Binary Coded Decimal Value of Hours ‘1’ Digit bits Contains a value from 0 to 9. bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINTEN[2:0]: Binary Coded Decimal Value of Minutes ‘10’ Digit bits Contains a value from 0 to 5. bit 3-0 MINONE[3:0]: Binary Coded Decimal Value of Minutes ‘1’ Digit bits Contains a value from 0 to 9.

 2019-2020 Microchip Technology Inc. DS30010198B-page 247 PIC24FJ128GL306 FAMILY REGISTER 19-13: ALMDATEL: RTCC ALARM DATE REGISTER LOW U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — WDAY2 WDAY1 WDAY0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-12 DAYTEN[1:0]: Binary Coded Decimal Value of Days ‘10’ Digit bits Contains a value from 0 to 3. bit 11-8 DAYONE[3:0]: Binary Coded Decimal Value of Days ‘1’ Digit bits Contains a value from 0 to 9. bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 WDAY[2:0]: Binary Coded Decimal Value of Weekdays ‘1’ Digit bits Contains a value from 0 to 6. REGISTER 19-14: ALMDATEH: RTCC ALARM DATE REGISTER HIGH R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — MTHTEN MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 YRTEN[3:0]: Binary Coded Decimal Value of Years ‘10’ Digit bits bit 11-8 YRONE[3:0]: Binary Coded Decimal Value of Years ‘1’ Digit bits bit 7-5 Unimplemented: Read as ‘0’ bit 4 MTHTEN: Binary Coded Decimal Value of Months ‘10’ Digit bit Contains a value either 0 or 1. bit 3-0 MTHONE[3:0]: Binary Coded Decimal Value of Months ‘1’ Digit bits Contains a value from 0 to 9.

DS30010198B-page 248  2019-2020 Microchip Technology Inc.

19.3.5 TIMESTAMP REGISTERS

REGISTER 19-15: TSATIMEL: RTCC TIMESTAMP A TIME REGISTER LOW(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 SECTEN[2:0]: Binary Coded Decimal Value of Seconds ‘10’ Digit bits Contains a value from 0 to 5. bit 11-8 SECONE[3:0]: Binary Coded Decimal Value of Seconds ‘1’ Digit bits Contains a value from 0 to 9. bit 7-0 Unimplemented: Read as ‘0’ Note 1: If TSAEN = 0, bits[15:0] can be used for persistent storage throughout a non-Power-on Reset (MCLR, WDT, etc.).

 2019-2020 Microchip Technology Inc. DS30010198B-page 249 PIC24FJ128GL306 FAMILY REGISTER 19-16: TSATIMEH: RTCC TIMESTAMP A TIME REGISTER HIGH(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-12 HRTEN[1:0]: Binary Coded Decimal Value of Hours ‘10’ Digit bits Contains a value from 0 to 2. bit 11-8 HRONE[3:0]: Binary Coded Decimal Value of Hours ‘1’ Digit bits Contains a value from 0 to 9. bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINTEN[2:0]: Binary Coded Decimal Value of Minutes ‘10’ Digit bits Contains a value from 0 to 5. bit 3-0 MINONE[3:0]: Binary Coded Decimal Value of Minutes ‘1’ Digit bits Contains a value from 0 to 9. Note 1: If TSAEN = 0, bits[15:0] can be used for persistence storage throughout a non-Power-on Reset (MCLR WDT, etc.).

DS30010198B-page 250  2019-2020 Microchip Technology Inc. REGISTER 19-17: TSADATEL: RTCC TIMESTAMP A DATE REGISTER LOW(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — WDAY2 WDAY1 WDAY0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-12 DAYTEN[1:0]: Binary Coded Decimal Value of Days ‘10’ Digit bits Contains a value from 0 to 3. bit 11-8 DAYONE[3:0]: Binary Coded Decimal Value of Days ‘1’ Digit bits Contains a value from 0 to 9. bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 WDAY[2:0]: Binary Coded Decimal Value of Weekdays ‘1’ Digit bits Contains a value from 0 to 6. Note 1: If TSAEN = 0, bits[15:0] can be used for persistence storage throughout a non-Power-on Reset (MCLR, WDT, etc.).

 2019-2020 Microchip Technology Inc. DS30010198B-page 251 PIC24FJ128GL306 FAMILY REGISTER 19-18: TSADATEH: RTCC TIMESTAMP A DATE REGISTER HIGH(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — MTHTEN MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 YRTEN[3:0]: Binary Coded Decimal Value of Years ‘10’ Digit bits bit 11-8 YRONE[3:0]: Binary Coded Decimal Value of Years ‘1’ Digit bits bit 7-5 Unimplemented: Read as ‘0’ bit 4 MTHTEN: Binary Coded Decimal Value of Months ‘10’ Digit bit Contains a value either 0 or 1. bit 3-0 MTHONE[2:0]: Binary Coded Decimal Value of Months ‘1’ Digit bits Contains a value from 0 to 9. Note 1: If TSAEN = 0, bits[15:0] can be used for persistence storage throughout a non-Power-on Reset (MCLR WDT, etc.).

DS30010198B-page 252  2019-2020 Microchip Technology Inc.

19.4 Calibration

19.4.1 CLOCK SOURCE CALIBRATION

A crystal oscillator that is connected to the RTCC may be calibrated to provide an accurate 1-second clock in two ways. First, coarse frequency adjustment is per- formed by adjusting the value written to the DIV[15:0] bits. Secondly, a 5-bit value can be written to the FDIV[4:0] control bits to perform a fine clock division. The DIVx and FDIVx values can be concatenated and considered as a 21-bit prescaler value. If the oscillator source is slightly faster than ideal, the FDIV[4:0] value can be increased to make a small decrease in the RTC frequency. The value of DIV[15:0] should be increased to make larger decreases in the RTC frequency. If the oscillator source is slower than ideal, FDIV[4:0] may be decreased for small calibration changes and DIV[15:0] may need to be decreased to make larger calibration changes. Before calibration, the user must determine the error of the crystal. This should be done using another timer resource on the device or an external timing reference. It is up to the user to include in the error value, the initial error of the crystal, drift due to temperature and drift due to crystal aging.

19.5 Alarm

• Configurable from half second to one year
• Enabled using the ALRMEN bit (RTCCON1H[15])
• One-time alarm and repeat alarm options are available

19.5.1 CONFIGURING THE ALARM

The alarm feature is enabled using the ALRMEN bit. This bit is cleared when an alarm is issued. Writes to the Alarm Value registers should only take place when ALRMEN = 0. As shown in Figure 19-2, the interval selection of the alarm is configured through the AMASK[3:0] bits (RTCCON1H[11:8]). These bits determine which and how many digits of the alarm must match the clock value for the alarm to occur. The alarm can also be configured to repeat based on a preconfigured interval. The amount of times this occurs, once the alarm is enabled, is stored in the ALMRPT[7:0] bits (RTCCON1H[7:0]). When the value of the ALMRPTx bits equals 00h and the CHIME bit (RTCCON1H[14]) is cleared, the repeat function is dis- abled and only a single alarm will occur. The alarm can be repeated, up to 255 times, by loading ALMRPT[7:0] with FFh. After each alarm is issued, the value of the ALMRPTx bits is decremented by one. Once the value has reached 00h, the alarm will be issued one last time, after which, the ALRMEN bit will be cleared automatically and the alarm will turn off. Indefinite repetition of the alarm can occur if the CHIME bit = 1. Instead of the alarm being disabled when the value of the ALMRPTx bits reaches 00h, it rolls over to FFh and continues counting indefinitely while CHIME is set.

19.5.2 ALARM INTERRUPT

At every alarm event, an interrupt is generated. This output is completely synchronous to the RTCC clock and can be used as a trigger clock to the other peripherals. Note: Changing any of the register bits, other than the RTCOE bit (RTCCON1L[7]), the ALMRPT[7:0] bits (RTCCON1H[7:0] and the CHIME bit, while the alarm is enabled (ALRMEN = 1), can result in a false alarm event leading to a false alarm interrupt. To avoid a false alarm event, the timer and alarm values should only be changed while the alarm is disabled (ALRMEN = 0).

 2019-2020 Microchip Technology Inc. DS30010198B-page 253 PIC24FJ128GL306 FAMILY FIGURE 19-2: ALARM MASK SETTINGS

19.6 Power Control

The RTCC includes a power control feature that allows the device to periodically wake-up an external device, wait for the device to be stable before sampling wake-up events from that device and then shut down the external device. This can be done completely autonomously by the RTCC, without the need to wake-up from the current lower power mode. To use this feature: 1. Enable the RTCC (RTCEN = 1). 2. Set the PWCEN bit (RTCCON1L[10]). 3. Configure the RTCC pin to drive the PWC control signal (RTCOE = 1 and OUTSEL[2:0] = 011). The polarity of the PWC control signal may be chosen using the PWCPOL bit (RTCCON1L[9]). An active-low or active-high signal may be used with the appropriate external switch to turn on or off the power to one or more external devices. The active-low setting may also be used in conjunction with an open-drain setting on the RTCC pin, in order to drive the ground pin(s) of the external device directly (with the appropriate external V DD pull-up device), without the need for external switches. Finally, the CHIME bit should be set to enable the PWC periodicity. Once the RTCC and PWC are enabled and running, the PWC logic will generate a control output and a sample gate output. The control output is driven out on the RTCC pin (when RTCOE = 1 and OUTSEL[2:0] = 011) and is used to power up or down the device, as described above. Once the control output is asserted, the stability window begins, in which the external device is given enough time to power up and provide a stable output. Once the output is stable, the RTCC provides a sample gate during the sample window. The use of this sample gate depends on the external device being used, but typically, it is used to mask out one or more wake-up signals from the external device. Finally, both the stability and the sample windows close after the expiration of the sample window and the external device is powered down. Note 1: Annually, except when configured for February 29. s ss ms s mm s s hh m m ss dh h m m s s dd hh m m ss mm d d h h mm s s Day of the Week Month Day Hours Minutes Seconds Alarm Mask Setting (AMASK[3:0]) 0000 - Every half second 0001 - Every second 0010 - Every 10 seconds 0011 - Every minute 0100 - Every 10 minutes 0101 - Every hour 0110 - Every day 0111 - Every week 1000 - Every month 1001 - Every year(1)

DS30010198B-page 254  2019-2020 Microchip Technology Inc.

19.6.1 POWER CONTROL CLOCK SOURCE

The stability and sample windows are controlled by the PWCSAMPx and PWCSTABx bit fields in the RTCCON3L register (RTCCON3L[15:8] and [7:0], respectively). As both the stability and sample windows are defined in terms of the RTCC clock, their absolute values vary by the value of the PWC clock base period (T PWCCLK). For example, using a 32.768 kHz SOSC input clock would produce a T PWCCLK of 1/32768 = 30.518 µs. The 8-bit magnitude of PWCSTABx and PWCSAMPx allows for a window size of 0 to 255 TPWCCLK. The period of the PWC clock can also be adjusted with a 1:1, 1:16, 1:64 or 1:256 prescaler, determined by the PWCPS[1:0] bits (RTCCON2L[7:6]). In addition, certain values for the PWCSTABx and PWCSAMPx fields have specific control meanings in determining power control operations. If either bit field is 00h, the corresponding window is inactive. In addition, if the PWCSTABx field is FFh, the stability window remains active continuously, even if power control is disabled.

19.7 Event Timestamping

The RTCC includes a set of Timestamp registers that may be used for the capture of Time and Date register values when an external input signal is received. The RTCC will trigger a timestamp event when a low pulse occurs on the TMPRN pin.

19.7.1 TIMESTAMP OPERATION

The event input is enabled for timestamping using the TSAEN bit (RTCCON1L[0]). When the timestamp event occurs, the present time and date values will be stored in the TSATIMEL/H and TSADATEL/H registers, the TSAEVT status bit (RTCSTATL[3]) will be set and an RTCC interrupt will occur. A new timestamp capture event cannot occur until the user clears the TSAEVT status bit.

19.7.2 MANUAL TIMESTAMP OPERATION

The current time and date may be captured in the TSATIMEL/H and TSADATEL/H registers by writing a ‘1’ to the TSAEVT bit location while the timestamp func- tionality is enabled (TSAEN = 1). This write will not set the TSAEVT bit, but it will initiate a timestamp capture. The TSAEVT bit will be set when the capture operation is complete. The user must poll the TSAEVT bit to determine when the capture operation is complete. After the Timestamp registers have been read, the TSAEVT bit should be cleared to allow further hardware or software timestamp capture events. Note 1: The TSATIMEL/H and TSADATEL/H regis- ter pairs can be used for data storage when TSAEN = 0. The values of TSATIMEL/H and TSADATEL/H will be maintained throughout all types of non-Power-on Resets (MCLR , WDT, etc).

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20.1 User Interface

20.1.1 POLYNOMIAL INTERFACE

The CRC module can be programmed for CRC polynomials of up to the 32nd order, using up to 32 bits. Polynomial length, which reflects the highest exponent in the equation, is selected by the PLEN[4:0] bits (CRCCON2[4:0]). The CRCXORL and CRCXORH registers control which exponent terms are included in the equation. Setting a particular bit includes that exponent term in the equa- tion. Functionally, this includes an XOR operation on the corresponding bit in the CRC engine. Clearing the bit disables the XOR. For example, consider two CRC polynomials, one a 16-bit and the other a 32-bit equation. EQUATION 20-1: 16-BIT, 32-BIT CRC POLYNOMIALS To program these polynomials into the CRC generator, set the register bits, as shown in Table 20-1. Note that the appropriate positions are set to ‘1’ to indi- cate that they are used in the equation (for example, X26 and X23). The ‘0’ bit required by the equation is always XORed; thus, X0 is a don’t care. For a poly- nomial of length 32, it is assumed that the 32 nd bit will be used. Therefore, the X[31:1] bits do not have the 32nd bit.

20.1.2 DATA INTERFACE

The module incorporates a FIFO that works with a variable datum width. Input datum width can be config- ured to any value, between 1 and 32 bits, using the DWIDTH[4:0] bits (CRCCON2[12:8]). When the datum width is greater than 15, the FIFO is 4 words deep. When the DWIDTHx bits are between 15 and 8, the FIFO is 8 words deep. When the DWIDTHx bits are less than 8, the FIFO is 16 words deep. The data for which the CRC is to be calculated must first be written into the FIFO. Even if the datum width is less than 8, the smallest data element that can be written into the FIFO is 1 byte. For example, if the DWIDTHx bits are 5, then the size of the data is DWIDTH[4:0] + 1 or 6. The data are written as a whole byte; the two unused upper bits are ignored by the module. Once datum is written into the MSb of the CRCDAT reg- isters (that is, the MSb as defined by the datum width), the value of the VWORD[4:0] bits (CRCCON1[12:8]) increments by one. For example, if the DWIDTHx bits are 24, the VWORDx bits will increment when bit 7 of CRCDATH is written. Therefore, CRCDATL must always be written to before CRCDATH. The CRC engine starts shifting data when the CRCGO bit (CRCCON1[4]) is set and the value of the VWORDx bits is greater than zero. Each word is copied out of the FIFO into a buffer register, which decrements the VWORDx bits. The data are then shifted out of the buffer. The CRC engine continues shifting at a rate of two bits per instruction cycle, until the VWORDx bits reach zero. This means that for a given data width, it takes half that number of instructions for each word to complete the calculation. For example, it takes 16 cycles to calculate the CRC for a single word of 32-bit data. When the VWORDx bits reach the maximum value for the configured value of the DWIDTHx bits (4, 8 or 16), the CRCFUL bit (CRCCON1[7]) becomes set. When the VWORDx bits reac h zero, the CRCMPT bit (CRCCON1[6]) becomes set. The FIFO is emptied and the VWORD[4:0] bits are set to ‘ 00000’ whenever CRCEN is ‘0’. At least one instruction cycle must pass after a write to CRCWDAT before a read of the VWORDx bits is done. and X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 X16 + X12 + X5 + 1 TABLE 20-1: CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIALS CRC Control Bits Bit Values 16-Bit Polynomial 32-Bit Polynomial PLEN[4:0] 01111 11111 X[31:16] 0000 0000 0000 0001 0000 0100 1100 0001 X[15:1] 0001 0000 0010 000 0001 1101 1011 011

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20.1.3 DATA SHIFT DIRECTION

The LENDIAN bit (CRCCON1[3]) is used to control the shift direction. By default, the CRC will shift data through the engine, MSb first. Setting LENDIAN (= 1) causes the CRC to shift data, LSb first. This setting allows better integration with various communication schemes and removes the overhead of reversing the bit order in software. Note that this only changes the direction that the data are shifted into the engine. The result of the CRC calculation will still be a normal CRC result, not a reverse CRC result.

20.1.4 INTERRUPT OPERATION

The module generates an interrupt that is configurable by the user for either of two conditions. If CRCISEL is ‘0’, an interrupt is generated when the VWORD[4:0] bits make a transition from a value of ‘1’ to ‘0’. If CRCISEL is ‘1’, an interrupt will be generated after the CRC operation finishes and the module sets the CRCGO bit to ‘0’. Manually setting CRCGO to ‘0’ will not generate an interrupt. Note that when an interrupt occurs, the CRC calculation would not yet be complete. The module will still need (PLENx + 1)/2 clock cycles after the interrupt is generated until the CRC calculation is finished.

20.1.5 TYPICAL OPERATION

To use the module for a typical CRC calculation: 1. Set the CRCEN bit to enable the module. 2. Configure the module for desired operation: a) Program the desired polynomial using the CRCXOR registers and PLEN[4:0] bits. b) Configure the data width and shift direction using the DWIDTH[4:0] and LENDIAN bits. 3. Set the CRCGO bit to start the calculations. 4. Set the desired CRC non-direct initial value by writing to the CRCWDAT registers. 5. Load all data into the FIFO by writing to the CRCDAT registers as space becomes available (the CRCFUL bit must be zero before the next data loading). 6. Wait until the data FIFO is empty (CRCMPT bit is set). 7. Read the result: If the data width (DWIDTH[4:0] bits) is more than the polynomial length (PLEN[4:0] bits): a) Wait (DWIDTH[4:0] + 1)/2 instruction cycles to make sure that shifts from the shift buffer are finished. b) Change the data width to the polynomial length (DWIDTH[4:0] = PLEN[4:0]). c) Write one dummy data word to the CRCDAT registers. d) Wait two instruction cycles to move the data from the FIFO to the shift buffer and (PLEN[4:0] + 1)/2 instruction cycles to shift out the result. Or, if the data width (DWIDTH[4:0] bits) is less than the polynomial length (PLEN[4:0] bits): 1. Clear the CRC Interrupt Selection bit (CRCISEL = 0) to get the interrupt when all shifts are done. Clear the CRC interrupt flag. Write dummy data in the CRCDAT registers and wait until the CRC interrupt flag is set. 2. Read the final CRC result from the CRCWDAT registers. 3. Restore the data width (DWIDTH[4:0] bits) for further calculations (optional). If the data width (DWIDTH[4:0] bits) is equal to, or less than, the polynomial length (PLEN[4:0] bits): a) Clear the CRC Interrupt Selection bit (CRCISEL = 0) to get the interrupt when all shifts are done. b) Suspend the calculation by setting CRCGO = 0. c) Clear the CRC interrupt flag. d) Write the dummy data with the total data length equal to the polynomial length in the CRCDAT registers. e) Resume the calculation by setting CRCGO = 1. f) Wait until the CRC interrupt flag is set. g) Read the final CRC result from the CRCWDAT registers. There are eight registers used to control programmable CRC operation:

• CRCCON1
• CRCCON2
• CRCXORL
• CRCXORH
• CRCDATL
• CRCDATH
• CRCWDATL
• CRCWDATH The CRCCON1 and CRCCON2 registers (Register 20-1 and Register 20-2) control the operation of the module and configure the various settings. The CRCXOR registers ( Register 20-3 and Register 20-4) select the polynomial terms to be used in the CRC equation. The CRCDAT and CRCWDAT registers are each register pairs that serve as buffers for the double-word input data, and CRC processed output, respectively.

DS30010198B-page 258  2019-2020 Microchip Technology Inc. REGISTER 20-1: CRCCON1: C RC CONTROL 1 REGISTER R/W-0 U-0 R/W-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 CRCEN — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 bit 15 bit 8 HSC/R-0 HSC/R-1 R/W-0 HC/R/W-0 R/W-0 U-0 U-0 U-0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — bit 7 bit 0 Legend: HC = Hardware Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CRCEN: CRC Enable bit 1 = Enables module 0 = Disables module; all state machines, pointers and CRCWDAT/CRCDAT registers reset; other SFRs are NOT reset bit 14 Unimplemented: Read as ‘0’ bit 13 CSIDL: CRC Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-8 VWORD[4:0]: CRC Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN[4:0]  7 or 16 when PLEN[4:0] 7. bit 7 CRCFUL: CRC FIFO Full bit 1 = FIFO is full 0 = FIFO is not full bit 6 CRCMPT: CRC FIFO Empty bit 1 = FIFO is empty 0 = FIFO is not empty bit 5 CRCISEL: CRC Interrupt Selection bit 1 = Interrupt on FIFO is empty; the final word of datum is still shifting through the CRC 0 = Interrupt on shift is complete and results are ready bit 4 CRCGO: Start CRC bit 1 = Starts CRC serial shifter 0 = CRC serial shifter is turned off bit 3 LENDIAN: Data Shift Direction Select bit 1 = Data word is shifted into the CRC, starting with the LSb (little endian) 0 = Data word is shifted into the CRC, starting with the MSb (big endian) bit 2-0 Unimplemented: Read as ‘0’

 2019-2020 Microchip Technology Inc. DS30010198B-page 259 PIC24FJ128GL306 FAMILY REGISTER 20-2: CRCCON2: C RC CONTROL 2 REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 DWIDTH[4:0]: CRC Data Word Width Configuration bits Configures the width of the data word (Data Word Width – 1). bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 PLEN[4:0]: Polynomial Length Configuration bits Configures the length of the polynomial (Polynomial Length – 1).

DS30010198B-page 260  2019-2020 Microchip Technology Inc. REGISTER 20-3: CRCXORL: CRC XO R POLYNOMIAL REGISTER LOW R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X[15:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 X[7:1] — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 X[15:1]: XOR of Polynomial Term X n Enable bits bit 0 Unimplemented: Read as ‘0’ REGISTER 20-4: CRCXORH: CRC XOR POLYNOMIAL REGISTER HIGH R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X[31:24] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X[23:16] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 X[31:16]: XOR of Polynomial Term Xn Enable bits

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21.0 CONFIGURABLE LOGIC CELL

(CLC) The Configurable Logic Cell (CLC) module allows the user to specify combinations of signals as inputs to a logic function and to use the logic output to control other peripherals or I/O pins. This provides greater flexibility and potential in embedded designs, since the CLC module can operate outside the limitations of software execution and supports a vast amount of output designs. There are four input gates to the selected logic func- tion. These four input gates select from a pool of up to 32 signals that are selected using four data source selection multiplexers. Figure 21-1 shows an overview of the module. Figure 21-3 shows the details of the data source multiplexers and logic input gate connections. FIGURE 21-1: CLCx MODULE Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive refer- ence source. For more information, refer to “Configurable Logic Cell (CLC)” (www.microchip.com/DS70005298) in the “dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. Gate 1 Gate 2 Gate 3 Gate 4 Logic Function Input Data Selection Gates CLCx LCOE Logic LCPOL MODE[2:0] CLCx CLCIN[0] CLCIN[1] CLCIN[2] CLCIN[3] CLCIN[4] CLCIN[5] CLCIN[6] CLCIN[7] CLCIN[8] CLCIN[9] CLCIN[10] CLCIN[11] CLCIN[12] CLCIN[13] CLCIN[14] CLCIN[15] TRISx Control Interrupt det INTP INTN LCEN CLCxIF Sets Flag Note: All register bits shown in this figure can be found in the CLCxCONL register. Output Output CLCIN[16] CLCIN[17] CLCIN[18] CLCIN[19] CLCIN[20] CLCIN[21] CLCIN[22] CLCIN[23] CLCIN[24] CLCIN[25] CLCIN[26] CLCIN[27] CLCIN[28] CLCIN[29] CLCIN[30] CLCIN[31] See Figure 21-2 See Figure 21-3 Interrupt det

DS30010198B-page 262  2019-2020 Microchip Technology Inc. FIGURE 21-2: CLCx LOGIC FUNCTION COMBINATORIAL OPTIONS Gate 1 Gate 2 Gate 3 Gate 4 Logic Output Gate 1 Gate 2 Gate 3 Gate 4 Logic Output Gate 1 Gate 2 Gate 3 Gate 4 Logic Output S R Q Gate 1 Gate 2 Gate 3 Gate 4 Logic Output DQ Gate 1 Gate 2 Gate 3 Gate 4 Logic Output S R JQGate 2 Gate 3 Gate 4 Logic Output R Gate 1 K DQ Gate 1 Gate 2 Gate 3 Gate 4 Logic Output S R DQ Gate 1 Gate 3 Logic Output R Gate 4 Gate 2 MODE[2:0] = 000 MODE[2:0] = 010 MODE[2:0] = 001 MODE[2:0] = 011 MODE[2:0] = 100 MODE[2:0] = 110 MODE[2:0] = 101 MODE[2:0] = 111 LE AND – OR OR – XOR 4-Input AND S-R Latch 1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R 1-Input Transparent Latch with S and RJ-K Flip-Flop with R

 2019-2020 Microchip Technology Inc. DS30010198B-page 263 PIC24FJ128GL306 FAMILY FIGURE 21-3: CLCx INPUT SOURCE SELECTION DIAGRAM Gate 1 G1POL Data Gate 1 G1D1T Gate 2 Gate 3 Gate 4 Data Gate 2 Data Gate 3 Data Gate 4 G1D1N DS1x (CLCxSEL[2:0]) DS2x (CLCxSEL[6:4]) CLCIN[0] CLCIN[1] CLCIN[2] CLCIN[5] CLCIN[6] CLCIN[7] Data Selection Note: All controls are undefined at power-up. Data 1 Noninverted Data 1 Data 2 Noninverted Data 2 Data 3 Noninverted Data 3 Data 4 Noninverted Data 4 (Same as Data Gate 1) (Same as Data Gate 1) (Same as Data Gate 1) G1D2T G1D2N G1D3T G1D3N G1D4T G1D4N Inverted Inverted Inverted Inverted CLCIN[8] CLCIN[9] CLCIN[10] CLCIN[13] CLCIN[14] CLCIN[15] CLCIN[3] CLCIN[4] CLCIN[11] CLCIN[12] CLCIN[18] CLCIN[21] CLCIN[22] CLCIN[23] CLCIN[19] CLCIN[20] CLCIN[17] CLCIN[16] DS3x (CLCxSEL[10:8]) CLCIN[26] CLCIN[29] CLCIN[30] CLCIN[31] CLCIN[27] CLCIN[28] CLCIN[25] CLCIN[24] DS4x (CLCxSEL[14:12]) 000 111 000 111 000 111 000 111 (CLCxCONH[0])

DS30010198B-page 264  2019-2020 Microchip Technology Inc.

21.1 Control Registers

The CLCx module is controlled by the following registers:

• C L C x C O N L
• C L C x C O N H
• CLCxSEL
• C L C x G L S L
• C L C x G L S H The CLCx Control registers (CLCxCONL and CLCxCONH) are used to enable the module and inter- rupts, control the output enable bit, select output polarity and select the logic function. The CLCx Control registers also allow the user to control the logic polarity of not only the cell output, but also some intermediate variables. The CLCx Input MUX Select register (CLCxSEL) allows the user to select up to four data input sources using the four data input selection multiplexers. Each multiplexer has a list of eight data sources available. The CLCx Gate Logic Input Select registers (CLCxGLSL and CLCxGLSH) allow the user to select which outputs from each of the selection MUXes are used as inputs to the input gates of the logic cell. Each data source MUX outputs both a true and a negated version of its output. All of these eight signals are enabled, ORed together by the logic cell input gates. If no gate inputs are selected, the output will be zero or one, depending on the GxPOL bits. REGISTER 21-1: CLCxCONL: CL Cx CONTROL REGISTER LOW R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 bit 15 bit 8 R/W-0 R-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 LCOE LCOUT LCPOL — — MODE2 MODE1 MODE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 LCEN: CLCx Enable bit 1 = CLCx is enabled and mixing input signals 0 = CLCx is disabled and has logic zero outputs bit 14-12 Unimplemented: Read as ‘0’ bit 11 INTP: CLCx Positive Edge Interrupt Enable bit 1 = Interrupt will be generated when a rising edge occurs on LCOUT 0 = Interrupt will not be generated bit 10 INTN: CLCx Negative Edge Interrupt Enable bit 1 = Interrupt will be generated when a falling edge occurs on LCOUT 0 = Interrupt will not be generated bit 9-8 Unimplemented: Read as ‘0’ bit 7 LCOE: CLCx Port Enable bit 1 = CLCx port pin output is enabled 0 = CLCx port pin output is disabled bit 6 LCOUT: CLCx Data Output Status bit 1 = CLCx output high 0 = CLCx output low bit 5 LCPOL: CLCx Output Polarity Control bit 1 = The output of the module is inverted 0 = The output of the module is not inverted bit 4-3 Unimplemented: Read as ‘0’

 2019-2020 Microchip Technology Inc. DS30010198B-page 265 PIC24FJ128GL306 FAMILY bit 2-0 MODE[2:0]: CLCx Mode bits 111 = Cell is a 1-input transparent latch with S and R 110 = Cell is a JK flip-flop with R 101 = Cell is a 2-input D flip-flop with R 100 = Cell is a 1-input D flip-flop with S and R 011 = Cell is an SR latch 010 = Cell is a 4-input AND 001 = Cell is an OR-XOR 000 = Cell is an AND-OR REGISTER 21-1: CLCxCONL: CLCx CO NTROL REGISTER LOW (CONTINUED) REGISTER 21-2: CLCxCONH: CLCx CONTROL REGISTER (HIGH) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — G4POL G3POL G2POL G1POL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 G4POL: Gate 4 Polarity Control bit 1 = The output of Channel 4 logic is inverted when applied to the logic cell 0 = The output of Channel 4 logic is not inverted bit 2 G3POL: Gate 3 Polarity Control bit 1 = The output of Channel 3 logic is inverted when applied to the logic cell 0 = The output of Channel 3 logic is not inverted bit 1 G2POL: Gate 2 Polarity Control bit 1 = The output of Channel 2 logic is inverted when applied to the logic cell 0 = The output of Channel 2 logic is not inverted bit 0 G1POL: Gate 1 Polarity Control bit 1 = The output of Channel 1 logic is inverted when applied to the logic cell 0 = The output of Channel 1 logic is not inverted

DS30010198B-page 266  2019-2020 Microchip Technology Inc. REGISTER 21-3: CLCxSEL: CLCx INPUT MUX SELECT REGISTER U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 —D S 4 [ 2 : 0 ] —D S 3 [ 2 : 0 ] bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 —D S 2 [ 2 : 0 ] —D S 1 [ 2 : 0 ] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 DS4[2:0]: Data Selection MUX 4 Signal Selection bits 111 = MCCP3 OC out 110 = MCCP1 OC out 101 = Unimplemented 100 = LCD automation timer interrupt 011 = SPIx Input (SDIx) corresponding to the CLCx module(1) 010 = Comparator 3 output 001 = Module-specific CLCx output(1) 000 = CLCIND I/O pin bit 11 Unimplemented: Read as ‘0’ bit 10-8 DS3[2:0]: Data Selection MUX 3 Signal Selection bits 111 = MCCP3 OC out 110 = MCCP2 OC out 101 = DMA Channel 1 interrupt 100 = UARTx RX output corresponding to the CLCx module(1) 011 = SPIx Output (SDOx) corresponding to the CLCx module(1) 010 = Comparator 2 output 001 = CLCx output(1) 000 = CLCINC I/O pin bit 7 Unimplemented: Read as ‘0’ bit 6-4 DS2[2:0]: Data Selection MUX 2 Signal Selection bits 111 = MCCP2 OC out 110 = MCCP1 OC out 101 = DMA Channel 0 interrupt 100 = A/D conversion done interrupt 011 = UARTx TX input corresponding to the CLCx module(1) 010 = Comparator 1 output 001 = CLCx output(1) 000 = CLCINB I/O pin bit 3 Unimplemented: Read as ‘0’ bit 2-0 DS1[2:0]: Data Selection MUX 1 Signal Selection bits 111 = Timer3 match event 110 = Timer2 match event 101 = Unimplemented 100 = REFO output 011 = INTRC/LPRC clock source 010 = SOSC clock source 001 = System clock (TCY) 000 = CLCINA I/O pin Note 1: For more information, see Table 21-1.

 2019-2020 Microchip Technology Inc. DS30010198B-page 267 PIC24FJ128GL306 FAMILY TABLE 21-1: MODULE-SPECIFIC INPUT DATA SOURCES Bit Field Value Input Source CLC1 CLC2 CLC3 CLC4 DS4[2:0] 011 SDI1 SDI2 SDI1 SDI2

001 CLC2 Output CLC1 Output CLC4 Output CLC3 Output

DS3[2:0]

100 U1RX U2RX U3RX U4RX

011 SDO1 SDO2 SDO1 SDO2

001 CLC1 Output CLC2 Output CLC1 Output CLC2 Output

DS2[2:0] 011 U1TX U2TX U3TX U4TX

001 CLC2 Output CLC1 Output CLC2 Output CLC1 Output

REGISTER 21-4: CLCxGLSL: CLCx GATE LOGIC INPUT SELECT LOW REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 G2D4T: Gate 2 Data Source 4 True Enable bit 1 = The Data Source 4 signal is enabled for Gate 2 0 = The Data Source 4 signal is disabled for Gate 2 bit 14 G2D4N: Gate 2 Data Source 4 Negated Enable bit 1 = The Data Source 4 inverted signal is enabled for Gate 2 0 = The Data Source 4 inverted signal is disabled for Gate 2 bit 13 G2D3T: Gate 2 Data Source 3 True Enable bit 1 = The Data Source 3 signal is enabled for Gate 2 0 = The Data Source 3 signal is disabled for Gate 2 bit 12 G2D3N: Gate 2 Data Source 3 Negated Enable bit 1 = The Data Source 3 inverted signal is enabled for Gate 2 0 = The Data Source 3 inverted signal is disabled for Gate 2 bit 11 G2D2T: Gate 2 Data Source 2 True Enable bit 1 = The Data Source 2 signal is enabled for Gate 2 0 = The Data Source 2 signal is disabled for Gate 2 bit 10 G2D2N: Gate 2 Data Source 2 Negated Enable bit 1 = The Data Source 2 inverted signal is enabled for Gate 2 0 = The Data Source 2 inverted signal is disabled for Gate 2 bit 9 G2D1T: Gate 2 Data Source 1 True Enable bit 1 = The Data Source 1 signal is enabled for Gate 2 0 = The Data Source 1 signal is disabled for Gate 2

DS30010198B-page 268  2019-2020 Microchip Technology Inc. bit 8 G2D1N: Gate 2 Data Source 1 Negated Enable bit 1 = The Data Source 1 inverted signal is enabled for Gate 2 0 = The Data Source 1 inverted signal is disabled for Gate 2 bit 7 G1D4T: Gate 1 Data Source 4 True Enable bit 1 = The Data Source 4 signal is enabled for Gate 1 0 = The Data Source 4 signal is disabled for Gate 1 bit 6 G1D4N: Gate 1 Data Source 4 Negated Enable bit 1 = The Data Source 4 inverted signal is enabled for Gate 1 0 = The Data Source 4 inverted signal is disabled for Gate 1 bit 5 G1D3T: Gate 1 Data Source 3 True Enable bit 1 = The Data Source 3 signal is enabled for Gate 1 0 = The Data Source 3 signal is disabled for Gate 1 bit 4 G1D3N: Gate 1 Data Source 3 Negated Enable bit 1 = The Data Source 3 inverted signal is enabled for Gate 1 0 = The Data Source 3 inverted signal is disabled for Gate 1 bit 3 G1D2T: Gate 1 Data Source 2 True Enable bit 1 = The Data Source 2 signal is enabled for Gate 1 0 = The Data Source 2 signal is disabled for Gate 1 bit 2 G1D2N: Gate 1 Data Source 2 Negated Enable bit 1 = The Data Source 2 inverted signal is enabled for Gate 1 0 = The Data Source 2 inverted signal is disabled for Gate 1 bit 1 G1D1T: Gate 1 Data Source 1 True Enable bit 1 = The Data Source 1 signal is enabled for Gate 1 0 = The Data Source 1 signal is disabled for Gate 1 bit 0 G1D1N: Gate 1 Data Source 1 Negated Enable bit 1 = The Data Source 1 inverted signal is enabled for Gate 1 0 = The Data Source 1 inverted signal is disabled for Gate 1 REGISTER 21-4: CLCxGLSL: CLCx GATE LOGIC INPUT SELECT LOW REGISTER (CONTINUED)

 2019-2020 Microchip Technology Inc. DS30010198B-page 269 PIC24FJ128GL306 FAMILY REGISTER 21-5: CLCxGLSH: CLCx GATE LOGIC INPUT SELECT HIGH REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 G4D4T: Gate 4 Data Source 4 True Enable bit 1 = The Data Source 4 signal is enabled for Gate 4 0 = The Data Source 4 signal is disabled for Gate 4 bit 14 G4D4N: Gate 4 Data Source 4 Negated Enable bit 1 = The Data Source 4 inverted signal is enabled for Gate 4 0 = The Data Source 4 inverted signal is disabled for Gate 4 bit 13 G4D3T: Gate 4 Data Source 3 True Enable bit 1 = The Data Source 3 signal is enabled for Gate 4 0 = The Data Source 3 signal is disabled for Gate 4 bit 12 G4D3N: Gate 4 Data Source 3 Negated Enable bit 1 = The Data Source 3 inverted signal is enabled for Gate 4 0 = The Data Source 3 inverted signal is disabled for Gate 4 bit 11 G4D2T: Gate 4 Data Source 2 True Enable bit 1 = The Data Source 2 signal is enabled for Gate 4 0 = The Data Source 2 signal is disabled for Gate 4 bit 10 G4D2N: Gate 4 Data Source 2 Negated Enable bit 1 = The Data Source 2 inverted signal is enabled for Gate 4 0 = The Data Source 2 inverted signal is disabled for Gate 4 bit 9 G4D1T: Gate 4 Data Source 1 True Enable bit 1 = The Data Source 1 signal is enabled for Gate 4 0 = The Data Source 1 signal is disabled for Gate 4 bit 8 G4D1N: Gate 4 Data Source 1 Negated Enable bit 1 = The Data Source 1 inverted signal is enabled for Gate 4 0 = The Data Source 1 inverted signal is disabled for Gate 4 bit 7 G3D4T: Gate 3 Data Source 4 True Enable bit 1 = The Data Source 4 signal is enabled for Gate 3 0 = The Data Source 4 signal is disabled for Gate 3 bit 6 G3D4N: Gate 3 Data Source 4 Negated Enable bit 1 = The Data Source 4 inverted signal is enabled for Gate 3 0 = The Data Source 4 inverted signal is disabled for Gate 3 bit 5 G3D3T: Gate 3 Data Source 3 True Enable bit 1 = The Data Source 3 signal is enabled for Gate 3 0 = The Data Source 3 signal is disabled for Gate 3 bit 4 G3D3N: Gate 3 Data Source 3 Negated Enable bit 1 = The Data Source 3 inverted signal is enabled for Gate 3 0 = The Data Source 3 inverted signal is disabled for Gate 3

DS30010198B-page 270  2019-2020 Microchip Technology Inc. bit 3 G3D2T: Gate 3 Data Source 2 True Enable bit 1 = The Data Source 2 signal is enabled for Gate 3 0 = The Data Source 2 signal is disabled for Gate 3 bit 2 G3D2N: Gate 3 Data Source 2 Negated Enable bit 1 = The Data Source 2 inverted signal is enabled for Gate 3 0 = The Data Source 2 inverted signal is disabled for Gate 3 bit 1 G3D1T: Gate 3 Data Source 1 True Enable bit 1 = The Data Source 1 signal is enabled for Gate 3 0 = The Data Source 1 signal is disabled for Gate 3 bit 0 G3D1N: Gate 3 Data Source 1 Negated Enable bit 1 = The Data Source 1 inverted signal is enabled for Gate 3 0 = The Data Source 1 inverted signal is disabled for Gate 3 REGISTER 21-5: CLCxGLSH: CLCx GATE LOGIC INPUT SELECT HIGH REGISTER (CONTINUED)

 2019-2020 Microchip Technology Inc. DS30010198B-page 271 PIC24FJ128GL306 FAMILY 22.0 12-BIT A/D CONVERTER WITH THRESHOLD DETECT The A/D Converter has the following key features:

• Successive Approximation Register (SAR) Conversion
• Selectable 10-Bit or 12-Bit (default) Conversion Resolution
• Conversion Speeds of Up to 350 ksps (12-bit) and 400 ksps (10-bit)
• Up to 20 Analog Input Channels (internal and external)
• Multiple Internal Reference Input Channels
• External Voltage Reference Input Pins
• Unipolar Differential Sample-and-Hold (S/H) Amplifier
• Automated Threshold Scan and Compare Operation to Pre-Evaluate Conversion Results
• Selectable Conversion Trigger Source
• Fixed Length (one word per channel), Configurable Conversion Result Buffer
• Four Options for Results Alignment
• Configurable Interrupt Generation
• Enhanced DMA Operations with Indirect Address Generation
• Operation During CPU Sleep and Idle modes The 12-bit A/D Converter module is an enhanced version of the 10-bit module offered in earlier PIC24 devices. It is a Successive Approximation Register (SAR) Converter, enhanced with 12-bit resolution, a wide range of automatic sampling options, tighter inte- gration with other analog modules and a configurable results buffer. It also includes a unique Threshold Detect feature that allows the module itself to make simple decisions based on the conversion results, and enhanced opera- tion with the DMA Controller through Peripheral Indirect Addressing (PIA). A simplified block diagram for the module is shown in Figure 22-1.

22.1 Basic Operation

To perform a standard A/D conversion: 1. Configure the module: a) Configure port pins as analog inputs by setting the appropriate bits in the ANSELx registers (see Section 11.2 “Configuring Analog Port Pins (ANSELx)” for more information). b) Select the voltage reference source to match the expected range on analog inputs (AD1CON2[15:13]). c) Select the positive and negative multiplexer inputs for each channel (AD1CHS[15:0]). d) Select the analog conversion clock to match the desired data rate with the processor clock (AD1CON3[7:0]). e) Select the appropriate sample/conversion sequence (AD1CON1[7:4] and AD1CON3[12:8]). f) For Channel A scanning operations, select the positive channels to be included (AD1CSSH and AD1CSSL registers). g) Select how conversion results are presented in the buffer (AD1CON1[9:8] and AD1CON5 register). h) Select the interrupt rate (AD1CON2[5:2]). i) Turn on A/D module (AD1CON1[15]). 2. Configure the A/D interrupt (if required): a) Clear the AD1IF bit (IFS0[13]). b) Enable the AD1IE interrupt (IEC0[13]). c) Select the A/D interrupt priority (IPC3[6:4]). 3. If the module is configured for manual sampling, set the SAMP bit (AD1CON1[1]) to begin sampling. Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive reference source. For more information, refer to “12-Bit A/D Converter with Threshold Detect” (www.microchip.com/ DS39739) in the “dsPIC33/PIC24 Family Reference Manual” . The information in this data sheet supersedes the information in the FRM.

DS30010198B-page 272  2019-2020 Microchip Technology Inc. FIGURE 22-1: 12-BIT A/D CONVERTER BLOCK DIAGRAM (PIC24FJ128GL306 FAMILY) VREF+ AN12(1) AN0 AN1 AN2 Sample Control AVSS AVDD ADC1BUF0: ADC1BUF15 AD1CON1 AD1CON2 AD1CON3 AD1CHS AD1CHITL Control Logic Data Formatting Input MUX Control Conversion Control Internal Data Bus VR+VR- MUX B VINH VINL VINH VINH VINL VINL VR+ VR- VR Select VBG Note 1: Available ANx pins are package-dependent. AVSS AVDD AD1CON5 DMA Data Bus AD1CON4 Extended DMA Data MUX A AN13(1) AN14(1) AN16(1) AN15(1) AD1CSSH AD1RESDMA AD1CSSL SAR

 2019-2020 Microchip Technology Inc. DS30010198B-page 273 PIC24FJ128GL306 FAMILY

22.2 Extended DMA Operations

In addition to the standard features available on all 12-bit A/D Converters, PIC24FJ128GL306 family devices implement a limited extension of DMA functionality. This extension adds features that work with the device’s DMA Controller to expand the A/D module’s data storage abilities beyond the module’s built-in buffer. The Extended DMA functionality is controlled by the DMAEN bit (AD1CON1[11]); setting this bit enables the functionality. The DMABM bit (AD1CON1[12]) configures how the DMA feature operates.

22.2.1 EXTENDED BUFFER MODE

Extended Buffer mode (DMABM = 1) maps the A/D Data Buffer registers and data from all channels above 13 into a user-specified area of data RAM. This allows users to read the conversion results of channels above 13, which do not have their own memory-mapped A/D buffer locations, from data memory. To accomplish this, the DMA destination address must be configured in Peripheral Indirect Addressing mode, the DMA destination address must point to the begin- ning of the buffer, the DMA source address must be configured in “Remains Unchanged” mode and the source address should be pointing to the AD1RESDMA register. The DMA count must be set to generate an interrupt after the desired number of conversions. In Extended Buffer mode, the A/D control bits will function similarly to non-DMA modes. The BUFREGEN bit will still select between FIFO mode and Channel-Aligned mode, but the number of words in the destination FIFO will be determined by the SMPI[4:0] bits in DMA mode. In FIFO mode, the BUFM bit will still split the output FIFO into two sets of 13 results (the SMPIx bits should be set accord- ingly) and the BUFS bit will still indicate which set of results is being written to and which can be read.

22.2.2 PIA MODE

When DMABM = 0, the A/D module is configured to function with the DMA Controller for Peripheral Indirect Addressing (PIA) mode operations. In this mode, the A/D module generates an 11-bit Indirect Address (IA). This is ORed with the destination address in the DMA Controller to define where the A/D conversion data will be stored. In PIA mode, the buffer space is created as a series of contiguous smaller buffers, one per analog channel. The size of the channel buffer determines how many analog channels can be accommodated. The size of the buffer is selected by the DMABL[2:0] bits (AD1CON4[2:0]). The size options range from a single word per buffer to 128 words. Each channel is allocated a buffer of this size, regardless of whether or not the channel will actually have conversion data. The IA is created by combining the base address within a channel buffer with three to five bits (depending on the buffer size) to identify the channel. The base address ranges from zero to seven bits wide, depend- ing on the buffer size. The address is right-padded with a ‘0’ in order to maintain address alignment in the Data Space. The concatenated channel and base address bits are then left-padded with zeros, as necessary, to complete the 11-bit IA. The IA is configured to auto-increment which channel is written in each analog input’s sub-buffer during write operations by using the SMPIx bits (AD1CON2[6:2]). As with PIA operations for any DMA-enabled module, the base destination address in the DMADSTn register must be masked properly to accommodate the IA. Table 22-1 shows how complete addresses are formed. Note that the address masking varies for each buffer size option. Because of masking requirements, some address ranges may not be available for certain buffer sizes. Users should verify that the DMA base address is compatible with the buffer size selected. Figure 22-2 shows how the parts of the address define the buffer locations in data memory. In this case, the module “allocates” 256 bytes of data RAM (1000h to 1100h) for 32 buffers of four words each. However, this is not a hard allocation and nothing prevents these locations from being used for other purposes. For example, in the current case, if Analog Channels 1, 3 and 8 are being sampled and converted, conversion data will only be written to the channel buffers, starting at 1008h, 1018h and 1040h. The holes in the PIA buffer space can be used for any other purpose. It is the user’s responsibility to keep track of buffer locations and prevent data overwrites.

DS30010198B-page 274  2019-2020 Microchip Technology Inc. TABLE 22-1: INDIRECT ADDRESS GENERATION IN PIA MODE FIGURE 22-2: EXAMPLE OF BUFFER ADDRESS GENERATION IN PIA MODE (4-WORD BUFFERS PER CHANNEL) DMABL[2:0] Buffer Size per Channel (words) Generated Offset Address (lower 11 bits) Available Input Channels Allowable DMADSTn Addresses 000 1 000 00cc ccc0 32 xxxx xxxx xx00 0000 001 2 000 0ccc ccn0 32 xxxx xxxx x000 0000 010 4 000 cccc cnn0 32 xxxx xxxx 0000 0000 011 8 00c cccc nnn0 32 xxxx xxx0 0000 0000 100 16 0cc cccn nnn0 32 xxxx xx00 0000 0000 101 32 ccc ccnn nnn0 32 xxxx x000 0000 0000 110 64 ccc cnnn nnn0 16 xxxx x000 0000 0000 111 128 ccc nnnn nnn0 8 xxxx x000 0000 0000 Legend: ccc = Channel number (three to five bits), n = Base buffer address (zero to seven bits), x = User-definable range of DMADSTn for base address, 0 = Masked bits of DMADSTn for IA Data RAM Destination A/D Module (PIA Mode) BBA DMA Channel DMADSTn nn (0-3) 1000h (DMA Base Address) Range Channel ccccc (0-31) 000 cccc cnn0 (IA) 1000h DMABL[2:0] = 010 (4 Words Per Input) 1008h 1010h 1018h 10F8h 1100h Ch 0 Buffer (4 Words) Ch 1 Buffer (4 Words) Ch 2 Buffer (4 Words) Ch 3 Buffer (4 Words) Ch 27 Buffer (4 Words) Ch 29 Buffer (4 Words) Ch 31 Buffer (4 Words) 10F0h (Buffer Base Address) 1000h 1002h 1004h 1006h Ch 0, Word 0 Ch 0, Word 1 Ch 0, Word 2 Ch 0, Word 3 Ch 1, Word 0 Ch 1, Word 1 Ch 1, Word 2 Ch 1, Word 3 1008h 100Ah 100Ch 100Eh 0001 0000 0000 0000 0001 0000 0000 0010 0001 0000 0000 0100 0001 0000 0000 0110 0001 0000 0000 1000 0001 0000 0000 1010 0001 0000 0000 1100 0001 0000 0000 1110 DMA Base Address Address Mask Channel Address Buffer Address 1038h 1040h Ch 7 Buffer (4 Words) Ch 8 Buffer (4 Words)

 2019-2020 Microchip Technology Inc. DS30010198B-page 275 PIC24FJ128GL306 FAMILY

22.3 Registers

The 12-bit A/D Converter is controlled through a total of 12 registers:

• AD1CON1 through AD1CON5 (Register 22-1 through Register 22-5)
• A D 1 C H S (Register 22-6)
• ANCFG ( Register 22-7)
• AD1CHITH and AD1CHITL (Register 22-8 and Register 22-9)
• AD1CSSH and AD1CSSL (Register 22-10 and Register 22-11)
• AD1RESDMA (not shown) – The 16-bit conversion buffer for Extended Buffer mode REGISTER 22-1: AD1CON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADON —A D S I D L D M A B M (1) DMAEN MODE12 FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 HSC/R/W-0 HSC/R/C-0 SSRC3 SSRC2 SSRC1 SSRC0 — ASAM SAMP DONE bit 7 bit 0 Legend: C = Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: A/D Operating Mode bit 1 = A/D Converter is operating 0 = A/D Converter is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: A/D Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 DMABM: Extended DMA Buffer Mode Select bit (1) 1 = Extended Buffer mode: Buffer address is defined by the DMADSTn register 0 = PIA mode: Buffer addresses are defined by the DMA Controller and AD1CON4[2:0] bit 11 DMAEN: Extended DMA/Buffer Enable bit 1 = Extended DMA and buffer features are enabled 0 = Extended features are disabled bit 10 MODE12: A/D 12-Bit Operation Mode bit 1 = 12-bit A/D operation 0 = 10-bit A/D operation bit 9-8 FORM[1:0]: Data Output Format bits (see formats following) 11 = Fractional result, signed, left justified 10 = Absolute fractional result, unsigned, left justified 01 = Decimal result, signed, right justified 00 = Absolute decimal result, unsigned, right justified bit 7-4 SSRC[3:0]: Sample Clock Source Select bits 0000 = SAMP is cleared by software 0001 = INT0 0010 = Timer3 0011 = Timer5 0101 = Timer1 (will not trigger during Sleep mode) 0110 = Timer1 (may trigger during Sleep mode) 0111 = Auto-Convert mode Note 1: This bit is only available when Extended DMA and buffer features are available (DMAEN = 1).

DS30010198B-page 276  2019-2020 Microchip Technology Inc. bit 3 Unimplemented: Read as ‘0’ bit 2 ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after last conversion; SAMP bit is auto-set 0 = Sampling begins when SAMP bit is manually set bit 1 SAMP: A/D Sample Enable bit 1 = A/D Sample-and-Hold amplifiers are sampling 0 = A/D Sample-and-Hold amplifiers are holding bit 0 DONE: A/D Conversion Status bit 1 = A/D conversion cycle has completed 0 = A/D conversion cycle has not started or is in progress REGISTER 22-1: AD1CON1: A/D CONTROL REGISTER 1 (CONTINUED) Note 1: This bit is only available when Extended DMA and buffer features are available (DMAEN = 1).

 2019-2020 Microchip Technology Inc. DS30010198B-page 277 PIC24FJ128GL306 FAMILY REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 r-0 R/W-0 R/W-0 U-0 U-0 PVCFG1 PVCFG0 NVCFG0 — BUFREGEN CSCNA — — bit 15 bit 8 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 PVCFG[1:0]: A/D Converter Positive Voltage Reference Configuration bits 1x = Unimplemented, do not use 01 =E x t e r n a l VREF+ 00 =A VDD bit 13 NVCFG0: A/D Converter Negative Voltage Reference Configuration bit 1 = AVSS 0 = AVSS bit 12 Reserved: Maintain as ‘0’ bit 11 BUFREGEN: A/D Buffer Register Enable bit 1 = Conversion result is loaded into the buffer location determined by the converted channel 0 = A/D result buffer is treated as a FIFO bit 10 CSCNA: Scan Input Selections for CH0+ During Sample A bit 1 = Scans inputs 0 = Does not scan inputs bit 9-8 Unimplemented: Read as ‘0’ bit 7 BUFS: Buffer Fill Status bit When DMAEN = 1 and DMABM = 1: 1 = A/D is currently filling the destination buffer from [buffer start + (buffer size/2)] to [buffer start + (buffer size – 1)]. User should access data located from [buffer start] to [buffer start + (buffer size/2) – 1]. 0 = A/D is currently filling the destination buffer from [buffer start] to [buffer start + (buffer size/2) – 1]. User should access data located from [buffer start + (buffer size/2)] to [buffer start + (buffer size – 1)]. When DMAEN = 1 = A/D is currently filling ADC1BUF13-ADC1BUF25, user should access data in ADC1BUF0-ADC1BUF12 0 = A/D is currently filling ADC1BUF0-ADC1BUF12, user should access data in ADC1BUF13-ADC1BUF25

DS30010198B-page 278  2019-2020 Microchip Technology Inc. bit 6-2 SMPI[4:0]: Interrupt Sample/DMA Increment Rate Select bits When DMAEN = 1 and DMABM = 0: 11111 = Increments the DMA address after completion of the 32nd sample/conversion operation 11110 = Increments the DMA address after completion of the 31st sample/conversion operation 00001 = Increments the DMA address after completion of the 2nd sample/conversion operation 00000 = Increments the DMA address after completion of each sample/conversion operation When DMAEN = 1 and DMABM = 1: 11111 = Resets the DMA offset after completion of the 32nd sample/conversion operation 11110 = Resets the DMA offset after completion of the 31nd sample/conversion operation 00001 = Resets the DMA offset after completion of the 2nd sample/conversion operation 00000 = Resets the DMA offset after completion of every sample/conversion operation When DMAEN = 11111 = Interrupts at the completion of the conversion for each 32nd sample 11110 = Interrupts at the completion of the conversion for each 31st sample 00001 = Interrupts at the completion of the conversion for every other sample 00000 = Interrupts at the completion of the conversion for each sample bit 1 BUFM: Buffer Fill Mode Select bit 1 = Starts buffer filling at ADC1BUF0 on first interrupt and ADC1BUF13 on next interrupt 0 = Always starts filling buffer at ADC1BUF0 bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2 (CONTINUED)

 2019-2020 Microchip Technology Inc. DS30010198B-page 279 PIC24FJ128GL306 FAMILY REGISTER 22-3: AD1CON3: A/D CONTROL REGISTER 3 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC(1) EXTSAM PUMPEN (2) SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADRC: A/D Conversion Clock Source bit(1) 1 = Dedicated ADC RC clock generator (4 MHz nominal) 0 = Clock derived from system clock bit 14 EXTSAM: Extended Sampling Time bit 1 = A/D is still sampling after SAMP = 0 0 = A/D is finished sampling bit 13 PUMPEN: Charge Pump Enable bit(2) 1 = Charge pump for switches is enabled 0 = Charge pump for switches is disabled bit 12-8 SAMC[4:0]: Auto-Sample Time Select bits 11111 = 31 TAD 00001 = 1 TAD 00000 = 0 TAD bit 7-0 ADCS[7:0]: A/D Conversion Clock Select bits 11111111 = 256 • TCY = TAD 00000001 = 2 • T CY = TAD 00000000 = TCY =T AD Note 1: Selecting the internal ADC RC clock requires that ADCSx be one or greater. Setting ADCSx = 0 when ADRC = 1 will violate the TAD (minimum) specification. 2: The user should enable the charge pump if AVDD is < 2.7V. Longer sample times are required due to the increase of the internal resistance of the MUX if the charge pump is disabled.

DS30010198B-page 280  2019-2020 Microchip Technology Inc. REGISTER 22-4: AD1CON4: A/D CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 DMABL[2:0]: DMA Buffer Size Select bits(1) 111 = Allocates 128 words of buffer to each analog input 110 = Allocates 64 words of buffer to each analog input 101 = Allocates 32 words of buffer to each analog input 100 = Allocates 16 words of buffer to each analog input 011 = Allocates 8 words of buffer to each analog input 010 = Allocates 4 words of buffer to each analog input 001 = Allocates 2 words of buffer to each analog input 000 = Allocates 1 word of buffer to each analog input Note 1: The DMABL[2:0] bits are only used when AD1CON1[11] = 1 and AD1CON1[12] = 0; otherwise, their value is ignored.

 2019-2020 Microchip Technology Inc. DS30010198B-page 281 PIC24FJ128GL306 FAMILY REGISTER 22-5: AD1CON5: A/D CONTROL REGISTER 5 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 ASEN LPEN —B G R E Q — — ASINT1 ASINT0 bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — WM1 WM0 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ASEN: Auto-Scan Enable bit 1 = Auto-scan is enabled 0 = Auto-scan is disabled bit 14 LPEN: Low-Power Enable bit 1 = Low power is enabled after scan 0 = Full power is enabled after scan bit 13 Unimplemented: Read as ‘0’ bit 12 BGREQ: Band Gap Request bit 1 = Band gap is enabled when the A/D is enabled and active 0 = Band gap is not enabled by the A/D bit 11-10 Unimplemented: Read as ‘0’ bit 9-8 ASINT[1:0]: Auto-Scan (Threshold Detect) Interrupt Mode bits 11 = Interrupt after Threshold Detect sequence has completed and a valid compare has occurred 10 = Interrupt after a valid compare has occurred 01 = Interrupt after Threshold Detect sequence has completed 00 = No interrupt bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 WM[1:0]: Write Mode bits 11 = Reserved 10 = Auto-compare only (conversion results are not saved, but interrupts are generated when a valid match occurs, as defined by the CMx and ASINTx bits) 01 = Convert and save (conversion results are saved to locations as determined by the register bits when a match occurs, as defined by the CMx bits) 00 = Legacy operation (conversion data are saved to a location determined by the buffer register bits) bit 1-0 CM[1:0]: Compare Mode bits 11 = Outside Window mode: Valid match occurs if the conversion result is outside of the window defined by the corresponding buffer pair 10 = Inside Window mode: Valid match occurs if the conversion result is inside the window defined by the corresponding buffer pair 01 = Greater Than mode: Valid match occurs if the result is greater than the value in the corresponding buffer register 00 = Less Than mode: Valid match occurs if the result is less than the value in the corresponding buffer register

DS30010198B-page 282  2019-2020 Microchip Technology Inc. REGISTER 22-6: AD1CHS: A/D SAMPLE SELECT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB2 CH0NB1 CH0NB0 CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA2 CH0NA1 CH0NA0 CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 CH0NB[2:0]: Sample B Channel 0 Negative Input Select bits 1xx = Unimplemented 011 = Unimplemented 010 = AN1- 001 = Unimplemented 000 = AVSS bit 12-8 CH0SB[4:0]: Sample B Channel 0 Positive Input Select bits 11111 = Reserved 11110 = AVDD(1) 11101 = AVSS(1) 11100 = Band Gap Reference (VBG)(1) 10001-11011 = Reserved 10000 = AN16 01111 = AN15 01110 = AN14 01101 = AN13 01100 = AN12 01011 = AN11 01010 = AN10 01001 = AN9 01000 = AN8 00111 = AN7 00110 = AN6 00101 = AN5 00100 = AN4 00011 = AN3 00010 = AN2 00001 = AN1 00000 = AN0 bit 7-5 CH0NA[2:0]: Sample A Channel 0 Negative Input Select bits Same definitions as for CHONB[2:0]. bit 4-0 CH0SA[4:0]: Sample A Channel 0 Positive Input Select bits Same definitions as for CHOSB[4:0]. Note 1: These input channels do not have corresponding memory-mapped result buffers.

 2019-2020 Microchip Technology Inc. DS30010198B-page 283 PIC24FJ128GL306 FAMILY REGISTER 22-7: ANCFG: A/D BAND GAP REFERENCE CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — VBGEN3 (1) VBGEN2(1) VBGEN1(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2 VBGEN3: A/D Band Gap Reference Enable bit(1) 1 = Band gap reference is enabled 0 = Band gap reference is disabled bit 1 VBGEN2: Comparator Band Gap Reference Enable bit(1) 1 = Band gap reference is enabled 0 = Band gap reference is disabled bit 0 VBGEN1: VREG, BOR, HLVD, FRC, NVM and A/D Boost Band Gap Reference Enable bit(1) 1 = Band gap reference is enabled 0 = Band gap reference is disabled Note 1: When a module requests a band gap reference voltage, that reference will be enabled automatically after a brief start-up time. The user can manually enable the band gap references using the ANCFG register, before enabling the module requesting the band gap reference, to avoid this start-up time (~1 ms).

DS30010198B-page 284  2019-2020 Microchip Technology Inc. REGISTER 22-8: AD1CHITH: A/D SCAN COMPARE HIT REGISTER HIGH U/0 U/0 U/0 U/0 U/0 U/0 U/0 U/0 bit 15 bit 8 U/0 U/0 U/0 U/0 U/0 U/0 U/0 R/W-0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 Unimplemented: Read as ‘0’ bit 0 CHH16: A/D Compare Hit bit If CM[1:0] = 11: 1 = A/D Result Buffer n has been written with data or a match has occurred 0 = A/D Result Buffer n has not been written with data For All Other Values of CM[1:0]: 1 = A match has occurred on A/D Result Channel n 0 = No match has occurred on A/D Result Channel n REGISTER 22-9: AD1CHITL: A/D SCAN COMPARE HIT REGISTER LOW R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHH[15:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHH[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 CHH[15:0]: A/D Compare Hit bits If CM[1:0] = 11: 1 = A/D Result Buffer n has been written with data or a match has occurred 0 = A/D Result Buffer n has not been written with data For All Other Values of CM[1:0]: 1 = A match has occurred on A/D Result Channel n 0 = No match has occurred on A/D Result Channel n

 2019-2020 Microchip Technology Inc. DS30010198B-page 285 PIC24FJ128GL306 FAMILY REGISTER 22-10: AD1CSSH: A/D INPUT SCAN SELECT REGISTER HIGH U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 CSS[30:28]: A/D Input Scan Selection bits 1 = Includes corresponding channel for input scan 0 = Skips channel for input scan bit 11-1 Unimplemented: Read as ‘0’ bit 0 CSS16: A/D Input Scan Selection bit 1 = Includes corresponding channel for input scan 0 = Skips channel for input scan REGISTER 22-11: AD1CSSL: A/D INPUT SCAN SELECT REGISTER LOW R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS[15:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 CSS[15:0]: A/D Input Scan Selection bits 1 = Includes corresponding channel for input scan 0 = Skips channel for input scan

DS30010198B-page 286  2019-2020 Microchip Technology Inc. FIGURE 22-3: 12-BIT A/D CONVERTER ANALOG INPUT MODEL EQUATION 22-1: A/D CONVERSION CLOCK PERIOD CPINVA Rs ANx ILEAKAGE RIC  250 Sampling Switch RSS CHOLD AVSS = 40 pF500 nA Legend: CPIN VT ILEAKAGE RIC RSS CHOLD = Input Capacitance = Threshold Voltage = Leakage Current at the Pin due to = Interconnect Resistance = Sampling Switch Resistance = Sample/Hold Capacitance Various Junctions Note: The CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if Rs  2.5 k. (RSS  3 k) AVDD VT = 0.6V VT = 0.6V SS = S/H Input Capacitance Sampling Switch RMIN RMAX AVDDMIN AVDD (V) AVDDMAX TAD = TCY (ADCS + 1) ADCS = – 1TAD TCY Note: Based on TCY = 2/FOSC; Doze mode and PLL are disabled.

 2019-2020 Microchip Technology Inc. DS30010198B-page 287 PIC24FJ128GL306 FAMILY FIGURE 22-4: 12-BIT A/ D TRANSFER FUNCTION 0010 0000 0001 (2049) 0010 0000 0010 (2050) 0010 0000 0011 (2051) 0001 1111 1101 (2045) 0001 1111 1110 (2046) 0001 1111 1111 (2047) 1111 1111 1110 (4094) 1111 1111 1111 (4095) 0000 0000 0000 (0) 0000 0000 0001 (1) Output Code 0010 0000 0000 (2048) (VINH – VINL) VR- VR+ – VR- 4096 4096 VR+ VR- + VR-+ 4095 * (VR+ – VR-) 4096 VR- + (Binary (Decimal)) Voltage Level

DS30010198B-page 288  2019-2020 Microchip Technology Inc. FIGURE 22-5: 10-BIT A/ D TRANSFER FUNCTION 10 0000 0001 (513) 10 0000 0010 (514) 10 0000 0011 (515) 01 1111 1101 (509) 01 1111 1110 (510) 01 1111 1111 (511) 11 1111 1110 (1022) 11 1111 1111 (1023) 00 0000 0000 (0) 00 0000 0001 (1) Output Code 10 0000 0000 (512) (VINH – VINL) VR- VR+ – VR- 1024 512 * (V R+ – VR-) 1024 VR+ VR- + VR-+ 1023 * (VR+ – VR-) 1024 VR- + (Binary (Decimal)) Voltage Level

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23.0 TRIPLE COMPARATOR

The triple comparator module provides three dual input comparators. The inputs to the comparator can be configured to use any one of five external analog inputs (CxINA, CxINB, CxINC, CxIND and CV REF+) and a voltage reference input from one of the internal band gap references or the comparator voltage reference generator (VBG and CVREF). The comparator outputs may be directly connected to the CxOUT pins. When the respective COE bit equals ‘1’, the I/O pad logic makes the unsynchronized output of the comparator available on the pin. A simplified block diagram of the module in shown in Figure 23-1. Diagrams of the possible individual comparator configurations are shown in Figure 23-2 through Figure 23-4. Each comparator has its own control register, CMxCON (Register 23-1), for enabling and configuring its operation. The output and event status of all three comparators is provided in the CMSTAT register (Register 23-2). FIGURE 23-1: TRIPLE COMP ARATOR MODULE BLOCK DIAGRAM Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive ref- erence source. For more information, refer to “Scalable Comparator Module” (www.microchip.com/DS39734 ) in the “dsPIC33/PIC24 Family Reference Man- ual”. The information in this data sheet supersedes the information in the FRM. C1 VIN- VIN+CxINB CxINC CxINA CxIND CVREF+ VBG VIN- VIN+ VIN- VIN+ COE C1OUT Pin CPOL Trigger/Interrupt Logic CEVT EVPOL[1:0] COUT Input Select Logic CCH[1:0] CREF COE C2OUT Pin CPOL Trigger/Interrupt Logic CEVT EVPOL[1:0] COUT COE C3OUT Pin CPOL Trigger/Interrupt Logic CEVT EVPOL[1:0] COUT CVREF+ CVREFM1:0 CVREFP(1) 1100 Note 1: Refer to the CVRCON register (Register 24-1) for bit details. Comparator Voltage Reference

 2019-2020 Microchip Technology Inc. DS30010198B-page 291 PIC24FJ128GL306 FAMILY FIGURE 23-4: INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1 AND CVREFP =1 Comparator CxIND > CVREF Compare Cx VIN- VIN+ COE CxIND CVREF+ CxOUT Pin Comparator VBG > CVREF Compare Cx VIN- VIN+ COE VBG CVREF+ CxOUT Pin Comparator CxINC > CVREF Compare Cx VIN- VIN+ COE CxINC CVREF+ CxOUT Pin Comparator CxINB > CVREF Compare Cx VIN- VIN+ COE CxINB CVREF+ CxOUT Pin CEN = 1, CCH[1:0] = 00, CVREFM[1:0] = xx CEN = 1, CCH[1:] = 10, CVREFM[1:0] = xx CEN = 1, CCH[1:0] = 11, CVREFM[1:0] = 00 CEN = 1, CCH[1:0] = 01, CVREFM[1:0] = xx

DS30010198B-page 292  2019-2020 Microchip Technology Inc. REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 HS/R/W-0 HSC/R-0 CEN COE CPOL — — — CEVT COUT bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 bit 7 bit 0 Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CEN: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 14 COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only bit 13 CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 12-10 Unimplemented: Read as ‘0’ bit 9 CEVT: Comparator Event bit 1 = Comparator event that is defined by EVPOL[1:0] has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = Comparator event has not occurred bit 8 COUT: Comparator Output bit When CPOL = 0: 1 =V IN+ > VIN- 0 =V IN+ < VIN- When CPOL = 1: 1 =V IN+ < VIN- 0 =V IN+ > VIN- bit 7-6 EVPOL[1:0]: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0) 10 = Trigger/event/interrupt is generated on transition of the comparator output: If CPOL = 0 (noninverted polarity): High-to-low transition only. If CPOL = 1 (inverted polarity): Low-to-high transition only. 01 = Trigger/event/interrupt is generated on transition of comparator output: If CPOL = 0 (noninverted polarity): Low-to-high transition only. If CPOL = 1 (inverted polarity): High-to-low transition only. 00 = Trigger/event/interrupt generation is disabled bit 5 Unimplemented: Read as ‘0’

 2019-2020 Microchip Technology Inc. DS30010198B-page 293 PIC24FJ128GL306 FAMILY bit 4 CREF: Comparator Reference Select bits (noninverting input) 1 = Noninverting input connects to the internal CV REF voltage 0 = Noninverting input connects to the CxINA pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH[1:0]: Comparator Channel Select bits 11 = Inverting input of the comparator connects to the internal selectable reference voltage specified by the CVREFM[1:0] bits in the CVRCON register 10 = Inverting input of the comparator connects to the CxIND pin 01 = Inverting input of the comparator connects to the CxINC pin 00 = Inverting input of the comparator connects to the CxINB pin REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) (CONTINUED) REGISTER 23-2: CMSTAT: COMPARA TOR MODULE STATUS REGISTER R/W-0 U-0 U-0 U-0 U-0 HSC/R-0 HSC/R-0 HSC/R-0 CMIDL — — — — C3EVT C2EVT C1EVT bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 HSC/R-0 HSC/R-0 HSC/R-0 — — — — — C3OUT C2OUT C1OUT bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMIDL: Comparator Stop in Idle Mode bit 1 = Discontinues operation of all comparators when device enters Idle mode 0 = Continues operation of all enabled comparators in Idle mode bit 14-11 Unimplemented: Read as ‘0’ bit 10 C3EVT: Comparator 3 Event Status bit (read-only) Shows the current event status of Comparator 3 (CM3CON[9]). bit 9 C2EVT: Comparator 2 Event Status bit (read-only) Shows the current event status of Comparator 2 (CM2CON[9]). bit 8 C1EVT: Comparator 1 Event Status bit (read-only) Shows the current event status of Comparator 1 (CM1CON[9]). bit 7-3 Unimplemented: Read as ‘0’ bit 2 C3OUT: Comparator 3 Output Status bit (read-only) Shows the current output of Comparator 3 (CM3CON[8]). bit 1 C2OUT: Comparator 2 Output Status bit (read-only) Shows the current output of Comparator 2 (CM2CON[8]). bit 0 C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON[8]).

DS30010198B-page 294  2019-2020 Microchip Technology Inc. NOTES:

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24.0 COMPARATOR VOLTAGE

24.1 Configuring the Comparator

The voltage reference module is controlled through the CVRCON register ( Register 24-1). The comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. The primary differ- ence between the ranges is the size of the steps selected by the CV REF Value Selection bits (CVR[4:0]), with one range offering finer resolution. The comparator reference supply voltage can come from either V DD and V SS, or the external V REF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON[5]). The settling time of the comparator voltage reference must be considered when changing the CVREF output. FIGURE 24-1: COMPARATOR VOLTAG E REFERENCE BLOCK DIAGRAM Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive reference source. For more information, refer to “Dual Comparator Module” (www.microchip.com/DS39710 ) in the “dsPIC33/PIC24 Family Reference Man- ual”. The information in this data sheet supersedes the information in the FRM. 32-to-1 MUX CVR[4:0] RCVREN CVRSS = 0 AVDD CVREF+ CVRSS = 1 CVRSS = 0 CVREF- CVRSS = 1 R R R R R R

32 Steps CVREF

DS30010198B-page 296  2019-2020 Microchip Technology Inc. REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CVREFP CVREFM1 CVREFM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 CVREFP: Comparator Voltage Reference Select bit (valid only when CREF is ‘1’) 1 = CV REF+ is used as a reference voltage to the comparators 0 = The CVR[4:0] bits (5-bit DAC) within this module provide the reference voltage to the comparators bit 9-8 CVREFM[1:0]: Comparator Band Gap Reference Source Select bits (valid only when CCH[1:0] = 11) 00 = Band gap voltage is provided as an input to the comparators 01 = Reserved 10 = Reserved 11 = CVREF+ is provided as an input to the comparators bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit is powered on 0 = CVREF circuit is powered down bit 6 CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on the CVREF pin 0 = CVREF voltage level is disconnected from the CVREF pin bit 5 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = CVREF+ – CVREF- 0 = Comparator reference source, CVRSRC = AVDD – AVSS bit 4-0 CVR[4:0]: Comparator VREF Value Selection bits (0  CVR[4:0]  31) When CVRSS = 1: CVREF = (CVREF-) + (CVR[4:0]/32)  (CVREF+ – CVREF-) When CVRSS = 0: CVREF = (AVSS) + (CVR[4:0]/32)  (AVDD – AVSS)

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25.0 HIGH/LOW-VOLTAGE DETECT

(HLVD) The High/Low-Voltage Detect (HLVD) module is a programmable circuit that allows the user to specify both the device voltage trip point and the direction of change. An interrupt flag is set if the device experiences an excursion past the trip point in the direction of change. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. The HLVDIF flag may be set during a POR or BOR event. The firmware should clear the flag before the application uses it for the first time, even if the interrupt was disabled. The HLVD Control register (see Register 25-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned off” by the user under software control, which minimizes the current consumption for the device. FIGURE 25-1: HIGH/LOW-VOLTAGE DE TECT (HLVD) MODULE BLOCK DIAGRAM Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive reference source. For more information, refer to “High-Level Integration with Programmable High/Low-Voltage Detect (HLVD)” (www.microchip.com/DS39725) in the “dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. Set VDD 16-to-1 MUX HLVDEN HLVDL[3:0]HLVDIN VDD Externally Generated Trip Point HLVDIF CMPEN Band Gap VDIR 1.2V Typical

DS30010198B-page 298  2019-2020 Microchip Technology Inc. REGISTER 25-1: HLVDCON: HIGH/LOW-V OLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 R/W-0 HS/ HC/R-0 HS/HC/R-0 HS/HC/R-0 HLVDEN —L S I D L — VDIR BGVST IRVST HLVDEVT (2) bit 15 bit 8 R/S-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 CMPEN(3) — — — HLVDL3 HLVDL2 HLVDL1 HLVDL0 bit 7 bit 0 Legend: HS = Hardware Settable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared S = Settable bit bit 15 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD is enabled 0 = HLVD is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 LSIDL: HLVD Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 Unimplemented: Read as ‘0’ bit 11 VDIR: Voltage Change Direction Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL[3:0]) 0 = Event occurs when voltage equals or falls below trip point (HLVDL[3:0]) bit 10 BGVST: Band Gap Voltage Stable Flag bit 1 = Indicates that the band gap voltage is stable 0 = Indicates that the band gap voltage is unstable bit 9 IRVST: Internal Reference Voltage Stable Flag bit 1 = Internal reference voltage is stable; the High-Voltage Detect logic generates the interrupt flag at the specified voltage range 0 = Internal reference voltage is unstable; the High-Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 8 HLVDEVT: High/Low-Voltage Detect Event Status bit (2) 1 = HLVD event is true during current instruction cycle 0 = HLVD event is not true during current instruction cycle bit 7 CMPEN: High/Low-Voltage Detect Comparator Enable bit(3) 1 = HLVD comparator is enabled 0 = HLVD comparator is disabled bit 6-4 Unimplemented: Read as ‘0’ bit 3-0 HLVDL[3:0]: High/Low-Voltage Detection Limit bits 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Trip Point 1(1) 1101 = Trip Point 2(1) 1100 = Trip Point 3(1) 0100 = Trip Point 11 (1) 00xx = Unused Note 1: For the actual trip point, see Section 30.0 “Electrical Characteristics”. 2: The HLVDIF flag cannot be cleared by software unless HLVDEVT = 0. The voltage must be monitored so that the HLVD condition (as set by VDIR and HLVDL[3:0]) is not asserted. 3: CMPEN can only be written when the HLVDEN bit = 1.

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26.0 DEADMAN TIMER (DMT)

The primary function of the Deadman Timer (DMT) is to interrupt the processor in the event of a software mal- function. The DMT, which works on the system clock, is a free-running instruction fetch timer. The DMT is clocked whenever an instruction fetch occurs until a count match occurs. Instructions are not fetched when the processor is in Sleep mode. The DMT can be enabled in the Configuration fuse or by software in the DMTCON register by setting the ON bit. The DMT consists of a 32-bit counter with a time-out count match value, as specified by the two 16-bit Configuration Fuse registers: FDMTCNTL and FDMTCNTH. A DMT is typically used in mission-critical and safety- critical applications, where any single failure of software functionality and sequencing must be detected. Figure 26-1 shows a block diagram of the Deadman Timer module. FIGURE 26-1: DEADMAN TIMER BLOCK DIAGRAM Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “ Deadman Timer (DMT) ” (www.microchip.com/DS70005155) in the “dsPIC33/PIC24 Family Reference Man- ual”. The information in this data sheet supersedes the information in the FRM. Note 1: DMT Max. Count is controlled by the initial value of the FDMTCNTL and FDMTCNTH Configuration registers. 2: DMT window interval is controlled by the value of the FDMTIVTL and FDMTIVTH Configuration registers. DMT Enable 32-Bit Counter System Clock DMT Event BAD1 BAD2 Improper Sequence Flag Instruction Fetched Strobe(2) (Counter) = DMT Max. Count(1)

DS30010198B-page 300  2019-2020 Microchip Technology Inc.

26.1 Deadman Timer Control Registers

REGISTER 26-1: DMTCON: DEADMAN TIMER CONTROL REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ON: DMT Module Enable bit(1) 1 = Deadman Timer module is enabled 0 = Deadman Timer module is not enabled bit 14-0 Unimplemented: Read as ‘0’ Note 1: This bit has control only when DMTDIS = 0 in the FDMT register. REGISTER 26-2: DMTPRECLR: DEADMAN TIMER PRECLEAR REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STEP1[7:0] bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 STEP1[7:0]: DMT Preclear Enable bits 01000000 = Enables the Deadman Timer preclear (STEP1) All Other Write Patterns =Sets the BAD1 flag; these bits are cleared when a DMT Reset event occurs. STEP1[7:0] bits are also cleared if the STEP2[7:0] bits are loaded with the correct value in the correct sequence. bit 7-0 Unimplemented: Read as ‘0’

 2019-2020 Microchip Technology Inc. DS30010198B-page 301 PIC24FJ128GL306 FAMILY REGISTER 26-3: DMTCLR: DEADMAN TIMER CLEAR REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STEP2[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 STEP2[7:0]: DMT Clear Timer bits 00001000 = Clears STEP1[7:0], STEP2[7:0] and the Deadman Timer if preceded by the correct load- ing of the STEP1[7:0] bits in the correct sequence. The write to these bits may be verified by reading the DMTCNTL/H register pair and observing the counter being reset. All Other Write Patterns = Sets the BAD2 bit; the value of STEP1[7:0] will remain unchanged and the new value being written to STEP2[7:0] will be captured. These bits are cleared when a DMT Reset event occurs.

DS30010198B-page 302  2019-2020 Microchip Technology Inc. REGISTER 26-4: DMTSTAT: DEADMAN TIMER STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 HC/R-0 HC/R-0 HC/R-0 U-0 U-0 U-0 U-0 R-0 BAD1 BAD2 DMTEVENT — — — —W I N O P N bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 BAD1: Deadman Timer Bad STEP1[7:0] Value Detect bit 1 = Incorrect STEP1[7:0] value was detected 0 = Incorrect STEP1[7:0] value was not detected bit 6 BAD2: Deadman Timer Bad STEP2[7:0] Value Detect bit 1 = Incorrect STEP2[7:0] value was detected 0 = Incorrect STEP2[7:0] value was not detected bit 5 DMTEVENT: Deadman Timer Event bit 1 = Deadman Timer event was detected (counter expired, or bad STEP1[7:0] or STEP2[7:0] value was entered prior to counter increment) 0 = Deadman Timer event was not detected bit 4-1 Unimplemented: Read as ‘0’ bit 0 WINOPN: Deadman Timer Clear Window bit 1 = Deadman Timer clear window is open 0 = Deadman Timer clear window is not open

 2019-2020 Microchip Technology Inc. DS30010198B-page 303 PIC24FJ128GL306 FAMILY REGISTER 26-5: DMTCNTL: DEADMAN TIMER COUNT REGISTER LOW R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 COUNTER[15:8] bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 COUNTER[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 COUNTER[15:0]: Read Current Contents of Lower DMT Counter bits REGISTER 26-6: DMTCNTH: DEADMAN TIMER COUNT REGISTER HIGH R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 COUNTER[31:24] bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 COUNTER[23:16] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 COUNTER[31:16]: Read Current Contents of Higher DMT Counter bits

DS30010198B-page 304  2019-2020 Microchip Technology Inc. REGISTER 26-7: DMTPSCNTL: DMT POST-CONFIGURE COUNT STATUS REGISTER LOW R-y R-y R-y R-y R-y R-y R-y R-y PSCNT[15:8] bit 15 bit 8 R-y R-y R-y R-y R-y R-y R-y R-y PSCNT[7:0] bit 7 bit 0 Legend: y = Value from Configuration bit on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PSCNT[15:0]: Lower DMT Instruction Count Value Configuration Status bits This is always the value of the FDMTCNTL Configuration register. REGISTER 26-8: DMTPSCNTH: DMT POST-CONFIGURE COUNT STATUS REGISTER HIGH R-y R-y R-y R-y R-y R-y R-y R-y PSCNT[31:24] bit 15 bit 8 R-y R-y R-y R-y R-y R-y R-y R-y PSCNT[23:16] bit 7 bit 0 Legend: y = Value from Configuration bit on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PSCNT[31:16]: Higher DMT Instruction Count Value Configuration Status bits This is always the value of the FDMTCNTH Configuration register.

 2019-2020 Microchip Technology Inc. DS30010198B-page 305 PIC24FJ128GL306 FAMILY REGISTER 26-9: DMTPSINTVL: DMT POST-CONFIGURE INTERVAL STATUS REGISTER LOW R-y R-y R-y R-y R-y R-y R-y R-y PSINTV[15:8] bit 15 bit 8 R-y R-y R-y R-y R-y R-y R-y R-y PSINTV[7:0] bit 7 bit 0 Legend: y = Value from Configuration bit on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PSINTV[15:0]: Lower DMT Window Interval Configuration Status bits This is always the value of the FDMTIVTL Configuration register. REGISTER 26-10: DMTPSINTVH: DMT POST-CONFIGURE INTERVAL STATUS REGISTER HIGH R-y R-y R-y R-y R-y R-y R-y R-y PSINTV[31:24] bit 15 bit 8 R-y R-y R-y R-y R-y R-y R-y R-y PSINTV[23:16] bit 7 bit 0 Legend: y = Value from Configuration bit on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PSINTV[15:0]: Higher DMT Window Interval Configuration Status bits This is always the value of the FDMTIVTH Configuration register.

DS30010198B-page 306  2019-2020 Microchip Technology Inc. REGISTER 26-11: DMTHOLDREG: DMT HOLD REGISTER (1) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 UPRCNT[15:8] bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 UPRCNT[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 UPRCNT[15:0]: DMTCNTH Register Value When DMTCNTL/DMTCNTH were Last Read bits Note 1: The DMTHOLDREG register is initialized to ‘0’ on Reset, and is only loaded when the DMTCNTL and DMTCNTH registers are read.

 2019-2020 Microchip Technology Inc. DS30010198B-page 307 PIC24FJ128GL306 FAMILY

27.0 SPECIAL FEATURES

PIC24FJ128GL306 family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are:

• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation

27.1 Configuration Bits

The Configuration bits are stored in the last page loca- tion of implemented program memory. These bits can be set or cleared to select various device configurations. There are two types of Configuration bits: system oper- ation bits and code-protect bits. The system operation bits determine the power-on settings for system-level components, such as the oscillator and the Watchdog Timer. The code-protect bits prevent program memory from being read and written.

27.1.1 CONSIDERATIONS FOR

CONFIGURING PIC24FJ128GL306 FAMILY DEVICES In PIC24FJ128GL306 family devices, the Configuration bytes are implemented as volatile memory. This means that configuration data must be programmed each time the device is powered up. Configuration data are stored in the three words at the top of the on-chip program memory space, known as the Flash Configuration Words. Their specific locations are shown in Table 27-1. The configuration data are automatically loaded from the Flash Configuration Words to the proper Configuration registers during device Resets. When creating applications for these devices, users should always specifically allocate the location of the Flash Configuration Word for configuration data. This is to make certain that program code is not stored in this address when the code is compiled. The upper byte of all Flash Configuration Words in program memory should always be ‘0000 0000’. This makes them appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing ‘ 0’s to these locations has no effect on device operation. Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive reference source. For more information, refer to the following sections of the “dsPIC33/PIC24 Family Reference Man- ual”. The information in this data sheet supersedes the information in the FRM.

• “Watchdog Timer (WDT)” (www.microchip.com/DS39697)
• “High-Level Device Integration” (www.microchip.com/DS39719)
• “Programming and Diagnostics” (www.microchip.com/DS39716) Note: Configuration data are reloaded on all types of device Resets.

DS30010198B-page 308  2019-2020 Microchip Technology Inc. TABLE 27-1: CONFIGURATION WORD ADDRESSES Configuration Register PIC24FJ128GL30X PIC24FJ64GL30X FSEC 0x015F00 0x00AF00 FBSLIM 0x015F10 0x00AF10 FSIGN 0x015F14 0x00AF14 FOSCSEL 0x015F18 0x00AF18 FOSC 0x015F1C 0x00AF1C FWDT 0x015F20 0x00AF20 FPOR 0x015F24 0x00AF24 FICD 0x015F28 0x00AF28 FDMTIVTL 0x015F2C 0x00AF2C FDMTIVTH 0x015F30 0x00AF30 FDMTCNTL 0x015F34 0x00AF34 FDMTCNTH 0x015F38 0x00AF38 FDMT 0x015F3C 0x00AF3C FDEVOPT1 0x015F40 0x00AF40

 2019-2020 Microchip Technology Inc. DS30010198B-page 309 PIC24FJ128GL306 FAMILY TABLE 27-2: CONFIGURATION REGISTER MAP Register Name Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FSEC — AIVTDIS — — — CSS[2:0] CWRP GSS[1:0] GWRP —B S E N B S S [ 1 : 0 ] B W R P FBSLIM — — — — BSLIM[12:0] FOSCSEL — — — — — — — r(2) r(2) IESO PLLMODE[3:0] FNOSC[2:0] FOSC — — — — — — — — — FCKSM[1:0] IOL1WAY PLLSS SOSCSEL OSCIOFNC POSCMD[1:0] FWDT — — WDTCLK[1:0] — WDTCMX — WDTWIN[1:0] WINDIS FWDTEN[1:0] FWPSA WDTPS[3:0] FDMTIVTL — DMTIVT[15:0] FDMTIVTH — DMTIVT[31:16] FDMTCNTL — DMTCNT[15:0] FDMTCNTH — DMTCNT[31:16] FDEVOPT1 — — — — — —S M B 3 E N — — — — — ALTI2C1 SOSCHP TMPRPIN ALTCMPI — Legend: — = unimplemented, read as ‘ 1’. Note 1: Bit is reserved, maintain as ‘1’. 2: Bit is reserved, maintain as ‘0’.

DS30010198B-page 310  2019-2020 Microchip Technology Inc. REGISTER 27-1: FSEC CONFIGURATION REGISTER U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 23 bit 16 R/PO-1 U-1 U-1 U-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 AIVTDIS — — — CSS2 CSS1 CSS0 CWRP bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 U-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 GSS1 GSS0 GWRP — BSEN BSS1 BSS0 BWRP bit 7 bit 0 Legend: PO = Program Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15 AIVTDIS: Alternate Interrupt Vector Table Disable bit 1 = Disables AIVT; AIVTEN bit (INTCON2[8]) is not available 0 = Enables AIVT; AIVTEN bit (INTCON2[8]) is available bit 14-12 Unimplemented: Read as ‘1’ bit 11-9 CSS[2:0]: Configuration Segment (CS) Code Protection Level bits 111 = No protection (other than CWRP) 110 = Standard security 10x = Enhanced security 0xx = High security bit 8 CWRP: Configuration Segment Program Write Protection bit 1 = Configuration Segment is not write-protected 0 = Configuration Segment is write-protected bit 7-6 GSS[1:0]: General Segment (GS) Code Protection Level bits 11 = No protection (other than GWRP) 10 = Standard security 0x = High security bit 5 GWRP: General Segment Program Write Protection bit 1 = General Segment is not write-protected 0 = General Segment is write-protected bit 4 Unimplemented: Read as ‘1’ bit 3 BSEN: Boot Segment (BS) Control bit 1 = No Boot Segment is enabled 0 = Boot Segment size is determined by BSLIM[12:0] bit 2-1 BSS[1:0]: Boot Segment Code Protection Level bits 11 = No protection (other than BWRP) 10 = Standard security 0x = High security bit 0 BWRP: Boot Segment Program Write Protection bit 1 = Boot Segment can be written 0 = Boot Segment is write-protected

 2019-2020 Microchip Technology Inc. DS30010198B-page 311 PIC24FJ128GL306 FAMILY REGISTER 27-2: FBSLIM CO NFIGURATION REGISTER U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 23 bit 16 U - 1 U - 1 U - 1 R / P O - 1R / P O - 1R / P O - 1R / P O - 1R / P O - 1 — — — BSLIM[12:8] bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 BSLIM[7:0] bit 7 bit 0 Legend: PO = Program Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-13 Unimplemented: Read as ‘1’ bit 12-0 BSLIM[12:0]: Active Boot Segment Code Flash Page Address Limit (inverted) bits This bit field contains the last active Boot Segment Page + 1 (i.e., first page address of GS). The value is stored as an inverted page address, such that programming additional ‘0’s can only increase the size of BS. If the BSLIM[12:0] bits are set to all ‘1’s (unprogrammed default), the active Boot Segment size is zero.

DS30010198B-page 312  2019-2020 Microchip Technology Inc. REGISTER 27-3: FSIGN CONFIGURATION REGISTER U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 23 bit 16 r-0 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 15 bit 8 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 7 bit 0 Legend: PO = Program Once bit r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15 Reserved: Maintain as ‘0’ bit 14-0 Unimplemented: Read as ‘1’

 2019-2020 Microchip Technology Inc. DS30010198B-page 313 PIC24FJ128GL306 FAMILY REGISTER 27-4: FOSCSEL CONFIGURATION REGISTER U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 23 bit 16 U-1 U-1 U-1 U-1 U-1 U-1 r-0 r-0 bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 IESO PLLMODE3 PLLMODE2 PLLMODE1 PLLMODE0 FNOSC2 FNOSC1 FNOSC0 bit 7 bit 0 Legend: PO = Program Once bit r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-10 Unimplemented: Read as ‘1’ bit 9-8 Reserved: Maintain as ‘0’ bit 7 IESO: Two-Speed Oscillator Start-up Enable bit 1 = Starts up the device with FRC, then automatically switches to the user-selected oscillator when ready 0 = Starts up the device with the user-selected oscillator source bit 6-3 PLLMODE[3:0]: Frequency Multiplier Select bits 1111 = No PLL is used (PLLEN bit is unavailable) 1110 = 8x PLL is selected 1101 = 6x PLL is selected 1100 = 4x PLL is selected 0111 = 96 MHz PLL is selected (Input Frequency = 48 MHz) 0110 = 96 MHz PLL is selected (Input Frequency = 32 MHz) 0101 = 96 MHz PLL is selected (Input Frequency = 24 MHz) 0100 = 96 MHz PLL is selected (Input Frequency = 20 MHz) 0011 = 96 MHz PLL is selected (Input Frequency = 16 MHz) 0010 = 96 MHz PLL is selected (Input Frequency = 12 MHz) 0001 = 96 MHz PLL is selected (Input Frequency = 8 MHz) 0000 = 96 MHz PLL is selected (Input Frequency = 4 MHz) bit 2-0 FNOSC[2:0]: Oscillator Selection bits 111 = Oscillator with Frequency Divider (OSCFDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with PLL (FRCPLL) 000 = Fast RC Oscillator (FRC)

DS30010198B-page 314  2019-2020 Microchip Technology Inc. REGISTER 27-5: FOSC CONFIGURATION REGISTER U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 23 bit 16 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 FCKSM1 FCKSM0 IOL1WAY PLLSS SOSCSEL OSCIOFNC POSCMD1 POSCMD0 bit 7 bit 0 Legend: PO = Program Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-8 Unimplemented: Read as ‘1’ bit 7-6 FCKSM[1:0]: Clock Switching and Monitor Selection bits 1x = Clock switching and the Fail-Safe Clock Monitor are disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching and the Fail-Safe Clock Monitor are enabled bit 5 IOL1WAY: Peripheral Pin Select Configuration bit 1 = The IOLOCK bit can be set only once (with unlock sequence). 0 = The IOLOCK bit can be set and cleared as needed (with unlock sequence) bit 4 PLLSS: PLL Secondary Selection Configuration bit This Configuration bit only takes effect when the PLL is NOT being used by the system (i.e., not selected as part of the system clock source). Used to generate an independent clock out of REFO. 1 = PLL is fed by the Primary Oscillator 0 = PLL is fed by the on-chip Fast RC (FRC) Oscillator bit 3 SOSCSEL: SOSC Selection Configuration bit 1 = Crystal (SOSCI/SOSCO) mode 0 = Digital (SCLKI) Externally Supplied Clock mode bit 2 OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output signal is active on the OSCO pin (when the Primary Oscillator is disabled or configured for EC mode) 0 = CLKO output is disabled bit 1-0 POSCMD[1:0]: Primary Oscillator Configuration bits 11 = Primary Oscillator mode is disabled 10 = HS Oscillator mode is selected (10 MHz-32 MHz) 01 = XT Oscillator mode is selected (1.5 MHz-10 MHz) 00 = External Clock mode is selected

 2019-2020 Microchip Technology Inc. DS30010198B-page 315 PIC24FJ128GL306 FAMILY REGISTER 27-6: FWDT CONFIGURATION REGISTER U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 23 bit 16 U-1 R/PO-1 R/PO-1 U-1 R/PO-1 U-1 R/PO-1 R/PO-1 — WDTCLK1 WDTCLK0 — WDTCMX — WDTWIN1 WDTWIN0 bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 WINDIS FWDTEN1 FWDTEN0 FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: PO = Program Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-15 Unimplemented: Read as ‘1’ bit 14-13 WDTCLK[1:0]: Watchdog Timer Clock Select bits (when WDTCMX = 1) 11 = Always uses LPRC 10 = Uses FRC when WINDIS = 0, system clock is not LPRC and device is not in Sleep; otherwise, uses LPRC 01 = Always uses SOSC 00 = Uses peripheral clock when system clock is not LPRC and device is not in Sleep; otherwise, uses LPRC bit 12 Unimplemented: Read as ‘1’ bit 11 WDTCMX: WDT Clock MUX Control bit 1 = Enables WDT clock MUX, WDT clock is selected by WDTCLK[1:0] 0 = WDT clock is LPRC bit 10 Unimplemented: Read as ‘1’ bit 9-8 WDTWIN[1:0]: Watchdog Timer Window Width bits 11 = WDT window is 25% of the WDT period 10 = WDT window is 37.5% of the WDT period 01 = WDT window is 50% of the WDT period 00 = WDT window is 75% of the WDT period bit 7 WINDIS: Windowed Watchdog Timer Disable bit 1 = Windowed WDT is disabled 0 = Windowed WDT is enabled bit 6-5 FWDTEN[1:0]: Watchdog Timer Enable bits 11 = WDT is enabled 10 = WDT is disabled (control is placed on the SWDTEN bit) 01 = WDT is enabled only while device is active and disabled in Sleep; SWDTEN bit is disabled 00 = WDT and SWDTEN are disabled bit 4 FWPSA: Watchdog Timer Prescaler bit 1 = WDT prescaler ratio of 1:128 0 = WDT prescaler ratio of 1:32

DS30010198B-page 316  2019-2020 Microchip Technology Inc. bit 3-0 WDTPS[3:0]: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 REGISTER 27-6: FWDT CONFIGURATION REGISTER (CONTINUED)

 2019-2020 Microchip Technology Inc. DS30010198B-page 317 PIC24FJ128GL306 FAMILY REGISTER 27-7: FPOR CONFIGURATION REGISTER U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 23 bit 16 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 15 bit 8 U-1 U-1 U-1 U-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 — — — — DNVPEN LPCFG BOREN1 BOREN0 bit 7 bit 0 Legend: PO = Program Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-4 Unimplemented: Read as ‘1’ bit 3 DNVPEN: Downside Voltage Protection Enable bit 1 = Downside protection is enabled when BOR is inactive 0 = Downside protection is disabled when BOR is inactive bit 2 LPCFG: Low-Power Regulator Control bit 1 = Retention feature is not available 0 = Retention feature is available and controlled by RETEN during Sleep bit 1-0 BOREN[1:0]: Brown-out Reset Enable bits 11 = Brown-out Reset is enabled in hardware; SBOREN bit is disabled 10 = Brown-out Reset is enabled only while device is active and is disabled in Sleep; SBOREN bit is disabled 01 = Brown-out Reset is controlled with the SBOREN bit setting 00 = Brown-out Reset is disabled in hardware; SBOREN bit is disabled

DS30010198B-page 318  2019-2020 Microchip Technology Inc. REGISTER 27-8: FICD CONFIGURATION REGISTER U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 23 bit 16 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 15 bit 8 r-1 U-1 R/PO-0 U-1 U-1 U-1 R/PO-1 R/PO-1 — —J T A G E N — — — ICS1 ICS0 bit 7 bit 0 Legend: PO = Program Once bit r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-8 Unimplemented: Read as ‘1’ bit 7 Reserved: Maintain as ‘1’ bit 6 Unimplemented: Read as ‘1’ bit 5 JTAGEN: JTAG Port Enable bit 1 = JTAG port is enabled 0 = JTAG port is disabled bit 4-2 Unimplemented: Read as ‘1’ bit 1-0 ICS[1:0]: ICD Communication Channel Select bits 11 = Communicates on PGC1/PGD1 10 = Communicates on PGC2/PGD2 01 = Communicates on PGC3/PGD3 00 = Reserved; do not use

 2019-2020 Microchip Technology Inc. DS30010198B-page 319 PIC24FJ128GL306 FAMILY REGISTER 27-9: FDMTIVTL CONFIGURATION REGISTER U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 23 bit 16 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 DMTIVT[15:8] bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 DMTIVT[7:0] bit 7 bit 0 Legend: PO = Program Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15-0 DMTIVT[15:0]: DMT Window Interval Lower 16 bits REGISTER 27-10: FDMTIVTH CONFIGURATION REGISTER U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 23 bit 16 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 DMTIVT[31:24] bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 DMTIVT[23:16] bit 7 bit 0 Legend: PO = Program Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15-0 DMTIVT[31:16]: DMT Window Interval Higher 16 bits

DS30010198B-page 320  2019-2020 Microchip Technology Inc. REGISTER 27-11: FDMTCNTL CONFIGURATION REGISTER U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 23 bit 16 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 DMTCNT[15:8] bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 DMTCNT[7:0] bit 7 bit 0 Legend: PO = Program Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15-0 DMTCNT[15:0]: DMT Instruction Count Time-out Value Lower 16 bits REGISTER 27-12: FDMTCNTH CONFIGURATION REGISTER U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 23 bit 16 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 DMTCNT[31:24] bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 DMTCNT[23:16] bit 7 bit 0 Legend: PO = Program Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15-0 DMTIVT[31:16]: DMT Instruction Count Time-out Value Higher 16 bits

 2019-2020 Microchip Technology Inc. DS30010198B-page 321 PIC24FJ128GL306 FAMILY REGISTER 27-13: FDMT CONFIGURATION REGISTER U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 23 bit 16 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 15 bit 8 U-1 U-1 U-1 U-1 U-1 U-1 U-1 R/PO-1 bit 7 bit 0 Legend: PO = Program Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-1 Unimplemented: Read as ‘1’ bit 0 DMTDIS: DMT Disable bit 1 = DMT is disabled 0 = DMT is enabled

DS30010198B-page 322  2019-2020 Microchip Technology Inc. REGISTER 27-14: FDEVOPT1 CONFIGURATION REGISTER U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 23 bit 16 U-1 U-1 U-1 U-1 U-1 R/PO-1 U-1 U-1 bit 15 bit 8 U-1 U-1 U-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 U-1 — — — ALTI2C1 SOSCHP TMPRPIN ALTCMPI — bit 7 bit 0 Legend: PO = Program Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-11 Unimplemented: Read as ‘1’ bit 10 SMB3EN: SMBus 3.0 Levels Enable bit(2) 1 = SMBus 3.0 input levels 0 = Normal I2C input levels bit 9-5 Unimplemented: Read as ‘1’ bit 4 ALTI2C1: Alternate I2C1 bit 1 = SDA1 and SCL1 on RG2 and RG3 0 = ASDA1 and ASCL1 on RB5 and RB4 bit 3 SOSCHP: SOSC High-Power Enable bit (valid only when SOSCSEL = 1) 1 = SOSC High-Power mode is enabled 0 = SOSC Low-Power mode is enabled (see Section 9.10.3 “Low-Power SOSC Operation” for more information) bit 2 TMPRPIN: Tamper Pin Enable bit 1 = TMPRN pin function is disabled 0 = TMPRN pin function is enabled bit 1 ALTCMPI: Alternate Comparator Input Enable bit 1 = C2INC and C3INC are on their standard pin locations 0 = C2INC and C3INC are on RG7(1) bit 0 Unimplemented: Read as ‘1’ Note 1: RG7 is used for multiple functions, but only one use case is allowable. 2: SMBus mode is enabled by the SMEN bit (I2CxCONL[8]).

 2019-2020 Microchip Technology Inc. DS30010198B-page 323 PIC24FJ128GL306 FAMILY TABLE 27-3: PIC24FJ CORE DEVICE ID REGISTERS TABLE 27-4: DEVICE ID BIT FIELD DESCRIPTIONS TABLE 27-5: PIC24FJ128GL306 FAMILY DEVICE IDs

27.2 Unique Device Identifier (UDID)

All PIC24FJ128GL306 family devices are individually encoded during final manufacturing with a Unique Device Identifier, or UDID. The UDID cannot be erased by a bulk erase command or any other user-accessible means. This feature allows for manufacturing traceability of Microchip Technology devices in applica- tions where this is a requirement. It may also be used by the application manufacturer for any number of things that may require unique identification, such as:

• Tracking the device
• Unique serial number
• Unique security key The UDID comprises five 24-bit program words. When taken together, these fields form a unique 120-bit identifier. The UDID is stored in five read-only locations, located between 0x801600 and 0x801608 in the device config- uration space. Table 27-6 lists the addresses of the Identifier Words and shows their contents. Address Name Bit 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 FF0000h DEVID FAMID[7:0] DEV[7:0] FF0002h DEVREV — REV[3:0] Bit Field Register Description FAMID[7:0] DEVID Encodes the family ID of the device; FAMID = 0x22. DEV[7:0] DEVID Encodes the individual ID of the device. REV[3:0] DEVREV Encodes the sequential (numerical) revision identifier of the device. Device DEVID PIC24FJ128GL306 0x220E PIC24FJ64GL306 0x2206 PIC24FJ128GL305 0x220C PIC24FJ64GL305 0x2204 PIC24FJ128GL303 0x220A PIC24FJ64GL303 0x2202 PIC24FJ128GL302 0x2208 PIC24FJ64GL302 0x2200 TABLE 27-6: UDID ADDRESSES UDID Address Description UDID1 0x801600 UDID Word 1 UDID2 0x801602 UDID Word 2 UDID3 0x801604 UDID Word 3 UDID4 0x801606 UDID Word 4 UDID5 0x801608 UDID Word 5

DS30010198B-page 324  2019-2020 Microchip Technology Inc.

27.3 On-Chip Voltage Regulator

All PIC24FJ128GL306 family devices power their core digital logic at a nominal 1.8V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ128GL306 family incorporate an on-chip regulator that allows the device to run its core logic from V DD. This regulator is always enabled. It provides a constant voltage (1.8V nominal) to the digital core logic, from a V DD of about 2.1V, all the way up to the device’s VDDMAX. It does not have the capability to boost V DD levels. In order to prevent brown-out conditions when the voltage drops too low for the regulator, the Brown- out Reset occurs. Then, the regulator output follows VDD with a typical voltage drop of 300 mV. A low-ESR capacitor (such as ceramic) must be connected to the VCAP pin ( Figure 27-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor (C EFC) is provided in Section 30.1 “DC Characteristics”. FIGURE 27-1: CONNE CTIONS FOR THE ON-CHIP REGULATOR

27.3.1 ON-CHIP REGULATOR AND POR

The voltage regulator takes approximately 10 µs for it to generate output. During this time, designated as T VREG, code execution is disabled. T VREG is applied every time the device resumes operation after any power-down, including Sleep mode. T VREG is deter- mined by the status of the VREGS bit (RCON[8]) and the WDTWIN[1:0] Configuration bits (FWDT[9:8]). Refer to Section 30.0 “Electrical Characteristics” for more information on TVREG.

27.3.2 VOLTAGE REGULATOR STANDBY

The on-chip regulator always consumes a small incre- mental amount of current over IDD/IPD, including when the device is in Sleep mode, even though the core digital logic does not require power. To provide addi- tional savings in applications where power resources are critical, the regulator can be made to enter Standby mode, on its own, whenever the device goes into Sleep mode. This feature is controlled by the VREGS bit (RCON[8]). Clearing the VREGS bit enables the Standby mode. When waking up from Standby mode, the regulator needs to wait for T VREG to expire before wake-up.

27.3.3 LOW-VOLTAGE RETENTION

When in Sleep mode, PIC24FJ128GL306 family devices may use a separate low-power, low-voltage retention regulator to power critical circuits. This regu- lator, which operates at 1.2V nominal, maintains power to data RAM and the RTCC, while all other core digital logic is powered down. The low-voltage retention regu- lator is described in more detail in Section 10.2.4 “Low-Voltage Retention Regulator”. VDD VCAP VSS PIC24FJXXXGL30X CEFC 3.3V(1) Note 1: This is a typical operating voltage. Refer to Section 30.0 “Electrical Characteristics” for the full operating ranges of VDD. (10 F typ.) Note: For more information, see Section 30.0 “Electrical Characteristics”. The infor- mation in this data sheet supersedes the information in the FRM.

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27.4 Watchdog Timer (WDT)

For PIC24FJ128GL306 family devices, the WDT is driven by the LPRC Oscillator, the Secondary Oscillator (SOSC) or the system timer. When the device is in Sleep mode, the LPRC Oscillator will be used. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. With a 32 kHz input, the prescaler yields a nominal WDT Time-out (T WDT) period of 1 ms in 5-bit mode or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPS[3:0] Config- uration bits (FWDT[3:0]), which allow the selection of a total of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler time-out periods, ranges from 1 ms to 131 seconds can be achieved. The WDT, prescaler and postscaler are reset:

• On any device Reset
• On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSCx bits) or by hardware (i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to resume normal operation
• B y a CLRWDT instruction during normal execution If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE (RCON[3:2]) bits will need to be cleared in software after the device wakes up. The WDT Time-out Flag bit, WDTO (RCON[4]), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software.

27.4.1 WINDOWED OPERATION

The Watchdog Timer has an optional Fixed Window mode of operation. In this Windowed mode, CLRWDT instructions can only reset the WDT during the last 1/4 of the programmed WDT period. A CLRWDT instruction executed before that window causes a WDT Reset, similar to a WDT time-out. Windowed WDT mode is enabled by programming the WINDIS Configuration bit (FWDT[7]) to ‘0’.

27.4.2 CONTROL REGISTER

The WDT is enabled or disabled by the FWDTEN[1:0] Configuration bits (FWDT[6:5]). When the Configuration bits, FWDTEN[1:0] = 11, the WDT is always enabled. The WDT can be optionally controlled in software when the Configuration bits, FWDTEN[1:0] = 10. When FWDTEN[1:0] = 00, the Watchdog Timer is always dis- abled. The WDT is enabled in software by setting the SWDTEN control bit (RCON[5]). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user to enable the WDT for critical code segments and disable the WDT during non-critical code segments for maximum power savings. Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed.

DS30010198B-page 326  2019-2020 Microchip Technology Inc. FIGURE 27-2: WDT BLOCK DIAGRAM WDT Overflow Wake from 32 kHz Prescaler Postscaler FWPSA SWDTEN FWDTEN[1:0] Reset Sleep or Idle Mode LPRC Control (5-bit/7-bit) 1:1 to 1:32.768 WDTPS[3:0] 1 ms/4 ms WDT Counter SOSC FRC Peripheral Clock WDTCLK[1:0] LPRC WINDIS System Clock (LRPC) Sleep CLRWDT Instr. PWRSAV Instr. All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode

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27.5 Program Verification and

PIC24FJ128GL306 family devices offer basic implementation of CodeGuard™ Security that supports General Segment (GS) security and Boot Segment (BS) security. This feature helps protect individual intellectual property.

27.6 JTAG Interface

PIC24FJ128GL306 family devices implement a JTAG interface, which supports boundary scan device testing.

27.7 In-Circuit Serial Programming™

PIC24FJ128GL306 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock (PGCx) and data (PGDx), and three other lines for power (V DD), ground (VSS) and MCLR. This allows customers to man- ufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.

27.8 Customer OTP Memory

PIC24FJ128GL306 family devices provide 256 bytes of One-Time-Programmable (OTP) memory, located at addresses, 801700h through 8017FEh. This memory can be used for persistent storage of application-specific information that will not be erased by reprogramming the device. This includes many types of information, such as (but not limited to):

• Application checksums
• Code revision information
• Product information
• Serial numbers
• System manufacturing dates
• Manufacturing lot numbers Customer OTP memory may be programmed in any mode, including user RTSP mode, but it cannot be erased. Data are not cleared by a chip erase.

27.9 In-Circuit Debugger

This function allows simple debugging functions when used with MPLAB ® X IDE. Debugging functionality is controlled through the PGCx (Emulation/Debug Clock) and PGDx (Emulation/Debug Data) pins. To use the in-circuit debugger function of the device, the design must implement ICSP™ connections to MCLR , VDD, VSS and the PGCx/PGDx pin pair, desig- nated by the ICS[1:0] Configuration bits. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. Note: For more information on usage, con- figuration and operation, refer to “CodeGuard™ Intermediate Security” (www.microchip.com/DS70005182) in the “dsPIC33/PIC24 Family Reference Manual”. Note: Do not write the OTP memory more than once. Writing to the OTP memory more than once may result in an ECC Double-Bit Error (ECCDBE).

DS30010198B-page 328  2019-2020 Microchip Technology Inc. NOTES:

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28.0 INSTRUCTION SET SUMMARY

The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while main- taining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories:

• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
• Control operations Table 28-1 shows the general symbols used in describing the instructions. The PIC24F instruction set summary in Table 28-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands:
• The first source operand, which is typically a register, ‘Wb’, without any address modifier
• The second source operand, which is typically a register, ‘Ws’, with or without an address modifier
• The destination of the result, which is typically a register, ‘Wd’, with or without an address modifier However, word or byte-oriented file register instructions have two operands:
• The file register specified by the value, ‘f’
• The destination, which could either be the file register, ‘f’, or the W0 register, which is denoted as ‘WREG’ Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands:
• The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’)
• The bit in the W register or file register (specified by a literal value or indirectly by the contents of register, ‘Wb’) The literal instructions that involve data movement may use some of the following operands:
• A literal value to be loaded into a W register or file register (specified by the value of ‘k’)
• The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’) However, literal instructions that involve arithmetic or logical operations use some of the following operands:
• The first source operand, which is a register, ‘Wb’, without any address modifier
• The second source operand, which is a literal value
• The destination of the result (only if not the same as the first source operand), which is typically a register, ‘Wd’, with or without an address modifier The control instructions may use some of the following operands:
• A program memory address
• The mode of the Table Read and Table Write instructions All instructions are a single word, except for certain double-word instructions, which were made double- word instructions so that all the required information is available in these 48 bits. In the second word, the 8M S b s a r e ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the Program Counter is changed as a result of the instruc- tion. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (uncondi- tional/computed branch), indirect CALL/GOTO, all Table Reads and Table Writes, and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the sub- sequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. Note: This chapter is a brief summary of the PIC24F Instruction Set Architecture (ISA) and is not intended to be a comprehensive reference source.

DS30010198B-page 330  2019-2020 Microchip Technology Inc. TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “ text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation [n:m] Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit Bit Selection field (used in word addressed instructions) {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address {0000h...1FFFh} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit14 14-bit unsigned literal {0...16383} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388607}; LSb must be ‘0’ None Field does not require an entry, may be blank PC Program Counter Slit10 10-bit signed literal {-512...511} Slit16 16-bit signed literal {-32768...32767} Slit6 6-bit signed literal {-16...16} Wb Base W register {W0..W15} Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register  { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor Working register pair (direct addressing) Wn One of 16 Working registers {W0..W15} Wnd One of 16 destination Working registers {W0..W15} Wns One of 16 source Working registers {W0..W15} WREG W0 (Working register used in file register instructions) Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }

 2019-2020 Microchip Technology Inc. DS30010198B-page 331 PIC24FJ128GL306 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected ADD ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC ADDC f f = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C, DC, N, OV, Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C, DC, N, OV, Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C, DC, N, OV, Z AND AND f f = f .AND. WREG 1 1 N, Z AND f,WREG WREG = f .AND. WREG 1 1 N, Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N, Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N, Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N, Z ASR ASR f f = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C, N, OV, Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N, Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N, Z BCLR BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None BRA BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if Greater Than or Equal 1 1 (2) None BRA GEU,Expr Branch if Unsigned Greater Than or Equal 1 1 (2) None BRA GT,Expr Branch if Greater Than 1 1 (2) None BRA GTU,Expr Branch if Unsigned Greater Than 1 1 (2) None BRA LE,Expr Branch if Less Than or Equal 1 1 (2) None BRA LEU,Expr Branch if Unsigned Less Than or Equal 1 1 (2) None BRA LT,Expr Branch if Less Than 1 1 (2) None BRA LTU,Expr Branch if Unsigned Less Than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None BSET BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None BSW BSW.C Ws,Wb Write C bit to Ws[Wb] 1 1 None BSW.Z Ws,Wb Write Z bit to Ws[Wb] 1 1 None BTG BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 (2 or 3) None BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 (2 or 3) None

DS30010198B-page 332  2019-2020 Microchip Technology Inc. BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 (2 or 3) None BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 (2 or 3) None BTST BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws[Wb] to C 1 1 C BTST.Z Ws,Wb Bit Test Ws[Wb] to Z 1 1 Z BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z CALL CALL lit23 Call Subroutine 2 2 None CALL Wn Call Indirect Subroutine 1 2 None CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO, Sleep COM COM f f = f 11 N , Z COM f,WREG WREG = f 11 N , Z COM Ws,Wd Wd = Ws 11 N , Z CP CP f Compare f with WREG 1 1 C, DC, N, OV, Z CP Wb,#lit5 Compare Wb with lit5 1 1 C, DC, N, OV, Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C, DC, N, OV, Z CP0 CP0 f Compare f with 0x0000 1 1 C, DC, N, OV, Z CP0 Ws Compare Ws with 0x0000 1 1 C, DC, N, OV, Z CPB CPB f Compare f with WREG, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,Ws Compare Wb with Ws, with Borrow (Wb – Ws – C) 1 1 C, DC, N, OV, Z CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, Skip if = 1 1 (2 or 3) None CPSGT CPSGT Wb,Wn Compare Wb with Wn, Skip if > 1 1 (2 or 3) None CPSLT CPSLT Wb,Wn Compare Wb with Wn, Skip if < 1 1 (2 or 3) None CPSNE CPSNE Wb,Wn Compare Wb with Wn, Skip if  11 (2 or 3) None DAW DAW.B Wn Wn = Decimal Adjust Wn 1 1 C DEC DEC f f = f –1 1 1 C, DC, N, OV, Z DEC f,WREG WREG = f –1 1 1 C, DC, N, OV, Z DEC Ws,Wd Wd = Ws – 1 1 1 C, DC, N, OV, Z DEC2 DEC2 f f = f – 2 1 1 C, DC, N, OV, Z DEC2 f,WREG WREG = f – 2 1 1 C, DC, N, OV, Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C, DC, N, OV, Z DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None DIV DIV.SW Wm,Wn Signed 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UW Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N, Z, C, OV EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected

 2019-2020 Microchip Technology Inc. DS30010198B-page 333 PIC24FJ128GL306 FAMILY GOTO GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC INC f f = f + 1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z INC2 INC2 f f = f + 2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z INC2 Ws,Wd Wd = Ws + 2 1 1 C, DC, N, OV, Z IOR IOR f f = f .IOR. WREG 1 1 N, Z IOR f,WREG WREG = f .IOR. WREG 1 1 N, Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N, Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N, Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N, Z LNK LNK #lit14 Link Frame Pointer 1 1 None LSR LSR f f = Logical Right Shift f 1 1 C, N, OV, Z LSR f,WREG WREG = Logical Right Shift f 1 1 C, N, OV, Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C, N, OV, Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N, Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N, Z MOV MOV f,Wn Move f to Wn 1 1 None MOV [Wns+Slit10],Wnd Move [Wns+Slit10] to Wnd 1 1 None MOV f Move f to f 1 1 N, Z MOV f,WREG Move f to WREG 1 1 N, Z MOV #lit16,Wn Move 16-bit Literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit Literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wns,[Wns+Slit10] Move Wns to [Wns+Slit10] 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 N, Z MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None MUL MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) 1 1 None MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) 1 1 None MUL f W3:W2 = f * WREG 1 1 None NEG NEG f f = f + 1 1 1 C, DC, N, OV, Z NEG f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z NEG Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z NOP NOP No Operation 1 1 None NOPR No Operation 1 1 None POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) 1 2 None POP.S Pop Shadow Registers 1 1 All PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns+1) to Top-of-Stack (TOS) 1 2 None PUSH.S Push Shadow Registers 1 1 None TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected

DS30010198B-page 334  2019-2020 Microchip Technology Inc. PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 Times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 Times 1 1 None RESET RESET Software Device Reset 1 1 None RETFIE RETFIE Return from Interrupt 1 3 (2) None RETLW RETLW #lit10,Wn Return with Literal in Wn 1 3 (2) None RETURN RETURN Return from Subroutine 1 3 (2) None RLC RLC f f = Rotate Left through Carry f 1 1 C, N, Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C, N, Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C, N, Z RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N, Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N, Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N, Z RRC RRC f f = Rotate Right through Carry f 1 1 C, N, Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C, N, Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C, N, Z RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N, Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N, Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N, Z SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C, N, Z SETM SETM f f = FFFFh 1 1 None SETM WREG WREG = FFFFh 1 1 None SETM Ws Ws = FFFFh 1 1 None SL SL f f = Left Shift f 1 1 C, N, OV, Z SL f,WREG WREG = Left Shift f 1 1 C, N, OV, Z SL Ws,Wd Wd = Left Shift Ws 1 1 C, N, OV, Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N, Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N, Z SUB SUB f f = f – WREG 1 1 C, DC, N, OV, Z SUB f,WREG WREG = f – WREG 1 1 C, DC, N, OV, Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C, DC, N, OV, Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C, DC, N, OV, Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C, DC, N, OV, Z SUBB SUBB f f = f – WREG – (C) 1 1 C, DC, N, OV, Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C, DC, N, OV, Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C, DC, N, OV, Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C, DC, N, OV, Z SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C, DC, N, OV, Z SUBR SUBR f f = WREG – f 1 1 C, DC, N, OV, Z SUBR f,WREG WREG = WREG – f 1 1 C, DC, N, OV, Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C, DC, N, OV, Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C, DC, N, OV, Z SUBBR SUBBR f f = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C, DC, N, OV, Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C, DC, N, OV, Z SWAP SWAP.b Wn Wn = Nibble Swap Wn 1 1 None SWAP Wn Wn = Byte Swap Wn 1 1 None TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected

 2019-2020 Microchip Technology Inc. DS30010198B-page 335 PIC24FJ128GL306 FAMILY TBLRDH TBLRDH Ws,Wd Read Prog[23:16] to Wd[7:0] 1 2 None TBLRDL TBLRDL Ws,Wd Read Prog[15:0] to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws[7:0] to Prog[23:16] 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog[15:0] 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR. WREG 1 1 N, Z XOR f,WREG WREG = f .XOR. WREG 1 1 N, Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N, Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N, Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N, Z ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C, Z, N TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected

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29.0 DEVELOPMENT SUPPORT

Move a design from concept to production in record time with Microchip’s award-winning development tools. Microchip tools work together to provide state of the art debugging for any project with easy-to-use Graphical User Interfaces (GUIs) in our free MPLAB® X and Atmel Studio Integrated Development Environments (IDEs), and our code generation tools. Providing the ultimate ease-of-use experience, Microchip’s line of programmers, debuggers and emulators work seamlessly with our software tools. Microchip development boards help evaluate the best silicon device for an application, while our line of third party tools round out our comprehensive development tool solutions. Microchip’s MPLAB X and Atmel Studio ecosystems provide a variety of embedded design tools to consider, which sup- port multiple devices, such as PIC® MCUs, AVR® MCUs, SAM MCUs and dsPIC® DSCs. MPLAB X tools are compatible with Windows®, Linux® and Mac® operating systems while Atmel Studio tools are compatible with Windows. Go to the following website for more information and details: https://www.microchip.com/development-tools/

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30.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of the PIC24FJ128GL306 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(†) Voltage on any general purpose digital or analog pin (5.5V tolerant, including MCLR) with respect to VSS: Maximum current out of VSS pin: Maximum current into VDD pin (Note 1): Maximum output current sunk by any I/O pin: Maximum output current sourced by any I/O pin: Maximum current sunk by group of I/Os between two VSS Pins (Note 2): Maximum current sourced by group of I/Os between two VDD pins (Note 2): Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 30-1). 2: Only on the 28-lead and 36-lead packages can AVDD/AVSS be considered for grouping of I/Os. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

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30.1 DC Characteristics

FIGURE 30-1: PIC24FJ128GL306 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) TABLE 30-1: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit PIC24FJ128GL306: Operating Junction Temperature Range T J -40 — +135 °C Operating Ambient Temperature Range T A -40 — +125 °C Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD –  IOH) PD PINT + PI/O W I/O Pin Power Dissipation: PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation P DMAX (TJ – TA)/JA W Frequency Voltage (VDD) (Note 1) 3.6V 3.6V (Note 1) Note 1: Lower operating boundary is 2.0V or VBOR (when BOR is enabled), whichever is lower. For best analog performance, operate above 2.2V. PIC24FJ128GL306 TABLE 30-2: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Notes Package Thermal Resistance, 6x6 mm 28-Pin QFN JA 38.4 — °C/W (Note 1) Package Thermal Resistance, 4x4x0.6 mm 28-Pin UQFN JA 38.7 — °C/W (Note 1) Package Thermal Resistance, 7.50 mm 28-Pin SOIC JA 79.0 — °C/W (Note 1) Package Thermal Resistance, 5.30 mm 28-Pin SSOP JA 67.1 — °C/W (Note 1) Package Thermal Resistance, 5x5 mm 36-Pin UQFN JA 35.4 — °C/W (Note 1) Package Thermal Resistance, 6x6x0.5 mm 48-Pin UQFN JA 28.3 — °C/W (Note 1) Package Thermal Resistance, 7x7x1 mm 48-Pin TQFP JA 71.0 — °C/W (Note 1) Package Thermal Resistance, 9x9x0.9 mm 64-Pin QFN JA 23.0 — °C/W (Note 1) Package Thermal Resistance, 10x10x1 mm 64-Pin TQFP JA 68.9 — °C/W (Note 1) Note 1: Junction to ambient thermal resistance; Theta-JA (JA) numbers are achieved by package simulations.

 2019-2020 Microchip Technology Inc. DS30010198B-page 341 PIC24FJ128GL306 FAMILY TABLE 30-3: TEMPERATURE AND VOLTAGE SPECIFICATIONS Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param No. Symbol Characteristic Min Typ Max Units Conditions Operating Voltage DC10 V DD Supply Voltage 2.0 — 3.6 V BOR is disabled VBOR — 3.6 V BOR is enabled DC16 V POR VDD Start Voltage to Ensure Internal Power-on Reset Signal VSS —— V (Note 1) DC17A SV DD Recommended VDD Rise Rate to Ensure Internal Power-on Reset Signal 1V/20 ms — 1V/10 µS sec (Notes 1 and 3) DC17B V BOR Brown-out Reset Voltage on VDD Transition, High-to-Low 1.95 2.1 2.2 V (Note 2) Note 1: If the VPOR or SVDD parameters are not met, or the application experiences slow power-down VDD ramp rates, it is recommended to enable and use BOR. 2: On a rising VDD power-up sequence, application firmware execution begins at the higher of the VPORREL or VBOR level (when BOREN = 1). 3: VDD rise times outside this window may not internally reset the processor and are not parametrically tested.

DS30010198B-page 342  2019-2020 Microchip Technology Inc. TABLE 30-4: OPERATING CURRENT (I DD) Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter No. Typical(1) Max(2) Units Operating Temperature VDD Conditions Operating Current (IDD)(3) DC19 208.8 350 µA -40°C to +125°C 2.0V 0.5 MIPS, FOSC = 1 MHz215.4 350 µA 3.3V DC20 362.3 550 µA -40°C to +125°C 2.0V 1 MIPS, FOSC = 2 MHz366.4 550 µA 3.3V DC23 1.3 1.6 mA -40°C to +125°C 2.0V 4 MIPS, FOSC = 8 MHz1.35 1.6 mA 3.3V DC24 5 6.2 mA -40°C to +125°C 2.0V 16 MIPS, FOSC = 32 MHz5.1 6.2 mA 3.3V DC31 41.5 130 µA -40°C to +85°C 2.0V LPRC (16 KIPS), FOSC = 32 kHz 47.4 130 µA 3.3V 55.5 310 µA -40°C to +125°C 2.0V 61.9 310 µA 3.3V DC32 1.34 1.7 mA -40°C to +125°C 2.0V FRC (4 MIPS), FOSC = 8 MHz1.35 1.7 mA 3.3V Note 1: Data in the “Typical” column are at 3.3V, +25°C unless otherwise stated. Typical parameters are for design guidance only and are not tested. 2: Data in “Max” column are production tested. 3: Base IDD current is measured with:

• Oscillator is configured in EC mode without PLL (FNOSC[2:0] (FOSCSEL[2:0]) = 010, PLLMODE[3:0] (FOSCSEL[6:3]) = 1111 and POSCMOD[1:0] (FOSC[1:0]) = 00)
• OSCI pin is driven with external square wave, with levels from 0.3V to V DD – 0.3V
• OSCO is configured as an I/O in the Configuration Words (OSCIOFCN (FOSC[2]) = 0)
• FSCM is disabled (FCKSM[1:0] (FOSC[7:6]) = 11)
• Secondary Oscillator circuit is disabled (SOSCSEL (FOSC[3]) = 0)
• Main and low-power BOR circuits are disabled (BOREN[1:0] (FPOR[1:0]) = 00 and LPBOREN (FPOR[3]) = 0)
• Watchdog Timer is disabled (FWDTEN[1:0] (FWDT[6:5]) = 00)
• All I/O pins (except OSCI) are configured as outputs and driving low
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
• JTAG is disabled (JTAGEN (FICD[5]) = 0)
• NOP instructions are executed

 2019-2020 Microchip Technology Inc. DS30010198B-page 343 PIC24FJ128GL306 FAMILY TABLE 30-5: IDLE CURRENT (I IDLE) Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter No. Typical(1) Max(2) Units Operating Temperature VDD Conditions Idle Current (IIDLE)(3) DC40 110 250 µA -40°C to +85°C 2.0V

1 MIPS,

FOSC = 2 MHz 121.3 250 µA 3.3V 130.2 325 µA -40°C to +125°C 2.0V 130.2 325 µA 3.3V DC43 329.7 500 µA -40°C to +85°C 2.0V

4 MIPS,

FOSC = 8 MHz 357.5 500 µA 3.3V 350 600 µA -40°C to +125°C 2.0V 370.9 600 µA 3.3V DC47 1.2 1.8 mA -40°C to +85°C 2.0V

16 MIPS,

FOSC = 32 MHz 1.3 1.8 mA 3.3V 1.22 1.9 mA -40°C to +125°C 2.0V 1.31 1.9 mA 3.3V DC50 369.6 550 µA -40°C to +85°C 2.0V FRC (4 MIPS), FOSC = 8 MHz 375.1 550 µA 3.3V 382.9 650 µA -40°C to +125°C 2.0V 388.9 650 µA 3.3V DC51 37.5 110 µA -40°C to +85°C 2.0V LPRC (16 KIPS), FOSC = 32 kHz 43.3 110 µA 3.3V 50.8 300 µA -40°C to +125°C 2.0V 57.1 300 µA 3.3V Note 1: Data in the “Typical” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Data in “Max” column are production tested. 3: Base IIDLE current is measured with:

• Oscillator is configured in EC mode without PLL (FNOSC[2:0] (FOSCSEL[2:0]) = 010, PLLMODE[3:0] (FOSCSEL[6:3]) = 1111 and POSCMOD[1:0] (FOSC[1:0]) = 00)
• OSCI pin is driven with external square wave, with levels from 0.3V to V DD – 0.3V
• OSCO is configured as an I/O in Configuration Words (OSCIOFCN (FOSC[2]) = 0)
• FSCM is disabled (FCKSM[1:0] (FOSC[7:6]) = 11)
• Secondary Oscillator circuit is disabled (SOSCSEL (FOSC[3]) = 0)
• Main and low-power BOR circuits are disabled (BOREN[1:0] (FPOR[1:0]) = 00 and LPBOREN (FPOR[3]) = 0)
• Watchdog Timer is disabled (FWDTEN[1:0] (FWDT[6:5]) = 00)
• All I/O pins (except OSCI) are configured as outputs and driving low
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
• JTAG is disabled (JTAGEN (FICD[5]) = 0)
• pwrsav #1 (IDLE) instruction is executed

DS30010198B-page 344  2019-2020 Microchip Technology Inc. TABLE 30-6: POWER-DOWN CURRENT (I PD) Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter No. Typical(1) Max(2) Units Operating Temperature VDD Conditions Power-Down Current(5,6) DC60 3.47 10 µA -40°C 2.0V Sleep(3) 4.31 10 µA +25°C 9.93 20 µA +85°C 38.79 150 µA +125°C 3.72 10 µA -40°C 3.3V4.6 10 µA +25°C 10.27 20 µA +85°C 39.45 150 µA +125°C DC61 272.7 Note 7 nA -40°C 2.0V Low-Voltage Retention Sleep (4)

450 Note 7 nA +25°C

4.5 Note 7 µA +85°C

28.7 Note 7 µA +125°C

336 Note 7 nA -40°C

3.3V460 Note 7 nA +25°C

29 Note 7 µA +125°C

Note 1: Data in the “Typical” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Data in “Max” column are production tested. 3: The retention low-voltage regulator is disabled; RETEN (RCON[12]) = 0, LPCFG (FPOR[2]) = 1. 4: The retention low-voltage regulator is enabled; RETEN (RCON[12]) = 1, LPCFG (FPOR[2]) = 0. 5: Base IPD current is measured with:

• Oscillator is configured in FRC mode without PLL (FNOSC[2:0] (FOSCSEL[2:0]) = 000, PLLMODE[3:0] (FOSCSEL[6:3]) = 1111 and POSCMOD[1:0] (FOSC[1:0]) = 11)
• OSCO is configured as an I/O in Configuration Words (OSCIOFCN (FOSC[2]) = 0)
• FSCM is disabled (FCKSM[1:0] (FOSC[7:6]) = 11)
• Secondary Oscillator circuit is disabled (SOSCSEL (FOSC[3]) = 0)
• Main and low-power BOR circuits are disabled (BOREN[1:0] (FPOR[1:0]) = 00 and LPBOREN (FPOR[3]) = 0)
• Watchdog Timer is disabled (FWDTEN[1:0] (FWDT[6:5]) = 00)
• All I/O pins are configured as outputs and driving low
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
• JTAG is disabled (JTAGEN (FICD[5]) = 0)
• pwrsav #0 (SLEEP) instruction is executed 6: These currents are measured on the device containing the most memory in this family. 7: For design guidance, please refer to Figure 30-2 and Figure 30-3.

 2019-2020 Microchip Technology Inc. DS30010198B-page 345 PIC24FJ128GL306 FAMILY FIGURE 30-2: I PD VS. TEMPERATURE GRAPHS (PAGE 1 OF 2)(1,2) 100 110 120 130 140 150IPD (uA) -40-35-30-25-20-15-10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95100105110115120125 Temperature (ºC) Base IPD (Extended, V=3.3V) Typical Max 100 110 120IPD (uA) -40-35-30-25-20-15-10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95100105110115120125 Temperature (ºC) IPD Retention (Extended, V=3.3V) Typical Max Note 1: For base IPD, temperature points of -40°C, +25°C and +125°C are production tested only. 2: For IPD retention, data provided are characterized but not production tested.

DS30010198B-page 346  2019-2020 Microchip Technology Inc. FIGURE 30-3: I PD VS. TEMPERATURE GRAPHS (PAGE 2 OF 2)(1,2) 25IPD (uA) -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 Temperature (ºC) Base IPD (Industrial, V=3.3V) Typical Max 15IPD (uA) -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 Temperature (ºC) IPD Retention (Industrial, V=3.3V) Typical Max Note 1: For base IPD, temperature points of -40°C, +25°C and +125°C are production tested only. 2: For IPD retention, data provided are characterized but not production tested.

 2019-2020 Microchip Technology Inc. DS30010198B-page 347 PIC24FJ128GL306 FAMILY TABLE 30-7: CURRENT (BOR, WDT, HLVD, ADC, LCD, DMT, RTCC)(3) Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter No. Typical(1) Max Units Operating Temperature VDD Conditions Incremental Current Brown-out Reset (BOR)(2) DC70 1.3 5 µA -40°C to +85°C 2.0V BOR(2)2 5 µA 3.3V 1.5 10 µA -40°C to +125°C 2.0V 2.1 10 µA 3.3V Incremental Current Watchdog Timer (WDT)(2) DC71 0.27 1 µA -40°C to +85°C 2.0V WDT(2)0.35 1 µA 3.3V 0.55 5 µA -40°C to +125°C 2.0V 0.6 5 µA 3.3V Incremental Current High/Low-Voltage Detect (HLVD)(2) DC72 1.9 5 µA -40°C to +85°C 2.0V HLVD(2)2.6 5 µA 3.3V 2.6 10 µA -40°C to +125°C 2.0V 3.3 10 µA 3.3V Incremental Current ADC (ADC)(2) DC73 379.6 700 µA -40°C to +85°C 2.0V ADC(2) with internal RC clock522.7 700 µA 3.3V 398.6 750 µA -40°C to +125°C 2.0V 522 750 µA 3.3V Incremental Current LCD (LCD)(2) DC74 1.3 12 µA -40°C to +125°C 2.0V LCD (low-power resistor ladder)1.7 12 µA 3.3V DC75 7.8 25 µA -40°C to +125°C 2.0V LCD (medium power resistor ladder)12.2 25 µA 3.3V DC76 64.3 140 µA -40°C to +125°C 2.0V LCD (high-power resistor ladder)105.1 140 µA 3.3V DC77 10.2 25 (4) µA -40°C to +85°C 2.0V LCD + Charge Pump (low-power resistor ladder)10.2 25 (4) µA 3.3V DC78 11.5 45 (4) µA -40°C to +125°C 2.0V LCD + Charge Pump (low-power resistor ladder)13.8 45 (4) µA 3.3V DC79 40.1 70 (4) µA -40°C to +85°C 2.0V LCD + Charge Pump (medium power resistor ladder)39.2 70 (4) µA 3.3V Note 1: Data in the “Typical” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Incremental current while the module is enabled and running. 3: The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. The current includes the selected clock source enabled for WDT and RTCC. 4: These parameters are characterized but not tested in manufacturing.

DS30010198B-page 348  2019-2020 Microchip Technology Inc. DC80 43.1 85 (4) µA -40°C to +125°C 2.0V LCD + Charge Pump (medium power resistor ladder)42 85 (4) µA 3.3V DC81 299.2 420 (4) µA -40°C to +85°C 2.0V LCD + Charge Pump (high-power resistor ladder)252.8 420 (4) µA 3.3V DC82 295.5 420 (4) µA -40°C to +125°C 2.0V LCD + Charge Pump (high-power resistor ladder)237.6 420 (4) µA 3.3V Incremental Current DMT (DMT)(2) DC83 177.2 1000 nA -40°C to +85°C 2.0V DMT(2) 234.1 1000 nA 3.3V 575 1500 nA -40°C to +125°C 2.0V 750 1500 nA 3.3V Incremental Current Real-Time Clock and Calendar (RTCC)(2) DC84 786.4 — nA -40°C to +125°C 2.0V RTCC (with SOSC enabled in Low-Power mode)(2)894.6 — nA 3.3V DC85 500 1000 nA -40°C to +85°C 2.0V RTCC (with LPRC enabled)(2) 550 1000 nA 3.3V 570 1300 nA -40°C to +125°C 2.0V 600 1300 nA 3.3V TABLE 30-7: CURRENT (BOR, WDT, HLVD, ADC, LCD, DMT, RTCC)(3) (CONTINUED) Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter No. Typical(1) Max Units Operating Temperature VDD Conditions Note 1: Data in the “Typical” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Incremental current while the module is enabled and running. 3: The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. The current includes the selected clock source enabled for WDT and RTCC. 4: These parameters are characterized but not tested in manufacturing.

 2019-2020 Microchip Technology Inc. DS30010198B-page 349 PIC24FJ128GL306 FAMILY TABLE 30-8: I/O PIN INPUT SPECIFICATIONS Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param No. Symbol Characteristic Min Typ (1) Max Units Conditions VIL Input Low Voltage(3) DI10 I/O Pins with ST Buffer V SS — 0.2 V DD V DI11 I/O Pins with TTL Buffer V SS —0 . 1 5 V DD V DI15 MCLR VSS — 0.2 V DD V DI16 OSCI (EC mode) V SS — 0.2 V DD V DI18 I/O Pins with I 2C Buffer V SS — 0.3 V DD V DI19 I/O Pins with SMBus Buffer V SS — 0.8 V SMBus is enabled VIH Input High Voltage(3) DI20 I/O Pins with ST Buffer: with Analog Functions, Digital Only

0.8 VDD

5.5 V V DI21 I/O Pins with TTL Buffer: with Analog Functions, Digital Only 0.25 VDD + 0.8 0.25 VDD + 0.8 VDD 5.5 V V DI25 MCLR 0.8 VDD —V DD V DI26 OSCI (EC mode) 0.7 V DD —V DD V DI28 I/O Pins with I 2C Buffer: with Analog Functions, Digital Only

0.7 VDD

5.5 V V DI29 I/O Pins with SMBus Buffer: with Analog Functions, Digital Only 1.35 1.35 VDD 5.5 V V DI30 I CNPU CNx Pull-up Current 100 — 450 µA V DD = 3.3V, VPIN = VSS DI30A I CNPD CNx Pull-Down Current 150 — 550 µA V DD = 3.3V, VPIN = VDD IIL Input Leakage Current(2) DI50 I/O Ports — — ±1 µA V SS  VPIN  VDD, pin at high-impedance DI51 Analog Input Pins — — ±1 µA V SS  VPIN  VDD, pin at high-impedance DI55 MCLR —— ± 1 µ A V SS VPIN VDD DI56 OSCI/CLKI — — ±1 µA V SS VPIN VDD, EC, XT and HS modes Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Negative current is defined as current sourced by the pin. 3: Refer to Table 1-1 for I/O pin buffer types.

DS30010198B-page 350  2019-2020 Microchip Technology Inc. TABLE 30-9: I/O PIN OUTPUT SPECIFICATIONS Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param No. Symbol Characteristic Min Typ (1) Max Units Conditions VOL Output Low Voltage DO10 I/O Ports — — 0.35 V I OL = 6 mA, VDD = 3.6V —— 0 . 7 V I OL = 18 mA, VDD = 3.6V —— 0 . 4 V I OL = 5.0 mA, VDD = 2V DO16 RB15, RC15 — — 0.35 V I OL = 9 mA, VDD = 3.6V —— 0 . 3 5 V I OL = 6 mA, VDD = 2V VOH Output High Voltage DO20 I/O Ports 3.2 — — V I OH = -6.0 mA, VDD = 3.6V 2.7 — — V I OH = -18 mA, VDD = 3.6V 1.75 — — V I OH = -1.0 mA, VDD = 2V 0.9 — — V I OH = -10 mA, VDD = 2V DO26 RB15, RC15 3.25 — — V I OH = -6.0 mA, VDD = 3.6V 1.75 — — V I OH = -1.0 mA, VDD = 2V Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.

 2019-2020 Microchip Technology Inc. DS30010198B-page 351 PIC24FJ128GL306 FAMILY FIGURE 30-4: I/O V OL VS. IOL CHARACTER GRAPHS(1) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 6 8 10 12 14 16 18 VOL (V) IOL (mA) I/O VOL Versus IOL (VDD = 3.6V) -40C Typical 25C Typical 85C Typical 125C Typical Max 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 56789 1 0 1 1 VOL (V) IOL (mA) I/O VOL Versus IOL (VDD = 2.0V) -40C Typical 25C Typical 85C Typical 125C Typical Max Note 1: Production test conditions are given in Table 30-9.

DS30010198B-page 352  2019-2020 Microchip Technology Inc. FIGURE 30-5: I/O V OH VS. IOL CHARACTER GRAPHS(1) 2.7 2.8 2.9 3.1 3.2 3.3 3.4 3.5 3.6 IOL (mA) I/O VOH Versus IOL (VDD = 3.6V) -40C Typical 25C Typical 85C Typical 125C Typical Min 0.9 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 IOL (mA) I/O VOH Versus IOL (VDD = 2.0V) -40C Typical 25C Typical 85C Typical 125C Typical Min Note 1: Production test conditions are given in Table 30-9.

 2019-2020 Microchip Technology Inc. DS30010198B-page 353 PIC24FJ128GL306 FAMILY FIGURE 30-6: RC15, RB15 V OL VS. IOL CHARACTER GRAPHS(1) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 9 1 41 92 42 93 4 VOL (V) IOL (mA) RC15 & RB15 VOL Versus IOL (VDD = 3.6V) -40C Typical 25C Typical 85C Typical 125C Typical Max 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 6 8 10 12 14 16 18 20 VOL (V) IOL (mA) RC15 & RB15 VOL Versus IOL (VDD = 2.0V) -40C Typical 25C Typical 85C Typical 125C Typical Max Note 1: Production test conditions are given in Table 30-9.

DS30010198B-page 354  2019-2020 Microchip Technology Inc. FIGURE 30-7: RC15, RB15 V OH VS. IOL CHARACTER GRAPHS(1) 2.7 2.8 2.9 3.1 3.2 3.3 3.4 3.5 3.6 IOL (mA) RC15 & RB15 VOH Versus IOL (VDD = 3.6V) -40C Typical 25C Typical 85C Typical 125C Typical Min 0.9 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 IOL (mA) RC15 & RB15 VOH Versus IOL (VDD = 2.0V) -40C Typical 25C Typical 85C Typical 125C Typical Min Note 1: Production test conditions are given in Table 30-9.

 2019-2020 Microchip Technology Inc. DS30010198B-page 355 PIC24FJ128GL306 FAMILY TABLE 30-11: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS TABLE 30-10: PROGRAM MEMORY Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param No. Symbol Characteristic Min Typ (1) Max Units Conditions Program Flash Memory D130 E P Cell Endurance 10000 — — E/W -40 C to +125C D131 V PR VDD for Read 2.0 — 3.6 V D132B V DD for Self-Timed Write 2.0 — 3.6 V D133A T IW Self-Timed Word Write Cycle Time —2 0—µ s Self-Timed Row Write Cycle Time —1 . 5—m s D133B T IE Self-Timed Page Erase Time 20 — 40 ms D134 T RETD Characteristic Retention 20 — — Year If no other specifications are violated Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Operating Conditions: -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param No. Symbol Characteristics Min Typ Max Units Comments DVR T VREG Voltage Regulator Start-up Time — 10 — µs VREGS = 0 with any POR or BOR DVR10 V BG Internal Band Gap Reference 1.14 1.2 1.26 V DVR11 T BG Band Gap Reference Start-up Time —1 — m s DVR20 V RGOUT Regulator Output Voltage 1.6 1.8 2.0 V V DD > 1.9V DVR21 C EFC External Filter Capacitor Value 10 — — µF Series resistance < 3  recommended; < 5 required DVR30 V LVR Low-Voltage Regulator Output Voltage 0.9 — 1.2 V RETEN = 1, LPCFG = 0

DS30010198B-page 356  2019-2020 Microchip Technology Inc. TABLE 30-12: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Operating Conditions: -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param No. Symbol Characteristic Min Typ Max Units Conditions DC18 V HLVD HLVD Voltage on VDD Transition HLVDL[3:0] = 0101 3.24 — — V HLVDL[3:0] = 0110 2.93 — 3.39 V HLVDL[3:0] = 0111 2.73 — 3.17 V HLVDL[3:0] = 1000 2.62 — 3.06 V HLVDL[3:0] = 1001 2.39 — 2.8 V HLVDL[3:0] = 1010 2.29 — 2.68 V HLVDL[3:0] = 1011 2.18 — 2.56 V HLVDL[3:0] = 1100 2.08 — 2.45 V HLVDL[3:0] = 1101 1.98 — 2.34 V HLVDL[3:0] = 1110 1.88 — 2.23 V DC101 V THL HLVD Voltage on HLVDIN Pin Transition HLVDL[3:0] = 1111 —1 . 2 0— V DC105 T ONLVD HLVD Module Enable Time — 5 — µs From POR or HLVDEN = 1 Note 1: Trip points for values of HLVD[3:0], from ‘0000’ to ‘0011’, are not implemented.

 2019-2020 Microchip Technology Inc. DS30010198B-page 357 PIC24FJ128GL306 FAMILY TABLE 30-13: COMPARATO R DC SPECIFICATIONS TABLE 30-14: COMPARATOR VOLTAG E REFERENCE DC SPECIFICATIONS Operating Conditions: -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param No. Symbol Characteristic Min Typ Max Units Comments D300 V IOFF Input Offset Voltage — 12 50 mV (Note 1) D301 V ICM Input Common-Mode Voltage 0 — V DD V (Note 1) D302 CMRR Common-Mode Rejection Ratio 55 — — dB (Note 1) D306 I QCMP AVDD Quiescent Current per Comparator — 27 — µA Comparator is enabled D307 T RESP Response Time — 300 — ns (Note 2) D308 T MC2OV Comparator Mode Change to Valid Output — — 10 µs D309 I DD Operating Supply Current — 30 — µA AV DD = 3.3V Note 1: Parameters are characterized but not tested. 2: Measured with one input at VDD/2 and the other transitioning from VSS to VDD, 40 mV step, 15 mV overdrive. Operating Conditions: -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param No. Symbol Characteristic Min Typ Max Units Comments VR310 T SET Settling Time — — 10 µs (Note 1) VRD312 CVR UR Unit Resistor Value (R) — 4.5 — k  Note 1: Measures the interval while CVR[4:0] transitions from ‘11111’ to ‘00000’.

DS30010198B-page 358  2019-2020 Microchip Technology Inc.

30.2 AC Characteristics and Timing Parameters

The information contained in this section defines the PIC24FJ128GL306 family AC characteristics and timing parameters. TABLE 30-15: TEMPERATURE AND VO LTAGE SPECIFICATIONS – AC FIGURE 30-8: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS TABLE 30-16: CAPACITIV E LOADING REQUIREMENTS ON OUTPUT PINS AC CHARACTERISTICS Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Operating voltage VDD range as described in Section 30.1 “DC Characteristics”. Param No. Symbol Characteristic Min Typ (1) Max Units Conditions DO50 C OSCO OSCO/CLKO Pin — — 15 pF In XT and HS modes when the External Clock is used to drive OSCI DO56 C IO All I/O Pins and OSCO — — 50 pF EC mode DO58 C B SCLx, SDAx — — 400 pF In I 2C mode Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. VDD/2 CL RL Pin Pin VSS VSS CL RL =4 6 4 CL = 50 pF for all pins except OSCO 15 pF for OSCO output Load Condition 1 – for all pins except OSCO Load Condition 2 – for OSCO

 2019-2020 Microchip Technology Inc. DS30010198B-page 359 PIC24FJ128GL306 FAMILY FIGURE 30-9: EXTER NAL CLOCK TIMING TABLE 30-17: EXTERNAL CLO CK TIMING REQUIREMENTS Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param No. Symbol Characteristic Min Typ (1) Max Units Conditions OS10 F OSC External CLKI Frequency (External clocks allowed only in EC mode) DC MHz MHz EC ECPLL (Note 2) Oscillator Frequency 3.5 MHz MHz MHz MHz kHz XT XTPLL HS HSPLL SOSC OS20 T OSC TOSC = 1/FOSC — — — — See Parameter OS10 for FOSC value OS25 T CY Instruction Cycle Time(3) 62.5 — DC ns OS30 TosL, TosH External Clock in (OSCI) High or Low Time 0.45 x TOSC ——n s E C OS31 TosR, TosF External Clock in (OSCI) Rise or Fall Time — — 20 ns EC OS40 TckR CLKO Rise Time (4) —1 5 3 0 n s OS41 TckF CLKO Fall Time (4) —1 5 3 0 n s Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Represents input to the system clock prescaler. PLL dividers and postscalers must still be configured so that the system clock frequency does not exceed the maximum frequency shown in Figure 30-1. 3: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type, under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an External Clock applied to the OSCI/CLKI pin. When an External Clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. 4: Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 T CY) and high for the Q3-Q4 period (1/2 TCY). OSCI CLKO Q4 Q1 Q2 Q3 Q4 Q1 OS20 OS25 OS30 OS30 OS40 OS41 OS31OS31 Q1 Q2 Q3 Q4 Q2 Q3

DS30010198B-page 360  2019-2020 Microchip Technology Inc. TABLE 30-18: AC SPECIFICATIONS FOR PHASE-LOCKED LOOP (PLL) MODE Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Sym Characteristic Min Typ Max Units Conditions FIN Input Frequency Range 2 — 24 MHz FMIN Minimum Output Frequency from the Frequency Multiplier ——1 6 M H z 4 M H z F IN with 4x feedback ratio,

2 MHz FIN with 8x feedback ratio

FMAX Maximum Output Frequency from the Frequency Multiplier 96 — — MHz 4 MHz F IN with 24x net multiplication ratio,

24 MHz FIN with 4x net multiplication ratio

FSLEW Maximum Step Function of FIN at which the PLL will be Ensured to Maintain Lock -4 — +4 % Full input range of F IN TLOCK Lock Time for VCO — — 24 µs With the specified minimum, T REF, and a lock timer count of one cycle, this is the maximum VCO lock time supported JFM8 Cumulative Jitter of Frequency Multiplier Over Voltage and Temperature during Any Eight Consecutive Cycles of the PLL Output —— ± 0 . 1 2 % 4 M H z F IN with 4x feedback ratio TABLE 30-19: INTERNAL RC ACCURACY Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param No. Characteristic Min Typ (1) Max Units Conditions (Note 2) (Note 2) F20A FRC Accuracy @ 8 MHz with Enabled Self-Tune Feature A  +85°C F21 LPRC @ 32 kHz -20 — 20 % V CAP Output Voltage = 1.8V F22 OSCTUN Step-Size — 0.1 — %/bit F23 T LOCK FRC Self-Tune Lock Time(3) —5 8m s Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: To achieve this accuracy, physical stress applied to the microcontroller package (ex., by flexing the PCB) must be kept to a minimum. 3: Time from reference clock stable, and in range, to FRC tuned within range specified by F20 (with self-tune).

 2019-2020 Microchip Technology Inc. DS30010198B-page 361 PIC24FJ128GL306 FAMILY FIGURE 30-10: FRC ACCURACY OVER TEMPERATURE AND V DD(1) VDD (V) Note 1: Temperature points of -40°C, +25°C and +85°C are production tested only. TABLE 30-20: RC OSCILLATOR START-UP TIME Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param No. Symbol Characteristic Min Typ (1) Max Units Conditions FR0 T FRC FRC Oscillator Start-up Time —2— µ s FR1 T LPRC Low-Power RC Oscillator Start-up Time —5 0— µ s Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.

DS30010198B-page 362  2019-2020 Microchip Technology Inc. FIGURE 30-11: CLKO AND I/O TIMING CHARACTERISTICS TABLE 30-21: CLKO AND I/O TIMING REQUIREMENTS Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param No. Symbol Characteristic Min Typ (1) Max Units Conditions DO31 T IOR Port Output Rise Time — 10 25 ns DO32 T IOF Port Output Fall Time — 10 25 ns DI35 T INP INTx Pin High or Low Time (input) 1— — T CY DI40 T RBP CNx High or Low Time (input) 1— — T CY Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Note: Refer to Figure 30-8 for Load conditions. I/O Pin (Input) I/O Pin (Output) DI35 Old Value New Value DI40 DO31 DO32

 2019-2020 Microchip Technology Inc. DS30010198B-page 363 PIC24FJ128GL306 FAMILY TABLE 30-22: RESET AND BROWN-OUT RESET REQUIREMENTS Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param No. Symbol Characteristic Min Typ (1) Max Units Conditions SY10 T MCL MCLR Pulse Width (Low) 2 — — µs SY12 T POR Power-on Reset Delay — 2 — µs SY13 T IOZ I/O High-Impedance from MCLR Low or Watchdog Timer Reset Lesser of: (3 TCY + 2) or 700 —( 3 T CY + 2) µs SY25 T BOR Brown-out Reset Pulse Width 1——µ s V DD VBOR SY45 T RST Internal State Reset Time — 50 — µs SY71 T WAKEUP Wake-up Time from Sleep Mode — 7 — µs VREGS (RCON[8]) = 1, RETEN (RCON[12]) = 0, LPCFG (FPOR[2]) = 1 — 35 — µs VREGS (RCON[8]) = 0, RETEN (RCON[12]) = 0, LPCFG (FPOR[2]) = 1 — 210 — µs VREGS (RCON[8]) = 1, RETEN (RCON[12]) = 1, LPCFG (FPOR[2]) = 0 — 325 — µs VREGS (RCON[8]) = 0, RETEN (RCON[12]) = 1, LPCFG (FPOR[2]) = 0 Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated.

DS30010198B-page 364  2019-2020 Microchip Technology Inc. FIGURE 30-12: TIMER1 EXTERNAL CLOCK TIMING CHARACTERISTICS T1CK TMR1 TA10 TA11 TA15 TA20 TABLE 30-23: TIMER1 EXTERNAL CLOCK TIMING CHARACTERISTICS Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. No. Symbol Characteristics (1) Min Max Units Conditions TA10 T CKH T1CK High Time Synchronous 1 — T CY Must also meet Parameter TA15 Asynchronous 10 — ns TA11 T CKL T1CK Low Time Synchronous 1 — T CY Must also meet Parameter TA15 Asynchronous 10 — ns TA15 T CKP T1CK Input Period Synchronous 2 — T CY Asynchronous 20 — ns TA20 T CKEXTMRL Delay from External T1CK Clock Edge to Timer Increment —3 T CY Synchronous mode Note 1: These parameters are characterized but not tested in manufacturing.

 2019-2020 Microchip Technology Inc. DS30010198B-page 365 PIC24FJ128GL306 FAMILY FIGURE 30-13: MCCP TIMER MODE EXTE RNAL CLOCK TIMING CHARACTERISTICS TCKIx CCPxTMR TMR10 TMR11 TMR15 TMR20 TABLE 30-24: MCCP TIMER MODE TIMING REQUIREMENTS Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. No. Symbol Characteristics (1) Min Max Units Conditions TMR10 T CKH TCKIx High Time Synchronous 1 — T CY Must also meet Parameter TMR15 Asynchronous 10 — ns TMR11 T CKL TCKIx Low Time Synchronous 1 — T CY Must also meet Parameter TMR15 Asynchronous 10 — ns TMR15 T CKP TCKIx Input Period Synchronous 2 — T CY Asynchronous 20 — ns TMR20 T CKEXTMRL Delay from External TCKIx Clock Edge to Timer Increment —1T CY Note 1: These parameters are characterized but not tested in manufacturing.

 2019-2020 Microchip Technology Inc. DS30010198B-page 367 PIC24FJ128GL306 FAMILY FIGURE 30-16: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS TABLE 30-27: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Mode CKE CKP SMP Maximum Data Rate Typ.(1) Master Transmit Only (Half-Duplex) 0,10 ,10 ,1 25 MHz Master Transmit/Receive (Full-Duplex) 0,10 ,1 0 11 MHz 1 21 MHz Slave Transmit/Receive (Full-Duplex) 0,10 ,10 ,1 11 MHz Note 1: These parameters are characterized but not tested in manufacturing. SCKx (CKP = 0) SCKx (CKP = 1) SDOx SDIx SP10 SP10 SP40 SP41 SP35 MSb LSb LSb InMSb In

DS30010198B-page 368  2019-2020 Microchip Technology Inc. FIGURE 30-17: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SCKx (CKP = 0) SCKx (CKP = 1) SDOx SDIx SP36 SP35 LSb In LSb SP10 SP10 SP40 SP41 MSb In MSb

 2019-2020 Microchip Technology Inc. DS30010198B-page 369 PIC24FJ128GL306 FAMILY FIGURE 30-18: SPIx MODUL E SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS TABLE 30-28: SPIx MODULE MASTER MODE TIMING REQUIREMENTS Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. No. Symbol Characteristics (1) Min Max Units SP10 T SCL, TSCH SCKx Output Low or High Time 20 — ns SP35 T SCH2DOV, TSCL2DOV SDOx Data Output Valid After SCKx Edge — 7 ns SP36 T DOV2SC, TDOV2SCL SDOx Data Output Setup to First SCKx Edge 7 — ns SP40 T DIV2SCH, TDIV2SCL Setup Time of SDIx Data Input to SCKx Edge 7 — ns SP41 T SCH2DIL, TSCL2DIL Hold Time of SDIx Data Input to SCKx Edge 7 — ns Note 1: These parameters are characterized but not tested in manufacturing. SSx SCKx (CKP = 0) SCKx (CKP = 1) SDOx SP50 SP40 SP41 SP51 SP35 MSb LSb LSb In SP52 SP70 SP70 SDIx MSb In

DS30010198B-page 370  2019-2020 Microchip Technology Inc. FIGURE 30-19: SPIx MODUL E SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SSx SCKx (CKP = 0) SCKx (CKP = 1) SDOx SDIx SP60 MSb LSb SP51 LSb In SP52 SP70 SP40 SP41 SP50 SP70 SP35 MSb In TABLE 30-29: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param.No. Symbol Characteristics (1) Min Max Units SP70 T SCL, TSCH SCKx Input Low Time or High Time 45 — ns SP35 T SCH2DOV, TSCL2DOV SDOx Data Output Valid After SCKx Edge — 10 ns SP40 T DIV2SCH, TDIV2SCL Setup Time of SDIx Data Input to SCKx Edge 0 — ns SP41 T SCH2DIL, TSCL2DIL Hold Time of SDIx Data Input to SCKx Edge 7 — ns SP50 T SSL2SCH, TSSL2SCL SSx  to SCKx  or SCKx  Input 40 — ns SP51 T SSH2DOZ SSx  to SDOx Output High-Impedance 2.5 12 ns SP52 T SCH2SSH, TSCL2SSH SSx  After SCKx Edge 10 — ns SP60 T SSL2DOV SDOx Data Output Valid After SSx Edge — 12.5 ns Note 1: These parameters are characterized but not tested in manufacturing.

DS30010198B-page 372  2019-2020 Microchip Technology Inc. TABLE 30-30: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param No. Symbol Characteristics Min. (1) Max. Units Conditions IM10 T LO:SCL Clock Low Time 100 kHz mode T CY * (BRG + 2) — µs 400 kHz mode T CY * (BRG + 2) — µs

1 MHz mode T CY * (BRG + 2) — µs

IM11 T HI:SCL Clock High Time 100 kHz mode T CY * (BRG + 2) — µs 400 kHz mode T CY * (BRG + 2) — µs IM20 T F:SCL SDAx and SCLx Fall Time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 C B 300 ns

1 MHz mode — 100 ns

IM21 T R:SCL SDAx and SCLx Rise Time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 C B 300 ns

1 MHz mode — 300 ns

IM25 T SU:DAT Data Input Setup Time 100 kHz mode 250 — ns 400 kHz mode 100 — ns

1 MHz mode 100 — ns

IM26 T HD:DAT Data Input Hold Time 100 kHz mode 0 — µs 400 kHz mode 0 0.9 µs 1 MHz mode 0 0.3 µs IM30 T SU:STA Start Condition Setup Time 100 kHz mode T CY * (BRG + 2) — µs Only relevant for Repeated Start condition400 kHz mode T CY * (BRG + 2) — µs IM31 T HD:STA Start Condition Hold Time 100 kHz mode T CY * (BRG + 2) — µs After this period, the first clock pulse is generated400 kHz mode T CY * (BRG + 2) — µs IM33 T SU:STO Stop Condition Setup Time 100 kHz mode T CY * (BRG + 2) — µs 400 kHz mode T CY * (BRG + 2) — µs IM34 T HD:STO Stop Condition Hold Time 100 kHz mode T CY * (BRG + 2) — ns 400 kHz mode T CY * (BRG + 2) — ns

1 MHz mode T CY * (BRG + 2) — ns

IM40 T AA:SCL Output Valid from Clock 100 kHz mode — 3500 ns 400 kHz mode — 1000 ns

1 MHz mode — 350 ns

BF:SDA Bus Free Time 100 kHz mode 4.7 — µs The amount of time the bus must be free before a new transmission can start 400 kHz mode 1.3 — µs 1 MHz mode 0.5 — µs IM50 C B Bus Capacitive Loading 100 kHz mode — 400 pF 400 kHz mode — 400 pF

1 MHz mode — 10 pF

PGD Pulse Gobbler Delay 52 312 ns Note 1: BRG is the value of the I2C Baud Rate Generator.

DS30010198B-page 374  2019-2020 Microchip Technology Inc. TABLE 30-31: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param No. Symbol Characteristics Min. Max. Units Conditions IS10 T LO:SCL Clock Low Time 100 kHz mode 4.7 — µs CPU clock must be minimum 800 kHz 400 kHz mode 1.3 — µs CPU clock must be minimum 3.2 MHz 1 MHz mode 0.5 — µs IS11 T HI:SCL Clock High Time 100 kHz mode 4.0 — µs CPU clock must be minimum 800 kHz 400 kHz mode 0.6 — µs CPU clock must be minimum 3.2 MHz 1 MHz mode 0.5 — µs IS20 T F:SCL SDAx and SCLx Fall Time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns IS21 T R:SCL SDAx and SCLx Rise Time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns IS25 T SU:DAT Data Input Setup Time 100 kHz mode 250 — ns 400 kHz mode 100 — ns HD:DAT Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 µs 1 MHz mode 0 0.3 µs IS30 T SU:STA Start Condition Setup Time 100 kHz mode 4700 — ns Only relevant for Repeated Start condition400 kHz mode 600 — ns

1 MHz mode 250 — ns

IS31 T HD:STA Start Condition Hold Time 100 kHz mode 4000 — ns After this period, the first clock pulse is generated400 kHz mode 600 — ns IS33 T SU:STO Stop Condition Setup Time 100 kHz mode 4000 — ns 400 kHz mode 600 — ns

1 MHz mode 600 — ns

HD:STO Stop Condition Hold Time 100 kHz mode 4000 — ns 400 kHz mode 600 — ns AA:SCL Output Valid from Clock 100 kHz mode 0 3500 ns 400 kHz mode 0 1000 ns

1 MHz mode 0 350 ns

BF:SDA Bus Free Time 100 kHz mode 4.7 — µs The amount of time the bus must be free before a new transmission can start 400 kHz mode 1.3 — µs 1 MHz mode 0.5 — µs IS50 C B Bus Capacitive Loading 100 kHz mode — 400 pF 400 kHz mode — 400 pF

 2019-2020 Microchip Technology Inc. DS30010198B-page 375 PIC24FJ128GL306 FAMILY TABLE 30-32: A/D MODULE SPECIFICATIONS Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param No. Symbol Characteristic Min. Typ Max. Units Conditions Device Supply AD01 AV DD Module VDD Supply Greater of: VDD – 0.3 or 2.2 — Lesser of: VDD + 0.3 or 3.6 V AD02 AV SS Module VSS Supply V SS – 0.3 — V SS + 0.3 V Reference Inputs AD05 V REFH Reference Voltage High AV SS + 1.7 — AV DD V AD06 V REFL Reference Voltage Low AV SS —A V DD – 1.7 V Voltage AVSS – 0.3 — AV DD + 0.3 V Analog Inputs AD10 V INH-VINL Full-Scale Input Span V REFL —V REFH V (Note 2) Voltage AVSS – 0.3 — AV DD/3 V AD13 Leakage Current — ±1.0 ±610 nA V INL = AVSS = VREFL = 0V, AVDD = VREFH = 3V, Source Impedance = 2.5 k AD17 R IN Recommended Impedance of Analog Voltage Source A/D Accuracy AD20B Nr Resolution — 12 — bits AD21B INL Integral Nonlinearity — ±1 < ±2 LSb V INL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V, Conversion Rate = 125 ksps AD22B DNL Differential Nonlinearity — ±0.5 < ±1 (3) LSb V INL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V, Conversion Rate = 125 ksps AD23B G ERR Gain Error — ±0.6 -2 to +5 LSb V INL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V, Conversion Rate = 125 ksps AD24B E OFF Offset Error — ±0.5 -2 to +4 LSb V INL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V, Conversion Rate = 125 ksps AD25B Monotonicity (1) — — — — Guaranteed Note 1: The A/D conversion result never decreases with an increase in the input voltage. 2: Measurements are taken with the external VREF+ and VREF- used as the A/D voltage reference. 3: Code 2047 can have a DNL error of 1 LSb to <1.5 LSb and code 3071 can have a DNL error of 1 LSb to <2.5 LSb.

DS30010198B-page 376  2019-2020 Microchip Technology Inc. TABLE 30-33: A/D CONVERSION TIMING REQUIREMENTS (1) Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param No. Symbol Characteristic Min. Typ Max. Units Conditions Clock Parameters AD50 T AD A/D Clock Period 178 — — ns AD51 t RC A/D Internal RC Oscillator Period — 269.18 — ns Conversion Rate AD55 t CONV SAR Conversion Time, 12-Bit Mode —1 6 — T AD AD55A SAR Conversion Time, 10-Bit Mode —1 4 — T AD AD56 F CNV Throughput Rate — — 400 ksps AV DD > 2.7V, 10-bit mode —— 3 5 0 k s p s A V DD > 2.7V, 12-bit mode Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures.

 2019-2020 Microchip Technology Inc. DS30010198B-page 377 PIC24FJ128GL306 FAMILY FIGURE 30-24: 10-BIT AND 12-BIT ENOB 9.84 9.85 9.86 9.87 9.88 9.89 9.9 9.91 9.92 9.93 9.94 100 150 200 250 300 350 400 ENOB Conversion Rate (ŬƐƉƐ) 10-it Mode (ENOB) -40C 25C 85C 125C 11.4 11.45 11.5 11.55 11.6 11.65 11.7 11.75 11.8 100 150 300 350 ENOB 200 250 Conversion Rate (ŬƐƉƐ) 12-it Mode (ENOB) -40C 25C 85C 125C

DS30010198B-page 378  2019-2020 Microchip Technology Inc. FIGURE 30-25: 12-BIT INL DNL PLOTS -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0 500 1000 1500 2000 2500 3000 3500 4000 DNL, 12-bit Mode, 100KSPS, Vdd=3.3V -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 0 500 1000 1500 2000 2500 3000 3500 4000 INL, 12-bit Mode, 100KSPS, Vdd=3.3V -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0 500 1000 1500 2000 2500 3000 3500 4000 DNL, 12-bit Mode, 250KSPS, Vdd=3.3V -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 0 500 1000 1500 2000 2500 3000 3500 4000 INL, 12-bit Mode, 250KSPS, Vdd=3.3V -1.2 -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 0 500 1000 1500 2000 2500 3000 3500 4000DNL, 12-bit Mode, 350KSPS, Vdd=3.3V -0.5 0.5 1.5 0 500 1000 1500 2000 2500 3000 3500 4000 INL, 12-bit Mode, 350KSPS, Vdd=3.3V

 2019-2020 Microchip Technology Inc. DS30010198B-page 379 PIC24FJ128GL306 FAMILY FIGURE 30-26: 10-BIT INL DNL PLOTS -0.2 -0.15 -0.1 -0.05 0.05 0.1 0 200 400 600 800 1000 DNL, 10-bit Mode, 100KSPS, Vdd=3.3V -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 0 200 400 600 800 1000 INL, 10-bit Mode, 100KSPS, Vdd=3.3V -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0 200 400 600 800 1000 DNL, 10-bit Mode, 250KSPS, Vdd=3.3V -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 0 200 400 600 800 1000 INL, 10-bit Mode, 250KSPS, Vdd=3.3V -0.25 -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 0.25 0 200 400 600 800 1000 DNL, 10-bit Mode, 400KSPS, Vdd=3.3V -0.3 -0.2 -0.1 0.1 0.2 0.3 0 200 400 600 800 1000 INL, 10-bit Mode, 400KSPS, Vdd=3.3V

DS30010198B-page 380  2019-2020 Microchip Technology Inc. FIGURE 30-27: GAIN AND OFFSET VOLTAGES 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Oīset (LSB) VDD (V) 10-Bit Mode (Oīset) -40C 25C 85C 125C 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Oīset (LSB) VDD (V) 12-Bit Mode (Oīset) -40C 25C 85C 125C -0.4 -0.2 0.2 0.4 0.6 0.8 1.2 1.4 1.6 Gain (LSB) VDD (V) 12-Bit Mode (Gain) -40C 25C 85C 125C -0.4 -0.2 0.2 0.4 0.6 0.8 1.2 1.4 Gain (LSB) VDD (V) 10-Bit Mode (Gain) -40C 25C 85C 125C і Charge Pump Enabled ї і Charge Pump Enabled ї і Charge Pump Enabled ї і Charge Pump Enabled їі Charrge Puump Enabbled ї іі Charrge Puump Enabbled ї і Charrge Puump Enabled ї і Charrge Puump EEnablled ї

 2019-2020 Microchip Technology Inc. DS30010198B-page 381 PIC24FJ128GL306 FAMILY

31.0 PACKAGING INFORMATION

31.1 Package Marking Information

Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 28-Lead SSOP (5.30 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Example PIC24FJ128 GL302 1910017 28-Lead SOIC (7.50 mm) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN Example PIC24FJ128GL302 1910017 28-Lead UQFN (4x4x0.6 mm) XXXXXX XXXXXX YYWWNNN FJ128 GL302 1910017 Example XXXXXXXX 28-Lead QFN (6x6 mm) XXXXXXXX YYWWNNN 24FJ128 Example GL302 1910017 XXXXX PIC24

DS30010198B-page 382  2019-2020 Microchip Technology Inc.

31.1 Package Marking Information (Continued)

64-Lead TQFP (10x10x1 mm) XXXXXXXXXX XXXXXXXXXX YYWWNNN Example PIC24FJ128 GL306 1920017 XXXXXXXX 36-Lead UQFN (5x5 mm) XXXXXXXX YYWWNNN 24FJ128 Example GL303 1910017 XXXXXXXXXX 24FJ128 Example GL305 1910017 XXXXXXXX 64-Lead QFN (9x9x0.9 mm) XXXXXXXX YYWWNNN 24FJ128 Example GL306 1910017 XXXXXXXX 48-Lead UQFN (6x6 mm) XXXXXXXX YYWWNNN 48-Lead TQFP (7x7x1.0 mm) Example XXXXXXX XXXYYWW NNN FJ128GL 3051910 017

 2019-2020 Microchip Technology Inc. DS30010198B-page 383 PIC24FJ128GL306 FAMILY

31.2 Package Details

The following sections give the technical details of the packages.

DS30010198B-page 384  2019-2020 Microchip Technology Inc.

 2019-2020 Microchip Technology Inc. DS30010198B-page 385 PIC24FJ128GL306 FAMILY /g21/g27/g16/g47/g72/g68/g71/g3/g51/g79/g68/g86/g87/g76/g70/g3/g52/g88/g68/g71/g3/g41/g79/g68/g87/g15/g3/g49/g82/g3/g47/g72/g68/g71/g3/g51/g68/g70/g78/g68/g74/g72/g3/g11/g48/g47/g12/g3/g177/g3/g25/g91/g25/g3/g80/g80/g3/g37/g82/g71/g92/g3/g62/g52/g41/g49/g64 /g90/g76/g87/g75/g3/g19/g17/g24/g24/g3/g80/g80/g3/g38/g82/g81/g87/g68/g70/g87/g3/g47/g72/g81/g74/g87/g75 /g49/g82/g87/g72/g29/g41/g82/g85/g3/g87/g75/g72/g3/g80/g82/g86/g87/g3/g70/g88/g85/g85/g72/g81/g87/g3/g83/g68/g70/g78/g68/g74/g72/g3/g71/g85/g68/g90/g76/g81/g74/g86/g15/g3/g83/g79/g72/g68/g86/g72/g3/g86/g72/g72/g3/g87/g75/g72/g3/g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g51/g68/g70/g78/g68/g74/g76/g81/g74/g3/g54/g83/g72/g70/g76/g73/g76/g70/g68/g87/g76/g82/g81/g3/g79/g82/g70/g68/g87/g72/g71/g3/g68/g87/g3 /g75/g87/g87/g83/g29/g18/g18/g90/g90/g90/g17/g80/g76/g70/g85/g82/g70/g75/g76/g83/g17/g70/g82/g80/g18/g83/g68/g70/g78/g68/g74/g76/g81/g74

DS30010198B-page 386  2019-2020 Microchip Technology Inc. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

 2019-2020 Microchip Technology Inc. DS30010198B-page 387 PIC24FJ128GL306 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

DS30010198B-page 388  2019-2020 Microchip Technology Inc.

 2019-2020 Microchip Technology Inc. DS30010198B-page 389 PIC24FJ128GL306 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

DS30010198B-page 390  2019-2020 Microchip Technology Inc. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

 2019-2020 Microchip Technology Inc. DS30010198B-page 391 PIC24FJ128GL306 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

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DS30010198B-page 394  2019-2020 Microchip Technology Inc. 0LFURFKLS7HFKQRORJ\\'UDZLQJ&5HY% /HDG3ODVWLF6KULQN6PDOO2XWOLQH PP%RG\\>6623@ 6,/.6&5((1 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 1RWHV 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 )RUEHVWVROGHULQJUHVXOWVWKHUPDOYLDVLIXVHGVKRXOGEHILOOHGRUWHQWHGWRDYRLGVROGHUORVVGXULQJ UHIORZSURFHVV )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWS ZZZPLFURFKLSFRPSDFNDJLQJ 1RWH 'LPHQVLRQ/LPLWV 8QLWV &RQWDFW3LWFK 0,//,0(7(56 %6& 0,1 0$; &RQWDFW3DG/HQJWK &RQWDFW3DG:LGWK 120 &&RQWDFW3DG6SDFLQJ &RQWDFW3DGWR&HQWHU3DG

 2019-2020 Microchip Technology Inc. DS30010198B-page 395 PIC24FJ128GL306 FAMILY B A 0.10 C 0.10 C 0..07 C A B 0.05 C (DATUM B) (DATUM A) C SEATING PLANE NOTE 1 N TOP VIEW SIDE VIEW BOTTOM VIEW NOTE 1 N

0.10 C A B

0.10 C 0.08 C Microchip Technology Drawing C04-436–M5 Rev B Sheet 1 of 2 D E A 16X b e K L 36X For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 36-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M5) - 5x5 mm Body [UQFN] With Corner Anchors SEE DETAIL A

DS30010198B-page 396  2019-2020 Microchip Technology Inc. Microchip Technology Drawing C04-436–M5 Rev B Sheet 2 of 2 Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Exposed Pad Width Terminal Thickness Pitch Standoff Units Dimension Limits A b e L E N

0.40 BSC

0.152 REF

3.60 0.30 0.15 0.50 0.00 0.20 0.40 3.70 0.55 0.02

5.00 BSC

3.80 0.50 0.25 0.60 0.05 MAX K 0.25 REF REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M Terminal-to-Exposed-Pad 36-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M5) - 5x5 mm Body [UQFN] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: With Corner Anchors Overall Length Exposed Pad Length D D2 3.60 3.70 3.80 C SEATING PLANE (A3) A DETAIL A

 2019-2020 Microchip Technology Inc. DS30010198B-page 397 PIC24FJ128GL306 FAMILY RECOMMENDED LAND PATTERN Dimension Limits Units Center Pad Width Contact Pad Spacing Center Pad Length Contact Pitch 3.80 3.80 MILLIMETERS E MAX 5.00 Contact Pad Length (X36 Contact Pad Width (X36) 0.80 0.20 NOM C1Contact Pad Spacing 5.00 Thermal Via Diameter V Thermal Via Pitch EV 0.30 1.00 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Contact Pad to Center Pad (X36) G 0.20 Corner Pad Length (X4) Corner Pad Width (X4) 0.85 0.85 EV EV Corner Pad Radius R 0.10 G ØV E SILK SCREEN R Microchip Technology Drawing C04-2436–M5 Rev B 36-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M5) - 5x5 mm Body [UQFN] With Corner Anchors

DS30010198B-page 398  2019-2020 Microchip Technology Inc. BA 0.10 C 0.10 C

0.07 C A B

0.05 C (DATUM B) (DATUM A) C SEATING PLANE NOTE 1 N TOP VIEW SIDE VIEW BOTTOM VIEW NOTE 1 N 0.10 C 0.08 C Microchip Technology Drawing C04-442A-M4 Sheet 1 of 2 52X For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 48-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M4) - 6x6 mm Body [UQFN] With Corner Anchors and 4.6x4.6 mm Exposed Pad D E 8X (b1) (K) e e 48X bL 8X (b2) A (A3)

 2019-2020 Microchip Technology Inc. DS30010198B-page 399 PIC24FJ128GL306 FAMILY Microchip Technology Drawing C04-442A-M4 Sheet 2 of 2 REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M 48-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M4) - 6x6 mm Body [UQFN] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: With Corner Anchors and 4.6x4.6 mm Exposed Pad Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Exposed Pad Width Terminal Thickness Pitch Standoff Units Dimension Limits A b e L E N

0.15 REF

0.35 0.15 0.50 0.00 0.20 0.40 0.55 0.02

6.00 BSC

0.45 0.25 0.60 0.05 MAX K 0.30 REFTerminal-to-Exposed-Pad Overall Length Exposed Pad Length D D2 4.50 4.60 4.70 Corner Anchor Pad b1 0.45 REF Corner Anchor Pad, Metal-free Zone b2 0.23 REF 4.50 4.60 4.70

DS30010198B-page 400  2019-2020 Microchip Technology Inc. RECOMMENDED LAND PATTERN Dimension Limits Units Center Pad Width Contact Pad Spacing Center Pad Length Contact Pitch 4.70 4.70 MILLIMETERS E MAX 6.00 Contact Pad Length (X48) Contact Pad Width (X48) 0.80 0.20 Microchip Technology Drawing C04-2442A-M4 NOM 48-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M4) - 6x6 mm Body [UQFN] C1Contact Pad Spacing 6.00 Contact Pad to Center Pad (X48) G1 0.25 Thermal Via Diameter V Thermal Via Pitch EV 0.33 1.20 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: With Corner Anchors and 4.6x4.6 mm Exposed Pad Pad Corner Radius (X 20) R 0.10 EV EV E R Contact Pad to Contact Pad G2 0.20 Corner Anchor Pad Length (X4) Corner Anchor Pad Width (X4) 0.90 0.90 ØV SILK SCREEN

 2019-2020 Microchip Technology Inc. DS30010198B-page 401 PIC24FJ128GL306 FAMILY C SEATING PLANE TOP VIEW SIDE VIEW 0.08 C Microchip Technology Drawing C04-300-PT Rev D Sheet 1 of 2 48X For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 48-Lead Plastic Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP] D D E E BA e e A A2 A1 48X b

0.08 C A-B D

D

0.20 C A-B D

0.20 C A-B D 4X

N NOTE 1

DS30010198B-page 402  2019-2020 Microchip Technology Inc. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Dimensioning and tolerancing per ASME Y14.5M Microchip Technology Drawing C04-300-PT Rev D Sheet 2 of 2 48-Lead Plastic Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP] H SECTION A-A c (L1) L Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Molded Package Width Molded Package Thickness Pitch Standoff Units Dimension Limits A b e L E N

0.50 BSC

1.00 0.45 0.17 0.05 0.22 0.60 MILLIMETERS MIN NOM 0.75 0.27 1.20 0.15 MAX L1 1.00 REFFootprint Overall Length Molded Package Length D

9.00 BSC

7.00 BSC

Terminal Thickness c 0.09 - 0.16 -0.08 -Lead Bend Radius -0.08 0.20Lead Bend Radius 3.5°0° 7°Foot Angle -0° -Lead Angle ࣄ2 12°11° 13°Mold Draft Angle 0.95 1.05

 2019-2020 Microchip Technology Inc. DS30010198B-page 403 PIC24FJ128GL306 FAMILY RECOMMENDED LAND PATTERN Dimension Limits Units C2Contact Pad Spacing Contact Pitch MILLIMETERS E MAX 8.40 Contact Pad Length (X48) Contact Pad Width (X48) 1.50 0.30 Microchip Technology Drawing C04-2300-PT Rev D NOM E G C1Contact Pad Spacing 8.40 Distance Between Pads G 0.20 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: SILK SCREEN 48-Lead Plastic Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP]

DS30010198B-page 404  2019-2020 Microchip Technology Inc. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

 2019-2020 Microchip Technology Inc. DS30010198B-page 405 PIC24FJ128GL306 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

DS30010198B-page 406  2019-2020 Microchip Technology Inc. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note:

 2019-2020 Microchip Technology Inc. DS30010198B-page 407 PIC24FJ128GL306 FAMILY

64 X b

C SEATING PLANE 4X N/4 TIPS TOP VIEW SIDE VIEW For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Microchip Technology Drawing C04-085C Sheet 1 of 2 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] D EE1 D A B

0.20 H A-B D

e A 0.08 C SEE DETAIL 1 AA E1/2 NOTE 1 NOTE 2 1 2 3 N 0.05

DS30010198B-page 408  2019-2020 Microchip Technology Inc. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] 13°12°11°EMold Draft Angle Bottom 13°12°11°DMold Draft Angle Top 0.270.220.17bLead Width 0.20-0.09cLead Thickness

10.00 BSCD1Molded Package Length

10.00 BSCE1Molded Package Width

12.00 BSCDOverall Length

12.00 BSCEOverall Width

7°3.5°0°IFoot Angle 0.750.600.45LFoot Length 0.15-0.05A1Standoff 1.051.000.95A2Molded Package Thickness 1.20--AOverall Height

0.50 BSCeLead Pitch

Footprint L1 1.00 REF 2. Chamfers at corners are optional; size may vary. 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. Notes: Microchip Technology Drawing C04-085C Sheet 2 of 2 L (L1) E c H X X=A—B OR D e/2 DETAIL 1 SECTION A-A T

 2019-2020 Microchip Technology Inc. DS30010198B-page 409 PIC24FJ128GL306 FAMILY RECOMMENDED LAND PATTERN For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Dimension Limits Units C1Contact Pad Spacing Contact Pad Spacing Contact Pitch MILLIMETERS E MAX 11.40 11.40 Contact Pad Length (X28) Contact Pad Width (X28) 1.50 0.30 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: 1. Dimensioning and tolerancing per ASME Y14.5M Microchip Technology Drawing C04-2085B Sheet 1 of 1 GDistance Between Pads 0.20 NOM 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] E G

DS30010198B-page 410  2019-2020 Microchip Technology Inc. NOTES:

DS30010198B-page 412  2019-2020 Microchip Technology Inc. NOTES:

 2019-2020 Microchip Technology Inc. DS30010198B-page 413 PIC24FJ128GL306 FAMILY INDEX A A/D Transfer Functions AC Characteristics B Block Diagrams Access Program Memory Using Data Access from Program Space Address Individual Comparator Configurations, Individual Comparator Configurations, Individual Comparator Configurations, MCLR SPIx Master/Slave Connection C Capture/Compare/PWM/Timer Character Graphs FRC Accuracy Over Temperature and V I/O V CLC

DS30010198B-page 414  2019-2020 Microchip Technology Inc. Code Examples Code Memory Programming Example Configurable Logic Cell. See CLC. CRC Cyclic Redundancy Check. See CRC. D DC Characteristics  Current (BOR, WDT, HLVD, ADC, LCD, Idle Current (I Deadman Timer Direct Memory Access Controller. See DMA. DMA E Equations Relationship Between Device and F G H

 2019-2020 Microchip Technology Inc. DS30010198B-page 415 PIC24FJ128GL306 FAMILY I I Communicating as Master in Single ICSP Write Inhibit Instruction Set Inter-Integrated Circuit. See I 2C. Interrupts J K L LCD Data Registers/Bits for Segment and COM SDATA Registers/Bits for Segment and COM M N O P Packaging Pin Descriptions

DS30010198B-page 416  2019-2020 Microchip Technology Inc. Program Memory Space Configuration Bits R Register Maps Registers ANCFG (A/D Band Gap Reference CLCxGLSH (CLCx Gate Logic Input CMxCON (Comparator x Control, CVRCON (Comparator Voltage DMTPSCNTH (DMT Post-Configure Count DMTPSCNTL (DMT Post-Configure Count DMTPSINTVH (DMT Post-Configure Interval DMTPSINTVL (DMT Post-Configure Interval ECCADDRH (ECC Fault Inject Address ECCADDRL (ECC Fault Inject Address ECCCONH (ECC Fault Injection ECCCONL (ECC Fault Injection IOCPDx (Interrupt-on-Change

 2019-2020 Microchip Technology Inc. DS30010198B-page 417 PIC24FJ128GL306 FAMILY REFOCONH (Reference Oscillator Control High) .... 111 UxRXREG (UARTx Receive, UxTXREG (UARTx Transmit, Resets MCLR RTCC

DS30010198B-page 418  2019-2020 Microchip Technology Inc. S Serial Peripheral Interface. See SPI. SPI T Timing Diagrams U Receiving Transmitting Universal Asynchronous Receiver Transmitter. See UART. V W

 2019-2020 Microchip Technology Inc. DS30010198B-page 419 PIC24FJ128GL306 FAMILY THE MICROCHIP WEBSITE Microchip provides online support via our WWW site at www.microchip.com. This website is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the website contains the following information:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com . Under “Support”, click on “Customer Change Notification” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the website at: http://microchip.com/support

DS30010198B-page 420  2019-2020 Microchip Technology Inc. NOTES:

 2019-2020 Microchip Technology Inc. DS30010198B-page 421 PIC24FJ128GL306 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . Architecture 24 = 16-Bit Modified Harvard without DSP Flash Memory Family FJ = Flash Program Memory Pin Count 02 = 28-pin (QFN, UQFN, SOIC, SSOP) 03 = 36-pin (UQFN) 05 = 48-pin (UQFN, TQFP) 06 = 64-pin (QFN, TQFP) Temperature Range I = -40 C to +85C (Industrial) E= - 4 0 C to +125C (Extended) Package ML = 28-Lead (6x6 mm) QFN (Plastic Quad Flat) MV = 28-Lead (4x4x.5 mm) UQFN (Plastic Ultra Thin Quad Flat) SO = 28-Lead (7.50 mm) SOIC (Plastic Small Outline) SS = 28-Lead (5.30 mm) SSOP (Plastic Shrink Small Outline) M5 = 36-Lead (5x5 mm) UQFN (Ultra Thin Plastic Quad Flat) M4 = 48-Lead (6x6 mm) UQFN (Ultra Thin Plastic Quad Flat) PT = 48-Lead (7x7x1 mm) TQFP (Thin Quad Flatpack) MR = 64-Lead (9x9x.9 mm) QFN (Plastic Quad Flat) PT = 64-Lead (10x10x1 mm) TQFP (Plastic Thin Quad Flatpack Pattern QTP, SQTP , Code or Special Requirements (blank otherwise) ES = Engineering Sample Examples: a) PIC24FJ128GL306-I/PT: PIC24F General Purpose Device, 64-Pin, Industrial Temp., TQFP Package. b) PIC24FJ128GL302-I/ML: PIC24F General Purpose Device, 28-Pin, Industrial Temp., QFN Package Microchip Trademark Architecture Flash Memory Family Program Memory Size (Kbytes) Product Group Pin Count Temperature Range Package Pattern PIC

24 FJ 128 GL3 06 T - I / PT - XXX

Tape and Reel Flag (if applicable)

DS30010198B-page 422  2019-2020 Microchip Technology Inc. NOTES:

 2019-2020 Microchip Technology Inc. DS30010198B-page 423 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP , INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2019-2020, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-6339-9 Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are co mmitted to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

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