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TLV2262A-Q1_16 TI1 | Alldatasheet

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FEATURES

(TOP VIEW) 1OUT 1IN - 1IN + VDD - /GND VDD + 2OUT 2IN - 2IN + 1 1 1OUT 1IN 1IN + VDD + 2IN + 2IN - 2OUT 4OUT 4IN 4IN + V DD - / GND 3IN + 3IN - 3OUT TLV2264A PW PACKAGE (TOP VIEW)

DESCRIPTION

www.ti.com SGLS193 DECEMBER 2008 Advanced LinCMOS RAIL-TO-RAIL OPERATIONAL AMPLIFIERS Qualified for Automotive

Applications

f kHz Low Input Bias Current pA Typ Fully Specified for Both Single-Supply and Split-Supply Operation Low Power 500 µ A Max Common-Mode Input Voltage Range Includes Negative Rail Low Input Offset Voltage 950 µ V Max at T A C Wide Supply Voltage Range 2.7 V to V Macromodel Included The TLV2262 and TLV2264 are dual and quad low voltage operational amplifiers from Texas Instruments. Both devices exhibit rail-to-rail output performance for increased dynamic range in single or split supply applications. The TLV226x family offers a compromise between the micropower TLV225x and the ac performance of the TLC227x. It has low supply current for battery-powered applications, while still having adequate ac performance for it. This family is fully characterized at V and V and is optimized for low-voltage applications. The noise performance has been dramatically improved over previous generations of CMOS amplifiers. Figure depicts the low level of noise voltage for this CMOS amplifier, which has only 200 µ A (typ) of supply current per amplifier. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. Advanced LinCMOS is a trademark of Texas Instruments. Parts, PSpice are trademarks of MicroSim Corporation. PRODUCTION DATA information is current as of publication date. Copyright 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

− High-Level Output Voltage − V HIGH-LEVEL OUTPUT VOL TAGE vs HIGH-LEVEL OUTPUT CURRENT ÁÁ ÁÁ ÁÁ ÁÁ VOH | IOH | − High-Level Output Current − m A 0.5 0 0 500 1000 3.5 1500 2000 2.5 1.5 TA = −55°C VDD = 3 V TA = 85°C TA = −40°C TA = 125°C TA = 25°C TLV2262A-Q1 TLV2264A-Q1 SGLS193 DECEMBER 2008 www.ti.com Figure The TLV226x, exhibiting high input impedance and low noise, are excellent for small-signal conditioning for high-impedance sources, such as piezoelectric transducers. Because of the micropower dissipation levels combined with 3-V operation, these devices work well in hand-held monitoring and remote-sensing applications. In addition, the rail-to-rail output feature with single or split supplies makes this family a great choice when interfacing with analog-to-digital converters (ADCs). For precision applications, the TLV226xA family is available and has a maximum input offset voltage of 950 µ The TLV2262/4 also makes great upgrades to the TLV2332/4 in standard designs. They offer increased output dynamic range, lower noise voltage and lower input offset voltage. This enhanced feature set allows them to be used in a wider range of applications. For range, see the TLV2432 and TLV2442 devices. If your design requires single amplifiers, please see the TLV2211/21/31 family. These devices are single rail-to-rail operational amplifiers in the SOT-23 package. Their small size and low power consumption make them ideal for high density, battery-powered equipment. ORDERING INFORMATION (1) T A PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING TSSOP PW pin) Reel of 2000 TLV2262AQPWRQ1 TQ262A C to 125 C TSSOP PW (14 pin) Reel of 2000 TLV2264AQPWRQ1 P2264AQ (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

IN− R3 R4 R1 R2 OUT VDD−/ GND TLV2262A-Q1 TLV2264A-Q1 www.ti.com SGLS193 DECEMBER 2008 EQUIVALENT SCHEMATIC (EACH AMPLIFIER) Table Actual Device Component Count COMPONENT TLV2262 TLV2264 Transistors Resistors Diodes Capacitors Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

(1) DISSIPATION RATINGS RECOMMENDED OPERATING CONDITIONS TLV2262A-Q1 TLV2264A-Q1 SGLS193 DECEMBER 2008 www.ti.com over operating free-air temperature range (unless otherwise noted) V DD Supply voltage (2) 0.3 V to V V ID Differential input voltage (3) V DD V I Input voltage range DD 0.3 to V DD+ I I Input current, any input mA I O Output current mA Total current into V DD+ mA Total current out of V DD mA Duration of short-circuit current (at or below) C (4) Unlimited P D Continuous total power dissipation See Dissipation Rating Table T A Operating free-air temperature range C to 125 C T stg Storage temperature range C to 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential voltages, are with respect to V DD (3) Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought below V DD 0.3 (4) The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded. T A C DERATING FACTOR T A C T A 125 C PACKAGE POWER RATING ABOVE T A C POWER RATING POWER RATING PW-8 525 mW 4.2 mW/ C 273 mW 105 mW PW-14 700 mW 5.6 mW/ C 364 mW 140 mW MIN MAX UNIT V DD Supply voltage (1) 2.7 V V I Input voltage V DD V DD+ 1.3 V V IC Common-mode input voltage V DD V DD+ 1.3 V T A Operating free-air temperature 125 C (1) All voltage values, except differential voltages, are with respect to V DD Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

www.ti.com SGLS193 DECEMBER 2008 V DD over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS T A MIN TYP MAX UNIT C 300 950 V IO Input offset voltage V DD 1.5 V IC V O R S Ω mV Full range 1500 Temperature coefficient α VIO V DD 1.5 V IC V O R S Ω C to 125 C µ C of input offset voltage Input offset voltage long-term V DD 1.5 V IC V O R S Ω C 0.003 µ V/mo drift (1) C 0.5 I IO Input offset current V DD 1.5 V IC V O R S Ω pA 125 C 800 C I IB Input bias current V DD 1.5 V IC V O R S Ω pA 125 C 800 0.3 C to to 2.2 Common-mode input voltage V ICR R S Ω V IO mV V range Full range to 1.7 I OH µ A C 2.99 C 2.85 I OH 100 µ A V OH High-level output voltage Full range 2.82 V C 2.7 I OH 400 µ A Full range 2.55 I OL µ A C C 100 150 I OL 500 µ A V OL Low-level output voltage V IC 1.5 V Full range 165 mV C 200 300 I OL mA Full range 300 C 100 R L k Ω (2) Large-signal differential A VD V IC 1.5 V O V to V Full range V/mV voltage amplification R L M Ω (2) C 100 r i(d) Differential input resistance C Ω Common-mode input r i(c) C Ω resistance Common-mode input c i(c) f kHz C pF capacitance Closed-loop output z o f 100 kHz, A V C 270 Ω impedance C Common-mode rejection CMRR V IC to 1.7 V O 1.5 R S Ω dB ratio Full range C 100 Supply voltage rejection ratio k SVR V DD 2.7 V to V IC V DD /2, No load dB Δ V DD Δ V IO Full range C 400 500 I DD Supply current V O 1.5 No load µ A Full range 500 (1) Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T A 150 C extrapolated to T A C using the Arrhenius equation and assuming an activation energy of 0.96 eV. (2) Referenced to 1.5 V Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

www.ti.com V DD over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS T A MIN TYP MAX UNIT C 0.35 0.55 V O 0.5 V to 1.7 R L k Ω (1) SR Slew rate at unity gain µ s C L 100 pF (1) Full range 0.25 f Hz C Equivalent input noise V n nV/ Hz voltage f kHz C f 0.1 Hz to Hz C 0.6 Peak-to-peak equivalent V N(PP) µ V input noise voltage f 0.1 Hz to Hz C I n Equivalent input noise current C 0.6 fA/ Hz A V C 0.03 Total harmonic distortion plus V O 0.5 V to 2.5 f kHz, THD+N noise R L k Ω (1) A V C 0.05 Gain-bandwidth product f kHz, R L k Ω (1) C L 100 pF (1) C 0.67 MHz Maximum output-swing V O(PP) A V R L k Ω (1) B OM C 395 kHz bandwidth C L 100 pF (1) To 0.1% C 5.6 A V Step V to t s Settling time µ s R L k Ω (1) C L 100 pF (1) To 0.01% C 12.5 φ m Phase margin at unity gain R L k Ω (1) C L 100 pF (1) C G m Gain margin R L k Ω (1) C L 100 pF (1) C dB (1) Referenced to 1.5 V Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

www.ti.com SGLS193 DECEMBER 2008 V DD over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS T A MIN TYP MAX UNIT C 300 950 V IO Input offset voltage V DD 2.5 V IC V O R S Ω mV Full range 1500 Temperature coefficient α VIO V DD 2.5 V IC V O R S Ω C to 125 C µ C of input offset voltage Input offset voltage long-term V DD 2.5 V IC V O R S Ω C 0.003 µ V/mo drift (1) C 0.5 I IO Input offset current V DD 2.5 V IC V O R S Ω pA 125 C 800 C I IB Input bias current V DD 2.5 V IC V O R S Ω pA 125 C 800 0.3 C to to 4.2 Common-mode input voltage V ICR R S Ω V IO mV V range Full range to 3.5 I OH µ A C 4.99 C 4.85 4.94 I OH 100 µ A V OH High-level output voltage Full range 4.82 V C 4.7 4.85 I OH 400 µ A Full range 4.5 I OL µ A C 0.01 C 0.09 0.15 I OL 500 µ A V OL Low-level output voltage V IC 2.5 V Full range 0.15 V C 0.2 0.3 I OL mA Full range 0.3 C 170 R L k Ω (2) Large-signal differential A VD V IC 2.5 V O V to V Full range V/mV voltage amplification R L M Ω (2) C 550 r i(d) Differential input resistance C Ω Common-mode input r i(c) C Ω resistance Common-mode input c i(c) f kHz C pF capacitance Closed-loop output z o f 100 kHz, A V C 240 Ω impedance C Common-mode rejection CMRR V IC to 2.7 V O 2.5 R S Ω dB ratio Full range C Supply voltage rejection ratio k SVR V DD 4.4 V to V IC V DD /2, No load dB Δ V DD Δ V IO Full range C 400 500 I DD Supply current V O 2.5 No load µ A Full range 500 (1) Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T A 150 C extrapolated to T A C using the Arrhenius equation and assuming an activation energy of 0.96 eV. (2) Referenced to 2.5 V Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

www.ti.com V DD over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS T A MIN TYP MAX UNIT C 0.35 0.55 V O 0.5 V to 3.5 R L k Ω (1) SR Slew rate at unity gain µ s C L 100 pF (1) Full range 0.25 f Hz C Equivalent input noise V n nV/ Hz voltage f kHz C f 0.1 Hz to Hz C 0.7 Peak-to-peak equivalent V N(PP) µ V input noise voltage f 0.1 Hz to Hz C 1.3 I n Equivalent input noise current C 0.6 fA/ Hz A V C 0.017 Total harmonic distortion plus V O 0.5 V to 2.5 f kHz, THD+N noise R L k Ω (1) A V C 0.03 Gain-bandwidth product f kHz, R L k Ω (1) C L 100 pF (1) C 0.71 MHz Maximum output-swing V O(PP) A V R L k Ω (1) B OM C 185 kHz bandwidth C L 100 pF (1) To 0.1% C 6.4 A V Step 0.5 V to 2.5 t s Settling time µ s R L k Ω (1) C L 100 pF (1) To 0.01% C 14.1 φ m Phase margin at unity gain R L k Ω (1) C L 100 pF (1) C G m Gain margin R L k Ω (1) C L 100 pF (1) C dB (1) Referenced to 2.5 V Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

www.ti.com SGLS193 DECEMBER 2008 V DD over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS T A MIN TYP MAX UNIT C 300 950 V IO Input offset voltage V DD 1.5 V IC V O R S Ω mV Full range 1500 Temperature coefficient α VIO V DD 1.5 V IC V O R S Ω C to 125 C µ C of input offset voltage Input offset voltage long-term V DD 1.5 V IC V O R S Ω C 0.003 µ V/mo drift (1) C 0.5 I IO Input offset current V DD 1.5 V IC V O R S Ω pA 125 C 800 C I IB Input bias current V DD 1.5 V IC V O R S Ω pA 125 C 800 0.3 C to to 2.2 Common-mode input voltage V ICR R S Ω V IO mV V range Full range to 1.7 I OH µ A C 2.99 C 2.85 I OH 100 µ A V OH High-level output voltage Full range 2.82 V C 2.7 I OH 400 µ A Full range 2.6 I OL µ A C C 100 150 I OL 500 µ A V OL Low-level output voltage V IC 1.5 V Full range 150 mV C 200 300 I OL mA Full range 300 C 100 R L k Ω (2) Large-signal differential A VD V IC 1.5 V O V to V Full range V/mV voltage amplification R L M Ω (2) C 100 r i(d) Differential input resistance C Ω Common-mode input r i(c) C Ω resistance Common-mode input c i(c) f kHz C pF capacitance Closed-loop output z o f 100 kHz, A V C 270 Ω impedance C Common-mode rejection CMRR V IC to 1.7 V O 1.5 R S Ω dB ratio Full range C 100 Supply voltage rejection ratio k SVR V DD 2.7 V to V IC V DD /2, No load dB Δ V DD Δ V IO Full range C 0.8 I DD Supply current V O 1.5 No load mA Full range (1) Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T A 150 C extrapolated to T A C using the Arrhenius equation and assuming an activation energy of 0.96 eV. (2) Referenced to 1.5 V Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

www.ti.com V DD over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS T A MIN TYP MAX UNIT C 0.35 0.55 V O 0.5 V to 1.7 R L k Ω (1) SR Slew rate at unity gain µ s C L 100 pF (1) Full range 0.25 f Hz C Equivalent input noise V n nV/ Hz voltage f kHz C f 0.1 Hz to Hz C 0.6 Peak-to-peak equivalent V N(PP) µ V input noise voltage f 0.1 Hz to Hz C I n Equivalent input noise current C 0.6 fA/ Hz A V C 0.03 Total harmonic distortion plus V O 0.5 V to 2.5 f kHz, THD+N noise R L k Ω (1) A V C 0.05 Gain-bandwidth product f kHz, R L k Ω (1) C L 100 pF (1) C 0.67 MHz Maximum output-swing V O(PP) A V R L k Ω (1) B OM C 395 kHz bandwidth C L 100 pF (1) To 0.1% C 5.6 A V Step V to t s Settling time µ s R L k Ω (1) C L 100 pF (1) To 0.01% C 12.5 φ m Phase margin at unity gain R L k Ω (1) C L 100 pF (1) C G m Gain margin R L k Ω (1) C L 100 pF (1) C dB (1) Referenced to 1.5 V Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

www.ti.com SGLS193 DECEMBER 2008 V DD over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS T A MIN TYP MAX UNIT C 300 950 V IO Input offset voltage V DD 2.5 V IC V O R S Ω mV Full range 1500 Temperature coefficient α VIO V DD 2.5 V IC V O R S Ω C to 125 C µ C of input offset voltage Input offset voltage long-term V DD 2.5 V IC V O R S Ω C 0.003 µ V/mo drift (1) C 0.5 I IO Input offset current V DD 2.5 V IC V O R S Ω pA 125 C 800 C I IB Input bias current V DD 2.5 V IC V O R S Ω pA 125 C 800 0.3 C to to 4.2 Common-mode input voltage V ICR R S Ω V IO mV V range Full range to 3.5 I OH µ A C 4.99 C 4.85 4.94 I OH 100 µ A V OH High-level output voltage Full range 4.82 V C 4.7 4.85 I OH 400 µ A Full range 4.5 I OL µ A C 0.01 C 0.09 0.15 I OL 500 µ A V OL Low-level output voltage V IC 2.5 V Full range 0.15 V C 0.2 0.3 I OL mA Full range 0.3 C 170 R L k Ω (2) Large-signal differential A VD V IC 2.5 V O V to V Full range V/mV voltage amplification R L M Ω (2) C 550 r i(d) Differential input resistance C Ω Common-mode input r i(c) C Ω resistance Common-mode input c i(c) f kHz C pF capacitance Closed-loop output z o f 100 kHz, A V C 240 Ω impedance C Common-mode rejection CMRR V IC to 2.7 V O 2.5 R S Ω dB ratio Full range C Supply voltage rejection ratio k SVR V DD 4.4 V to V IC V DD /2, No load dB Δ V DD Δ V IO Full range C 0.8 I DD Supply current V O 2.5 No load mA Full range (1) Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T A 150 C extrapolated to T A C using the Arrhenius equation and assuming an activation energy of 0.96 eV. (2) Referenced to 2.5 V Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

www.ti.com V DD over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS T A MIN TYP MAX UNIT C 0.35 0.55 V O 0.5 V to 3.5 R L k Ω (1) SR Slew rate at unity gain µ s C L 100 pF (1) Full range 0.25 f Hz C Equivalent input noise V n nV/ Hz voltage f kHz C f 0.1 Hz to Hz C 0.7 Peak-to-peak equivalent V N(PP) µ V input noise voltage f 0.1 Hz to Hz C 1.3 I n Equivalent input noise current C 0.6 fA/ Hz A V C 0.017 Total harmonic distortion plus V O 0.5 V to 2.5 f kHz, THD+N noise R L k Ω (1) A V C 0.03 Gain-bandwidth product f kHz, R L k Ω (1) C L 100 pF (1) C 0.71 MHz Maximum output-swing V O(PP) A V R L k Ω (1) B OM C 185 kHz bandwidth C L 100 pF (1) To 0.1% C 6.4 A V Step 0.5 V to 2.5 t s Settling time µ s R L k Ω (1) C L 100 pF (1) To 0.01% C 14.1 φ m Phase margin at unity gain R L k Ω (1) C L 100 pF (1) C G m Gain margin R L k Ω (1) C L 100 pF (1) C dB (1) Referenced to 2.5 V Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

www.ti.com SGLS193 DECEMBER 2008 For all curves where V DD all loads are referenced to 2.5 For all curves where V DD all loads are referenced to 1.5 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. Table of Graphs FIGURE Distribution V IO Input offset voltage vs Common mode voltage α VIO Input offset voltage temperature coefficient Distribution I IB IO Input bias and input offset currents vs Free air temperature vs Supply voltage V I Input voltage vs Free air temperature V OH High-level output voltage vs High-level output current 15, V OL Low-level output voltage vs Low-level output current 16, 17, V O(PP) Maximum peak-to-peak output voltage vs Frequency vs Supply voltage I OS Short-circuit output current vs Free-air temperature V ID Differential input voltage vs Output voltage 23, A VD Differential voltage amplification vs Load resistance vs Frequency 26, A VD Large-signal differential voltage amplification vs Free-air temperature 28, z o Output impedance vs Frequency 30, vs Frequency CMRR Common-mode rejection ratio vs Free-air temperature vs Frequency 34, k SVR Supply-voltage rejection ratio vs Free-air temperature 36, I DD Supply current vs Free-air temperature 38, vs Load capacitance SR Slew rate vs Free-air temperature V O Inverting large-signal pulse response 42, V O Voltage-follower large-signal pulse response 44, V O Inverting small-signal pulse response 46, V O Voltage-follower small-signal pulse response 48, V n Equivalent input noise voltage vs Frequency 50, Input noise voltage Over a 10-second period Integrated noise voltage vs Frequency THD+N Total harmonic distortion plus noise vs Frequency vs Supply voltage Gain-bandwidth product vs Free-air temperature vs Frequency 26, φ m Phase margin vs Load capacitance G m Gain margin vs Load capacitance B Unity-gain bandwidth vs Load capacitance Overestimation of phase margin vs Load capacitance Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

Precentage of Amplifiers − % DISTRIBUTION OF TLV2262 INPUT OFFSET VOL TAGE VIO − Input Offset Voltage − mV

841 Amplifiers From 2 Wafer Lots

VDD ± = ± 1.5 V TA = 25°C Precentage of Amplifiers − % DISTRIBUTION OF TLV2262 INPUT OFFSET VOL TAGE VIO − Input Offset Voltage − mV VDD ± = ± 2.5 V TA = 25°C Percentage of Amplifiers − % DISTRIBUTION OF TLV2264 INPUT OFFSET VOL TAGE

2272 Amplifiers From 2 Wafer Lots

VDD ±/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr= ± 1.5 V TA = 25°C VIO − Input Offset Voltage − mV Percentage of Amplifiers − % DISTRIBUTION OF TLV2264 INPUT OFFSET VOL TAGE VDD ±/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr= ± 2.5 V TA = 25°C VIO − Input Offset Voltage − mV TLV2262A-Q1 TLV2264A-Q1 SGLS193 DECEMBER 2008 www.ti.com Figure Figure Figure Figure Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

− Input Offset Voltage − mV 0.5 INPUT OFFSET VOL TAGE vs COMMON-MODE INPUT VOL TAGE −0.5 −1 0 51 2 4 3 VDD = 5 V R S = 50 W TA = 25°C ÁÁ ÁÁ ÁÁ ÁÁ VIO VIC − Common-Mode Input Voltage − V − Input Offset Voltage − mV 0.5 INPUT OFFSET VOL TAGE vs COMMON-MODE INPUT VOL TAGE −0.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 VDD = 3 V R S = 50 W TA = 25°C ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ VIO VIC − Common-Mode Input Voltage − V DISTRIBUTION OF TLV2262 INPUT OFFSET VOLT AGE TEMPERA TURE COEFFICIENT Percentage of Amplifiers − % −5 −4 −3 −2 −1 0 1 2 3 4 5

128 Amplifiers From 2 Wafer Lots

VDD ± = ± 1.5 V P Package TA = 25°C to 85°C a VIO − Temperature Coefficient − m V/°C DISTRIBUTION OF TLV2262 INPUT OFFSET VOLT AGE TEMPERA TURE COEFFICIENT Percentage of Amplifiers − % −5 −4 −3 −2 −1 0 1 2 3 4 5 VDD ± = ± 2.5 V P Package TA = 25°C to 85°C a VIO − Temperature Coefficient − m V/°C TLV2262A-Q1 TLV2264A-Q1 www.ti.com SGLS193 DECEMBER 2008 Figure Figure Figure Figure Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

DISTRIBUTION OF TLV2264 INPUT OFFSET VOLT AGE TEMPERA TURE COEFFICIENT Percentage of Amplifiers − % −5 −4 −3 −2 −1 0 1 2 3 4 5

128 Amplifiers From

2 Wafer Lots

VDD ± = ± 1.5 V N Package TA = 25°C to 125°C a VIO − Temperature Coefficient of Input Offset Voltage − mV/°C DISTRIBUTION OF TLV2264 INPUT OFFSET VOLT AGE TEMPERA TURE COEFFICIENT Percentage of Amplifiers − % −5 −4 −3 −2 −1 0 1 2 3 4 5 VDD ± = ± 2.5 V N Package TA = 25°C to 125°C a VIO − Temperature Coefficient of Input Offset Voltage − mV/°C 25 45 65 85 IIB and IIO − Input Bias and Input Offset Currents − pA INPUT BIAS AND INPUT OFFSET CURRENTS vs FREE-AIR TEMPERA TURE 105 125 IIB IIO VDD ± = ± 2.5 V VIC = 0 VO = 0 R S = 50 W TA − Free-Air Temperature − °C ÁÁ ÁÁ ÁÁ ÁÁ IIB IIO 1 1.5 2 2.5 − Input Voltage − V 0.5 1.5 INPUT VOL TAGE vs SUPPL Y VOLTAGE 2.5 3 3.5 4 −0.5 −1.5 −2.5 R S = 50 W TA = 25°C | VIO | ≤ 5 mV ÁÁ ÁÁ ÁÁ ÁÁ VI |VDD ± | − Supply Voltage − V TLV2262A-Q1 TLV2264A-Q1 SGLS193 DECEMBER 2008 www.ti.com Figure 10. Figure 11. Figure 12. Figure 13. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

− Input Voltage − V INPUT VOL TAGE vs FREE-AIR TEMPERA TURE −55 −35 −15 5 25 45 65 85 | VIO | ≤ 5 mV VDD = 5 V ÁÁ ÁÁ ÁÁ VI TA − Free-Air Temperature − °C 105 125 − High-Level Output Voltage − V HIGH-LEVEL OUTPUT VOL TAGE vs HIGH-LEVEL OUTPUT CURRENT ÁÁ ÁÁ ÁÁ ÁÁ VOH | IOH | − High-Level Output Current − m A 0.5 0 0 500 1000 3.5 1500 2000 2.5 1.5 TA = −55°C VDD = 3 V TA = 85°C TA = −40°C TA = 125°C TA = 25°C − Low-Level Output Voltage − V LOW -LEVEL OUTPUT VOL TAGE vs LOW -LEVEL OUTPUT CURRENT ÁÁ ÁÁ ÁÁ ÁÁ VOL 0.4 0.2 1.2 0 1 2 3 0.8 0.6 1.4 4 5 TA = 85°C TA = − 40°C TA = 25°C VDD = 3 V VIC = 1.5 V TA = − 55°C TA = 125°C IOL − Low-Level Output Current − mA 0.6 0.4 0.2 0 1 2 3 − Low-Level Output Voltage − V 0.8 LOW -LEVEL OUTPUT VOL TAGE vs LOW -LEVEL OUTPUT CURRENT 1.2 4 5 ÁÁ ÁÁ ÁÁ ÁÁ VOL IOL − Low-Level Output Current − mA VDD = 3 V TA = 25°C VIC = 0 VIC = 0.75 V VIC = 1.5 V TLV2262A-Q1 TLV2264A-Q1 www.ti.com SGLS193 DECEMBER 2008 Figure 14. Figure 15. Figure 16. Figure 17. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

− High-Level Output Voltage − V HIGH-LEVEL OUTPUT VOL TAGE vs HIGH-LEVEL OUTPUT CURRENT ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ VOH | IOH | − High-Level Output Current − mA 0 500 1000 1500 2000 2500 3000 TA = 25°C TA = 85°C VDD = 5 V TA = −40°C TA = 125°C TA = −55°C 0.6 0.4 0.2 0 1 2 3 − Low-Level Output Voltage − V 1.2 LOW -LEVEL OUTPUT VOL TAGE vs LOW -LEVEL OUTPUT CURRENT 1.4 4 5 6 0.8 VDD = 5 V VIC = 2.5 V TA = −40°C ÁÁ ÁÁ ÁÁ ÁÁ VOL IOL − Low-Level Output Current − mA TA = 85°C TA = 25°C TA = 125°C TA = −55°C 2 3 4 5 − Short-Circuit Output Current − mA SHORT -CIRCUIT OUTPUT CURRENT vs SUPPL Y VOLTAGE 6 7 8 IOS VDD − Supply Voltage − V VID = −100 mV VID = 100 mV VIC = VDD /2 TA = 25°C − Maximum Peak-to-Peak Output Voltage − V f − Frequency − Hz MAXIMUM PEAK-T O-PEAK OUTPUT VOL TAGE vs FREQUENCY 103 104 105 106 ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ VO(PP) R I = 10 kW TA = 25°C VDD = 5 V VDD = 3 V TLV2262A-Q1 TLV2264A-Q1 SGLS193 DECEMBER 2008 www.ti.com Figure 18. Figure 19. Figure 20. Figure 21. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

− Short-Circuit Output Current − mA SHORT -CIRCUIT OUTPUT CURRENT vs FREE-AIR TEMPERA TURE IOS TA − Free-Air Temperature − °C −50 −25 0 25 50 75 100 VO = 2.5 V VDD = 5 V VID = −100 mV VID = 100 mV −75 125 800 0 0.5 1 1.5 − Differential Input Voltage − 400 200 600 DIFFERENTIAL INPUT VOL TAGE vs OUTPUT VOL TAGE 1000 2 2.5 3 −200 −400 −600 −800 −1000 VDD = 3 V R I = 50 kW VIC = 1.5 V TA = 25°C V ID Vm VO − Output Voltage − V DIFFERENTIAL VOL TAGE AMPLIFICA TION vs LOAD RESIST ANCE R L − Load Resistance − kW − Differential Voltage Amplification − V/mV ÁÁ ÁÁ ÁÁ ÁÁ A VD 100 1000 VDD = 3 V VDD = 5 V VO(PP) = 2 V TA = 25°C 103 104 105 106 800 0 1 3 − Differential Input Voltage − 400 200 600 DIFFERENTIAL INPUT VOL TAGE vs OUTPUT VOL TAGE 1000 2 4 5 −200 −400 −600 −800 −1000 V ID Vm VO − Output Voltage − V VDD = 5 V VIC = 2.5 V R L = 50 kW TA = 25°C TLV2262A-Q1 TLV2264A-Q1 www.ti.com SGLS193 DECEMBER 2008 Figure 22. Figure 23. Figure 24. Figure 25. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

om − Phase Margin fm f − Frequency − Hz LARGE-SIGNAL DIFFERENTIAL VOL TAGE AMPLIFICA TION AND PHASE MARGIN vs FREQUENCY −20 −40 103 104 105 106 107 180° 135° 90° 45° −45° −90° AVD − Large-Signal Differential ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ A VD Voltage Amplification − dB Gain Phase Margin VDD = 3 V C L = 100 pF TA = 25°C om − Phase Margin fm f − Frequency − Hz −20 −40 103 104 105 106 107 180° 135° 90° 45° −45° −90° LARGE-SIGNAL DIFFERENTIAL VOL TAGE AMPLIFICA TION AND PHASE MARGIN vs FREQUENCY AVD − Large-Signal Differential ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ A VD Voltage Amplification − dB Gain Phase Margin VDD = 5 V C L= 100 pF TA = 25°C 100 LARGE-SIGNAL DIFFERENTIAL VOLT AGE AMPLIFICA TION vs FREE-AIR TEMPERA TURE 1000 −50 −25 0 25 50 75 100 TA − Free-Air Temperature − °C − Large-Signal Differential Voltage A VD Amplification − V/mV R L = 1 MW R L = 50 kW R L = 10 kW VDD = 3 V VIC = 1.5 V VO = 0.5 V to 2.5 V 125−75 100 LARGE-SIGNAL DIFFERENTIAL VOLT AGE AMPLIFICA TION vs FREE-AIR TEMPERA TURE 1000 −50 −25 0 25 50 75 100 TA − Free-Air Temperature − °C − Large-Signal Differential Voltage A VD Amplification − V/mV R L = 1 MW 10000 125−75 R L = 50 kW R L = 10 kW VDD = 5 V VIC = 2.5 V VO = 1 V to 4 V TLV2262A-Q1 TLV2264A-Q1 SGLS193 DECEMBER 2008 www.ti.com Figure 26. Figure 27. Figure 28. Figure 29. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

0.1 − Output Impedance − f− Frequency − Hz OUTPUT IMPEDANCE vs FREQUENCY 100 1000 102 103 104 105 VDD = 3 V TA = 25°C A V = 100 A V = 10 A V = 1 Wzo 0.1 − Output Impedance − f− Frequency − Hz OUTPUT IMPEDANCE vs FREQUENCY 100 1000 102 103 104 105 VDD = 5 V TA = 25°C A V = 100 A V = 10 A V = 1 Wzo CMMR − Common-Mode Rejection Ratio − dB COMMON-MODE REJECTION RA TIO vs FREE-AIR TEMPERA TURE − 50 − 25 0 25 50 75 100 TA − Free-Air Temperature − °C 125− 75 VDD = 5 V VDD = 3 V 100 CMRR − Common-Mode Rejection Ratio − dB f − Frequency − Hz COMMON-MODE REJECTION RA TIO vs FREQUENCY 101 102 103 104 105 106 VDD = 5 V VIC = 2.5 V VDD = 5 V VIC = 1.5 V TA = 25°C TLV2262A-Q1 TLV2264A-Q1 www.ti.com SGLS193 DECEMBER 2008 Figure 30. Figure 31. Figure 32. Figure 33. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

− Supply-Voltage Rejection Ratio − dB f − Frequency − Hz SUPPLY-VOLT AGE REJECTION RA TIO vs FREQUENCY −20 kSVR− kSVR+ 101 102 103 104 105 106 ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ kSVR VDD = 3 V TA = 25°C 100 − Supply-Voltage Rejection Ratio − dB f − Frequency − Hz SUPPLY-VOLT AGE REJECTION RA TIO vs FREQUENCY −20 kSVR+ 101 102 103 104 105 106 ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ kSVR kSVR− VDD = 5 V TA = 25°C 100 − Supply-Voltage Rejection Ratio − dB 105 110 −50 −25 0 25 50 75 100 ÁÁ ÁÁ ÁÁ ÁÁ kSVR TA − Free-Air Temperature − °C VDD = 2.7 V to 8 V VIC = VO = VDD /2 125−75 TLV2262 SUPPLY-VOLT AGE REJECTION RA TIO vs FREE-AIR TEMPERA TURE 100 − Supply-Voltage Rejection Ratio − dB 105 110 −50 −25 0 25 50 75 100 ÁÁ ÁÁ ÁÁ ÁÁ kSVR TA − Free-Air Temperature − °C VDD = 2.7 V to 8 V VIC = VO = VDD /2 125−75 TLV2264 SUPPLY-VOLT AGE REJECTION RA TIO vs FREE-AIR TEMPERA TURE TLV2262A-Q1 TLV2264A-Q1 SGLS193 DECEMBER 2008 www.ti.com Figure 34. Figure 35. Figure 36. Figure 37. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

−50 −25 0 25 50 75 100 − Supply Current − Am ÁÁ ÁÁ ÁÁ ÁÁ IDD TA − Free-Air Temperature − °C VDD = 5 V VO = 2.5 V VDD = 3 V VO = 1.5 V 125−75 TLV2262 SUPPL Y CURRENT vs FREE-AIR TEMPERA TURE 800 600 400 1000 1200 −50 −25 0 25 50 75 100 − Supply Current − Am ÁÁ ÁÁ ÁÁ ÁÁ IDD TA − Free-Air Temperature − °C VDD = 5 V VO = 2.5 V VDD = 3 V VO = 1.5 V 125−75 TLV2264 SUPPL Y CURRENT vs FREE-AIR TEMPERA TURE 0.8 0.4 0.2 0.6 SR − Slew Rate − SLEW RA TE vs LOAD CAP ACITANCE SR− SR+ VDD = 5 V A V = −1 TA = 25°C 101 102 103 104 C L − Load Capacitance − pF smV/ 0.6 0.4 0.2 SR − Slew Rate − 0.8 SLEW RA TE vs FREE-AIR TEMPERA TURE 1.2 −50 −25 0 25 50 75 100 SR− SR+ smV/ TA − Free-Air Temperature − °C VDD = 5 V R L = 50 kW C L = 100 pF A V = 1 125−75 TLV2262A-Q1 TLV2264A-Q1 www.ti.com SGLS193 DECEMBER 2008 Figure 38. Figure 39. Figure 40. Figure 41. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

1.5 0.5 0 2 4 6 8 10 12 − Output Voltage − V 2.5 INVERTING LARGE-SIGNAL PULSE RESPONSE 14 16 18 20 VO t − Time − ms A V = −1 TA = 25°C VDD = 3 V R L = 50 kW C L = 100 pF 0 2 4 6 8 10 12 14 16 18 20 INVERTING LARGE-SIGNAL PULSE RESPONSE t − Time − ms − Output Voltage − VVO A V = −1 TA = 25°C VDD = 5 V R L = 50 kW C L = 100 pF 1.5 0.5 0 2 4 6 8 10 12 2.5 VOLT AGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE 14 16 18 20 − Output Voltage − VVO t − Time − ms A V = −1 TA = 25°C VDD = 3 V R L = 50 kW C L = 100 pF 0 2 4 6 8 10 12 14 16 18 20 VOLT AGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE − Output Voltage − VVO t − Time − ms VDD = 5 V R L = 50 kW C L = 100 pF A V = −1 TA = 25°C TLV2262A-Q1 TLV2264A-Q1 SGLS193 DECEMBER 2008 www.ti.com Figure 42. Figure 43. Figure 44. Figure 45. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

0.7 0.65 0.9 0.6 0 2 4 6 8 10 12 0.8 0.75 0.85 INVERTING SMALL-SIGNAL PULSE RESPONSE 0.95 14 16 18 20 VDD = 3 V R L = 50 kW C L = 100 pF − Output Voltage − VVO t − Time − ms A V = − 1 TA = 25°C 2.5 2.45 2.4 0 2 4 6 8 10 12 VO − Output Voltage − V 2.55 2.6 INVERTING SMALL-SIGNAL PULSE RESPONSE 2.65 14 16 18 20 VO VDD = 5 V R L = 50 kW C L = 100 pF AV = −1 TA = 25°C t − Time − ms 0.8 0.75 0.7 0 2 4 6 8 10 12 0.85 0.9 VOLT AGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE 0.95 14 16 18 20 VDD = 3 V R L = 50 kW C L = 100 pF VO − Output Voltage − VVO t − Time − ms AV = 1 TA = 25°C 2.5 2.45 2.4 0 2 4 6 8 10 12 2.55 2.6 VOLT AGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE 2.65 14 16 18 20 VDD = 5 V R L = 50 kW C L = 100 pF AV = 1 TA = 25°C VO − Output Voltage − VVO t − Time − ms TLV2262A-Q1 TLV2264A-Q1 www.ti.com SGLS193 DECEMBER 2008 Figure 46. Figure 47. Figure 48. Figure 49. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

− Equivalent Input Noise Voltage − f − Frequency − Hz EQUIV ALENT INPUT NOISE VOL TAGE vs FREQUENCY 101 102 103 104 VDD = 3 V R S = 20 W TA = 25°C V n nV/ Hz − Equivalent Input Noise Voltage − f − Frequency − Hz EQUIV ALENT INPUT NOISE VOL TAGE vs FREQUENCY 101 102 103 104 VDD = 5 V R S = 20 W TA = 25°C V n nV/ Hz 0 2 4 6 Input Noise Voltage − nV 250 750 t − Time − s INPUT NOISE VOL TAGE OVER A 10-SECOND PERIOD 1000 8 10 500 −250 −500 −750 −1000 VDD = 5 V f = 0.1 Hz to 10 Hz TA = 25°C 0.1 Integrated Noise Voltage − f − Frequency − Hz INTEGRA TED NOISE VOL TAGE vs FREQUENCY 100 1 10 1 102 103 104 105 Vm Calculated Using Ideal Pass-Band Filter Lower Frequency = 1 Hz TA = 25°C TLV2262A-Q1 TLV2264A-Q1 SGLS193 DECEMBER 2008 www.ti.com Figure 50. Figure 51. Figure 52. Figure 53. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

Gain-Bandwidth Product − kHz GAIN-BANDWIDTH PRODUCT vs SUPPL Y VOLTAGE VDD − Supply Voltage − V 820 780 740 700 0 2 3 5 860 900 7 8 1 4 6 THD + N − Total Harmonic Distortion Plus Noise − % f − Frequency − Hz TOT AL HARMONIC DIST ORTION PLUS NOISE vs FREQUENCY 10−1 10−2 10−3 101 102 103 104 104 A V = 100 A V = 10 A V = 1 VDD = 5 V R L = 50 kW TA = 25°C Gain-Bandwidth Product − kHz GAIN-BANDWIDTH PRODUCT vs FREE-AIR TEMPERA TURE TA − Free-Air Temperature − °C 800 600 400 1000 1200 −50 −25 0 25 50 100 75 VDD = 5 V f = 10 kHz C L = 100 pF −75 125 om − Phase Margin PHASE MARGIN vs LOAD CAP ACITANCE 10 10 2 103 104 C L − Load Capacitance − pF mf 75° 60° 45° 30° 15° R null = 50 W R null = 100 W TA = 25°C R null = 20 W R null = 10 W 50 kW 50 kW VDD −/GND VDD + R null C L VI R null = 0 TLV2262A-Q1 TLV2264A-Q1 www.ti.com SGLS193 DECEMBER 2008 Figure 54. Figure 55. Figure 56. Figure 57. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

− Unity-Gain Bandwidth − kHz 800 UNITY -GAIN BANDWIDTH vs LOAD CAP ACITANCE 1000 10 10 2 103 104 C L − Load Capacitance − pF ÁÁ ÁÁ ÁÁ ÁÁ TA = 25°C Gain Margin − dB GAIN MARGIN vs LOAD CAP ACITANCE 10 10 2 103 104 C L − Load Capacitance − pF R null = 20 W R L = 50 kW A V = 1 TA = 25°C R null = 0 R null = 10 W R null = 100 W R null = 50 W Overestimation of Phase Margin OVERESTIMA TION OF PHASE MARGIN vs LOAD CAP ACITANCE C L − Load Capacitance − pF 10° 10 10 2 103 104 R null = 100 W R null = 50 W R null = 20 W 12° 14° R null = 10 W TA = 25°C TLV2262A-Q1 TLV2264A-Q1 SGLS193 DECEMBER 2008 www.ti.com Figure 58. Figure 59. NOTE: See application information. Figure 60. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

Dq m1 /C0043tan–1 /C04662 × p ×UGB W × R null× C L/C0467 Dq m1 /C0043improvement in phase margin UGBW /C0043unity-gain bandwidth frequency R null/C0043output series resistance C L /C0043load capacitance Where : (1) F /C00431 1 /C0041gm × R null F /C0043factor reducing frequency of pole gm /C0043small-signal output transconductance (typically 4.83× 10– 3mhos) R null/C0043output series resistance Where : (2) Dq m2 /C0043tan–1/C0551/C0561 /C0562 UGBW /C0466F × P 2/C0467/C0551/C0563 /C0564 – tan–1 /C0466UGBW P 2 /C0467 Dq m2 /C0043reduction in phase margin UGBW /C0043unity-gain bandwidth frequency F /C0043factor from equation (2) P 2 /C0043unadjusted pole (70 MHz @ 10 pF, 7 MHz @100 pF, etc.) Where : (3) TLV2262A-Q1 TLV2264A-Q1 www.ti.com SGLS193 DECEMBER 2008 The TLV226x is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure and Figure illustrate its ability to drive loads greater than 400 pF while maintaining good gain and phase margins null 0). A smaller series resistor null at the output of the device (see Figure improves the gain and phase margins when driving large capacitive loads. Figure and Figure show the effects of adding series resistances of Ω Ω Ω and 100 Ω The addition of this series resistor has two effects: the first is that it adds a zero to the transfer function and the second is that it reduces the frequency of the pole associated with the output load in the transfer function. The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To calculate the improvement in phase margin, Equation can be used. The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure To use Equation UGBW must be approximated from Figure Using Equation alone overestimates the improvement in phase margin as illustrated in Figure The overestimation is caused by the decrease in the frequency of the pole associated with the load, providing additional phase shift and reducing the overall improvement in phase margin. The pole associated with the load is reduced by the factor calculated in Equation For the TLV226x, the pole associated with the load is typically MHz with 100-pF load capacitance. This value varies inversely with C L at C L pF, use MHz, at C L 1000 pF, use 700 kHz, and so on. Reducing the pole associated with the load introduces phase shift, thereby reducing phase margin. This results in an error in the increase in phase margin expected by considering the zero alone (see Equation Equation approximates the reduction in phase margin due to the movement of the pole associated with the load. The result of this equation can be subtracted from the result of the Equation to better approximate the improvement in phase margin. Using these equations with Figure and Figure enables the designer to choose the appropriate output series resistance to optimize the design of circuits driving large capacitive loads. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

50 kΩ 50 kΩ VDD− /GND VDD+ R null C L VI Macromodel Information TLV2262A-Q1 TLV2264A-Q1 SGLS193 DECEMBER 2008 www.ti.com Figure 61. Series-Resistance Circuit Macromodel information provided was derived using Microsim Parts the model generation software used with Microsim PSpice The Boyle macromodel (1) and subcircuit in Figure are generated using the TLV226x typical electrical and operating characteristics at T A Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): Maximum positive output voltage swing Maximum negative output voltage swing Slew rate Quiescent power dissipation Input bias current Open-loop voltage amplification Unity-gain frequency Common-mode rejection ratio Phase margin DC output resistance AC output resistance Short-circuit output current limit (1) Boyle, Cohn, Pederson, and Solomon, Macromodeling of Integrated Circuit Operational Amplifiers, IEEE Journal of Solid-State Circuits SC-9, 353 (1974). Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

− + .SUBCKT TLV226x 1 2 3 4 5 C1 11 12 5.5E−12 C2 6 7 20.00E−12 DC 5 53 DX DE 54 5 DX DLP 90 91 DX DLN 92 90 DX DP 4 3 DX FB 7 99 POL Y (5) VB VC VE VLP + VLN 0 8.84E6 −10E6 10E6 10E6 −10E6 GA 6 0 11 12 62.83E−6 GCM 0 6 10 99 12.34E−9 ISS 3 10 DC 11.05E−6 HLIM 90 0 VLIM 1K J1 11 2 10 JX J2 12 1 10 JX R2 6 9 100.0E3 RD1 60 11 15.92E3 RD2 60 12 15.92E3 R01 8 5 135 R02 7 99 135 RP 3 4 15.87E3 RSS 10 99 18.18E6 VAD 60 4 −.5 VB 9 0 DC 0 VC 3 53 DC .615 VE 54 4 DC .615 VLIM 7 8 DC 0 VLP 91 0 DC 1 VLN 0 92 DC 5.1 .MODEL DX D (IS=800.0E−18) .MODEL JX PJF (IS=500.0E−15 BETA=325E−6 + VTO=−.08) .ENDS VCC+ RP IN − IN+ VCC− VAD RD1 J1 J2 RSS ISS RD2 VE DE DP VC DC EGND VB FB GCM GA VLIM RO1 RO2 HLIM DLP DLN VLNVLP TLV2262A-Q1 TLV2264A-Q1 www.ti.com SGLS193 DECEMBER 2008 Figure 62. Boyle Macromodel and Subcircuit Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1

www.ti.com 31-Jan-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLV2262AQDRQ1 OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 125 TLV2262AQPWRQ1 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TQ262A TLV2262QDRQ1 OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 125 TLV2264AQDRQ1 OBSOLETE SOIC D 14 TBD Call TI Call TI -40 to 125 TLV2264AQPWRQ1 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 P2264AQ TLV2264QDRQ1 OBSOLETE SOIC D 14 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

www.ti.com 31-Jan-2016 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV2262-Q1, TLV2262A-Q1, TLV2264-Q1, TLV2264A-Q1 :

Catalog: TLV2262 , TLV2262A , TLV2264 , TLV2264A
Military: TLV2262M , TLV2262AM , TLV2264AM NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Military - QML certified for Military and Defense Applications

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 21-Apr-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV2262AQPWRQ1 TSSOP PW 8 2000 367.0 367.0 35.0 TLV2264AQPWRQ1 TSSOP PW 14 2000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 21-Apr-2016 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C TYP6.6 6.2

1.2 MAX

6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT (5.8)

0.05 MAX

0.05 MIN

8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

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Product Information

P2264AQ specifications and overview.

Summary

Advanced LinCMOS RAIL-TO-RAIL OPERATIONAL AMPLIFIERS

Description

Advanced LinCMOS RAIL-TO-RAIL OPERATIONAL AMPLIFIERS

Source title P2264AQ Datasheet(PDF) - Texas Instruments

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