P2005A ALSC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 10
Technical content
Features
FCC approved method of EMI attenuation. Provides up to 15dB of EMI suppression. Generates a 1X or ½ X low EMI spread spectrum clock of the input frequency. Input frequency range: 8MHz to 32MHz. Internal loop filter minimizes external components and board space. Frequency deviation: o P2005A: ± 1% to ± 3% SSON# control pin for spread spectrum enable and disable options. Low cycle-to-cycle jitter. 3.3V or 5V operating voltage range. 16mA output drives. TTL or CMOS compatible outputs. Ultra-low power CMOS design. Available in 8-pin SOIC and TSSOP. Product Description The P2005X is a versatile spread spectrum frequency modulator designed specifically for input clock frequencies from 8MHz to 32MHz. Refer Output Frequency Selection Table. The P2005X can generate an EMI reduced clock from crystal, ceramic resonator, or system clock. The P2005X offers various percentage deviations ranging form ±0.6% to ±3.0%. Refer Frequency Deviation Selections Table. The P2005X reduces electromagnetic inte rference (EMI) at the clock source, allowing system wide reduction of EMI of down stream clock and data dependent signals. The P2005X allows significant system co st savings by reducing the number of circuit board layers ferrite beads, shielding and other passive components that are traditionally required to pass EMI regulations. The P2005X uses the most efficient and optimized modulation profile approved by the FCC and is implemented in a proprietary all digital method. The P2005X modulates the output of a single PLL in order to “spread” the bandwidth of a synthesized clock, and more importantly, decreases the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most frequency generators. Lowering EMI by increasing a signal’s bandwidth is called ‘spread spectrum clock generation’.
Applications
The P2005X is targeted towards EMI management for high-speed digital applications such as PC peripheral devices, consumer electronics and embedded controller systems. Block Diagram VSS XIN Frequency Divider Feedback Divider Modulation Phase Detector Loop Filter VCO Output Divider MODOUT PLL VDD SSON# DIV2 SR0 Crystal Oscillator XOUT
rev 1.0 General purpose EMI Reduction IC 2 of 10 Notice: The information in this document is subject to change without notice. XOUT 4 5 P2005X XIN /CLK DIV2 VSS SR0 SSON# ModOUT VDD Pin Configuration Pin Description Pin# Pin Name Type Description 1 XIN/CLK I Connect to crystal or clock. 2 XOUT O Crystal output.
3 DIV2 I
Digital logic input used to select normal output mode or divide-by-two output mode. When this pin is HIGH, the frequency of the output clock is the same as the input clock frequency. When it is tied low, the output frequency is half the input clock frequency. This pin has an internal pull-up resistor. 4 VSS P Ground to entire chip. Connect to system ground.
5 SR0 I Digital logic input used to select Spreading Range Refer Modulation Output and
Spreading Range Selection Table. This pin has an internal pull-up resistor.
6 SSON# I
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum function enabled when LOW, disabled when HIGH. This pin has an internal pull-low resistor. 7 ModOUT O Spread spectrum clock output. 8 VDD P Power supply for the ent ire chip (+3.3V or 5.0V) Output Frequency Selections Input Frequency 8 MHz 12 MHz 16 MHz 20 MHz 24 MHz 28 MHz 32 MHz 0 (1/2 X) 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz DIV2 1 (1X) 8 MHz 12 MHz 16 MHz 20 MHz 24 MHz 28 MHz 32 MHz Output Frequency Frequency Deviation Selections as a Function of Input Frequency Input Frequency Range P/N SR0
8 MHz 12 MHz 16 MHz 20 MHz 24 MHz 28 MHz 32 MHz
Rate (KHz) P2005A P2005S (XIN/20) * 62.5
rev 1.0 General purpose EMI Reduction IC 3 of 10 Notice: The information in this document is subject to change without notice. Spread Spectrum The Output Frequency Selection Table and the Frequency Deviations Selections Table illustrate the two possible spread spectrum options. The optimal setting s hould minimize system EMI to the fullest without affecting system performance. The spreading is describe d as a percentage deviation of the center frequency (Note: The center frequency is the frequency of the external reference input on CLKIN, Pin1). Example: The P2005X is designed for communications, digital video and imaging applications. It is not only optimized for operation in the 8MHz – 32MHz range, but its output frequency can be ext ended down to one half of the input clock frequency using the divide-by-two feature. This feature extends low frequency as low as to 4MHz. Setting Pin 3 low (DIV2 = 0; Divide-by-two mode) sets the output frequency (ModOUT) to half the frequency of the input clock (CLKIN). This is a simple way to generate a spread spectrum modulated low frequency clock when only a higher frequency signal is available. If you want the output frequency to be the same as the input, you can either set DIV2=1 or leave it unconnected. Selecting the P2005X’s spread options is a matter of ei ther setting SR0=1 or SR0=0. Setting SR0=0 set as a lower modulation spread, while setting it to 1 introduc es a wider spectral spread in the output clock. Refer Modulation output and Spreading Selections Tables. The example given in the figure below shows the device set to the divide-by-two mode (DIV2=0) with a lower spectrum range (SR0=0). The versatility provided by allowing both clock division and spread spectrum on one chip is already proving to be a popular solution among leading system manufacturers. CLKIN XOUT DIV2 VSS MODOUT SR0 SSON# VDD 8.832MHz Crystal Modulated 4.416MHz is connected to CLK input pin of the system +3.3V 0.1µF P2005X
rev 1.0 General purpose EMI Reduction IC 4 of 10 Notice: The information in this document is subject to change without notice. EMC Software Simulation By using Alliance’s proprietary EMC simulation software – EMI-Lator®, radiated system level EMI analysis can be made easier, allowing quantitative measure on t he benefits of Alliance’s EMI reduction products. The simulation engine of this EMC software has already been characterized to correlate with the electrical characteristics of Alliance EMI reduction ICs. The figure below is an illustration of this simulation result. Please visit our website at www.alsc.com for information on how to obtain a free copy and demonstration of EMI-Lator ®. Simulation results From EMI-Lator®
rev 1.0 General purpose EMI Reduction IC 5 of 10 Notice: The information in this document is subject to change without notice. Absolute Maximum Ratings Symbol Parameter Rating Unit VDD, VIN Voltage on any pin with respect to GND -0.5 to + 7.0 V TSTG Storage temperature -65 to +125 °C TA Operating temperature 0 to 70 °C Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Symbol Parameter Min Typ Max Unit VIL Input low voltage GND – 0.3 - 0.8 V VIH Input high voltage 2.0 - V DD + 0.3 V IIL Input low current (pull-up resistors on inputs SR0, SR1, CP0 and CP1) - - -35 µA IIH Input high current (pull-down resistor on input SSON#) - - 35 µA IXOL XOUT Output Low Current (@ 0.4V, V DD = 3.3V) - 3 - mA IXOH XOUT Output High Current (@ 2.5V, V DD = 3.3V) 3 VOL Output low voltage (V DD = 3.3V, IOL = 20mA) - - 0.4 V VOH Output high voltage (V DD = 3.3V, IOH = 20mA) 2.5 - - V ICC Dynamic supply current normal mode (3.3V, and 15pF loading) 6.0 7.0 8.3 mA IDD Static supply current standby mode - 0.6 - mA VDD Operating voltage 3.1 3.3 5.5 V tON Power up time (first locked cloc k cycle after power up) - 0.18 - mS ZOUT Clock output impedance - 50 - Ω
rev 1.0 General purpose EMI Reduction IC 6 of 10 Notice: The information in this document is subject to change without notice. Symbol Parameter Min Typ Max Unit fIN Input frequency 8 - 32 MHz fOUT Output frequency 4 - 32 MHz tJC Jitter (cycle to cycle) - - 360 ps tD Output duty cycle 45 50 55 % *tLH and tHL are measured into a capacitive load of 15pF
rev 1.0 General purpose EMI Reduction IC 7 of 10 Notice: The information in this document is subject to change without notice. D E H D A2 A θ L C B e
Package Information
Symbol Dimensions in inches Dimensions in millimeters Min Max Min Max A 0.057 0.071 1.45 1.80 A1 0.004 0.010 0.10 0.25 A2 0.053 0.069 1.35 1.75 B 0.012 0.020 0.31 0.51 C 0.004 0.01 0.10 0.25 D 0.186 0.202 4.72 5.12 E 0.148 0.164 3.75 4.15 e 0.050 BSC 1.27 BSC H 0.224 0.248 5.70 6.30 L 0.012 0.028 0.30 0.70 θ 0° 8° 0° 8°
rev 1.0 General purpose EMI Reduction IC 8 of 10 Notice: The information in this document is subject to change without notice. E H A D B C L θ e 8-Pin TSSOP Dimensions in inches Dimensions in millimeters Symbol Min Max Min Max A 0.047 1.10 A1 0.002 0.006 0.05 0.15 A2 0.031 0.041 0.80 1.05 B 0.007 0.012 0.19 0.30 C 0.004 0.008 0.09 0.20 D 0.114 0.122 2.90 3.10 E 0.169 0.177 4.30 4.50 e 0.026 BSC 0.65 BSC H 0.244 0.260 6.20 6.60 L 0.018 0.030 0.45 0.75 θ 0° 8° 0° 8°
rev 1.0 General purpose EMI Reduction IC 9 of 10 Notice: The information in this document is subject to change without notice. Ordering Codes Part Number Marking Package type Qty/reel Temperature P2005X-08ST P2005X 8 PIN SOIC, TUBE 0°C To 70°C P2005X-08SR P2005X 8-PIN SOIC, TAPE AND REEL 2,500 0°C To 70°C P2005X-08TT P2005X 8-PIN TSSOP, TUBE 0°C To 70°C P2005X-08TR P2005X 8-PIN TSSOP, TAPE AND REEL 2,500 0°C To 70°C
rev 1.0 General purpose EMI Reduction IC 10 of 10 Notice: The information in this document is subject to change without notice. Licensed under U.S Patent Nos 5,488,627 and 5,631,921 © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make ch anges to this document and its products at any time without notice. Alliance assumes no responsibility for any errors t hat may appear in this document. The data contained herein represents Alliance's best data and/or estimate s at the time of issuance. Alliance rese rves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not in tended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or lia bility arising out of the applic ation or use of any product described herein, and disclaims any express or implied warrant ies related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, mercha ntability, or infringement of any intellec tual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any pa tent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alli ance or third parties. Alliance does not aut horize its products for use as critical components in life-supporting systems where a malfunction or fa ilure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. Alliance Semiconductor Corporation 2595, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Preliminary Information Part Number: P2005X Document Version: v1.0