NCP1010_V01 ONSEMI | Alldatasheet
Document overview
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- PDF pages: 25
Technical content
Features
- Built−in 700 V MOSFET with Typical RDSon of 11 /C0087 and 22 /C0087
- Large Creepage Distance Between High−V oltage Pins
- Current−Mode Fixed Frequency Operation: 65 kHz – 100 kHz − 130 kHz
- Skip−Cycle Operation at Low Peak Currents Only: No Acoustic Noise!
- Dynamic Self−Supply, No Need for an Auxiliary Winding
- Internal 1.0 ms Soft−Start
- Latched Overvoltage Protection with Auxiliary Winding Operation
- Frequency Jittering for Better EMI Signature
- Auto−Recovery Internal Output Short−Circuit Protection
- Below 100 mW Standby Power if Auxiliary Winding is Used
- Internal Temperature Shutdown
- Direct Optocoupler Connection
- SPICE Models Available for TRANsient Analysis
- These are Pb−Free and Halide−Free Devices Typical Applications
- Low Power AC/DC Adapters for Chargers
- Auxiliary Power Supplies (USB, Appliances,TVs, etc.) PDIP−7 CASE 626A AP SUFFIX MARKING DIAGRAMS P101xAPyy AWL YYWWG SOT−223 CASE 318E ST SUFFIX1
4 AYW
/C0071 x = Current Limit (0, 1, 2, 3, 4) y = Oscillator Frequency A (65 kHz), B (100 kHz), C (130 kHz) yy = 06 (65 kHz), 10 (100 kHz), 13 (130 kHz) A = Assembly Location WL = Wafer Lot YY, Y = Year WW, W = Work Week /C0071 or G = Pb−Free Package (Note: Microdot may be in either location) See detailed ordering and shipping information in the package dimensions section on page 21 of this data sheet.
ORDERING INFORMATION
7 GND
5 DRAIN
- Informative values only, with: Tamb = 50°C, Fswitching = 65 kHz, circuit mounted on minimum copper area as recommended.
Figure 1. Typical Application Example
shunt which serves as an opto fail−safe protection. 3 5 Drain Drain Connection The internal drain MOSFET connection. Figure 2. Simplified Internal Circuit Architecture
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 www.onsemi.com ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ MAXIMUM RATINGS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Rating ÁÁÁÁÁ ÁÁÁÁÁ Symbol ÁÁÁÁÁÁ ÁÁÁÁÁÁ Value ÁÁÁÁ ÁÁÁÁ Unit Power Supply Voltage on all pins, except Pin 5 (Drain) VCC −0.3 to 10 V Drain Voltage − −0.3 to 700 V Drain Current Peak during Transformer Saturation NCP1010/11 NCP1012/13/14 IDS(pk) 550 1.0 mA A Maximum Current into Pin 1 when Activating the 8.7 V Active Clamp I_VCC 15 mA Thermal Characteristics P Suffix, Case 626A Junction−to−Lead Junction−to−Air, 2.0 oz (70 /C0109m) Printed Circuit Copper Clad 0.36 Sq. Inch (2.32 Sq. Cm) 1.0 Sq. Inch (6.45 Sq. Cm) ST Suffix, Plastic Package Case 318E Junction−to−Lead Junction−to−Air, 2.0 oz (70 /C0109m) Printed Circuit Copper Clad 0.36 Sq. Inch (2.32 Sq. Cm) 1.0 Sq. Inch (6.45 Sq. Cm) R/C0113JL R/C0113JA R/C0113JL R/C0113JA 9.0 °C/W Maximum Junction Temperature TJmax 150 °C Storage Temperature Range − −60 to +150 °C ESD Capability, Human Body Model (All pins except HV) − 2.0 kV ESD Capability, Machine Model − 200 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 8.0 V unless otherwise noted.) Rating Pin Symbol Min Typ Max Unit SUPPLY SECTION AND VCC MANAGEMENT VCC Increasing Level at which the Current Source Turns−off 1 VCCOFF 7.9 8.5 9.1 V VCC Decreasing Level at which the Current Source Turns−on 1 VCCON 6.9 7.5 8.1 V Hysteresis between VCCOFF and VCCON 1 − − 1.0 − V VCC Decreasing Level at which the Latch−off Phase Ends 1 VCClatch 4.4 4.7 5.1 V VCC Decreasing Level at which the Internal Latch is Released 1 VCCreset − 3.0 − V Internal IC Consumption, MOSFET Switching at 65 kHz (Note 2) 1 ICC1 − 0.92 1.1 mA Internal IC Consumption, MOSFET Switching at 100 kHz (Note 2) 1 ICC1 − 0.95 1.15 mA Internal IC Consumption, MOSFET Switching at 130 kHz (Note 2) 1 ICC1 − 0.98 1.2 mA Internal IC Consumption, Latch−off Phase, VCC = 6.0 V 1 ICC2 − 290 − /C0109A Active Zener Voltage Positive Offset to VCCOFF 1 Vclamp 140 200 300 mV Latch−off Current NCP1012/13/14 0 °C < TJ < 125°C −40°C < TJ < 125°C NCP1010/11 0 °C < TJ < 125°C −40°C < TJ < 125°C
1 ILatch
6.3 5.8 5.8 5.3 7.4 7.4 7.3 7.3 9.2 9.2 9.0 9.0 mA POWER SWITCH CIRCUIT Power Switch Circuit On−state Resistance NCP1012/13/14 (Id = 50 mA) T J = 25°C TJ = 125°C NCP1010/11 (Id = 50 mA) T J = 25°C TJ = 125°C
5 RDSon −
/C0087 2. See characterization curves for temperature evolution. 3. Adjust di/dt to reach Ipeak in 3.2 /C0109sec. 4. See characterization curves for temperature evolution.
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 www.onsemi.com ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 8.0 V unless otherwise noted.) Rating UnitMaxTypMinSymbolPin POWER SWITCH CIRCUIT Power Switch Circuit and Startup Breakdown Voltage (ID(off) = 120 /C0109A, TJ = 25°C)
5 BVdss 700 − − V
Power Switch and Startup Breakdown Voltage Off−state Leakage Current TJ = −40°C (Vds = 650 V) TJ = 25°C (Vds = 700 V) TJ = 125°C (Vds = 700 V) IDS(OFF) 120 /C0109A Switching Characteristics (RL = 50 /C0087, Vds Set for Idrain = 0.7 x Ilim) Turn−on Time (90%−10%) Turn−off Time (10%−90%) ton toff ns INTERNAL STARTUP CURRENT SOURCE High−voltage Current Source, VCC = 8.0 V NCP1012/13/14 0 °C < TJ < 125°C −40°C < TJ < 125°C NCP1010/11 0 °C < TJ < 125°C −40°C < TJ < 125°C
1 IC1
5.0 5.0 5.0 5.0 8.0 8.0 8.0 8.0 10.3 11.5 mA High−voltage Current Source, VCC = 0 1 IC2 − 10 − mA Minimum Start−up Drain Voltage (Istart = 0.5 mA, Vcc = Vcc(on) − 0.2 V) 5 Vstart(min) − 15 − V CURRENT COMPARATOR TJ = 25°C (Note 2) Maximum Internal Current Setpoint, NCP1010 (Note 3) 5 Ipeak (22) 90 100 110 mA Maximum Internal Current Setpoint, NCP1011 (Note 3) 5 Ipeak (22) 225 250 275 mA Maximum Internal Current Setpoint, NCP1012 (Note 3) 5 Ipeak (11) 225 250 275 mA Maximum Internal Current Setpoint, NCP1013 (Note 3) 5 Ipeak (11) 315 350 385 mA Maximum Internal Current Setpoint, NCP1014 (Note 3) 5 Ipeak (11) 405 450 495 mA Default Internal Current Setpoint for Skip−Cycle Operation, Percentage of Max Ip − ILskip − 25 − % Propagation Delay from Current Detection to Drain OFF State − TDEL − 125 − ns Leading Edge Blanking Duration − TLEB − 250 − ns INTERNAL OSCILLATOR Oscillation Frequency, 65 kHz Version, TJ = 25°C (Note 4) − fOSC 59 65 71 kHz Oscillation Frequency, 100 kHz Version, TJ = 25°C (Note 4) − fOSC 90 100 110 kHz Oscillation Frequency, 130 kHz Version, TJ = 25°C (Note 4) − fOSC 117 130 143 kHz Frequency Dithering Compared to Switching Frequency (with active DSS) − fdither − /C00343.3 − % Maximum Duty−cycle − Dmax 62 67 72 % FEEDBACK SECTION Internal Pull−up Resistor 4 Rup − 18 − k/C0087 Internal Soft−Start (Guaranteed by Design) − Tss − 1.0 − ms SKIP−CYCLE GENERATION Default Skip Mode Level on FB Pin 4 Vskip − 0.5 − V TEMPERATURE MANAGEMENT Temperature Shutdown − TSD 140 150 160 °C Hysteresis in Shutdown − − − 50 − °C 2. See characterization curves for temperature evolution. 3. Adjust di/dt to reach Ipeak in 3.2 /C0109sec. 4. See characterization curves for temperature evolution. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 www.onsemi.com
APPLICATION INFORMATION
The NCP101X offers a complete current−mode control solution (actually an enhanced NCP1200 controller section) together with a high−voltage power MOSFET in a monolithic structure. The component integrates everything needed to build a rugged and low−cost Switch−Mode Power Supply (SMPS) featuring low standby power. The Quick Selection Table on Page 2, details the differences between references, mainly peak current setpoints and operating frequency. No need for an auxiliary winding: onsemi Very High V oltage Integrated Circuit technology lets you supply the IC directly from the high−voltage DC rail. We call it Dynamic Self−Supply (DSS). This solution simplifies the transformer design and ensures a better control of the SMPS in difficult output conditions, e.g. constant current operations. However, for improved standby performance, an auxiliary winding can be connected to the V CC pin to disable the DSS operation. Short−circuit protection: By permanently monitoring the feedback line activity, the IC is able to detect the presence of a short−circuit, immediately reducing the output power for a total system protection. Once the short has disappeared, the controller resumes and goes back to normal operation. Fail−safe optocoupler and OVP: When an auxiliary winding is connected to the V CC pin, the device stops its internal Dynamic Self−Supply and takes its operating power from the auxiliary winding. A 8.7 V active clamp is connected between V CC and ground. In case the current injected in this clamp exceeds a level of 7.4 mA (typical), the controller immediately latches off and stays in this position until V CC cycles down to 3.0 V (e.g. unplugging the converter from the wall). By adjusting a limiting resistor in series with the V CC terminal, it becomes possible to implement an overvoltage protection function, latching off the circuit in case of broken optocoupler or feedback loop problems. Low standby−power: If SMPS naturally exhibits a good efficiency at nominal load, it begins to be less efficient when the output power demand diminishes. By skipping unneeded switching cycles, the NCP101X drastically reduces the power wasted during light load conditions. An auxiliary winding can further help decreasing the standby power to extremely low levels by invalidating the DSS operation. Typical measurements show results below 80 mW @ 230 Vac for a typical 7.0 W universal power supply. No acoustic noise while operating: Instead of skipping cycles at high peak currents, the NCP101X waits until the peak current demand falls below a fixed 1/4 of the maximum limit. As a result, cycle skipping can take place without having a singing transformer … You can thus select cheap magnetic components free of noise problems. SPICE model: A dedicated model to run transient cycle−by−cycle simulations is available but also an averaged version to help close the loop. Ready−to−use templates can be downloaded in OrCAD’s PSpice, and INTUSOFT’s IsSpice4 from ON Semiconductor web site, NCP101X related section. Dynamic Self−Supply When the power supply is first powered from the mains outlet, the internal current source (typically 8.0 mA) is biased and charges up the V CC capacitor from the drain pin. Once the voltage on this VCC capacitor reaches the VCCOFF level (typically 8.5 V), the current source turns off and pulses are delivered by the output stage: the circuit is awake and activates the power MOSFET. Figure 15 details the internal circuitry. Figure 15. The Current Source Regulates VCC
Figure 18. NCP101X Facing a Fault Condition (Vin = 150 Vdc)
1 V Ripple
thermal runaway while in a fault condition. leakage effects have been removed. Figure 19. A typical drain−ground waveshape where leakage effects are not accounted for.
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 www.onsemi.com Plugging Equations 7 and 8 into Equation 6 leads to /C0116Vds(t) /C0117/C0043Vin and thus, PDSS /C0043Vin /C0032ICC1 (eq. 9) . The worse case occurs at high line, when Vin equals 370 Vdc. With ICC1 = 1.1 mA (65 kHz version), we can expect a DSS dissipation around 407 mW. If you select a higher switching frequency version, the ICC1 increases and it is likely that the DSS consumption exceeds that number. In that case, we recommend to add an auxiliary winding in order to offer more dissipation room to the power MOSFET. Please read application note AND8125/D, “Evaluating the Power Capability of the NCP101X Members” to help in selecting the right part/configuration for your application. Lowering the Standby Power with an Auxiliary Winding The DSS operation can bother the designer when its dissipation is too high and extremely low standby power is a must. In both cases, one can connect an auxiliary winding to disable the self−supply. The current source then ensures the startup sequence only and stays in the off state as long as V CC does not drop below VCCON or 7.5 V. Figure 20 shows that the insertion of a resistor (Rlimit) between the auxiliary DC level and the VCC pin is mandatory to not damage the internal 8.7 V active Zener diode during an overshoot for instance (absolute maximum current is 15 mA) and to implement the fail−safe optocoupler protection as offered by the active clamp. Please note that there cannot be bad interaction between the clamping voltage of the internal Zener and VCC OFF since this clamping voltage is actually built on top of VCC OFF with a fixed amount of offset (200 mV typical). Self−supplying controllers in extremely low standby applications often puzzles the designer. Actually, if a SMPS operated at nominal load can deliver an auxiliary voltage of an arbitrary 16 V (Vnom), this voltage can drop to below 10 V (Vstby) when entering standby. This is because the recurrence of the switching pulses expands so much that the low frequency refueling rate of the V CC capacitor is not enough to keep a constant auxiliary voltage. Figure 21 portrays a typical scope shot of a SMPS entering deep standby (output unloaded). So care must be taken when calculating Rlimit 1) to not trigger the V CC over current latch [by injecting 6.3 mA (min. value) into the active clamp] in normal operation but 2) not to drop too much voltage over Rlimit when entering standby. Otherwise the DSS could reactivate and the standby performance would degrade. We are thus able to bound Rlimit between two equations: Vnom /C0042Vclamp Itrip /C0118Rlimit /C0118Vstby /C0042VCCON ICC1 (eq. 10) Where: Vnom is the auxiliary voltage at nominal load. Vstdby is the auxiliary voltage when standby is entered. Itrip is the current corresponding to the nominal operation. It must be selected to avoid false tripping in overshoot conditions. ICC1 is the controller consumption. This number slightly decreases compared to ICC1 from the spec since the part in standby almost does not switch. VCC ON is the level above which Vaux must be maintained to keep the DSS in the OFF mode. It is good to shoot around 8.0 V in order to offer an adequate design margin, e.g. to not reactivate the startup source (which is not a problem in itself if low standby power does not matter). Since Rlimit shall not bother the controller in standby, e.g. keep Vaux to around 8.0 V (as selected above), we purposely select a Vnom well above this value. As explained before, experience shows that a 40% decrease can be seen on auxiliary windings from nominal operation down to standby mode. Let’s select a nominal auxiliary winding of 20 V to offer sufficient margin regarding 8.0 V when in standby (Rlimit also drops voltage in standby …). Plugging the values in Equation 10 gives the limits within which Rlimit shall be selected: 20 /C00428.7 6.3 m /C0118Rlimit /C011812 /C00428 1.1 m (eq. 11) 1.8 k /C0116Rlimit /C01163.6 k , that is to say: If we design a power supply delivering 12 V, then the ratio between auxiliary and power must be: 12/20 = 0.6. The OVP latch will activate when the clamp current exceeds 6.3 mA. This will occur when Vaux increases to: 8.7 V + 1.8 k x (6.4m + 1.1m) = 22.2 V for the first boundary or 8.7 V + power output, it will respectively give 22.2 x 0.6 = 13.3 V and 35.7 x 0.6 = 21.4 V. As one can see, tweaking the Rlimit value will allow the selection of a given overvoltage output level. Theoretically predicting the auxiliary drop from nominal to standby is an almost impossible exercise since many parameters are involved, including the converter time constants. Fine tuning of Rlimit thus requires a few iterations and experiments on a breadboard to check Vaux variations but also output voltage excursion in fault. Once properly adjusted, the fail−safe protection will preclude any lethal voltage runaways in case a problem would occur in the feedback loop. When an OVP occurs, all switching pulses are permanently disabled, the output voltage thus drops to zero. The V CC cycles up and down between 8.5–4.7 V and stays in this state until the user unplugs the power supply and forces V CC to drop below 3.0 V (VCC reset). Below this value, the internal OVP latch is reset and when the high voltage is reapplied, a new startup sequence can take place in an attempt to restart the converter.
blocked to the maximum until the supply enters regulation. Figure 24. Soft−Start is activated during a startup sequence or an OCP condition.
0 V (Fresh PON)
4.7 V (Overload)
Figure 25. A non−latching shutdown where pulses are stopped as long as the NPN is biased.
Figure 28. The Drain−Source Wave Shall Always be Positive . . .
- In any case, the lateral MOSFET body−diode shall
normal operation as shown by Figure 28. later on how it affects the calculation.
- A current−mode architecture is, by definition,
sensitive to subharmonic oscillations. with duty−cycles below 40% is possible.
- Lateral MOSFETs have a poorly dopped
drop and finally, Ip the maximum peak current. and Ip is still pushed to the maximum.
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 www.onsemi.com The Flyback transfer formula dictates that: Pout /C0104/C00431 2 ·L p·I p 2 ·F s w (eq. 19) which, by extracting Ip and plugging into Equation 19, leads to: Tsw /C0043Lp 2 · Pout /C0104·F s w·L p/C0504· /C04661 Vin /C00411 N · (Vout /C0041Vf)/C0467 (eq. 20) Extracting Lp from Equation 20 gives: Lpcritical /C0043 (Vin · Vr)2 · /C0104 2·F s w·[ P o u t·( V r2 /C00412·V r·V i n /C0041Vin2)] (eq. 21) , with Vr = N . (V out + Vf) and /C0104 the efficiency. If Lp critical gives the inductance value above which DCM operation is lost, there is another expression we can write to connect Lp, the primary peak current bounded by the NCP101X and the maximum duty−cycle that needs to stay below 50%: Lpmax /C0043DCmax · Vinmin · Tsw Ipmax (eq. 22) where Vinmin corresponds to the lowest rectified bulk voltage, hence the longest ton duration or largest duty−cycle. Ip max is the available peak current from the considered part, e.g. 350 mA typical for the NCP1013 (however, the minimum value of this parameter shall be considered for reliable evaluation). Combining Equations 21 and 22 gives the maximum theoretical power you can pass respecting the peak current capability of the NCP101X, the maximum duty−cycle and the discontinuous mode operation: Pmax :/C0043Tsw2 · Vinmin2 ·V r2 · /C0104· (eq. 23) Fsw (2 · Lpmax · Vr2 /C00414 · Lpmax · Vr · Vinmin /C00412 · Lpmax · Vinmin2) From Equation 22 we obtain the operating duty−cycle d /C0043Ip · Lp Vin · Tsw (eq. 24) which lets us calculate the RMS current circulating in the MOSFET: IdRMS /C0043Ip · d 3/C0504(eq. 25) . From this equation, we obtain the average dissipation in the MOSFET: Pavg /C00431 3 ·I p2 ·d·R DSon (eq. 26) to which switching losses shall be added. If we stick to Equation 23, compute Lp and follow the above calculations, we will discover that a power supply built with the NCP101X and operating from a 100 Vac line minimum will not be able to deliver more than 7.0 W continuous, regardless of the selected switching frequency (however the transformer core size will go down as Fswitching is increased). This number increases significantly when operated from a single European mains (18 W). Application note AND8125/D, “Evaluating the Power Capability of the NCP101X Members” details how to assess the available power budget from all the NCP101X series. Example 1. A 12 V 7.0 W SMPS operating on a large mains with NCP101X: Vin = 100 Vac to 250 Vac or 140 Vdc to 350 Vdc once rectified, assuming a low bulk ripple Efficiency = 80% V out = 12 V , Iout = 580 mA Fswitching = 65 kHz Ip max = 350 mA – 10% = 315 mA Applying the above equations leads to: Selected maximum reflected voltage = 120 V with Vout = 12 V , secondary drop = 0.5 V → Np:Ns = 1:0.1 Lp critical = 3.2 mH Ip = 292 mA Duty−cycle worse case = 50% Idrain RMS = 119 mA PMOSFET = 354 mW at RDSon = 24 /C0087 (TJ > 100°C) PDSS = 1.1 mA x 350 V = 385 mW, if DSS is used Secondary diode voltage stress = (350 x 0.1) + 12 = 47 V (e.g. a MBRS360T3, 3.0 A/60 V would fit) Example 2. A 12 V 16 W SMPS operating on narrow European mains with NCP101X: Vin = 230 Vac /C0034 15%, 276 Vdc for Vin min to 370 Vdc once rectified Efficiency = 80% V out = 12 V , Iout = 1.25 A Fswitching = 65 kHz Ip max = 350 mA – 10% = 315 mA Applying the equations leads to: Selected maximum reflected voltage = 250 V with Vout = 12 V, secondary drop = 0.5 V → Np:Ns = 1:0.05 Lp = 6.6 mH Ip = 0.305 mA Duty−cycle worse case = 0.47 Idrain RMS = 121 mA P MOSFET = 368 mW at RDSon = 24 /C0087 (TJ > 100°C) PDSS = 1.1 mA x 370 V = 407 mW, if DSS is used below an ambient of 50°C. Secondary diode voltage stress = (370 x 0.05) + 12 = 30.5 V (e.g. a MBRS340T3, 3.0 A/40 V) Please note that these calculations assume a flat DC rail whereas a 10 ms ripple naturally affects the final voltage available on the transformer end. Once the Bulk capacitor has been selected, one should check that the resulting ripple (min Vbulk?) is still compatible with the above calculations. As an example, to benefit from the largest operating range, a 7.0 W board was built with a 47 /C0109F bulk capacitor which ensured discontinuous operation even in the ripple minimum waves.
Figure 30. An NCP1012−Based Flyback Converter Delivering 6.5 W
11 V J2
- Efficiency at Vin = 100 Vac and Pout = 6.5 W = 75.7%
- Efficiency at Vin = 230 Vac and Pout = 6.5 W = 76.5%
Figure 31. The NCP1012−Based PCB Layout . . . and its Associated Component Placement
Figure 32. A Typical Converter Delivering 7.0 W from a Universal Mains
12 V @
1102 Silver Lake Road
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 www.onsemi.com (kHz) Package Type Shipping† RDSon (/C0087) Ipk (mA) NCP1010AP065G 65 PDIP−7 (Pb−Free) 50 Units / Rail 23 100 NCP1010AP100G 100 23 100 NCP1010AP130G 130 23 100 NCP1010ST65T3G 65 SOT−223 (Pb−Free) 4000 / Tape & Reel 23 100 NCP1010ST100T3G 100 23 100 NCP1010ST130T3G 130 23 100 NCP1011AP065G 65 PDIP−7 (Pb−Free)
50 Units / Rail 23 250
50 Units / Rail
SOT−223 (Pb−Free) 4000 / Tape & Reel 23 250 NCP1011ST100T3G 100 23 250 NCP1011ST130T3G 130 23 250 NCP1012AP065G 65 PDIP−7 (Pb−Free)
50 Units / Rail 11 250
NCP1012AP100G 100 50 Units / Rail 11 250 NCP1012AP133G 130 50 Units / Rail 11 250 NCP1012ST65T3G 65 SOT−223 (Pb−Free) 4000 / Tape & Reel 11 250 NCP1012ST100T3G 100 11 250 NCP1012ST130T3G 130 4000 / Tape & Reel 11 250 NCP1013AP065G 65 PDIP−7 (Pb−Free) 50 Units / Rail 11 350 NCP1013AP100G 100 11 350 NCP1013AP133G 130 11 350 NCP1013ST65T3G 65 SOT−223 (Pb−Free) 4000 / Tape & Reel 11 350 NCP1013ST100T3G 100 11 350 NCP1013ST130T3G 130 11 350 NCP1014AP065G 65 PDIP−7 (Pb−Free)
50 Units / Rail 11 450
NCP1014AP100G 100 50 Units / Rail 11 450 NCP1014ST65T3G 65 SOT−223 (Pb−Free) 4000 / Tape & Reel 11 450 NCP1014ST100T3G 100 11 450 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
PDIP−7 (PDIP−8 LESS PIN 6) CASE 626A ISSUE C DATE 22 APR 2015 SCALE 1:1 NOTE 8 D b L A eB XXXXXXXXX AWL YYWWG E GENERIC MARKING DIAGRAM* XXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb −Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ /C0071”, may or may not be present. A TOP VIEW C SEATING PLANE
0.010 CASIDE VIEW
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK- AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED. 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY . 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). M c B H NOTE 5 e e/2 A2 NOTE 3 M B M NOTE 6 M DIM MIN MAX INCHES A −−−− 0.210 A1 0.015 −−−− b 0.014 0.022 C 0.008 0.014 D 0.355 0.400 D1 0.005 −−−− e 0.100 BSC E 0.300 0.325 M −−−− 10 −−− 5.33 0.38 −−− 0.35 0.56 0.20 0.36 9.02 10.16 0.13 −−−
2.54 BSC
7.62 8.26 −−− 10 MIN MAX MILLIMETERS E1 0.240 0.280 6.10 7.11 0.060 TYP 1.52 TYP A2 0.115 0.195 2.92 4.95 L 0.115 0.150 2.92 3.81 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98AON11774DDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1PDIP−7 (PDIP−8 LESS PIN 6) © Semiconductor Components Industries, LLC, 2019 www.onsemi.com
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN INCHES. PDIP−7, GULL WING CASE 626AA ISSUE A DATE 17 DEC 2019 SCALE 1:1 GENERIC MARKING DIAGRAM* xxxxxxx = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ /C0071”, may or may not be present. 5 8 F −H− GAUGE PLANE G K A SB H E D P N T MLJ 0.015 TOP VIEW SIDE VIEW BOTTOM VIEW
0.015 DP MAX
A 0.365 0.385 B 0.240 0.260 C 0.120 0.150 D 0.018 TYP E 0.039 TYP F 0.045 0.065 G 0.100 BSC H 0.023 0.033 J K 0.004 0.012 L 0.036 0.044 M 0 8 N 12 TYP P 0.300 BSC S 0.372 0.388 /C0095/C0095 /C0095 R 0.016 TYP 0.004 FRONT VIEW R 0.030 xxxxxxxxxxx AWL YYWW
0.010 TYP
C1 0.124 0.162 C MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS http://onsemi.com © Semiconductor Components Industries, LLC, 2002 October, 2002 − Rev. 0 Case Outline Number: XXX DOCUMENT NUMBER: STATUS: NEW STANDARD: DESCRIPTION: 98AON18634D ON SEMICONDUCTOR STANDARD PDIP−7, GULL WING (MINUS PIN #6), APL SUFFIX Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2
DOCUMENT NUMBER: 98AON18634D PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION. REQ. BY L. TESAR. 24 MAY 2004 A OBSOLETED. 17 DEC 2019 © Semiconductor Components Industries, LLC, 2004 May, 2004 − Rev. 01O Case Outline Number: 626AA ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising o ut of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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